Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	411	1			T34	1		T53	3		T197	2
all_values[1]	428	1			T34	1		T197	3		T47	1
all_values[2]	440	1			T39	1		T53	2		T197	2
all_values[3]	424	1			T39	1		T53	2		T197	2
all_values[4]	436	1			T34	2		T53	1		T197	1
all_values[5]	454	1			T34	1		T53	3		T197	7
all_values[6]	417	1			T53	3		T197	4		T47	1
all_values[7]	428	1			T39	1		T53	3		T45	3
all_values[8]	439	1			T34	1		T39	1		T53	1
all_values[9]	455	1			T51	1		T197	3		T49	1
all_values[10]	439	1			T39	1		T197	2		T49	1
all_values[11]	445	1			T51	1		T53	1		T197	3
all_values[12]	433	1			T34	2		T53	2		T197	3
all_values[13]	452	1			T39	1		T53	2		T197	4
all_values[14]	427	1			T34	1		T53	3		T197	1
all_values[15]	406	1			T53	3		T197	5		T49	1
all_values[16]	406	1			T53	1		T197	4		T269	1
all_values[17]	436	1			T34	1		T53	5		T197	4
all_values[18]	442	1			T39	2		T53	1		T197	3
all_values[19]	452	1			T34	1		T51	1		T197	1
all_values[20]	410	1			T34	1		T39	1		T53	3
all_values[21]	434	1			T34	1		T53	2		T197	5
all_values[22]	428	1			T53	2		T197	3		T45	1
all_values[23]	414	1			T39	1		T53	2		T45	3
all_values[24]	427	1			T39	1		T53	1		T197	2
all_values[25]	463	1			T197	2		T49	2		T269	3
all_values[26]	428	1			T53	1		T197	3		T45	1