Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	424	1			T28	4		T210	1		T216	4
all_values[1]	457	1			T22	1		T215	1		T216	1
all_values[2]	404	1			T22	1		T210	1		T205	1
all_values[3]	424	1			T28	1		T210	1		T216	9
all_values[4]	425	1			T210	1		T216	1		T71	2
all_values[5]	464	1			T28	1		T210	1		T205	1
all_values[6]	422	1			T216	3		T60	1		T63	2
all_values[7]	458	1			T28	1		T216	4		T63	1
all_values[8]	467	1			T28	1		T210	2		T205	1
all_values[9]	465	1			T205	1		T216	3		T63	1
all_values[10]	431	1			T210	1		T216	4		T272	2
all_values[11]	464	1			T216	2		T290	2		T98	1
all_values[12]	450	1			T216	2		T290	1		T272	2
all_values[13]	430	1			T205	1		T216	4		T71	1
all_values[14]	464	1			T210	1		T216	3		T272	5
all_values[15]	453	1			T205	1		T216	4		T71	4
all_values[16]	415	1			T28	1		T216	3		T63	1
all_values[17]	439	1			T22	1		T210	1		T205	2
all_values[18]	438	1			T28	1		T215	1		T210	2
all_values[19]	450	1			T210	1		T216	2		T71	2
all_values[20]	436	1			T22	1		T205	1		T216	1
all_values[21]	414	1			T28	1		T215	1		T216	1
all_values[22]	450	1			T210	2		T205	3		T216	2
all_values[23]	400	1			T28	1		T210	3		T205	1
all_values[24]	399	1			T205	1		T216	2		T71	1
all_values[25]	436	1			T60	1		T71	1		T291	2
all_values[26]	430	1			T216	4		T60	1		T63	1