Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.33	100.00	95.99	100.00		100.00	100.00	100.00

Total test records in report: 900

T785	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.1989644431	Aug 25 12:59:14 AM UTC 24	Aug 25 12:59:35 AM UTC 24	2413665905 ps
T786	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.462814966	Aug 25 12:58:13 AM UTC 24	Aug 25 12:59:39 AM UTC 24	2142736050 ps
T787	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.2445198738	Aug 25 12:59:29 AM UTC 24	Aug 25 12:59:39 AM UTC 24	277587705 ps
T788	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random.1495051403	Aug 25 12:59:29 AM UTC 24	Aug 25 12:59:40 AM UTC 24	121562316 ps
T209	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.503163805	Aug 25 12:57:14 AM UTC 24	Aug 25 12:59:41 AM UTC 24	17659491030 ps
T789	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.2285581629	Aug 25 12:59:36 AM UTC 24	Aug 25 12:59:41 AM UTC 24	103061871 ps
T191	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.4196761901	Aug 25 12:56:41 AM UTC 24	Aug 25 12:59:42 AM UTC 24	6303398165 ps
T231	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2863099502	Aug 25 12:56:39 AM UTC 24	Aug 25 12:59:44 AM UTC 24	23948857704 ps
T790	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.786371576	Aug 25 12:57:07 AM UTC 24	Aug 25 12:59:45 AM UTC 24	49006352132 ps
T791	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.191106016	Aug 25 12:59:32 AM UTC 24	Aug 25 12:59:45 AM UTC 24	92869144 ps
T792	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2283381848	Aug 25 12:59:39 AM UTC 24	Aug 25 12:59:46 AM UTC 24	254120879 ps
T793	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.1509605318	Aug 25 12:59:33 AM UTC 24	Aug 25 12:59:46 AM UTC 24	1154616015 ps
T794	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.3906897961	Aug 25 12:59:44 AM UTC 24	Aug 25 12:59:47 AM UTC 24	403247284 ps
T795	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.4247680311	Aug 25 12:59:20 AM UTC 24	Aug 25 12:59:47 AM UTC 24	1417841672 ps
T796	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.879434301	Aug 25 12:59:45 AM UTC 24	Aug 25 12:59:47 AM UTC 24	9055725 ps
T797	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_large_delays.3929917632	Aug 25 12:55:44 AM UTC 24	Aug 25 12:59:48 AM UTC 24	43222914888 ps
T798	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.1778537309	Aug 25 12:59:40 AM UTC 24	Aug 25 12:59:49 AM UTC 24	95340559 ps
T799	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.1044054069	Aug 25 12:59:47 AM UTC 24	Aug 25 12:59:50 AM UTC 24	17907873 ps
T800	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1408871864	Aug 25 12:59:28 AM UTC 24	Aug 25 12:59:50 AM UTC 24	4162860206 ps
T801	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.862338281	Aug 25 12:58:38 AM UTC 24	Aug 25 12:59:50 AM UTC 24	833177666 ps
T802	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1327784155	Aug 25 12:59:25 AM UTC 24	Aug 25 12:59:50 AM UTC 24	116227195 ps
T803	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2431179092	Aug 25 12:58:32 AM UTC 24	Aug 25 12:59:51 AM UTC 24	37602652037 ps
T8	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.4254155351	Aug 25 12:59:03 AM UTC 24	Aug 25 12:59:51 AM UTC 24	252200153 ps
T804	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.917479538	Aug 25 12:59:28 AM UTC 24	Aug 25 12:59:52 AM UTC 24	4127577155 ps
T805	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.1084156943	Aug 25 12:59:51 AM UTC 24	Aug 25 12:59:53 AM UTC 24	11551338 ps
T806	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.635746840	Aug 25 12:59:35 AM UTC 24	Aug 25 12:59:55 AM UTC 24	1596890793 ps
T807	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.338421531	Aug 25 12:59:49 AM UTC 24	Aug 25 12:59:56 AM UTC 24	498822192 ps
T808	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.1494775380	Aug 25 12:59:54 AM UTC 24	Aug 25 12:59:57 AM UTC 24	135212839 ps
T173	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.2132083803	Aug 25 12:58:25 AM UTC 24	Aug 25 12:59:57 AM UTC 24	4422397647 ps
T809	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.258838574	Aug 25 12:59:53 AM UTC 24	Aug 25 12:59:58 AM UTC 24	15634592 ps
T810	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random.446424830	Aug 25 12:59:47 AM UTC 24	Aug 25 12:59:58 AM UTC 24	66639312 ps
T811	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.3658567795	Aug 25 12:59:48 AM UTC 24	Aug 25 12:59:58 AM UTC 24	54139364 ps
T812	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.334442602	Aug 25 12:59:56 AM UTC 24	Aug 25 12:59:59 AM UTC 24	9987125 ps
T813	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.1428426905	Aug 25 12:59:51 AM UTC 24	Aug 25 12:59:59 AM UTC 24	1457610816 ps
T814	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.1051875234	Aug 25 12:59:46 AM UTC 24	Aug 25 01:00:01 AM UTC 24	1309768187 ps
T815	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.2976514449	Aug 25 12:59:59 AM UTC 24	Aug 25 01:00:01 AM UTC 24	17397790 ps
T816	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.705264436	Aug 25 12:59:41 AM UTC 24	Aug 25 01:00:02 AM UTC 24	257910902 ps
T817	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.2418232162	Aug 25 12:58:31 AM UTC 24	Aug 25 01:00:03 AM UTC 24	51369941433 ps
T818	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3336776200	Aug 25 12:59:11 AM UTC 24	Aug 25 01:00:04 AM UTC 24	3725705160 ps
T819	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.4192233442	Aug 25 12:59:52 AM UTC 24	Aug 25 01:00:05 AM UTC 24	544459586 ps
T820	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.1922165818	Aug 25 12:57:12 AM UTC 24	Aug 25 01:00:06 AM UTC 24	1614564304 ps
T149	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.2715764023	Aug 25 12:57:36 AM UTC 24	Aug 25 01:00:08 AM UTC 24	49777706120 ps
T821	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2966697894	Aug 25 12:59:46 AM UTC 24	Aug 25 01:00:10 AM UTC 24	2841285345 ps
T822	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1569465764	Aug 25 12:59:56 AM UTC 24	Aug 25 01:00:11 AM UTC 24	2591424592 ps
T823	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.1977577522	Aug 25 12:59:32 AM UTC 24	Aug 25 01:00:11 AM UTC 24	19308329005 ps
T158	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.606262103	Aug 25 12:54:35 AM UTC 24	Aug 25 01:00:11 AM UTC 24	64799822124 ps
T824	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1027062625	Aug 25 12:58:37 AM UTC 24	Aug 25 01:00:12 AM UTC 24	1614117834 ps
T825	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.3922522128	Aug 25 12:56:47 AM UTC 24	Aug 25 01:00:12 AM UTC 24	18549438252 ps
T826	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.1057589635	Aug 25 01:00:02 AM UTC 24	Aug 25 01:00:13 AM UTC 24	895534469 ps
T827	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.328904020	Aug 25 01:00:06 AM UTC 24	Aug 25 01:00:13 AM UTC 24	64962032 ps
T828	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1243855157	Aug 25 01:00:11 AM UTC 24	Aug 25 01:00:14 AM UTC 24	14524844 ps
T829	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.3237620953	Aug 25 01:00:00 AM UTC 24	Aug 25 01:00:14 AM UTC 24	712560666 ps
T830	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.1501083613	Aug 25 01:00:11 AM UTC 24	Aug 25 01:00:14 AM UTC 24	128837403 ps
T831	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_slow_rsp.567581279	Aug 25 12:56:39 AM UTC 24	Aug 25 01:00:16 AM UTC 24	26621628377 ps
T832	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.3068176480	Aug 25 12:59:24 AM UTC 24	Aug 25 01:00:16 AM UTC 24	2760935645 ps
T833	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.1794849154	Aug 25 12:56:34 AM UTC 24	Aug 25 01:00:16 AM UTC 24	25038005026 ps
T834	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.1687564398	Aug 25 12:57:56 AM UTC 24	Aug 25 01:00:18 AM UTC 24	1429058501 ps
T835	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random.1719098394	Aug 25 12:59:59 AM UTC 24	Aug 25 01:00:18 AM UTC 24	1856008004 ps
T225	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.1263926621	Aug 25 12:55:00 AM UTC 24	Aug 25 01:00:19 AM UTC 24	53053924989 ps
T204	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.1720839520	Aug 25 01:00:06 AM UTC 24	Aug 25 01:00:19 AM UTC 24	2171465780 ps
T836	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random.726978529	Aug 25 01:00:12 AM UTC 24	Aug 25 01:00:19 AM UTC 24	671609404 ps
T837	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.3033888555	Aug 25 12:58:50 AM UTC 24	Aug 25 01:00:19 AM UTC 24	3857269400 ps
T838	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2331054367	Aug 25 01:00:17 AM UTC 24	Aug 25 01:00:20 AM UTC 24	12077551 ps
T839	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.1427111247	Aug 25 01:00:06 AM UTC 24	Aug 25 01:00:20 AM UTC 24	1386552550 ps
T840	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.1884293152	Aug 25 01:00:14 AM UTC 24	Aug 25 01:00:21 AM UTC 24	90774141 ps
T841	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.428368029	Aug 25 01:00:12 AM UTC 24	Aug 25 01:00:21 AM UTC 24	1320277188 ps
T842	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.1903010658	Aug 25 12:59:59 AM UTC 24	Aug 25 01:00:22 AM UTC 24	12067423981 ps
T843	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.4036861842	Aug 25 01:00:17 AM UTC 24	Aug 25 01:00:23 AM UTC 24	278766635 ps
T148	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_slow_rsp.1605612900	Aug 25 12:54:59 AM UTC 24	Aug 25 01:00:23 AM UTC 24	54584459277 ps
T844	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.2403647911	Aug 25 01:00:09 AM UTC 24	Aug 25 01:00:24 AM UTC 24	282481906 ps
T845	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.1524639746	Aug 25 01:00:15 AM UTC 24	Aug 25 01:00:24 AM UTC 24	1205331737 ps
T846	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.3969205766	Aug 25 12:59:52 AM UTC 24	Aug 25 01:00:30 AM UTC 24	181647549 ps
T847	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_large_delays.588695726	Aug 25 12:55:56 AM UTC 24	Aug 25 01:00:31 AM UTC 24	89263677005 ps
T266	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.4060398122	Aug 25 12:59:03 AM UTC 24	Aug 25 01:00:32 AM UTC 24	14177963808 ps
T848	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3256556878	Aug 25 12:59:52 AM UTC 24	Aug 25 01:00:32 AM UTC 24	605549994 ps
T138	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.2327235321	Aug 25 01:00:15 AM UTC 24	Aug 25 01:00:32 AM UTC 24	1315734460 ps
T849	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3146078111	Aug 25 01:00:12 AM UTC 24	Aug 25 01:00:33 AM UTC 24	2933936122 ps
T850	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.837663162	Aug 25 12:59:06 AM UTC 24	Aug 25 01:00:36 AM UTC 24	1630936793 ps
T851	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.3238337128	Aug 25 12:59:41 AM UTC 24	Aug 25 01:00:37 AM UTC 24	1209904802 ps
T852	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.2739672603	Aug 25 12:59:52 AM UTC 24	Aug 25 01:00:38 AM UTC 24	2147717713 ps
T244	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.3665316836	Aug 25 12:52:11 AM UTC 24	Aug 25 01:00:38 AM UTC 24	174901415599 ps
T243	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.2012690919	Aug 25 12:52:58 AM UTC 24	Aug 25 01:00:38 AM UTC 24	46050658754 ps
T853	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.2501134181	Aug 25 12:57:02 AM UTC 24	Aug 25 01:00:38 AM UTC 24	18386845522 ps
T214	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.2452101265	Aug 25 01:00:17 AM UTC 24	Aug 25 01:00:40 AM UTC 24	1019135165 ps
T854	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.597593734	Aug 25 12:58:20 AM UTC 24	Aug 25 01:00:42 AM UTC 24	19172451700 ps
T855	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1026090319	Aug 25 12:58:51 AM UTC 24	Aug 25 01:00:45 AM UTC 24	11074139346 ps
T856	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2496071928	Aug 25 12:58:27 AM UTC 24	Aug 25 01:00:47 AM UTC 24	4563770465 ps
T857	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.2565746439	Aug 25 12:57:14 AM UTC 24	Aug 25 01:00:47 AM UTC 24	64086732292 ps
T858	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.345109228	Aug 25 12:58:44 AM UTC 24	Aug 25 01:00:49 AM UTC 24	55282116514 ps
T238	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.972478349	Aug 25 12:53:24 AM UTC 24	Aug 25 01:00:50 AM UTC 24	47282401985 ps
T859	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3823445821	Aug 25 01:00:06 AM UTC 24	Aug 25 01:00:51 AM UTC 24	202600670 ps
T860	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.353789295	Aug 25 12:59:48 AM UTC 24	Aug 25 01:00:51 AM UTC 24	5214582931 ps
T861	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1150128261	Aug 25 12:58:56 AM UTC 24	Aug 25 01:00:54 AM UTC 24	41533144871 ps
T862	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.337173670	Aug 25 01:00:06 AM UTC 24	Aug 25 01:00:56 AM UTC 24	2470005953 ps
T863	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.1678819060	Aug 25 01:00:20 AM UTC 24	Aug 25 01:01:03 AM UTC 24	3268832318 ps
T864	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.364536877	Aug 25 01:00:19 AM UTC 24	Aug 25 01:01:04 AM UTC 24	250164729 ps
T245	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.3985211668	Aug 25 12:55:36 AM UTC 24	Aug 25 01:01:05 AM UTC 24	48594183104 ps
T265	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1709103648	Aug 25 12:59:16 AM UTC 24	Aug 25 01:01:09 AM UTC 24	27572386274 ps
T865	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.1160246839	Aug 25 12:58:38 AM UTC 24	Aug 25 01:01:14 AM UTC 24	9899397747 ps
T226	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1263613618	Aug 25 12:57:38 AM UTC 24	Aug 25 01:01:22 AM UTC 24	29194634533 ps
T866	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.835979095	Aug 25 12:58:00 AM UTC 24	Aug 25 01:01:24 AM UTC 24	22915405308 ps
T867	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.1583105949	Aug 25 12:56:26 AM UTC 24	Aug 25 01:01:24 AM UTC 24	83806239721 ps
T139	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.1029272122	Aug 25 12:57:25 AM UTC 24	Aug 25 01:01:26 AM UTC 24	29933469743 ps
T140	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.3860650879	Aug 25 12:54:10 AM UTC 24	Aug 25 01:01:28 AM UTC 24	35658274660 ps
T868	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.4002081245	Aug 25 01:00:20 AM UTC 24	Aug 25 01:01:30 AM UTC 24	3892976889 ps
T232	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.702661352	Aug 25 12:52:19 AM UTC 24	Aug 25 01:01:31 AM UTC 24	69808169900 ps
T235	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.2773587439	Aug 25 12:55:10 AM UTC 24	Aug 25 01:01:33 AM UTC 24	124311204262 ps
T869	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.1126572673	Aug 25 12:58:51 AM UTC 24	Aug 25 01:01:39 AM UTC 24	6487116300 ps
T870	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.2769287264	Aug 25 12:59:41 AM UTC 24	Aug 25 01:01:42 AM UTC 24	856113422 ps
T871	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.312380568	Aug 25 01:00:00 AM UTC 24	Aug 25 01:01:52 AM UTC 24	35420014553 ps
T872	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.2397740169	Aug 25 12:57:25 AM UTC 24	Aug 25 01:01:54 AM UTC 24	147661015840 ps
T239	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.2894372177	Aug 25 12:52:04 AM UTC 24	Aug 25 01:01:56 AM UTC 24	174014514984 ps
T873	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.2734296962	Aug 25 12:58:19 AM UTC 24	Aug 25 01:01:57 AM UTC 24	40682131408 ps
T874	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.2050595103	Aug 25 12:59:59 AM UTC 24	Aug 25 01:02:03 AM UTC 24	28849583147 ps
T150	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_large_delays.2001112459	Aug 25 12:56:56 AM UTC 24	Aug 25 01:02:08 AM UTC 24	59284207155 ps
T11	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.155111824	Aug 25 12:58:04 AM UTC 24	Aug 25 01:02:10 AM UTC 24	1771420003 ps
T875	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.2340300982	Aug 25 12:59:10 AM UTC 24	Aug 25 01:02:14 AM UTC 24	23289687885 ps
T876	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.2917860188	Aug 25 12:59:23 AM UTC 24	Aug 25 01:02:14 AM UTC 24	838687955 ps
T877	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1231079174	Aug 25 01:00:08 AM UTC 24	Aug 25 01:02:19 AM UTC 24	50069271650 ps
T240	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.3828947808	Aug 25 12:52:36 AM UTC 24	Aug 25 01:02:24 AM UTC 24	118987538457 ps
T878	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1321493671	Aug 25 12:56:19 AM UTC 24	Aug 25 01:02:41 AM UTC 24	119144496123 ps
T879	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.4221686842	Aug 25 12:58:46 AM UTC 24	Aug 25 01:02:50 AM UTC 24	26900443783 ps
T880	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.365621184	Aug 25 12:58:44 AM UTC 24	Aug 25 01:02:58 AM UTC 24	44537976232 ps
T881	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.3338019923	Aug 25 12:57:47 AM UTC 24	Aug 25 01:03:01 AM UTC 24	36080315067 ps
T203	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.1341392277	Aug 25 01:00:14 AM UTC 24	Aug 25 01:03:35 AM UTC 24	30902214640 ps
T882	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.2519399376	Aug 25 12:58:56 AM UTC 24	Aug 25 01:03:38 AM UTC 24	32788960007 ps
T883	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.1008680300	Aug 25 12:57:59 AM UTC 24	Aug 25 01:03:43 AM UTC 24	110638291074 ps
T884	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.634411625	Aug 25 12:58:10 AM UTC 24	Aug 25 01:03:43 AM UTC 24	68043847671 ps
T263	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.737469591	Aug 25 12:59:49 AM UTC 24	Aug 25 01:03:45 AM UTC 24	86324763259 ps
T885	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.636486328	Aug 25 01:00:20 AM UTC 24	Aug 25 01:03:51 AM UTC 24	6376153189 ps
T886	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.2599925626	Aug 25 12:59:30 AM UTC 24	Aug 25 01:03:56 AM UTC 24	84077974077 ps
T887	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.860712930	Aug 25 12:58:56 AM UTC 24	Aug 25 01:04:08 AM UTC 24	161607059121 ps
T141	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.760753565	Aug 25 12:54:48 AM UTC 24	Aug 25 01:04:23 AM UTC 24	67137819654 ps
T888	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.2608679237	Aug 25 12:57:50 AM UTC 24	Aug 25 01:04:35 AM UTC 24	30218919248 ps
T889	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.1152132014	Aug 25 12:59:48 AM UTC 24	Aug 25 01:04:45 AM UTC 24	38045162483 ps
T890	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.744677768	Aug 25 01:00:15 AM UTC 24	Aug 25 01:04:45 AM UTC 24	34477823524 ps
T891	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.4255396203	Aug 25 12:55:58 AM UTC 24	Aug 25 01:04:58 AM UTC 24	189183897585 ps
T892	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.3915587892	Aug 25 12:56:47 AM UTC 24	Aug 25 01:05:13 AM UTC 24	41792857051 ps
T142	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.1642794951	Aug 25 12:55:24 AM UTC 24	Aug 25 01:05:37 AM UTC 24	306924493462 ps
T893	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2990739989	Aug 25 12:56:56 AM UTC 24	Aug 25 01:05:38 AM UTC 24	72028041753 ps
T894	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.383585286	Aug 25 12:57:27 AM UTC 24	Aug 25 01:05:38 AM UTC 24	46640347109 ps
T143	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2676506206	Aug 25 01:00:00 AM UTC 24	Aug 25 01:05:57 AM UTC 24	29945689192 ps
T154	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2877088801	Aug 25 12:56:08 AM UTC 24	Aug 25 01:05:59 AM UTC 24	49150536559 ps
T895	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1617399150	Aug 25 12:58:00 AM UTC 24	Aug 25 01:06:25 AM UTC 24	117270931432 ps
T896	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.367987875	Aug 25 12:58:22 AM UTC 24	Aug 25 01:06:35 AM UTC 24	59991183003 ps
T897	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.3346619958	Aug 25 12:58:32 AM UTC 24	Aug 25 01:07:28 AM UTC 24	339769985362 ps
T144	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.3956933963	Aug 25 12:57:16 AM UTC 24	Aug 25 01:07:30 AM UTC 24	57778660352 ps
T898	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3641796346	Aug 25 12:58:11 AM UTC 24	Aug 25 01:07:43 AM UTC 24	47838415212 ps
T899	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2922851097	Aug 25 01:00:15 AM UTC 24	Aug 25 01:10:56 AM UTC 24	230137990610 ps
T900	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.3105995602	Aug 25 12:59:33 AM UTC 24	Aug 25 01:10:56 AM UTC 24	60578744952 ps

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random.3790622922
Short name	T3
Test name
Test status
Simulation time	393574520 ps
CPU time	3.44 seconds
Started	Aug 25 12:51:57 AM UTC 24
Finished	Aug 25 12:52:01 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790622922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3790622922
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/0.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.702661352
Short name	T232
Test name
Test status
Simulation time	69808169900 ps
CPU time	534.02 seconds
Started	Aug 25 12:52:19 AM UTC 24
Finished	Aug 25 01:01:31 AM UTC 24
Peak memory	220236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702661352 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.702661352
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/4.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.1657619293
Short name	T237
Test name
Test status
Simulation time	168885903290 ps
CPU time	328.22 seconds
Started	Aug 25 12:52:27 AM UTC 24
Finished	Aug 25 12:58:01 AM UTC 24
Peak memory	214312 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657619293 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.1657619293
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/5.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.166022730
Short name	T151
Test name
Test status
Simulation time	96149482209 ps
CPU time	207.65 seconds
Started	Aug 25 12:52:02 AM UTC 24
Finished	Aug 25 12:55:33 AM UTC 24
Peak memory	214240 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166022730 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.166022730
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/0.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.2012690919
Short name	T243
Test name
Test status
Simulation time	46050658754 ps
CPU time	452.35 seconds
Started	Aug 25 12:52:58 AM UTC 24
Finished	Aug 25 01:00:38 AM UTC 24
Peak memory	216016 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012690919 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.2012690919
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/10.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.1154482591
Short name	T216
Test name
Test status
Simulation time	283720043 ps
CPU time	24.98 seconds
Started	Aug 25 12:52:03 AM UTC 24
Finished	Aug 25 12:52:30 AM UTC 24
Peak memory	214172 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154482591 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.1154482591
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/0.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_unmapped_addr.3302571665
Short name	T29
Test name
Test status
Simulation time	2078418001 ps
CPU time	7.18 seconds
Started	Aug 25 12:52:05 AM UTC 24
Finished	Aug 25 12:52:13 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302571665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3302571665
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/1.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all.3712157531
Short name	T63
Test name
Test status
Simulation time	3482149190 ps
CPU time	36.76 seconds
Started	Aug 25 12:52:06 AM UTC 24
Finished	Aug 25 12:52:44 AM UTC 24
Peak memory	214500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712157531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.3712157531
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/1.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all.2255573798
Short name	T136
Test name
Test status
Simulation time	2931857814 ps
CPU time	48.84 seconds
Started	Aug 25 12:55:48 AM UTC 24
Finished	Aug 25 12:56:39 AM UTC 24
Peak memory	214240 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255573798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2255573798
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/26.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2990739989
Short name	T893
Test name
Test status
Simulation time	72028041753 ps
CPU time	514.37 seconds
Started	Aug 25 12:56:56 AM UTC 24
Finished	Aug 25 01:05:38 AM UTC 24
Peak memory	216028 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990739989 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.2990739989
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/33.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_zero_delays.432177837
Short name	T17
Test name
Test status
Simulation time	36106701 ps
CPU time	3.6 seconds
Started	Aug 25 12:52:02 AM UTC 24
Finished	Aug 25 12:52:07 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432177837 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.432177837
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/0.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all.3413802777
Short name	T65
Test name
Test status
Simulation time	811123233 ps
CPU time	14.86 seconds
Started	Aug 25 12:52:37 AM UTC 24
Finished	Aug 25 12:52:54 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413802777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.3413802777
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/7.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.606262103
Short name	T158
Test name
Test status
Simulation time	64799822124 ps
CPU time	331.02 seconds
Started	Aug 25 12:54:35 AM UTC 24
Finished	Aug 25 01:00:11 AM UTC 24
Peak memory	214248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606262103 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.606262103
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/20.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_large_delays.3724448660
Short name	T298
Test name
Test status
Simulation time	9945118168 ps
CPU time	8.3 seconds
Started	Aug 25 12:52:07 AM UTC 24
Finished	Aug 25 12:52:27 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724448660 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3724448660
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/2.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all.694447100
Short name	T111
Test name
Test status
Simulation time	52686561081 ps
CPU time	156.52 seconds
Started	Aug 25 12:52:12 AM UTC 24
Finished	Aug 25 12:55:09 AM UTC 24
Peak memory	213992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694447100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.694447100
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/3.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.2124406600
Short name	T13
Test name
Test status
Simulation time	449025914 ps
CPU time	33.14 seconds
Started	Aug 25 12:52:23 AM UTC 24
Finished	Aug 25 12:52:59 AM UTC 24
Peak memory	214172 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124406600 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.2124406600
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/4.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.2120266742
Short name	T10
Test name
Test status
Simulation time	10484523449 ps
CPU time	114.79 seconds
Started	Aug 25 12:55:40 AM UTC 24
Finished	Aug 25 12:57:37 AM UTC 24
Peak memory	216284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120266742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.2120266742
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/25.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_error.1991545665
Short name	T220
Test name
Test status
Simulation time	32597865880 ps
CPU time	85.84 seconds
Started	Aug 25 12:52:03 AM UTC 24
Finished	Aug 25 12:53:31 AM UTC 24
Peak memory	214244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991545665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1991545665
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/0.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.741988185
Short name	T14
Test name
Test status
Simulation time	1016974943 ps
CPU time	187.28 seconds
Started	Aug 25 12:52:22 AM UTC 24
Finished	Aug 25 12:55:40 AM UTC 24
Peak memory	215932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741988185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.741988185
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/4.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.2591765264
Short name	T15
Test name
Test status
Simulation time	6100920685 ps
CPU time	274.86 seconds
Started	Aug 25 12:53:27 AM UTC 24
Finished	Aug 25 12:58:06 AM UTC 24
Peak memory	216360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591765264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.2591765264
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/14.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.3339932692
Short name	T12
Test name
Test status
Simulation time	819995879 ps
CPU time	145.91 seconds
Started	Aug 25 12:54:43 AM UTC 24
Finished	Aug 25 12:57:12 AM UTC 24
Peak memory	214368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339932692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.3339932692
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/20.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.4254155351
Short name	T8
Test name
Test status
Simulation time	252200153 ps
CPU time	46.38 seconds
Started	Aug 25 12:59:03 AM UTC 24
Finished	Aug 25 12:59:51 AM UTC 24
Peak memory	214180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254155351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.4254155351
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/44.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device.1097848650
Short name	T36
Test name
Test status
Simulation time	648079804 ps
CPU time	21.41 seconds
Started	Aug 25 12:54:09 AM UTC 24
Finished	Aug 25 12:54:32 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097848650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.1097848650
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/18.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random.634623988
Short name	T62
Test name
Test status
Simulation time	915989500 ps
CPU time	13.72 seconds
Started	Aug 25 12:52:24 AM UTC 24
Finished	Aug 25 12:52:39 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634623988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.634623988
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/5.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.2213499460
Short name	T280
Test name
Test status
Simulation time	424195681 ps
CPU time	47.83 seconds
Started	Aug 25 12:52:13 AM UTC 24
Finished	Aug 25 12:53:14 AM UTC 24
Peak memory	214376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213499460 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.2213499460
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/3.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all.3149699219
Short name	T127
Test name
Test status
Simulation time	5328961773 ps
CPU time	54.69 seconds
Started	Aug 25 12:52:52 AM UTC 24
Finished	Aug 25 12:53:56 AM UTC 24
Peak memory	214240 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149699219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3149699219
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/9.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.760753565
Short name	T141
Test name
Test status
Simulation time	67137819654 ps
CPU time	567.64 seconds
Started	Aug 25 12:54:48 AM UTC 24
Finished	Aug 25 01:04:23 AM UTC 24
Peak memory	218012 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760753565 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.760753565
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/21.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3813897783
Short name	T247
Test name
Test status
Simulation time	13059531368 ps
CPU time	108.14 seconds
Started	Aug 25 12:53:14 AM UTC 24
Finished	Aug 25 12:55:05 AM UTC 24
Peak memory	216284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813897783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.3813897783
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/12.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.2214810737
Short name	T224
Test name
Test status
Simulation time	38079360975 ps
CPU time	321.39 seconds
Started	Aug 25 12:53:04 AM UTC 24
Finished	Aug 25 12:58:30 AM UTC 24
Peak memory	214440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214810737 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.2214810737
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/11.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.3292344215
Short name	T261
Test name
Test status
Simulation time	3351414278 ps
CPU time	172.21 seconds
Started	Aug 25 12:53:08 AM UTC 24
Finished	Aug 25 12:56:03 AM UTC 24
Peak memory	218332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292344215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.3292344215
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/11.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_error_random.84348684
Short name	T188
Test name
Test status
Simulation time	1252372978 ps
CPU time	15.59 seconds
Started	Aug 25 12:52:44 AM UTC 24
Finished	Aug 25 12:53:01 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84348684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.84348684
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/8.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_same_source.3253087000
Short name	T31
Test name
Test status
Simulation time	1647249658 ps
CPU time	9.07 seconds
Started	Aug 25 12:52:04 AM UTC 24
Finished	Aug 25 12:52:14 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253087000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.3253087000
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/1.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.703850234
Short name	T7
Test name
Test status
Simulation time	4198721110 ps
CPU time	200.88 seconds
Started	Aug 25 12:52:07 AM UTC 24
Finished	Aug 25 12:55:31 AM UTC 24
Peak memory	216484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703850234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.703850234
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/1.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke.3278248227
Short name	T80
Test name
Test status
Simulation time	488117396 ps
CPU time	2.88 seconds
Started	Aug 25 12:52:53 AM UTC 24
Finished	Aug 25 12:53:05 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278248227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3278248227
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/10.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device.3248689032
Short name	T22
Test name
Test status
Simulation time	23468523 ps
CPU time	2.44 seconds
Started	Aug 25 12:52:02 AM UTC 24
Finished	Aug 25 12:52:06 AM UTC 24
Peak memory	212048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248689032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.3248689032
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/0.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.461733805
Short name	T18
Test name
Test status
Simulation time	262637304 ps
CPU time	3.19 seconds
Started	Aug 25 12:52:03 AM UTC 24
Finished	Aug 25 12:52:08 AM UTC 24
Peak memory	212136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461733805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.461733805
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/0.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_error_random.3986764309
Short name	T16
Test name
Test status
Simulation time	94183983 ps
CPU time	2.51 seconds
Started	Aug 25 12:52:02 AM UTC 24
Finished	Aug 25 12:52:06 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986764309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.3986764309
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/0.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_large_delays.1826640567
Short name	T109
Test name
Test status
Simulation time	21081269761 ps
CPU time	63.24 seconds
Started	Aug 25 12:52:02 AM UTC 24
Finished	Aug 25 12:53:07 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826640567 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1826640567
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/0.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_slow_rsp.2795050492
Short name	T170
Test name
Test status
Simulation time	25831421023 ps
CPU time	114.82 seconds
Started	Aug 25 12:52:02 AM UTC 24
Finished	Aug 25 12:53:59 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795050492 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.2795050492
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/0.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_same_source.414937756
Short name	T33
Test name
Test status
Simulation time	1241205086 ps
CPU time	11.7 seconds
Started	Aug 25 12:52:02 AM UTC 24
Finished	Aug 25 12:52:15 AM UTC 24
Peak memory	212016 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414937756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.414937756
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/0.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke.4061122870
Short name	T2
Test name
Test status
Simulation time	83440446 ps
CPU time	1.26 seconds
Started	Aug 25 12:51:53 AM UTC 24
Finished	Aug 25 12:51:55 AM UTC 24
Peak memory	211244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061122870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.4061122870
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/0.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_large_delays.3264077778
Short name	T24
Test name
Test status
Simulation time	8449218730 ps
CPU time	9.35 seconds
Started	Aug 25 12:51:56 AM UTC 24
Finished	Aug 25 12:52:06 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264077778 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.3264077778
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/0.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.1796684368
Short name	T4
Test name
Test status
Simulation time	870564116 ps
CPU time	5.24 seconds
Started	Aug 25 12:51:56 AM UTC 24
Finished	Aug 25 12:52:02 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796684368 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1796684368
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/0.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.2333997854
Short name	T1
Test name
Test status
Simulation time	8419469 ps
CPU time	0.96 seconds
Started	Aug 25 12:51:53 AM UTC 24
Finished	Aug 25 12:51:55 AM UTC 24
Peak memory	211668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333997854 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.2333997854
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/0.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all.3914464512
Short name	T30
Test name
Test status
Simulation time	467754415 ps
CPU time	9.01 seconds
Started	Aug 25 12:52:03 AM UTC 24
Finished	Aug 25 12:52:14 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914464512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3914464512
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/0.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1259987391
Short name	T284
Test name
Test status
Simulation time	1165453309 ps
CPU time	177.94 seconds
Started	Aug 25 12:52:03 AM UTC 24
Finished	Aug 25 12:55:04 AM UTC 24
Peak memory	216232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259987391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.1259987391
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/0.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_unmapped_addr.3195024733
Short name	T19
Test name
Test status
Simulation time	656974547 ps
CPU time	6.23 seconds
Started	Aug 25 12:52:02 AM UTC 24
Finished	Aug 25 12:52:10 AM UTC 24
Peak memory	212260 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195024733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3195024733
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/0.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device.2686521225
Short name	T28
Test name
Test status
Simulation time	79658518 ps
CPU time	6.46 seconds
Started	Aug 25 12:52:04 AM UTC 24
Finished	Aug 25 12:52:11 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686521225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.2686521225
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/1.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.2894372177
Short name	T239
Test name
Test status
Simulation time	174014514984 ps
CPU time	585.02 seconds
Started	Aug 25 12:52:04 AM UTC 24
Finished	Aug 25 01:01:56 AM UTC 24
Peak memory	217940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894372177 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.2894372177
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/1.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.3403264219
Short name	T20
Test name
Test status
Simulation time	1188246061 ps
CPU time	4.48 seconds
Started	Aug 25 12:52:05 AM UTC 24
Finished	Aug 25 12:52:10 AM UTC 24
Peak memory	212328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403264219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.3403264219
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/1.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_error_random.4275560212
Short name	T49
Test name
Test status
Simulation time	1273011584 ps
CPU time	6.15 seconds
Started	Aug 25 12:52:05 AM UTC 24
Finished	Aug 25 12:52:12 AM UTC 24
Peak memory	212384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275560212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.4275560212
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/1.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random.3458852646
Short name	T32
Test name
Test status
Simulation time	1286430409 ps
CPU time	9.5 seconds
Started	Aug 25 12:52:04 AM UTC 24
Finished	Aug 25 12:52:14 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458852646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.3458852646
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/1.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_large_delays.3287186633
Short name	T483
Test name
Test status
Simulation time	49881186210 ps
CPU time	216.51 seconds
Started	Aug 25 12:52:04 AM UTC 24
Finished	Aug 25 12:55:44 AM UTC 24
Peak memory	212256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287186633 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3287186633
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/1.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_slow_rsp.27397164
Short name	T58
Test name
Test status
Simulation time	2261218576 ps
CPU time	13.57 seconds
Started	Aug 25 12:52:04 AM UTC 24
Finished	Aug 25 12:52:18 AM UTC 24
Peak memory	212188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27397164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.27397164
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/1.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_zero_delays.667798058
Short name	T27
Test name
Test status
Simulation time	189974930 ps
CPU time	5.33 seconds
Started	Aug 25 12:52:04 AM UTC 24
Finished	Aug 25 12:52:10 AM UTC 24
Peak memory	212260 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667798058 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.667798058
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/1.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke.3523629757
Short name	T23
Test name
Test status
Simulation time	36329437 ps
CPU time	1.29 seconds
Started	Aug 25 12:52:03 AM UTC 24
Finished	Aug 25 12:52:06 AM UTC 24
Peak memory	211136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523629757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3523629757
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/1.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_large_delays.347766012
Short name	T57
Test name
Test status
Simulation time	2977562744 ps
CPU time	10.9 seconds
Started	Aug 25 12:52:03 AM UTC 24
Finished	Aug 25 12:52:16 AM UTC 24
Peak memory	212172 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347766012 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.347766012
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/1.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.3573325590
Short name	T25
Test name
Test status
Simulation time	785434615 ps
CPU time	4.82 seconds
Started	Aug 25 12:52:04 AM UTC 24
Finished	Aug 25 12:52:09 AM UTC 24
Peak memory	212380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573325590 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3573325590
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/1.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.639714473
Short name	T21
Test name
Test status
Simulation time	9305250 ps
CPU time	1.03 seconds
Started	Aug 25 12:52:03 AM UTC 24
Finished	Aug 25 12:52:06 AM UTC 24
Peak memory	211104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639714473 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.639714473
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/1.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_error.2847634232
Short name	T120
Test name
Test status
Simulation time	4967950301 ps
CPU time	71.47 seconds
Started	Aug 25 12:52:07 AM UTC 24
Finished	Aug 25 12:53:20 AM UTC 24
Peak memory	214248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847634232 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.2847634232
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/1.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.1509154888
Short name	T215
Test name
Test status
Simulation time	509772604 ps
CPU time	15.22 seconds
Started	Aug 25 12:52:07 AM UTC 24
Finished	Aug 25 12:52:23 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509154888 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.1509154888
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/1.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device.1223095455
Short name	T252
Test name
Test status
Simulation time	505558012 ps
CPU time	9.59 seconds
Started	Aug 25 12:52:58 AM UTC 24
Finished	Aug 25 12:53:10 AM UTC 24
Peak memory	212324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223095455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.1223095455
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/10.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.3512285283
Short name	T102
Test name
Test status
Simulation time	14178913 ps
CPU time	1.97 seconds
Started	Aug 25 12:52:59 AM UTC 24
Finished	Aug 25 12:53:03 AM UTC 24
Peak memory	211132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512285283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.3512285283
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/10.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_error_random.4118253808
Short name	T334
Test name
Test status
Simulation time	608951892 ps
CPU time	8.68 seconds
Started	Aug 25 12:52:58 AM UTC 24
Finished	Aug 25 12:53:09 AM UTC 24
Peak memory	212448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118253808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.4118253808
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/10.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random.435980696
Short name	T328
Test name
Test status
Simulation time	349303014 ps
CPU time	9.15 seconds
Started	Aug 25 12:52:54 AM UTC 24
Finished	Aug 25 12:53:08 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435980696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.435980696
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/10.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_large_delays.2103049749
Short name	T481
Test name
Test status
Simulation time	20694983045 ps
CPU time	161.11 seconds
Started	Aug 25 12:52:55 AM UTC 24
Finished	Aug 25 12:55:43 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103049749 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2103049749
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/10.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_slow_rsp.904708093
Short name	T176
Test name
Test status
Simulation time	25082614842 ps
CPU time	90.47 seconds
Started	Aug 25 12:52:56 AM UTC 24
Finished	Aug 25 12:54:33 AM UTC 24
Peak memory	212388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904708093 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.904708093
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/10.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_zero_delays.3393504946
Short name	T108
Test name
Test status
Simulation time	49088882 ps
CPU time	6.82 seconds
Started	Aug 25 12:52:55 AM UTC 24
Finished	Aug 25 12:53:07 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393504946 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3393504946
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/10.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_same_source.2133167971
Short name	T332
Test name
Test status
Simulation time	82995283 ps
CPU time	8.14 seconds
Started	Aug 25 12:52:58 AM UTC 24
Finished	Aug 25 12:53:09 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133167971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2133167971
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/10.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_large_delays.4251877622
Short name	T335
Test name
Test status
Simulation time	1208747739 ps
CPU time	10.61 seconds
Started	Aug 25 12:52:54 AM UTC 24
Finished	Aug 25 12:53:10 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251877622 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.4251877622
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/10.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.2975088007
Short name	T344
Test name
Test status
Simulation time	1532605668 ps
CPU time	17.25 seconds
Started	Aug 25 12:52:54 AM UTC 24
Finished	Aug 25 12:53:16 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975088007 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.2975088007
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/10.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.2235009901
Short name	T105
Test name
Test status
Simulation time	18262461 ps
CPU time	1.71 seconds
Started	Aug 25 12:52:53 AM UTC 24
Finished	Aug 25 12:53:04 AM UTC 24
Peak memory	211236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235009901 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.2235009901
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/10.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all.1084538801
Short name	T200
Test name
Test status
Simulation time	773284944 ps
CPU time	37.74 seconds
Started	Aug 25 12:52:59 AM UTC 24
Finished	Aug 25 12:53:39 AM UTC 24
Peak memory	214164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084538801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1084538801
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/10.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_error.3642720072
Short name	T199
Test name
Test status
Simulation time	303845447 ps
CPU time	37.23 seconds
Started	Aug 25 12:52:59 AM UTC 24
Finished	Aug 25 12:53:39 AM UTC 24
Peak memory	214184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642720072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.3642720072
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/10.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.2147838246
Short name	T90
Test name
Test status
Simulation time	333476063 ps
CPU time	53.31 seconds
Started	Aug 25 12:52:59 AM UTC 24
Finished	Aug 25 12:53:55 AM UTC 24
Peak memory	214216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147838246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.2147838246
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/10.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.1887703398
Short name	T107
Test name
Test status
Simulation time	77388330 ps
CPU time	5.56 seconds
Started	Aug 25 12:52:59 AM UTC 24
Finished	Aug 25 12:53:06 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887703398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.1887703398
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/10.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_unmapped_addr.1752406986
Short name	T329
Test name
Test status
Simulation time	301615318 ps
CPU time	7.83 seconds
Started	Aug 25 12:52:58 AM UTC 24
Finished	Aug 25 12:53:09 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752406986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1752406986
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/10.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device.4198661130
Short name	T84
Test name
Test status
Simulation time	818575112 ps
CPU time	15.41 seconds
Started	Aug 25 12:53:03 AM UTC 24
Finished	Aug 25 12:53:20 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198661130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.4198661130
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/11.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.4242756852
Short name	T340
Test name
Test status
Simulation time	58906104 ps
CPU time	5.82 seconds
Started	Aug 25 12:53:06 AM UTC 24
Finished	Aug 25 12:53:13 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242756852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.4242756852
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/11.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_error_random.2844084821
Short name	T336
Test name
Test status
Simulation time	281960655 ps
CPU time	5.29 seconds
Started	Aug 25 12:53:04 AM UTC 24
Finished	Aug 25 12:53:11 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844084821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2844084821
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/11.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random.3446451779
Short name	T347
Test name
Test status
Simulation time	877444723 ps
CPU time	15.08 seconds
Started	Aug 25 12:53:01 AM UTC 24
Finished	Aug 25 12:53:17 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446451779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.3446451779
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/11.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_large_delays.1007514699
Short name	T550
Test name
Test status
Simulation time	28028759299 ps
CPU time	214.49 seconds
Started	Aug 25 12:53:02 AM UTC 24
Finished	Aug 25 12:56:40 AM UTC 24
Peak memory	212180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007514699 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1007514699
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/11.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_slow_rsp.2825199254
Short name	T535
Test name
Test status
Simulation time	19023970246 ps
CPU time	206.09 seconds
Started	Aug 25 12:53:02 AM UTC 24
Finished	Aug 25 12:56:32 AM UTC 24
Peak memory	212332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825199254 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.2825199254
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/11.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_zero_delays.144406438
Short name	T330
Test name
Test status
Simulation time	41965164 ps
CPU time	5.66 seconds
Started	Aug 25 12:53:02 AM UTC 24
Finished	Aug 25 12:53:09 AM UTC 24
Peak memory	212384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144406438 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.144406438
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/11.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_same_source.1831446574
Short name	T333
Test name
Test status
Simulation time	149679184 ps
CPU time	3.66 seconds
Started	Aug 25 12:53:04 AM UTC 24
Finished	Aug 25 12:53:09 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831446574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.1831446574
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/11.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke.3900124635
Short name	T103
Test name
Test status
Simulation time	74662664 ps
CPU time	1.85 seconds
Started	Aug 25 12:52:59 AM UTC 24
Finished	Aug 25 12:53:03 AM UTC 24
Peak memory	211132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900124635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.3900124635
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/11.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_large_delays.2222214339
Short name	T348
Test name
Test status
Simulation time	2641900690 ps
CPU time	15.83 seconds
Started	Aug 25 12:53:01 AM UTC 24
Finished	Aug 25 12:53:18 AM UTC 24
Peak memory	212268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222214339 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2222214339
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/11.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.608092758
Short name	T83
Test name
Test status
Simulation time	2234928920 ps
CPU time	11.34 seconds
Started	Aug 25 12:53:01 AM UTC 24
Finished	Aug 25 12:53:14 AM UTC 24
Peak memory	212388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608092758 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.608092758
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/11.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.3970104121
Short name	T104
Test name
Test status
Simulation time	19282078 ps
CPU time	1.78 seconds
Started	Aug 25 12:53:00 AM UTC 24
Finished	Aug 25 12:53:04 AM UTC 24
Peak memory	211132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970104121 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.3970104121
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/11.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all.3695237424
Short name	T355
Test name
Test status
Simulation time	367264356 ps
CPU time	18.56 seconds
Started	Aug 25 12:53:06 AM UTC 24
Finished	Aug 25 12:53:26 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695237424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.3695237424
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/11.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_error.1079576433
Short name	T236
Test name
Test status
Simulation time	4445170758 ps
CPU time	115.56 seconds
Started	Aug 25 12:53:08 AM UTC 24
Finished	Aug 25 12:55:06 AM UTC 24
Peak memory	213928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079576433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1079576433
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/11.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.3573911962
Short name	T274
Test name
Test status
Simulation time	25229193 ps
CPU time	8.25 seconds
Started	Aug 25 12:53:08 AM UTC 24
Finished	Aug 25 12:53:17 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573911962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.3573911962
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/11.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_unmapped_addr.2571888609
Short name	T342
Test name
Test status
Simulation time	378929211 ps
CPU time	7.84 seconds
Started	Aug 25 12:53:05 AM UTC 24
Finished	Aug 25 12:53:14 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571888609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2571888609
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/11.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device.1821203347
Short name	T119
Test name
Test status
Simulation time	54840521 ps
CPU time	8.32 seconds
Started	Aug 25 12:53:10 AM UTC 24
Finished	Aug 25 12:53:20 AM UTC 24
Peak memory	212456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821203347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.1821203347
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/12.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.4037780911
Short name	T202
Test name
Test status
Simulation time	8704610881 ps
CPU time	53.56 seconds
Started	Aug 25 12:53:10 AM UTC 24
Finished	Aug 25 12:54:06 AM UTC 24
Peak memory	212200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037780911 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.4037780911
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/12.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.2054768806
Short name	T349
Test name
Test status
Simulation time	42242297 ps
CPU time	5.67 seconds
Started	Aug 25 12:53:12 AM UTC 24
Finished	Aug 25 12:53:18 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054768806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.2054768806
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/12.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_error_random.3671396945
Short name	T118
Test name
Test status
Simulation time	658762986 ps
CPU time	8.03 seconds
Started	Aug 25 12:53:10 AM UTC 24
Finished	Aug 25 12:53:20 AM UTC 24
Peak memory	212056 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671396945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.3671396945
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/12.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random.3594223889
Short name	T339
Test name
Test status
Simulation time	56366828 ps
CPU time	2.63 seconds
Started	Aug 25 12:53:09 AM UTC 24
Finished	Aug 25 12:53:13 AM UTC 24
Peak memory	212316 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594223889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.3594223889
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/12.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_large_delays.1051307539
Short name	T583
Test name
Test status
Simulation time	100048115444 ps
CPU time	227.33 seconds
Started	Aug 25 12:53:10 AM UTC 24
Finished	Aug 25 12:57:01 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051307539 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1051307539
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/12.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_slow_rsp.883243776
Short name	T604
Test name
Test status
Simulation time	21941794839 ps
CPU time	238.46 seconds
Started	Aug 25 12:53:10 AM UTC 24
Finished	Aug 25 12:57:13 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883243776 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.883243776
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/12.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_zero_delays.2030780461
Short name	T121
Test name
Test status
Simulation time	277880289 ps
CPU time	9.52 seconds
Started	Aug 25 12:53:10 AM UTC 24
Finished	Aug 25 12:53:21 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030780461 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.2030780461
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/12.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_same_source.3686146490
Short name	T341
Test name
Test status
Simulation time	9574889 ps
CPU time	1.77 seconds
Started	Aug 25 12:53:10 AM UTC 24
Finished	Aug 25 12:53:13 AM UTC 24
Peak memory	211240 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686146490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3686146490
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/12.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke.4233837331
Short name	T338
Test name
Test status
Simulation time	10413247 ps
CPU time	1.75 seconds
Started	Aug 25 12:53:09 AM UTC 24
Finished	Aug 25 12:53:12 AM UTC 24
Peak memory	211004 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233837331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.4233837331
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/12.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_large_delays.694457222
Short name	T352
Test name
Test status
Simulation time	5849347019 ps
CPU time	13.5 seconds
Started	Aug 25 12:53:09 AM UTC 24
Finished	Aug 25 12:53:24 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694457222 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.694457222
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/12.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.4061167935
Short name	T358
Test name
Test status
Simulation time	13337610258 ps
CPU time	17.92 seconds
Started	Aug 25 12:53:09 AM UTC 24
Finished	Aug 25 12:53:28 AM UTC 24
Peak memory	212388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061167935 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.4061167935
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/12.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.2114164457
Short name	T337
Test name
Test status
Simulation time	13631879 ps
CPU time	1.62 seconds
Started	Aug 25 12:53:09 AM UTC 24
Finished	Aug 25 12:53:12 AM UTC 24
Peak memory	211176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114164457 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.2114164457
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/12.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all.1379039458
Short name	T403
Test name
Test status
Simulation time	477773121 ps
CPU time	64.12 seconds
Started	Aug 25 12:53:13 AM UTC 24
Finished	Aug 25 12:54:19 AM UTC 24
Peak memory	214180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379039458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1379039458
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/12.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3470047319
Short name	T386
Test name
Test status
Simulation time	1789221408 ps
CPU time	49.62 seconds
Started	Aug 25 12:53:13 AM UTC 24
Finished	Aug 25 12:54:04 AM UTC 24
Peak memory	212324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470047319 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3470047319
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/12.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.505953268
Short name	T288
Test name
Test status
Simulation time	567398150 ps
CPU time	160.37 seconds
Started	Aug 25 12:53:13 AM UTC 24
Finished	Aug 25 12:55:57 AM UTC 24
Peak memory	216232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505953268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.505953268
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/12.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_unmapped_addr.654322883
Short name	T350
Test name
Test status
Simulation time	57648542 ps
CPU time	7.47 seconds
Started	Aug 25 12:53:11 AM UTC 24
Finished	Aug 25 12:53:19 AM UTC 24
Peak memory	212300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654322883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.654322883
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/12.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device.1470505427
Short name	T85
Test name
Test status
Simulation time	748153973 ps
CPU time	15.23 seconds
Started	Aug 25 12:53:18 AM UTC 24
Finished	Aug 25 12:53:34 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470505427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.1470505427
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/13.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.1597811077
Short name	T253
Test name
Test status
Simulation time	5975136131 ps
CPU time	34.15 seconds
Started	Aug 25 12:53:18 AM UTC 24
Finished	Aug 25 12:53:54 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597811077 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.1597811077
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/13.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.1749694958
Short name	T123
Test name
Test status
Simulation time	16331201 ps
CPU time	2.23 seconds
Started	Aug 25 12:53:19 AM UTC 24
Finished	Aug 25 12:53:23 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749694958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.1749694958
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/13.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_error_random.1766784342
Short name	T366
Test name
Test status
Simulation time	2536013351 ps
CPU time	13.84 seconds
Started	Aug 25 12:53:18 AM UTC 24
Finished	Aug 25 12:53:33 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766784342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.1766784342
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/13.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random.755844845
Short name	T356
Test name
Test status
Simulation time	90417215 ps
CPU time	9.51 seconds
Started	Aug 25 12:53:15 AM UTC 24
Finished	Aug 25 12:53:26 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755844845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.755844845
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/13.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_large_delays.2713513506
Short name	T180
Test name
Test status
Simulation time	14934893510 ps
CPU time	76.58 seconds
Started	Aug 25 12:53:17 AM UTC 24
Finished	Aug 25 12:54:35 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713513506 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2713513506
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/13.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_slow_rsp.616166961
Short name	T477
Test name
Test status
Simulation time	55527302859 ps
CPU time	138.16 seconds
Started	Aug 25 12:53:18 AM UTC 24
Finished	Aug 25 12:55:39 AM UTC 24
Peak memory	212388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616166961 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.616166961
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/13.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_zero_delays.3795692465
Short name	T354
Test name
Test status
Simulation time	53654525 ps
CPU time	8.16 seconds
Started	Aug 25 12:53:15 AM UTC 24
Finished	Aug 25 12:53:25 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795692465 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.3795692465
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/13.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_same_source.4129905760
Short name	T122
Test name
Test status
Simulation time	18868841 ps
CPU time	1.94 seconds
Started	Aug 25 12:53:18 AM UTC 24
Finished	Aug 25 12:53:21 AM UTC 24
Peak memory	210932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129905760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.4129905760
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/13.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke.4240814825
Short name	T346
Test name
Test status
Simulation time	18466280 ps
CPU time	1.93 seconds
Started	Aug 25 12:53:14 AM UTC 24
Finished	Aug 25 12:53:17 AM UTC 24
Peak memory	211072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240814825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.4240814825
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/13.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_large_delays.841924349
Short name	T363
Test name
Test status
Simulation time	3050213689 ps
CPU time	16.23 seconds
Started	Aug 25 12:53:14 AM UTC 24
Finished	Aug 25 12:53:32 AM UTC 24
Peak memory	212448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841924349 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.841924349
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/13.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.3226741021
Short name	T360
Test name
Test status
Simulation time	1537319682 ps
CPU time	13.59 seconds
Started	Aug 25 12:53:15 AM UTC 24
Finished	Aug 25 12:53:30 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226741021 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.3226741021
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/13.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.4197306515
Short name	T345
Test name
Test status
Simulation time	9406713 ps
CPU time	1.84 seconds
Started	Aug 25 12:53:14 AM UTC 24
Finished	Aug 25 12:53:17 AM UTC 24
Peak memory	211072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197306515 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.4197306515
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/13.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all.1500325367
Short name	T267
Test name
Test status
Simulation time	5703004341 ps
CPU time	81.89 seconds
Started	Aug 25 12:53:19 AM UTC 24
Finished	Aug 25 12:54:43 AM UTC 24
Peak memory	214240 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500325367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1500325367
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/13.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_error.1730503444
Short name	T362
Test name
Test status
Simulation time	83149646 ps
CPU time	9.01 seconds
Started	Aug 25 12:53:21 AM UTC 24
Finished	Aug 25 12:53:31 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730503444 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.1730503444
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/13.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.2163510349
Short name	T281
Test name
Test status
Simulation time	368276945 ps
CPU time	40.73 seconds
Started	Aug 25 12:53:19 AM UTC 24
Finished	Aug 25 12:54:02 AM UTC 24
Peak memory	214312 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163510349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.2163510349
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/13.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.1559735739
Short name	T268
Test name
Test status
Simulation time	1019409076 ps
CPU time	153.02 seconds
Started	Aug 25 12:53:21 AM UTC 24
Finished	Aug 25 12:55:57 AM UTC 24
Peak memory	218336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559735739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.1559735739
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/13.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_unmapped_addr.884119377
Short name	T353
Test name
Test status
Simulation time	175333210 ps
CPU time	4.43 seconds
Started	Aug 25 12:53:19 AM UTC 24
Finished	Aug 25 12:53:25 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884119377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.884119377
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/13.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device.3684290764
Short name	T89
Test name
Test status
Simulation time	1110944991 ps
CPU time	28.69 seconds
Started	Aug 25 12:53:24 AM UTC 24
Finished	Aug 25 12:53:55 AM UTC 24
Peak memory	212136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684290764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.3684290764
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/14.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.972478349
Short name	T238
Test name
Test status
Simulation time	47282401985 ps
CPU time	439.19 seconds
Started	Aug 25 12:53:24 AM UTC 24
Finished	Aug 25 01:00:50 AM UTC 24
Peak memory	214444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972478349 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.972478349
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/14.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.684323358
Short name	T364
Test name
Test status
Simulation time	503586763 ps
CPU time	5.11 seconds
Started	Aug 25 12:53:26 AM UTC 24
Finished	Aug 25 12:53:32 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684323358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.684323358
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/14.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_error_random.1816267578
Short name	T370
Test name
Test status
Simulation time	2063575021 ps
CPU time	16.32 seconds
Started	Aug 25 12:53:25 AM UTC 24
Finished	Aug 25 12:53:42 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816267578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.1816267578
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/14.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random.2299989205
Short name	T359
Test name
Test status
Simulation time	32543166 ps
CPU time	5.33 seconds
Started	Aug 25 12:53:22 AM UTC 24
Finished	Aug 25 12:53:28 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299989205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.2299989205
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/14.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_large_delays.2005755052
Short name	T651
Test name
Test status
Simulation time	36836350728 ps
CPU time	260.03 seconds
Started	Aug 25 12:53:22 AM UTC 24
Finished	Aug 25 12:57:46 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005755052 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.2005755052
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/14.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_slow_rsp.4187382784
Short name	T153
Test name
Test status
Simulation time	28797519388 ps
CPU time	177.86 seconds
Started	Aug 25 12:53:23 AM UTC 24
Finished	Aug 25 12:56:24 AM UTC 24
Peak memory	212200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187382784 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.4187382784
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/14.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_zero_delays.1951690830
Short name	T357
Test name
Test status
Simulation time	55520315 ps
CPU time	4.96 seconds
Started	Aug 25 12:53:22 AM UTC 24
Finished	Aug 25 12:53:28 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951690830 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.1951690830
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/14.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_same_source.2348955122
Short name	T197
Test name
Test status
Simulation time	2574432000 ps
CPU time	10.38 seconds
Started	Aug 25 12:53:24 AM UTC 24
Finished	Aug 25 12:53:36 AM UTC 24
Peak memory	212384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348955122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.2348955122
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/14.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke.911073110
Short name	T206
Test name
Test status
Simulation time	92633105 ps
CPU time	2.25 seconds
Started	Aug 25 12:53:21 AM UTC 24
Finished	Aug 25 12:53:24 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911073110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.911073110
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/14.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_large_delays.3510037617
Short name	T196
Test name
Test status
Simulation time	2012067526 ps
CPU time	13.69 seconds
Started	Aug 25 12:53:21 AM UTC 24
Finished	Aug 25 12:53:36 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510037617 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3510037617
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/14.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.491618626
Short name	T373
Test name
Test status
Simulation time	6956622701 ps
CPU time	21.51 seconds
Started	Aug 25 12:53:21 AM UTC 24
Finished	Aug 25 12:53:44 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491618626 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.491618626
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/14.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.1072002140
Short name	T125
Test name
Test status
Simulation time	14006590 ps
CPU time	2.11 seconds
Started	Aug 25 12:53:21 AM UTC 24
Finished	Aug 25 12:53:24 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072002140 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.1072002140
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/14.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all.1871142454
Short name	T436
Test name
Test status
Simulation time	555793377 ps
CPU time	88.91 seconds
Started	Aug 25 12:53:27 AM UTC 24
Finished	Aug 25 12:54:58 AM UTC 24
Peak memory	214180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871142454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.1871142454
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/14.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_error.4083665803
Short name	T383
Test name
Test status
Simulation time	571540909 ps
CPU time	31.17 seconds
Started	Aug 25 12:53:29 AM UTC 24
Finished	Aug 25 12:54:02 AM UTC 24
Peak memory	214180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083665803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.4083665803
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/14.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.2825737792
Short name	T271
Test name
Test status
Simulation time	624144785 ps
CPU time	89.84 seconds
Started	Aug 25 12:53:29 AM UTC 24
Finished	Aug 25 12:55:01 AM UTC 24
Peak memory	216220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825737792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.2825737792
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/14.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_unmapped_addr.2521697367
Short name	T361
Test name
Test status
Simulation time	59205882 ps
CPU time	3.98 seconds
Started	Aug 25 12:53:26 AM UTC 24
Finished	Aug 25 12:53:31 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521697367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2521697367
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/14.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device.639101493
Short name	T87
Test name
Test status
Simulation time	4484313190 ps
CPU time	19.4 seconds
Started	Aug 25 12:53:34 AM UTC 24
Finished	Aug 25 12:53:54 AM UTC 24
Peak memory	212200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639101493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.639101493
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/15.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.608168352
Short name	T133
Test name
Test status
Simulation time	32115613825 ps
CPU time	172.51 seconds
Started	Aug 25 12:53:35 AM UTC 24
Finished	Aug 25 12:56:30 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608168352 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.608168352
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/15.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.3602882523
Short name	T369
Test name
Test status
Simulation time	199392189 ps
CPU time	4.52 seconds
Started	Aug 25 12:53:36 AM UTC 24
Finished	Aug 25 12:53:42 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602882523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.3602882523
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/15.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_error_random.545881840
Short name	T376
Test name
Test status
Simulation time	88613574 ps
CPU time	9 seconds
Started	Aug 25 12:53:36 AM UTC 24
Finished	Aug 25 12:53:46 AM UTC 24
Peak memory	212388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545881840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.545881840
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/15.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random.2740256615
Short name	T198
Test name
Test status
Simulation time	32959225 ps
CPU time	4.73 seconds
Started	Aug 25 12:53:32 AM UTC 24
Finished	Aug 25 12:53:38 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740256615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2740256615
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/15.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_large_delays.1559745710
Short name	T491
Test name
Test status
Simulation time	78826414264 ps
CPU time	138.44 seconds
Started	Aug 25 12:53:33 AM UTC 24
Finished	Aug 25 12:55:54 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559745710 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1559745710
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/15.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_slow_rsp.834390379
Short name	T182
Test name
Test status
Simulation time	4946408391 ps
CPU time	65.81 seconds
Started	Aug 25 12:53:33 AM UTC 24
Finished	Aug 25 12:54:40 AM UTC 24
Peak memory	212380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834390379 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.834390379
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/15.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_zero_delays.2791601282
Short name	T194
Test name
Test status
Simulation time	11180548 ps
CPU time	1.66 seconds
Started	Aug 25 12:53:32 AM UTC 24
Finished	Aug 25 12:53:35 AM UTC 24
Peak memory	211132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791601282 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.2791601282
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/15.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_same_source.976810767
Short name	T368
Test name
Test status
Simulation time	33056930 ps
CPU time	3.59 seconds
Started	Aug 25 12:53:36 AM UTC 24
Finished	Aug 25 12:53:41 AM UTC 24
Peak memory	212316 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976810767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.976810767
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/15.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke.3648947008
Short name	T365
Test name
Test status
Simulation time	34019637 ps
CPU time	2.03 seconds
Started	Aug 25 12:53:29 AM UTC 24
Finished	Aug 25 12:53:32 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648947008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3648947008
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/15.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_large_delays.2420557488
Short name	T86
Test name
Test status
Simulation time	2241431753 ps
CPU time	19.49 seconds
Started	Aug 25 12:53:31 AM UTC 24
Finished	Aug 25 12:53:52 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420557488 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2420557488
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/15.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.1394017593
Short name	T377
Test name
Test status
Simulation time	1173536015 ps
CPU time	15.59 seconds
Started	Aug 25 12:53:31 AM UTC 24
Finished	Aug 25 12:53:48 AM UTC 24
Peak memory	212324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394017593 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.1394017593
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/15.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.655073766
Short name	T367
Test name
Test status
Simulation time	35757986 ps
CPU time	1.77 seconds
Started	Aug 25 12:53:31 AM UTC 24
Finished	Aug 25 12:53:34 AM UTC 24
Peak memory	211136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655073766 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.655073766
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/15.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all.3533192318
Short name	T394
Test name
Test status
Simulation time	279614973 ps
CPU time	30.81 seconds
Started	Aug 25 12:53:37 AM UTC 24
Finished	Aug 25 12:54:09 AM UTC 24
Peak memory	212324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533192318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3533192318
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/15.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_error.2593933850
Short name	T387
Test name
Test status
Simulation time	183936894 ps
CPU time	24.4 seconds
Started	Aug 25 12:53:39 AM UTC 24
Finished	Aug 25 12:54:05 AM UTC 24
Peak memory	214180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593933850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2593933850
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/15.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.4212996308
Short name	T163
Test name
Test status
Simulation time	3247797856 ps
CPU time	94.67 seconds
Started	Aug 25 12:53:37 AM UTC 24
Finished	Aug 25 12:55:14 AM UTC 24
Peak memory	214440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212996308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.4212996308
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/15.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.2200524911
Short name	T273
Test name
Test status
Simulation time	2339819955 ps
CPU time	68.07 seconds
Started	Aug 25 12:53:39 AM UTC 24
Finished	Aug 25 12:54:49 AM UTC 24
Peak memory	214432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200524911 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.2200524911
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/15.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_unmapped_addr.1088083295
Short name	T380
Test name
Test status
Simulation time	1149344601 ps
CPU time	14.74 seconds
Started	Aug 25 12:53:36 AM UTC 24
Finished	Aug 25 12:53:52 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088083295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1088083295
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/15.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device.3090869445
Short name	T128
Test name
Test status
Simulation time	54030395 ps
CPU time	10.13 seconds
Started	Aug 25 12:53:45 AM UTC 24
Finished	Aug 25 12:53:56 AM UTC 24
Peak memory	212328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090869445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.3090869445
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/16.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.2763208483
Short name	T230
Test name
Test status
Simulation time	27596433102 ps
CPU time	328.26 seconds
Started	Aug 25 12:53:45 AM UTC 24
Finished	Aug 25 12:59:19 AM UTC 24
Peak memory	214568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763208483 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.2763208483
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/16.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.2181333825
Short name	T132
Test name
Test status
Simulation time	93695792 ps
CPU time	7.7 seconds
Started	Aug 25 12:53:50 AM UTC 24
Finished	Aug 25 12:53:58 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181333825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.2181333825
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/16.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_error_random.289675147
Short name	T381
Test name
Test status
Simulation time	38005663 ps
CPU time	2.51 seconds
Started	Aug 25 12:53:48 AM UTC 24
Finished	Aug 25 12:53:52 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289675147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.289675147
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/16.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random.2834519850
Short name	T91
Test name
Test status
Simulation time	368809942 ps
CPU time	11.36 seconds
Started	Aug 25 12:53:43 AM UTC 24
Finished	Aug 25 12:53:55 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834519850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.2834519850
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/16.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_large_delays.1870555004
Short name	T35
Test name
Test status
Simulation time	11953215055 ps
CPU time	38.42 seconds
Started	Aug 25 12:53:44 AM UTC 24
Finished	Aug 25 12:54:24 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870555004 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.1870555004
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/16.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_slow_rsp.1230857239
Short name	T474
Test name
Test status
Simulation time	33130379289 ps
CPU time	109.45 seconds
Started	Aug 25 12:53:45 AM UTC 24
Finished	Aug 25 12:55:37 AM UTC 24
Peak memory	212200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230857239 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1230857239
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/16.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_zero_delays.4111217019
Short name	T378
Test name
Test status
Simulation time	47175778 ps
CPU time	4.03 seconds
Started	Aug 25 12:53:44 AM UTC 24
Finished	Aug 25 12:53:49 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111217019 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.4111217019
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/16.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_same_source.3467563127
Short name	T382
Test name
Test status
Simulation time	41987749 ps
CPU time	4.19 seconds
Started	Aug 25 12:53:47 AM UTC 24
Finished	Aug 25 12:53:53 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467563127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.3467563127
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/16.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke.1493318655
Short name	T374
Test name
Test status
Simulation time	44627291 ps
CPU time	2.36 seconds
Started	Aug 25 12:53:41 AM UTC 24
Finished	Aug 25 12:53:44 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493318655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1493318655
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/16.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_large_delays.3078373757
Short name	T92
Test name
Test status
Simulation time	8802580513 ps
CPU time	22.86 seconds
Started	Aug 25 12:53:42 AM UTC 24
Finished	Aug 25 12:54:06 AM UTC 24
Peak memory	212392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078373757 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3078373757
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/16.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.48090826
Short name	T117
Test name
Test status
Simulation time	4444910632 ps
CPU time	23 seconds
Started	Aug 25 12:53:43 AM UTC 24
Finished	Aug 25 12:54:07 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48090826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.48090826
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/16.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.3915117865
Short name	T372
Test name
Test status
Simulation time	18236965 ps
CPU time	1.85 seconds
Started	Aug 25 12:53:41 AM UTC 24
Finished	Aug 25 12:53:43 AM UTC 24
Peak memory	211132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915117865 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.3915117865
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/16.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all.4069188768
Short name	T388
Test name
Test status
Simulation time	77522838 ps
CPU time	11.95 seconds
Started	Aug 25 12:53:53 AM UTC 24
Finished	Aug 25 12:54:06 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069188768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.4069188768
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/16.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_error.2734878553
Short name	T256
Test name
Test status
Simulation time	13828195670 ps
CPU time	62.92 seconds
Started	Aug 25 12:53:53 AM UTC 24
Finished	Aug 25 12:54:58 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734878553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.2734878553
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/16.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3745455568
Short name	T279
Test name
Test status
Simulation time	483643820 ps
CPU time	103.06 seconds
Started	Aug 25 12:53:53 AM UTC 24
Finished	Aug 25 12:55:38 AM UTC 24
Peak memory	214184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745455568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.3745455568
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/16.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.4011408500
Short name	T282
Test name
Test status
Simulation time	2574169504 ps
CPU time	68.51 seconds
Started	Aug 25 12:53:54 AM UTC 24
Finished	Aug 25 12:55:04 AM UTC 24
Peak memory	214236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011408500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.4011408500
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/16.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_unmapped_addr.1640145901
Short name	T384
Test name
Test status
Simulation time	439996710 ps
CPU time	11.76 seconds
Started	Aug 25 12:53:50 AM UTC 24
Finished	Aug 25 12:54:02 AM UTC 24
Peak memory	212324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640145901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1640145901
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/16.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device.1602052515
Short name	T260
Test name
Test status
Simulation time	295339244 ps
CPU time	7.03 seconds
Started	Aug 25 12:53:59 AM UTC 24
Finished	Aug 25 12:54:07 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602052515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.1602052515
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/17.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.94851423
Short name	T152
Test name
Test status
Simulation time	46891710774 ps
CPU time	96.37 seconds
Started	Aug 25 12:53:59 AM UTC 24
Finished	Aug 25 12:55:37 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94851423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.94851423
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/17.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.1036180718
Short name	T399
Test name
Test status
Simulation time	930609573 ps
CPU time	11.5 seconds
Started	Aug 25 12:54:02 AM UTC 24
Finished	Aug 25 12:54:14 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036180718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.1036180718
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/17.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_error_random.4045558600
Short name	T392
Test name
Test status
Simulation time	69138075 ps
CPU time	8.2 seconds
Started	Aug 25 12:54:00 AM UTC 24
Finished	Aug 25 12:54:09 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045558600 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.4045558600
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/17.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random.2853281537
Short name	T93
Test name
Test status
Simulation time	1277035153 ps
CPU time	22.37 seconds
Started	Aug 25 12:53:56 AM UTC 24
Finished	Aug 25 12:54:20 AM UTC 24
Peak memory	212384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853281537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.2853281537
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/17.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_large_delays.4067249350
Short name	T155
Test name
Test status
Simulation time	47591871804 ps
CPU time	240.91 seconds
Started	Aug 25 12:53:57 AM UTC 24
Finished	Aug 25 12:58:02 AM UTC 24
Peak memory	211720 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067249350 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.4067249350
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/17.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_slow_rsp.4235468989
Short name	T440
Test name
Test status
Simulation time	13620521337 ps
CPU time	65.01 seconds
Started	Aug 25 12:53:57 AM UTC 24
Finished	Aug 25 12:55:04 AM UTC 24
Peak memory	211788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235468989 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.4235468989
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/17.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_zero_delays.986763129
Short name	T385
Test name
Test status
Simulation time	30032625 ps
CPU time	5.95 seconds
Started	Aug 25 12:53:56 AM UTC 24
Finished	Aug 25 12:54:03 AM UTC 24
Peak memory	212448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986763129 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.986763129
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/17.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_same_source.4260828895
Short name	T389
Test name
Test status
Simulation time	229458349 ps
CPU time	5.7 seconds
Started	Aug 25 12:54:00 AM UTC 24
Finished	Aug 25 12:54:06 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260828895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.4260828895
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/17.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke.3708463449
Short name	T131
Test name
Test status
Simulation time	172798246 ps
CPU time	2.37 seconds
Started	Aug 25 12:53:55 AM UTC 24
Finished	Aug 25 12:53:58 AM UTC 24
Peak memory	212448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708463449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3708463449
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/17.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_large_delays.3113921034
Short name	T401
Test name
Test status
Simulation time	2491501457 ps
CPU time	21.5 seconds
Started	Aug 25 12:53:55 AM UTC 24
Finished	Aug 25 12:54:18 AM UTC 24
Peak memory	212200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113921034 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.3113921034
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/17.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.646839074
Short name	T390
Test name
Test status
Simulation time	1735885800 ps
CPU time	9.8 seconds
Started	Aug 25 12:53:56 AM UTC 24
Finished	Aug 25 12:54:07 AM UTC 24
Peak memory	212256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646839074 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.646839074
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/17.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.2028745492
Short name	T130
Test name
Test status
Simulation time	9058092 ps
CPU time	1.66 seconds
Started	Aug 25 12:53:55 AM UTC 24
Finished	Aug 25 12:53:58 AM UTC 24
Peak memory	211132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028745492 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.2028745492
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/17.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all.1331511083
Short name	T408
Test name
Test status
Simulation time	1575637786 ps
CPU time	18.97 seconds
Started	Aug 25 12:54:03 AM UTC 24
Finished	Aug 25 12:54:23 AM UTC 24
Peak memory	212452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331511083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.1331511083
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/17.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_error.2589756676
Short name	T419
Test name
Test status
Simulation time	284631529 ps
CPU time	35.72 seconds
Started	Aug 25 12:54:04 AM UTC 24
Finished	Aug 25 12:54:41 AM UTC 24
Peak memory	212200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589756676 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.2589756676
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/17.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.704947253
Short name	T211
Test name
Test status
Simulation time	482192200 ps
CPU time	78.32 seconds
Started	Aug 25 12:54:03 AM UTC 24
Finished	Aug 25 12:55:23 AM UTC 24
Peak memory	216228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704947253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.704947253
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/17.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.3106345036
Short name	T250
Test name
Test status
Simulation time	6404178407 ps
CPU time	154.83 seconds
Started	Aug 25 12:54:05 AM UTC 24
Finished	Aug 25 12:56:43 AM UTC 24
Peak memory	216480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106345036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.3106345036
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/17.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_unmapped_addr.1356044515
Short name	T400
Test name
Test status
Simulation time	486646565 ps
CPU time	14.22 seconds
Started	Aug 25 12:54:00 AM UTC 24
Finished	Aug 25 12:54:15 AM UTC 24
Peak memory	212324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356044515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.1356044515
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/17.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.3860650879
Short name	T140
Test name
Test status
Simulation time	35658274660 ps
CPU time	431.66 seconds
Started	Aug 25 12:54:10 AM UTC 24
Finished	Aug 25 01:01:28 AM UTC 24
Peak memory	216008 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860650879 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.3860650879
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/18.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.2544657682
Short name	T398
Test name
Test status
Simulation time	26543875 ps
CPU time	2.15 seconds
Started	Aug 25 12:54:11 AM UTC 24
Finished	Aug 25 12:54:14 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544657682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.2544657682
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/18.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_error_random.3264469722
Short name	T414
Test name
Test status
Simulation time	1615361964 ps
CPU time	15.67 seconds
Started	Aug 25 12:54:10 AM UTC 24
Finished	Aug 25 12:54:27 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264469722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3264469722
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/18.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random.1260865383
Short name	T402
Test name
Test status
Simulation time	369681409 ps
CPU time	9.56 seconds
Started	Aug 25 12:54:08 AM UTC 24
Finished	Aug 25 12:54:18 AM UTC 24
Peak memory	211928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260865383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.1260865383
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/18.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_large_delays.959557136
Short name	T407
Test name
Test status
Simulation time	2242109287 ps
CPU time	12.92 seconds
Started	Aug 25 12:54:08 AM UTC 24
Finished	Aug 25 12:54:22 AM UTC 24
Peak memory	212188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959557136 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.959557136
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/18.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_slow_rsp.2388238725
Short name	T476
Test name
Test status
Simulation time	13658560306 ps
CPU time	88.66 seconds
Started	Aug 25 12:54:08 AM UTC 24
Finished	Aug 25 12:55:39 AM UTC 24
Peak memory	212204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388238725 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.2388238725
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/18.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_zero_delays.2658117652
Short name	T395
Test name
Test status
Simulation time	7916132 ps
CPU time	1.69 seconds
Started	Aug 25 12:54:08 AM UTC 24
Finished	Aug 25 12:54:10 AM UTC 24
Peak memory	211136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658117652 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.2658117652
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/18.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_same_source.2825883674
Short name	T406
Test name
Test status
Simulation time	440824011 ps
CPU time	9.77 seconds
Started	Aug 25 12:54:10 AM UTC 24
Finished	Aug 25 12:54:21 AM UTC 24
Peak memory	212256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825883674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2825883674
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/18.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke.1506947139
Short name	T391
Test name
Test status
Simulation time	8681543 ps
CPU time	1.34 seconds
Started	Aug 25 12:54:06 AM UTC 24
Finished	Aug 25 12:54:09 AM UTC 24
Peak memory	211132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506947139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.1506947139
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/18.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_large_delays.2855333760
Short name	T410
Test name
Test status
Simulation time	4738438428 ps
CPU time	16.69 seconds
Started	Aug 25 12:54:06 AM UTC 24
Finished	Aug 25 12:54:24 AM UTC 24
Peak memory	212456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855333760 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.2855333760
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/18.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.351160634
Short name	T417
Test name
Test status
Simulation time	3826434030 ps
CPU time	22.19 seconds
Started	Aug 25 12:54:07 AM UTC 24
Finished	Aug 25 12:54:30 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351160634 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.351160634
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/18.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.3810862096
Short name	T393
Test name
Test status
Simulation time	21778680 ps
CPU time	1.67 seconds
Started	Aug 25 12:54:06 AM UTC 24
Finished	Aug 25 12:54:09 AM UTC 24
Peak memory	211176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810862096 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.3810862096
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/18.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all.1827542057
Short name	T409
Test name
Test status
Simulation time	138232568 ps
CPU time	8.49 seconds
Started	Aug 25 12:54:14 AM UTC 24
Finished	Aug 25 12:54:24 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827542057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.1827542057
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/18.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1949775942
Short name	T262
Test name
Test status
Simulation time	1811954765 ps
CPU time	42.51 seconds
Started	Aug 25 12:54:15 AM UTC 24
Finished	Aug 25 12:54:59 AM UTC 24
Peak memory	212136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949775942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1949775942
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/18.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.3331884728
Short name	T189
Test name
Test status
Simulation time	3200027401 ps
CPU time	124.14 seconds
Started	Aug 25 12:54:14 AM UTC 24
Finished	Aug 25 12:56:21 AM UTC 24
Peak memory	216292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331884728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.3331884728
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/18.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.2006808274
Short name	T552
Test name
Test status
Simulation time	2353901106 ps
CPU time	142.55 seconds
Started	Aug 25 12:54:15 AM UTC 24
Finished	Aug 25 12:56:41 AM UTC 24
Peak memory	216544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006808274 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.2006808274
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/18.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_unmapped_addr.1692804426
Short name	T396
Test name
Test status
Simulation time	23287279 ps
CPU time	2.52 seconds
Started	Aug 25 12:54:10 AM UTC 24
Finished	Aug 25 12:54:14 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692804426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1692804426
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/18.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device.425802766
Short name	T228
Test name
Test status
Simulation time	1695613088 ps
CPU time	26.99 seconds
Started	Aug 25 12:54:22 AM UTC 24
Finished	Aug 25 12:54:51 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425802766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.425802766
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/19.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.3096093372
Short name	T254
Test name
Test status
Simulation time	7789628448 ps
CPU time	89.93 seconds
Started	Aug 25 12:54:22 AM UTC 24
Finished	Aug 25 12:55:55 AM UTC 24
Peak memory	212452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096093372 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.3096093372
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/19.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.8470100
Short name	T416
Test name
Test status
Simulation time	87098006 ps
CPU time	2.71 seconds
Started	Aug 25 12:54:26 AM UTC 24
Finished	Aug 25 12:54:30 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8470100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_ TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.8470100
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/19.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_error_random.191763780
Short name	T415
Test name
Test status
Simulation time	68791620 ps
CPU time	3.84 seconds
Started	Aug 25 12:54:25 AM UTC 24
Finished	Aug 25 12:54:29 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191763780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.191763780
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/19.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random.4239044042
Short name	T412
Test name
Test status
Simulation time	694918050 ps
CPU time	4.33 seconds
Started	Aug 25 12:54:20 AM UTC 24
Finished	Aug 25 12:54:25 AM UTC 24
Peak memory	212316 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239044042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.4239044042
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/19.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_large_delays.3926850856
Short name	T548
Test name
Test status
Simulation time	28409391875 ps
CPU time	135.46 seconds
Started	Aug 25 12:54:21 AM UTC 24
Finished	Aug 25 12:56:39 AM UTC 24
Peak memory	211664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926850856 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.3926850856
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/19.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_slow_rsp.162541263
Short name	T457
Test name
Test status
Simulation time	14691455050 ps
CPU time	60.89 seconds
Started	Aug 25 12:54:21 AM UTC 24
Finished	Aug 25 12:55:24 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162541263 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.162541263
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/19.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_zero_delays.3472912151
Short name	T411
Test name
Test status
Simulation time	44450702 ps
CPU time	3.66 seconds
Started	Aug 25 12:54:20 AM UTC 24
Finished	Aug 25 12:54:25 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472912151 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.3472912151
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/19.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_same_source.2238823323
Short name	T425
Test name
Test status
Simulation time	960311017 ps
CPU time	19.64 seconds
Started	Aug 25 12:54:24 AM UTC 24
Finished	Aug 25 12:54:45 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238823323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.2238823323
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/19.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke.198150657
Short name	T404
Test name
Test status
Simulation time	37553745 ps
CPU time	1.87 seconds
Started	Aug 25 12:54:16 AM UTC 24
Finished	Aug 25 12:54:19 AM UTC 24
Peak memory	211184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198150657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.198150657
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/19.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_large_delays.2326788465
Short name	T418
Test name
Test status
Simulation time	1514842653 ps
CPU time	11.55 seconds
Started	Aug 25 12:54:19 AM UTC 24
Finished	Aug 25 12:54:31 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326788465 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2326788465
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/19.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.966941579
Short name	T174
Test name
Test status
Simulation time	1965890776 ps
CPU time	10.66 seconds
Started	Aug 25 12:54:20 AM UTC 24
Finished	Aug 25 12:54:32 AM UTC 24
Peak memory	212324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966941579 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.966941579
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/19.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.1638130661
Short name	T405
Test name
Test status
Simulation time	9269734 ps
CPU time	1.58 seconds
Started	Aug 25 12:54:18 AM UTC 24
Finished	Aug 25 12:54:20 AM UTC 24
Peak memory	211132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638130661 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.1638130661
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/19.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all.2306571000
Short name	T115
Test name
Test status
Simulation time	4962938592 ps
CPU time	93.31 seconds
Started	Aug 25 12:54:26 AM UTC 24
Finished	Aug 25 12:56:01 AM UTC 24
Peak memory	214564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306571000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2306571000
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/19.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_error.4089481660
Short name	T223
Test name
Test status
Simulation time	5010625701 ps
CPU time	83.39 seconds
Started	Aug 25 12:54:27 AM UTC 24
Finished	Aug 25 12:55:53 AM UTC 24
Peak memory	212392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089481660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.4089481660
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/19.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.4037443054
Short name	T169
Test name
Test status
Simulation time	3650353556 ps
CPU time	165.81 seconds
Started	Aug 25 12:54:26 AM UTC 24
Finished	Aug 25 12:57:15 AM UTC 24
Peak memory	218600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037443054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.4037443054
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/19.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.2544450883
Short name	T283
Test name
Test status
Simulation time	151602606 ps
CPU time	17.77 seconds
Started	Aug 25 12:54:28 AM UTC 24
Finished	Aug 25 12:54:47 AM UTC 24
Peak memory	214368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544450883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.2544450883
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/19.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_unmapped_addr.1580545391
Short name	T181
Test name
Test status
Simulation time	442583659 ps
CPU time	11.7 seconds
Started	Aug 25 12:54:25 AM UTC 24
Finished	Aug 25 12:54:37 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580545391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.1580545391
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/19.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device.481128682
Short name	T210
Test name
Test status
Simulation time	116010917 ps
CPU time	7.25 seconds
Started	Aug 25 12:52:08 AM UTC 24
Finished	Aug 25 12:52:27 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481128682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.481128682
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/2.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.1654457247
Short name	T248
Test name
Test status
Simulation time	47147707444 ps
CPU time	227.05 seconds
Started	Aug 25 12:52:08 AM UTC 24
Finished	Aug 25 12:56:09 AM UTC 24
Peak memory	214248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654457247 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.1654457247
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/2.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.3178311873
Short name	T217
Test name
Test status
Simulation time	490569626 ps
CPU time	2.2 seconds
Started	Aug 25 12:52:08 AM UTC 24
Finished	Aug 25 12:52:22 AM UTC 24
Peak memory	212328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178311873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.3178311873
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/2.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_error_random.2453877127
Short name	T50
Test name
Test status
Simulation time	50967091 ps
CPU time	2.62 seconds
Started	Aug 25 12:52:08 AM UTC 24
Finished	Aug 25 12:52:12 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453877127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2453877127
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/2.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random.1928076280
Short name	T48
Test name
Test status
Simulation time	120651002 ps
CPU time	6.19 seconds
Started	Aug 25 12:52:07 AM UTC 24
Finished	Aug 25 12:52:25 AM UTC 24
Peak memory	211460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928076280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.1928076280
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/2.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_large_delays.3855495804
Short name	T478
Test name
Test status
Simulation time	44708655007 ps
CPU time	198.36 seconds
Started	Aug 25 12:52:08 AM UTC 24
Finished	Aug 25 12:55:40 AM UTC 24
Peak memory	212188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855495804 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3855495804
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/2.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_slow_rsp.3714825664
Short name	T79
Test name
Test status
Simulation time	11061840028 ps
CPU time	52.54 seconds
Started	Aug 25 12:52:08 AM UTC 24
Finished	Aug 25 12:53:02 AM UTC 24
Peak memory	212460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714825664 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.3714825664
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/2.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_zero_delays.2187411753
Short name	T53
Test name
Test status
Simulation time	408530554 ps
CPU time	6.52 seconds
Started	Aug 25 12:52:07 AM UTC 24
Finished	Aug 25 12:52:26 AM UTC 24
Peak memory	211520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187411753 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.2187411753
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/2.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_same_source.2832138957
Short name	T293
Test name
Test status
Simulation time	24570225 ps
CPU time	2.32 seconds
Started	Aug 25 12:52:08 AM UTC 24
Finished	Aug 25 12:52:22 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832138957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.2832138957
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/2.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke.2394517412
Short name	T26
Test name
Test status
Simulation time	95707274 ps
CPU time	1.59 seconds
Started	Aug 25 12:52:07 AM UTC 24
Finished	Aug 25 12:52:10 AM UTC 24
Peak memory	211244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394517412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2394517412
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/2.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.2019357485
Short name	T218
Test name
Test status
Simulation time	4441535675 ps
CPU time	9.14 seconds
Started	Aug 25 12:52:07 AM UTC 24
Finished	Aug 25 12:52:28 AM UTC 24
Peak memory	212384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019357485 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2019357485
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/2.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.4221522656
Short name	T51
Test name
Test status
Simulation time	15780456 ps
CPU time	0.97 seconds
Started	Aug 25 12:52:07 AM UTC 24
Finished	Aug 25 12:52:20 AM UTC 24
Peak memory	211128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221522656 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.4221522656
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/2.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all.176203764
Short name	T291
Test name
Test status
Simulation time	399696606 ps
CPU time	29.85 seconds
Started	Aug 25 12:52:08 AM UTC 24
Finished	Aug 25 12:52:50 AM UTC 24
Peak memory	214176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176203764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.176203764
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/2.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3154603424
Short name	T129
Test name
Test status
Simulation time	8512691166 ps
CPU time	86.52 seconds
Started	Aug 25 12:52:08 AM UTC 24
Finished	Aug 25 12:53:57 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154603424 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3154603424
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/2.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.684054303
Short name	T272
Test name
Test status
Simulation time	531571325 ps
CPU time	49.05 seconds
Started	Aug 25 12:52:08 AM UTC 24
Finished	Aug 25 12:53:19 AM UTC 24
Peak memory	214180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684054303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.684054303
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/2.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.2933755494
Short name	T269
Test name
Test status
Simulation time	91713814 ps
CPU time	4.86 seconds
Started	Aug 25 12:52:08 AM UTC 24
Finished	Aug 25 12:52:35 AM UTC 24
Peak memory	212136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933755494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.2933755494
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/2.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_unmapped_addr.3908942079
Short name	T47
Test name
Test status
Simulation time	689437467 ps
CPU time	3.95 seconds
Started	Aug 25 12:52:08 AM UTC 24
Finished	Aug 25 12:52:23 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908942079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.3908942079
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/2.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device.3825482758
Short name	T227
Test name
Test status
Simulation time	3337172753 ps
CPU time	13.48 seconds
Started	Aug 25 12:54:35 AM UTC 24
Finished	Aug 25 12:54:50 AM UTC 24
Peak memory	212396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825482758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.3825482758
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/20.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.920842780
Short name	T423
Test name
Test status
Simulation time	12284272 ps
CPU time	1.57 seconds
Started	Aug 25 12:54:41 AM UTC 24
Finished	Aug 25 12:54:44 AM UTC 24
Peak memory	211180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920842780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.920842780
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/20.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_error_random.1863177061
Short name	T426
Test name
Test status
Simulation time	922923105 ps
CPU time	9.3 seconds
Started	Aug 25 12:54:36 AM UTC 24
Finished	Aug 25 12:54:47 AM UTC 24
Peak memory	212324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863177061 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.1863177061
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/20.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random.121946241
Short name	T430
Test name
Test status
Simulation time	830208215 ps
CPU time	13.23 seconds
Started	Aug 25 12:54:32 AM UTC 24
Finished	Aug 25 12:54:47 AM UTC 24
Peak memory	212120 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121946241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.121946241
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/20.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_large_delays.3152747279
Short name	T561
Test name
Test status
Simulation time	21961401169 ps
CPU time	130.59 seconds
Started	Aug 25 12:54:34 AM UTC 24
Finished	Aug 25 12:56:47 AM UTC 24
Peak memory	212392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152747279 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.3152747279
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/20.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_slow_rsp.278962847
Short name	T527
Test name
Test status
Simulation time	10537842025 ps
CPU time	105.13 seconds
Started	Aug 25 12:54:34 AM UTC 24
Finished	Aug 25 12:56:21 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278962847 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.278962847
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/20.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_zero_delays.2397763424
Short name	T424
Test name
Test status
Simulation time	66292693 ps
CPU time	11.35 seconds
Started	Aug 25 12:54:32 AM UTC 24
Finished	Aug 25 12:54:45 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397763424 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2397763424
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/20.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_same_source.2202744072
Short name	T422
Test name
Test status
Simulation time	631341444 ps
CPU time	7.46 seconds
Started	Aug 25 12:54:35 AM UTC 24
Finished	Aug 25 12:54:44 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202744072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.2202744072
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/20.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke.3094381662
Short name	T177
Test name
Test status
Simulation time	73784330 ps
CPU time	1.97 seconds
Started	Aug 25 12:54:30 AM UTC 24
Finished	Aug 25 12:54:33 AM UTC 24
Peak memory	211136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094381662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.3094381662
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/20.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_large_delays.311860867
Short name	T159
Test name
Test status
Simulation time	2631040061 ps
CPU time	22.03 seconds
Started	Aug 25 12:54:31 AM UTC 24
Finished	Aug 25 12:54:55 AM UTC 24
Peak memory	212008 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311860867 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.311860867
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/20.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.2649086698
Short name	T420
Test name
Test status
Simulation time	743437128 ps
CPU time	8.5 seconds
Started	Aug 25 12:54:32 AM UTC 24
Finished	Aug 25 12:54:42 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649086698 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2649086698
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/20.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.3849464478
Short name	T178
Test name
Test status
Simulation time	16684488 ps
CPU time	1.3 seconds
Started	Aug 25 12:54:31 AM UTC 24
Finished	Aug 25 12:54:33 AM UTC 24
Peak memory	210848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849464478 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.3849464478
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/20.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all.3861531046
Short name	T451
Test name
Test status
Simulation time	3103451933 ps
CPU time	35.52 seconds
Started	Aug 25 12:54:43 AM UTC 24
Finished	Aug 25 12:55:20 AM UTC 24
Peak memory	212152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861531046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3861531046
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/20.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_error.2666484848
Short name	T450
Test name
Test status
Simulation time	4249438478 ps
CPU time	34.29 seconds
Started	Aug 25 12:54:43 AM UTC 24
Finished	Aug 25 12:55:18 AM UTC 24
Peak memory	212160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666484848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.2666484848
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/20.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.1091921554
Short name	T275
Test name
Test status
Simulation time	395679343 ps
CPU time	59 seconds
Started	Aug 25 12:54:43 AM UTC 24
Finished	Aug 25 12:55:44 AM UTC 24
Peak memory	216228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091921554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.1091921554
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/20.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_unmapped_addr.4223856712
Short name	T421
Test name
Test status
Simulation time	256453615 ps
CPU time	3.68 seconds
Started	Aug 25 12:54:38 AM UTC 24
Finished	Aug 25 12:54:43 AM UTC 24
Peak memory	212324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223856712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.4223856712
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/20.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device.2066432244
Short name	T229
Test name
Test status
Simulation time	457156353 ps
CPU time	9.04 seconds
Started	Aug 25 12:54:47 AM UTC 24
Finished	Aug 25 12:54:58 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066432244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.2066432244
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/21.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.4241377874
Short name	T434
Test name
Test status
Simulation time	457135499 ps
CPU time	4.55 seconds
Started	Aug 25 12:54:50 AM UTC 24
Finished	Aug 25 12:54:56 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241377874 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.4241377874
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/21.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_error_random.2520418141
Short name	T432
Test name
Test status
Simulation time	28784063 ps
CPU time	2.46 seconds
Started	Aug 25 12:54:49 AM UTC 24
Finished	Aug 25 12:54:52 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520418141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2520418141
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/21.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random.4247314206
Short name	T431
Test name
Test status
Simulation time	57860257 ps
CPU time	2.05 seconds
Started	Aug 25 12:54:45 AM UTC 24
Finished	Aug 25 12:54:49 AM UTC 24
Peak memory	212388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247314206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.4247314206
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/21.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_large_delays.1311455201
Short name	T581
Test name
Test status
Simulation time	68287886899 ps
CPU time	129.32 seconds
Started	Aug 25 12:54:46 AM UTC 24
Finished	Aug 25 12:56:58 AM UTC 24
Peak memory	212188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311455201 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.1311455201
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/21.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_slow_rsp.900730831
Short name	T497
Test name
Test status
Simulation time	58883246627 ps
CPU time	73.88 seconds
Started	Aug 25 12:54:47 AM UTC 24
Finished	Aug 25 12:56:03 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900730831 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.900730831
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/21.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_zero_delays.4218772000
Short name	T435
Test name
Test status
Simulation time	130579175 ps
CPU time	8.93 seconds
Started	Aug 25 12:54:46 AM UTC 24
Finished	Aug 25 12:54:57 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218772000 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.4218772000
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/21.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_same_source.1957089363
Short name	T441
Test name
Test status
Simulation time	4885081266 ps
CPU time	14.41 seconds
Started	Aug 25 12:54:49 AM UTC 24
Finished	Aug 25 12:55:04 AM UTC 24
Peak memory	212384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957089363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.1957089363
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/21.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke.3500404828
Short name	T429
Test name
Test status
Simulation time	18762694 ps
CPU time	1.7 seconds
Started	Aug 25 12:54:44 AM UTC 24
Finished	Aug 25 12:54:47 AM UTC 24
Peak memory	211180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500404828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.3500404828
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/21.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_large_delays.2398036742
Short name	T157
Test name
Test status
Simulation time	2109314038 ps
CPU time	15.2 seconds
Started	Aug 25 12:54:45 AM UTC 24
Finished	Aug 25 12:55:02 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398036742 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2398036742
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/21.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2949825383
Short name	T428
Test name
Test status
Simulation time	1748935883 ps
CPU time	18.82 seconds
Started	Aug 25 12:54:45 AM UTC 24
Finished	Aug 25 12:55:05 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949825383 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2949825383
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/21.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.1650768299
Short name	T427
Test name
Test status
Simulation time	8874211 ps
CPU time	1.67 seconds
Started	Aug 25 12:54:44 AM UTC 24
Finished	Aug 25 12:54:47 AM UTC 24
Peak memory	211128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650768299 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.1650768299
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/21.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all.472583474
Short name	T146
Test name
Test status
Simulation time	4508048939 ps
CPU time	96.95 seconds
Started	Aug 25 12:54:51 AM UTC 24
Finished	Aug 25 12:56:30 AM UTC 24
Peak memory	214244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472583474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.472583474
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/21.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_error.449697298
Short name	T466
Test name
Test status
Simulation time	3154051340 ps
CPU time	35.73 seconds
Started	Aug 25 12:54:53 AM UTC 24
Finished	Aug 25 12:55:30 AM UTC 24
Peak memory	212456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449697298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.449697298
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/21.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.3987538870
Short name	T208
Test name
Test status
Simulation time	644019017 ps
CPU time	127.95 seconds
Started	Aug 25 12:54:52 AM UTC 24
Finished	Aug 25 12:57:03 AM UTC 24
Peak memory	216228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987538870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.3987538870
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/21.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.2464663281
Short name	T285
Test name
Test status
Simulation time	795627651 ps
CPU time	116.49 seconds
Started	Aug 25 12:54:55 AM UTC 24
Finished	Aug 25 12:56:54 AM UTC 24
Peak memory	214496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464663281 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.2464663281
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/21.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_unmapped_addr.2494134016
Short name	T433
Test name
Test status
Simulation time	571578461 ps
CPU time	3.61 seconds
Started	Aug 25 12:54:50 AM UTC 24
Finished	Aug 25 12:54:55 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494134016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.2494134016
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/21.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device.3704834716
Short name	T168
Test name
Test status
Simulation time	578000936 ps
CPU time	14.88 seconds
Started	Aug 25 12:55:00 AM UTC 24
Finished	Aug 25 12:55:17 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704834716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.3704834716
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/22.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.1263926621
Short name	T225
Test name
Test status
Simulation time	53053924989 ps
CPU time	313.49 seconds
Started	Aug 25 12:55:00 AM UTC 24
Finished	Aug 25 01:00:19 AM UTC 24
Peak memory	214248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263926621 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.1263926621
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/22.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.545754282
Short name	T453
Test name
Test status
Simulation time	644818276 ps
CPU time	17.29 seconds
Started	Aug 25 12:55:03 AM UTC 24
Finished	Aug 25 12:55:21 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545754282 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.545754282
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/22.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_error_random.3334558593
Short name	T446
Test name
Test status
Simulation time	47513766 ps
CPU time	5.71 seconds
Started	Aug 25 12:55:02 AM UTC 24
Finished	Aug 25 12:55:09 AM UTC 24
Peak memory	212324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334558593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.3334558593
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/22.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random.73788836
Short name	T112
Test name
Test status
Simulation time	505987613 ps
CPU time	11.5 seconds
Started	Aug 25 12:54:59 AM UTC 24
Finished	Aug 25 12:55:12 AM UTC 24
Peak memory	212324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73788836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.73788836
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/22.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_large_delays.3257373032
Short name	T510
Test name
Test status
Simulation time	17414860223 ps
CPU time	69.8 seconds
Started	Aug 25 12:54:59 AM UTC 24
Finished	Aug 25 12:56:11 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257373032 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3257373032
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/22.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_slow_rsp.1605612900
Short name	T148
Test name
Test status
Simulation time	54584459277 ps
CPU time	319.61 seconds
Started	Aug 25 12:54:59 AM UTC 24
Finished	Aug 25 01:00:23 AM UTC 24
Peak memory	212200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605612900 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1605612900
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/22.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_zero_delays.2361991933
Short name	T439
Test name
Test status
Simulation time	31640500 ps
CPU time	2.55 seconds
Started	Aug 25 12:54:59 AM UTC 24
Finished	Aug 25 12:55:03 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361991933 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.2361991933
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/22.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_same_source.4029243857
Short name	T442
Test name
Test status
Simulation time	22617600 ps
CPU time	3.48 seconds
Started	Aug 25 12:55:01 AM UTC 24
Finished	Aug 25 12:55:05 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029243857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.4029243857
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/22.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke.2718142641
Short name	T437
Test name
Test status
Simulation time	149389142 ps
CPU time	1.77 seconds
Started	Aug 25 12:54:55 AM UTC 24
Finished	Aug 25 12:54:58 AM UTC 24
Peak memory	211132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718142641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2718142641
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/22.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_large_delays.4177438537
Short name	T165
Test name
Test status
Simulation time	1921295075 ps
CPU time	15.96 seconds
Started	Aug 25 12:54:58 AM UTC 24
Finished	Aug 25 12:55:15 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177438537 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.4177438537
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/22.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.705655970
Short name	T162
Test name
Test status
Simulation time	1027589472 ps
CPU time	12.22 seconds
Started	Aug 25 12:54:59 AM UTC 24
Finished	Aug 25 12:55:12 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705655970 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.705655970
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/22.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.183032501
Short name	T438
Test name
Test status
Simulation time	9201219 ps
CPU time	1.7 seconds
Started	Aug 25 12:54:57 AM UTC 24
Finished	Aug 25 12:54:59 AM UTC 24
Peak memory	211244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183032501 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.183032501
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/22.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all.2652696260
Short name	T462
Test name
Test status
Simulation time	276481407 ps
CPU time	24.03 seconds
Started	Aug 25 12:55:04 AM UTC 24
Finished	Aug 25 12:55:29 AM UTC 24
Peak memory	214372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652696260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2652696260
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/22.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_error.2191574364
Short name	T520
Test name
Test status
Simulation time	5037168681 ps
CPU time	69.95 seconds
Started	Aug 25 12:55:06 AM UTC 24
Finished	Aug 25 12:56:17 AM UTC 24
Peak memory	214436 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191574364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.2191574364
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/22.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1353744496
Short name	T172
Test name
Test status
Simulation time	4073451535 ps
CPU time	188.86 seconds
Started	Aug 25 12:55:06 AM UTC 24
Finished	Aug 25 12:58:18 AM UTC 24
Peak memory	216292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353744496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.1353744496
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/22.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.4001255046
Short name	T562
Test name
Test status
Simulation time	756130590 ps
CPU time	99.22 seconds
Started	Aug 25 12:55:06 AM UTC 24
Finished	Aug 25 12:56:47 AM UTC 24
Peak memory	214172 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001255046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.4001255046
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/22.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_unmapped_addr.2285383819
Short name	T161
Test name
Test status
Simulation time	229625188 ps
CPU time	5.35 seconds
Started	Aug 25 12:55:03 AM UTC 24
Finished	Aug 25 12:55:09 AM UTC 24
Peak memory	211664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285383819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.2285383819
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/22.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device.3555024089
Short name	T164
Test name
Test status
Simulation time	14553163 ps
CPU time	3.33 seconds
Started	Aug 25 12:55:10 AM UTC 24
Finished	Aug 25 12:55:15 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555024089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.3555024089
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/23.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.2773587439
Short name	T235
Test name
Test status
Simulation time	124311204262 ps
CPU time	377.28 seconds
Started	Aug 25 12:55:10 AM UTC 24
Finished	Aug 25 01:01:33 AM UTC 24
Peak memory	214440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773587439 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.2773587439
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/23.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1178715272
Short name	T464
Test name
Test status
Simulation time	502582134 ps
CPU time	12.74 seconds
Started	Aug 25 12:55:16 AM UTC 24
Finished	Aug 25 12:55:30 AM UTC 24
Peak memory	212084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178715272 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.1178715272
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/23.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_error_random.3242690632
Short name	T458
Test name
Test status
Simulation time	627286849 ps
CPU time	10.34 seconds
Started	Aug 25 12:55:13 AM UTC 24
Finished	Aug 25 12:55:25 AM UTC 24
Peak memory	212388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242690632 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3242690632
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/23.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random.722194099
Short name	T467
Test name
Test status
Simulation time	1862896162 ps
CPU time	23.17 seconds
Started	Aug 25 12:55:07 AM UTC 24
Finished	Aug 25 12:55:31 AM UTC 24
Peak memory	212384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722194099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.722194099
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/23.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_large_delays.2398125298
Short name	T190
Test name
Test status
Simulation time	25559713873 ps
CPU time	70.21 seconds
Started	Aug 25 12:55:09 AM UTC 24
Finished	Aug 25 12:56:21 AM UTC 24
Peak memory	212200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398125298 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2398125298
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/23.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_slow_rsp.4128543843
Short name	T501
Test name
Test status
Simulation time	15037619790 ps
CPU time	54.85 seconds
Started	Aug 25 12:55:09 AM UTC 24
Finished	Aug 25 12:56:06 AM UTC 24
Peak memory	212200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128543843 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.4128543843
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/23.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_zero_delays.3921570598
Short name	T167
Test name
Test status
Simulation time	174076707 ps
CPU time	6.12 seconds
Started	Aug 25 12:55:09 AM UTC 24
Finished	Aug 25 12:55:16 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921570598 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.3921570598
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/23.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_same_source.3059169614
Short name	T166
Test name
Test status
Simulation time	593326086 ps
CPU time	2.72 seconds
Started	Aug 25 12:55:12 AM UTC 24
Finished	Aug 25 12:55:16 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059169614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3059169614
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/23.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke.1188083071
Short name	T443
Test name
Test status
Simulation time	10374723 ps
CPU time	1.49 seconds
Started	Aug 25 12:55:06 AM UTC 24
Finished	Aug 25 12:55:08 AM UTC 24
Peak memory	211132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188083071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.1188083071
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/23.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_large_delays.4222886524
Short name	T38
Test name
Test status
Simulation time	2488668843 ps
CPU time	15.82 seconds
Started	Aug 25 12:55:06 AM UTC 24
Finished	Aug 25 12:55:23 AM UTC 24
Peak memory	212264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222886524 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.4222886524
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/23.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.4126971374
Short name	T447
Test name
Test status
Simulation time	3421897136 ps
CPU time	8.8 seconds
Started	Aug 25 12:55:07 AM UTC 24
Finished	Aug 25 12:55:17 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126971374 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.4126971374
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/23.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.702038118
Short name	T444
Test name
Test status
Simulation time	7894913 ps
CPU time	1.61 seconds
Started	Aug 25 12:55:06 AM UTC 24
Finished	Aug 25 12:55:08 AM UTC 24
Peak memory	211184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702038118 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.702038118
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/23.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all.3336781307
Short name	T449
Test name
Test status
Simulation time	6772420 ps
CPU time	1.12 seconds
Started	Aug 25 12:55:16 AM UTC 24
Finished	Aug 25 12:55:18 AM UTC 24
Peak memory	202420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336781307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.3336781307
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/23.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_error.1488879423
Short name	T463
Test name
Test status
Simulation time	1046325744 ps
CPU time	11.38 seconds
Started	Aug 25 12:55:17 AM UTC 24
Finished	Aug 25 12:55:29 AM UTC 24
Peak memory	212328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488879423 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1488879423
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/23.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.4026066702
Short name	T9
Test name
Test status
Simulation time	447979346 ps
CPU time	64.82 seconds
Started	Aug 25 12:55:17 AM UTC 24
Finished	Aug 25 12:56:24 AM UTC 24
Peak memory	214248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026066702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.4026066702
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/23.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.429538440
Short name	T597
Test name
Test status
Simulation time	2859129396 ps
CPU time	109.99 seconds
Started	Aug 25 12:55:18 AM UTC 24
Finished	Aug 25 12:57:10 AM UTC 24
Peak memory	216556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429538440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.429538440
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/23.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_unmapped_addr.3055537491
Short name	T448
Test name
Test status
Simulation time	46732968 ps
CPU time	2.17 seconds
Started	Aug 25 12:55:15 AM UTC 24
Finished	Aug 25 12:55:18 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055537491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.3055537491
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/23.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device.2997521699
Short name	T257
Test name
Test status
Simulation time	932738973 ps
CPU time	23.89 seconds
Started	Aug 25 12:55:23 AM UTC 24
Finished	Aug 25 12:55:48 AM UTC 24
Peak memory	212328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997521699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.2997521699
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/24.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.1642794951
Short name	T142
Test name
Test status
Simulation time	306924493462 ps
CPU time	604.37 seconds
Started	Aug 25 12:55:24 AM UTC 24
Finished	Aug 25 01:05:37 AM UTC 24
Peak memory	217948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642794951 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.1642794951
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/24.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.3113528937
Short name	T479
Test name
Test status
Simulation time	856247748 ps
CPU time	14.04 seconds
Started	Aug 25 12:55:25 AM UTC 24
Finished	Aug 25 12:55:41 AM UTC 24
Peak memory	212112 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113528937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.3113528937
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/24.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_error_random.3319168592
Short name	T472
Test name
Test status
Simulation time	2741247836 ps
CPU time	11.69 seconds
Started	Aug 25 12:55:24 AM UTC 24
Finished	Aug 25 12:55:37 AM UTC 24
Peak memory	212388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319168592 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3319168592
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/24.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random.1231954167
Short name	T456
Test name
Test status
Simulation time	76941953 ps
CPU time	2.13 seconds
Started	Aug 25 12:55:20 AM UTC 24
Finished	Aug 25 12:55:24 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231954167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.1231954167
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/24.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_large_delays.2369285165
Short name	T633
Test name
Test status
Simulation time	24425511463 ps
CPU time	128.33 seconds
Started	Aug 25 12:55:22 AM UTC 24
Finished	Aug 25 12:57:32 AM UTC 24
Peak memory	212200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369285165 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.2369285165
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/24.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_slow_rsp.3334533896
Short name	T495
Test name
Test status
Simulation time	3801051870 ps
CPU time	33.85 seconds
Started	Aug 25 12:55:23 AM UTC 24
Finished	Aug 25 12:55:58 AM UTC 24
Peak memory	212204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334533896 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.3334533896
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/24.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_zero_delays.2770827767
Short name	T460
Test name
Test status
Simulation time	31423775 ps
CPU time	4.41 seconds
Started	Aug 25 12:55:21 AM UTC 24
Finished	Aug 25 12:55:27 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770827767 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.2770827767
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/24.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_same_source.3911096558
Short name	T459
Test name
Test status
Simulation time	16005887 ps
CPU time	1.6 seconds
Started	Aug 25 12:55:24 AM UTC 24
Finished	Aug 25 12:55:27 AM UTC 24
Peak memory	211240 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911096558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3911096558
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/24.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke.2193424244
Short name	T37
Test name
Test status
Simulation time	45481783 ps
CPU time	1.9 seconds
Started	Aug 25 12:55:18 AM UTC 24
Finished	Aug 25 12:55:21 AM UTC 24
Peak memory	211136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193424244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2193424244
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/24.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_large_delays.2710784430
Short name	T470
Test name
Test status
Simulation time	2167967051 ps
CPU time	14.14 seconds
Started	Aug 25 12:55:19 AM UTC 24
Finished	Aug 25 12:55:35 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710784430 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.2710784430
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/24.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.2271201848
Short name	T471
Test name
Test status
Simulation time	3995760364 ps
CPU time	14.61 seconds
Started	Aug 25 12:55:19 AM UTC 24
Finished	Aug 25 12:55:35 AM UTC 24
Peak memory	212388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271201848 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2271201848
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/24.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.3253259772
Short name	T454
Test name
Test status
Simulation time	10180681 ps
CPU time	1.81 seconds
Started	Aug 25 12:55:19 AM UTC 24
Finished	Aug 25 12:55:22 AM UTC 24
Peak memory	211132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253259772 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.3253259772
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/24.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all.2693423987
Short name	T160
Test name
Test status
Simulation time	6878917874 ps
CPU time	30.22 seconds
Started	Aug 25 12:55:25 AM UTC 24
Finished	Aug 25 12:55:57 AM UTC 24
Peak memory	212164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693423987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2693423987
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/24.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_error.1067985439
Short name	T589
Test name
Test status
Simulation time	9196164772 ps
CPU time	94.59 seconds
Started	Aug 25 12:55:28 AM UTC 24
Finished	Aug 25 12:57:04 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067985439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.1067985439
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/24.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.4111520077
Short name	T519
Test name
Test status
Simulation time	269500407 ps
CPU time	47.29 seconds
Started	Aug 25 12:55:27 AM UTC 24
Finished	Aug 25 12:56:17 AM UTC 24
Peak memory	214180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111520077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.4111520077
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/24.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.790968853
Short name	T689
Test name
Test status
Simulation time	1301481877 ps
CPU time	158.55 seconds
Started	Aug 25 12:55:29 AM UTC 24
Finished	Aug 25 12:58:10 AM UTC 24
Peak memory	216428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790968853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.790968853
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/24.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_unmapped_addr.2741075407
Short name	T461
Test name
Test status
Simulation time	44807877 ps
CPU time	2.02 seconds
Started	Aug 25 12:55:24 AM UTC 24
Finished	Aug 25 12:55:27 AM UTC 24
Peak memory	212324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741075407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2741075407
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/24.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device.2684499011
Short name	T114
Test name
Test status
Simulation time	636209310 ps
CPU time	20.6 seconds
Started	Aug 25 12:55:35 AM UTC 24
Finished	Aug 25 12:55:56 AM UTC 24
Peak memory	212136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684499011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.2684499011
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/25.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.3985211668
Short name	T245
Test name
Test status
Simulation time	48594183104 ps
CPU time	324.41 seconds
Started	Aug 25 12:55:36 AM UTC 24
Finished	Aug 25 01:01:05 AM UTC 24
Peak memory	214248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985211668 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.3985211668
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/25.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.1635408503
Short name	T485
Test name
Test status
Simulation time	62570249 ps
CPU time	6.96 seconds
Started	Aug 25 12:55:38 AM UTC 24
Finished	Aug 25 12:55:46 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635408503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.1635408503
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/25.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_error_random.2539286063
Short name	T492
Test name
Test status
Simulation time	617161153 ps
CPU time	15.47 seconds
Started	Aug 25 12:55:38 AM UTC 24
Finished	Aug 25 12:55:55 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539286063 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2539286063
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/25.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random.2082026753
Short name	T488
Test name
Test status
Simulation time	1437413681 ps
CPU time	18.44 seconds
Started	Aug 25 12:55:32 AM UTC 24
Finished	Aug 25 12:55:52 AM UTC 24
Peak memory	212384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082026753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.2082026753
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/25.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_large_delays.1438129662
Short name	T192
Test name
Test status
Simulation time	39983458684 ps
CPU time	235.06 seconds
Started	Aug 25 12:55:33 AM UTC 24
Finished	Aug 25 12:59:32 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438129662 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.1438129662
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/25.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_slow_rsp.3021393479
Short name	T596
Test name
Test status
Simulation time	18981318778 ps
CPU time	90.84 seconds
Started	Aug 25 12:55:35 AM UTC 24
Finished	Aug 25 12:57:08 AM UTC 24
Peak memory	212332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021393479 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.3021393479
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/25.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_zero_delays.2615332278
Short name	T475
Test name
Test status
Simulation time	52977550 ps
CPU time	4.99 seconds
Started	Aug 25 12:55:32 AM UTC 24
Finished	Aug 25 12:55:38 AM UTC 24
Peak memory	212448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615332278 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.2615332278
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/25.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_same_source.195996588
Short name	T113
Test name
Test status
Simulation time	492716546 ps
CPU time	7.36 seconds
Started	Aug 25 12:55:36 AM UTC 24
Finished	Aug 25 12:55:44 AM UTC 24
Peak memory	212316 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195996588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.195996588
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/25.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke.295148348
Short name	T469
Test name
Test status
Simulation time	295110945 ps
CPU time	2.13 seconds
Started	Aug 25 12:55:30 AM UTC 24
Finished	Aug 25 12:55:33 AM UTC 24
Peak memory	212388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295148348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.295148348
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/25.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_large_delays.3895098741
Short name	T486
Test name
Test status
Simulation time	2339567246 ps
CPU time	14.24 seconds
Started	Aug 25 12:55:31 AM UTC 24
Finished	Aug 25 12:55:46 AM UTC 24
Peak memory	212392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895098741 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3895098741
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/25.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.4130801175
Short name	T482
Test name
Test status
Simulation time	950301890 ps
CPU time	11.2 seconds
Started	Aug 25 12:55:31 AM UTC 24
Finished	Aug 25 12:55:43 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130801175 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.4130801175
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/25.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.1112110418
Short name	T468
Test name
Test status
Simulation time	15379178 ps
CPU time	1.44 seconds
Started	Aug 25 12:55:30 AM UTC 24
Finished	Aug 25 12:55:32 AM UTC 24
Peak memory	211236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112110418 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.1112110418
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/25.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all.2572575965
Short name	T515
Test name
Test status
Simulation time	333466286 ps
CPU time	34.91 seconds
Started	Aug 25 12:55:38 AM UTC 24
Finished	Aug 25 12:56:15 AM UTC 24
Peak memory	214244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572575965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.2572575965
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/25.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_error.1195609616
Short name	T517
Test name
Test status
Simulation time	756932101 ps
CPU time	35.01 seconds
Started	Aug 25 12:55:40 AM UTC 24
Finished	Aug 25 12:56:16 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195609616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1195609616
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/25.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.1581864841
Short name	T276
Test name
Test status
Simulation time	46721399 ps
CPU time	13.19 seconds
Started	Aug 25 12:55:40 AM UTC 24
Finished	Aug 25 12:55:54 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581864841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.1581864841
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/25.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_unmapped_addr.3266850125
Short name	T39
Test name
Test status
Simulation time	96877583 ps
CPU time	1.95 seconds
Started	Aug 25 12:55:38 AM UTC 24
Finished	Aug 25 12:55:41 AM UTC 24
Peak memory	211236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266850125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3266850125
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/25.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device.352023691
Short name	T116
Test name
Test status
Simulation time	1328535324 ps
CPU time	27.27 seconds
Started	Aug 25 12:55:45 AM UTC 24
Finished	Aug 25 12:56:14 AM UTC 24
Peak memory	212120 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352023691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.352023691
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/26.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.55672590
Short name	T259
Test name
Test status
Simulation time	4164549036 ps
CPU time	33.57 seconds
Started	Aug 25 12:55:45 AM UTC 24
Finished	Aug 25 12:56:20 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55672590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.55672590
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/26.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.1070537246
Short name	T489
Test name
Test status
Simulation time	43439410 ps
CPU time	3.92 seconds
Started	Aug 25 12:55:47 AM UTC 24
Finished	Aug 25 12:55:52 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070537246 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.1070537246
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/26.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_error_random.4009138848
Short name	T500
Test name
Test status
Simulation time	1223361435 ps
CPU time	19.03 seconds
Started	Aug 25 12:55:45 AM UTC 24
Finished	Aug 25 12:56:06 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009138848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.4009138848
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/26.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random.568731767
Short name	T487
Test name
Test status
Simulation time	209208938 ps
CPU time	6.29 seconds
Started	Aug 25 12:55:43 AM UTC 24
Finished	Aug 25 12:55:50 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568731767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.568731767
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/26.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_large_delays.3929917632
Short name	T797
Test name
Test status
Simulation time	43222914888 ps
CPU time	240.15 seconds
Started	Aug 25 12:55:44 AM UTC 24
Finished	Aug 25 12:59:48 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929917632 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.3929917632
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/26.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_slow_rsp.2724815494
Short name	T43
Test name
Test status
Simulation time	10312139181 ps
CPU time	88.74 seconds
Started	Aug 25 12:55:45 AM UTC 24
Finished	Aug 25 12:57:16 AM UTC 24
Peak memory	212204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724815494 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.2724815494
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/26.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_zero_delays.2411794851
Short name	T494
Test name
Test status
Simulation time	74591403 ps
CPU time	12.58 seconds
Started	Aug 25 12:55:44 AM UTC 24
Finished	Aug 25 12:55:57 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411794851 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.2411794851
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/26.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_same_source.2066063564
Short name	T465
Test name
Test status
Simulation time	56581363 ps
CPU time	8.25 seconds
Started	Aug 25 12:55:45 AM UTC 24
Finished	Aug 25 12:55:54 AM UTC 24
Peak memory	212324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066063564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.2066063564
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/26.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke.727451202
Short name	T480
Test name
Test status
Simulation time	12634566 ps
CPU time	1.67 seconds
Started	Aug 25 12:55:40 AM UTC 24
Finished	Aug 25 12:55:43 AM UTC 24
Peak memory	211132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727451202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.727451202
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/26.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_large_delays.2268263875
Short name	T503
Test name
Test status
Simulation time	6129653043 ps
CPU time	24.1 seconds
Started	Aug 25 12:55:41 AM UTC 24
Finished	Aug 25 12:56:07 AM UTC 24
Peak memory	212200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268263875 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2268263875
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/26.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.2724979627
Short name	T508
Test name
Test status
Simulation time	2422093279 ps
CPU time	26.32 seconds
Started	Aug 25 12:55:41 AM UTC 24
Finished	Aug 25 12:56:09 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724979627 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.2724979627
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/26.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.2333049929
Short name	T484
Test name
Test status
Simulation time	8459003 ps
CPU time	1.63 seconds
Started	Aug 25 12:55:41 AM UTC 24
Finished	Aug 25 12:55:44 AM UTC 24
Peak memory	211128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333049929 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.2333049929
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/26.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_error.3273515233
Short name	T537
Test name
Test status
Simulation time	527263970 ps
CPU time	37.33 seconds
Started	Aug 25 12:55:53 AM UTC 24
Finished	Aug 25 12:56:32 AM UTC 24
Peak memory	212136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273515233 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.3273515233
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/26.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.2791336084
Short name	T705
Test name
Test status
Simulation time	2134623000 ps
CPU time	149.45 seconds
Started	Aug 25 12:55:51 AM UTC 24
Finished	Aug 25 12:58:23 AM UTC 24
Peak memory	216228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791336084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.2791336084
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/26.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.815323579
Short name	T662
Test name
Test status
Simulation time	980840055 ps
CPU time	119.43 seconds
Started	Aug 25 12:55:53 AM UTC 24
Finished	Aug 25 12:57:55 AM UTC 24
Peak memory	216492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815323579 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.815323579
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/26.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_unmapped_addr.4156057846
Short name	T490
Test name
Test status
Simulation time	31836875 ps
CPU time	4.53 seconds
Started	Aug 25 12:55:47 AM UTC 24
Finished	Aug 25 12:55:53 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156057846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.4156057846
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/26.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device.3390267724
Short name	T516
Test name
Test status
Simulation time	632049591 ps
CPU time	15.74 seconds
Started	Aug 25 12:55:58 AM UTC 24
Finished	Aug 25 12:56:15 AM UTC 24
Peak memory	212328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390267724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.3390267724
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/27.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.4255396203
Short name	T891
Test name
Test status
Simulation time	189183897585 ps
CPU time	531.45 seconds
Started	Aug 25 12:55:58 AM UTC 24
Finished	Aug 25 01:04:58 AM UTC 24
Peak memory	217944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255396203 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.4255396203
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/27.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.3050921812
Short name	T518
Test name
Test status
Simulation time	1652008811 ps
CPU time	16.45 seconds
Started	Aug 25 12:55:59 AM UTC 24
Finished	Aug 25 12:56:16 AM UTC 24
Peak memory	212388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050921812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.3050921812
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/27.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_error_random.2596521863
Short name	T499
Test name
Test status
Simulation time	363466415 ps
CPU time	5.39 seconds
Started	Aug 25 12:55:58 AM UTC 24
Finished	Aug 25 12:56:05 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596521863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2596521863
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/27.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random.3081086753
Short name	T507
Test name
Test status
Simulation time	66570336 ps
CPU time	11.68 seconds
Started	Aug 25 12:55:55 AM UTC 24
Finished	Aug 25 12:56:09 AM UTC 24
Peak memory	212384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081086753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.3081086753
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/27.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_large_delays.588695726
Short name	T847
Test name
Test status
Simulation time	89263677005 ps
CPU time	271.32 seconds
Started	Aug 25 12:55:56 AM UTC 24
Finished	Aug 25 01:00:31 AM UTC 24
Peak memory	212384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588695726 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.588695726
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/27.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_slow_rsp.187756916
Short name	T42
Test name
Test status
Simulation time	10851379292 ps
CPU time	66.95 seconds
Started	Aug 25 12:55:57 AM UTC 24
Finished	Aug 25 12:57:06 AM UTC 24
Peak memory	212388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187756916 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.187756916
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/27.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_zero_delays.2007484166
Short name	T496
Test name
Test status
Simulation time	17084056 ps
CPU time	3.16 seconds
Started	Aug 25 12:55:55 AM UTC 24
Finished	Aug 25 12:56:00 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007484166 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.2007484166
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/27.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_same_source.2607048499
Short name	T498
Test name
Test status
Simulation time	25282151 ps
CPU time	4.29 seconds
Started	Aug 25 12:55:58 AM UTC 24
Finished	Aug 25 12:56:04 AM UTC 24
Peak memory	212384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607048499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.2607048499
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/27.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke.3901391018
Short name	T445
Test name
Test status
Simulation time	15207136 ps
CPU time	1.7 seconds
Started	Aug 25 12:55:54 AM UTC 24
Finished	Aug 25 12:55:57 AM UTC 24
Peak memory	211240 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901391018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3901391018
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/27.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_large_delays.3729953702
Short name	T514
Test name
Test status
Simulation time	3114536367 ps
CPU time	17.1 seconds
Started	Aug 25 12:55:55 AM UTC 24
Finished	Aug 25 12:56:14 AM UTC 24
Peak memory	212240 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729953702 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.3729953702
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/27.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3581250321
Short name	T504
Test name
Test status
Simulation time	1322063485 ps
CPU time	10.06 seconds
Started	Aug 25 12:55:55 AM UTC 24
Finished	Aug 25 12:56:07 AM UTC 24
Peak memory	212324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581250321 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3581250321
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/27.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.2564222371
Short name	T493
Test name
Test status
Simulation time	9280343 ps
CPU time	1.71 seconds
Started	Aug 25 12:55:54 AM UTC 24
Finished	Aug 25 12:55:57 AM UTC 24
Peak memory	211120 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564222371 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.2564222371
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/27.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all.2266031244
Short name	T553
Test name
Test status
Simulation time	1697929985 ps
CPU time	41.35 seconds
Started	Aug 25 12:55:59 AM UTC 24
Finished	Aug 25 12:56:42 AM UTC 24
Peak memory	214500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266031244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2266031244
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/27.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_error.1402022326
Short name	T538
Test name
Test status
Simulation time	274165826 ps
CPU time	30.67 seconds
Started	Aug 25 12:56:00 AM UTC 24
Finished	Aug 25 12:56:32 AM UTC 24
Peak memory	212328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402022326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.1402022326
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/27.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.2038852374
Short name	T740
Test name
Test status
Simulation time	806797823 ps
CPU time	163.36 seconds
Started	Aug 25 12:56:00 AM UTC 24
Finished	Aug 25 12:58:47 AM UTC 24
Peak memory	218280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038852374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.2038852374
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/27.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.2329873601
Short name	T289
Test name
Test status
Simulation time	5504627611 ps
CPU time	75.69 seconds
Started	Aug 25 12:56:01 AM UTC 24
Finished	Aug 25 12:57:19 AM UTC 24
Peak memory	216284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329873601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.2329873601
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/27.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_unmapped_addr.2148519740
Short name	T509
Test name
Test status
Simulation time	96607541 ps
CPU time	9.43 seconds
Started	Aug 25 12:55:58 AM UTC 24
Finished	Aug 25 12:56:09 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148519740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2148519740
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/27.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device.3857335827
Short name	T249
Test name
Test status
Simulation time	1070246379 ps
CPU time	22.64 seconds
Started	Aug 25 12:56:08 AM UTC 24
Finished	Aug 25 12:56:33 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857335827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.3857335827
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/28.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2877088801
Short name	T154
Test name
Test status
Simulation time	49150536559 ps
CPU time	583.23 seconds
Started	Aug 25 12:56:08 AM UTC 24
Finished	Aug 25 01:05:59 AM UTC 24
Peak memory	217944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877088801 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.2877088801
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/28.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.734733421
Short name	T530
Test name
Test status
Simulation time	633102063 ps
CPU time	13.95 seconds
Started	Aug 25 12:56:10 AM UTC 24
Finished	Aug 25 12:56:25 AM UTC 24
Peak memory	212072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734733421 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.734733421
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/28.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_error_random.2104717160
Short name	T513
Test name
Test status
Simulation time	19139317 ps
CPU time	2.8 seconds
Started	Aug 25 12:56:10 AM UTC 24
Finished	Aug 25 12:56:14 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104717160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.2104717160
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/28.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random.1961394484
Short name	T523
Test name
Test status
Simulation time	662317925 ps
CPU time	12.88 seconds
Started	Aug 25 12:56:06 AM UTC 24
Finished	Aug 25 12:56:20 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961394484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.1961394484
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/28.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_large_delays.3422514844
Short name	T564
Test name
Test status
Simulation time	19270963249 ps
CPU time	40.19 seconds
Started	Aug 25 12:56:07 AM UTC 24
Finished	Aug 25 12:56:49 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422514844 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.3422514844
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/28.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_slow_rsp.1548145605
Short name	T44
Test name
Test status
Simulation time	36537629562 ps
CPU time	102.01 seconds
Started	Aug 25 12:56:07 AM UTC 24
Finished	Aug 25 12:57:51 AM UTC 24
Peak memory	212204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548145605 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.1548145605
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/28.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_zero_delays.4057511373
Short name	T511
Test name
Test status
Simulation time	64949088 ps
CPU time	3.05 seconds
Started	Aug 25 12:56:07 AM UTC 24
Finished	Aug 25 12:56:11 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057511373 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.4057511373
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/28.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_same_source.1903566824
Short name	T512
Test name
Test status
Simulation time	19038423 ps
CPU time	1.81 seconds
Started	Aug 25 12:56:08 AM UTC 24
Finished	Aug 25 12:56:12 AM UTC 24
Peak memory	211184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903566824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1903566824
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/28.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke.1296378835
Short name	T502
Test name
Test status
Simulation time	68110719 ps
CPU time	1.92 seconds
Started	Aug 25 12:56:03 AM UTC 24
Finished	Aug 25 12:56:06 AM UTC 24
Peak memory	211136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296378835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.1296378835
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/28.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_large_delays.1087201202
Short name	T524
Test name
Test status
Simulation time	1892413411 ps
CPU time	14.33 seconds
Started	Aug 25 12:56:04 AM UTC 24
Finished	Aug 25 12:56:20 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087201202 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.1087201202
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/28.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.3794105607
Short name	T529
Test name
Test status
Simulation time	1529318324 ps
CPU time	19.21 seconds
Started	Aug 25 12:56:04 AM UTC 24
Finished	Aug 25 12:56:25 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794105607 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3794105607
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/28.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.1391084619
Short name	T505
Test name
Test status
Simulation time	10141959 ps
CPU time	1.85 seconds
Started	Aug 25 12:56:04 AM UTC 24
Finished	Aug 25 12:56:07 AM UTC 24
Peak memory	211232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391084619 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.1391084619
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/28.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all.2080075723
Short name	T528
Test name
Test status
Simulation time	119795739 ps
CPU time	12.43 seconds
Started	Aug 25 12:56:10 AM UTC 24
Finished	Aug 25 12:56:24 AM UTC 24
Peak memory	212084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080075723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.2080075723
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/28.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_error.3210708579
Short name	T555
Test name
Test status
Simulation time	741835928 ps
CPU time	30.57 seconds
Started	Aug 25 12:56:12 AM UTC 24
Finished	Aug 25 12:56:45 AM UTC 24
Peak memory	214180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210708579 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.3210708579
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/28.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.2439827363
Short name	T761
Test name
Test status
Simulation time	809969703 ps
CPU time	170.35 seconds
Started	Aug 25 12:56:11 AM UTC 24
Finished	Aug 25 12:59:05 AM UTC 24
Peak memory	216228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439827363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.2439827363
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/28.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.3137462553
Short name	T588
Test name
Test status
Simulation time	313145024 ps
CPU time	49.05 seconds
Started	Aug 25 12:56:12 AM UTC 24
Finished	Aug 25 12:57:03 AM UTC 24
Peak memory	214172 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137462553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.3137462553
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/28.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_unmapped_addr.3425175835
Short name	T526
Test name
Test status
Simulation time	478205321 ps
CPU time	9.78 seconds
Started	Aug 25 12:56:10 AM UTC 24
Finished	Aug 25 12:56:21 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425175835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3425175835
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/28.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device.3241386846
Short name	T135
Test name
Test status
Simulation time	1466912629 ps
CPU time	19.43 seconds
Started	Aug 25 12:56:18 AM UTC 24
Finished	Aug 25 12:56:38 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241386846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.3241386846
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/29.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1321493671
Short name	T878
Test name
Test status
Simulation time	119144496123 ps
CPU time	376.58 seconds
Started	Aug 25 12:56:19 AM UTC 24
Finished	Aug 25 01:02:41 AM UTC 24
Peak memory	214244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321493671 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.1321493671
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/29.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.792414442
Short name	T536
Test name
Test status
Simulation time	395555216 ps
CPU time	9.15 seconds
Started	Aug 25 12:56:21 AM UTC 24
Finished	Aug 25 12:56:32 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792414442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.792414442
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/29.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_error_random.911678632
Short name	T540
Test name
Test status
Simulation time	3257360446 ps
CPU time	14.69 seconds
Started	Aug 25 12:56:19 AM UTC 24
Finished	Aug 25 12:56:35 AM UTC 24
Peak memory	212188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911678632 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.911678632
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/29.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random.1361496838
Short name	T533
Test name
Test status
Simulation time	516903697 ps
CPU time	10.64 seconds
Started	Aug 25 12:56:16 AM UTC 24
Finished	Aug 25 12:56:28 AM UTC 24
Peak memory	211812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361496838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.1361496838
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/29.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_large_delays.186990250
Short name	T768
Test name
Test status
Simulation time	32116673151 ps
CPU time	174.39 seconds
Started	Aug 25 12:56:17 AM UTC 24
Finished	Aug 25 12:59:15 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186990250 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.186990250
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/29.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_slow_rsp.3463381718
Short name	T680
Test name
Test status
Simulation time	13371039348 ps
CPU time	106.89 seconds
Started	Aug 25 12:56:18 AM UTC 24
Finished	Aug 25 12:58:07 AM UTC 24
Peak memory	212204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463381718 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.3463381718
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/29.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_zero_delays.1683920981
Short name	T525
Test name
Test status
Simulation time	16795677 ps
CPU time	2.96 seconds
Started	Aug 25 12:56:16 AM UTC 24
Finished	Aug 25 12:56:21 AM UTC 24
Peak memory	211968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683920981 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.1683920981
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/29.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_same_source.3827905983
Short name	T551
Test name
Test status
Simulation time	1504913941 ps
CPU time	20.2 seconds
Started	Aug 25 12:56:19 AM UTC 24
Finished	Aug 25 12:56:41 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827905983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.3827905983
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/29.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke.3950791103
Short name	T521
Test name
Test status
Simulation time	66557491 ps
CPU time	2.66 seconds
Started	Aug 25 12:56:14 AM UTC 24
Finished	Aug 25 12:56:17 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950791103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.3950791103
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/29.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_large_delays.3885262978
Short name	T40
Test name
Test status
Simulation time	2374028888 ps
CPU time	17.13 seconds
Started	Aug 25 12:56:15 AM UTC 24
Finished	Aug 25 12:56:34 AM UTC 24
Peak memory	212448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885262978 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3885262978
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/29.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.95530838
Short name	T534
Test name
Test status
Simulation time	1049059258 ps
CPU time	12.93 seconds
Started	Aug 25 12:56:15 AM UTC 24
Finished	Aug 25 12:56:29 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95530838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.95530838
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/29.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.1188064365
Short name	T522
Test name
Test status
Simulation time	9181831 ps
CPU time	1.76 seconds
Started	Aug 25 12:56:15 AM UTC 24
Finished	Aug 25 12:56:18 AM UTC 24
Peak memory	211132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188064365 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.1188064365
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/29.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all.3840454238
Short name	T683
Test name
Test status
Simulation time	9925111209 ps
CPU time	105.24 seconds
Started	Aug 25 12:56:21 AM UTC 24
Finished	Aug 25 12:58:09 AM UTC 24
Peak memory	214244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840454238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.3840454238
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/29.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_error.2079545930
Short name	T251
Test name
Test status
Simulation time	2746601487 ps
CPU time	43.42 seconds
Started	Aug 25 12:56:23 AM UTC 24
Finished	Aug 25 12:57:08 AM UTC 24
Peak memory	214248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079545930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.2079545930
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/29.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.1726926496
Short name	T736
Test name
Test status
Simulation time	2206377839 ps
CPU time	139.78 seconds
Started	Aug 25 12:56:21 AM UTC 24
Finished	Aug 25 12:58:44 AM UTC 24
Peak memory	216296 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726926496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.1726926496
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/29.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.2828084897
Short name	T645
Test name
Test status
Simulation time	3650664609 ps
CPU time	76.7 seconds
Started	Aug 25 12:56:23 AM UTC 24
Finished	Aug 25 12:57:42 AM UTC 24
Peak memory	214240 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828084897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.2828084897
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/29.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_unmapped_addr.2134935903
Short name	T546
Test name
Test status
Simulation time	5672394236 ps
CPU time	16.94 seconds
Started	Aug 25 12:56:21 AM UTC 24
Finished	Aug 25 12:56:39 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134935903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.2134935903
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/29.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device.2464358541
Short name	T205
Test name
Test status
Simulation time	714205025 ps
CPU time	12.26 seconds
Started	Aug 25 12:52:11 AM UTC 24
Finished	Aug 25 12:52:27 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464358541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.2464358541
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/3.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.3665316836
Short name	T244
Test name
Test status
Simulation time	174901415599 ps
CPU time	487.05 seconds
Started	Aug 25 12:52:11 AM UTC 24
Finished	Aug 25 01:00:38 AM UTC 24
Peak memory	217412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665316836 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.3665316836
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/3.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.408310988
Short name	T70
Test name
Test status
Simulation time	325422376 ps
CPU time	4.97 seconds
Started	Aug 25 12:52:12 AM UTC 24
Finished	Aug 25 12:52:19 AM UTC 24
Peak memory	212136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408310988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.408310988
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/3.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_error_random.2218023462
Short name	T301
Test name
Test status
Simulation time	113442888 ps
CPU time	7.27 seconds
Started	Aug 25 12:52:11 AM UTC 24
Finished	Aug 25 12:52:33 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218023462 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2218023462
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/3.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random.3354171283
Short name	T74
Test name
Test status
Simulation time	670428072 ps
CPU time	11.06 seconds
Started	Aug 25 12:52:10 AM UTC 24
Finished	Aug 25 12:52:42 AM UTC 24
Peak memory	212380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354171283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.3354171283
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/3.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_large_delays.3953265134
Short name	T46
Test name
Test status
Simulation time	4301389955 ps
CPU time	8.17 seconds
Started	Aug 25 12:52:11 AM UTC 24
Finished	Aug 25 12:52:23 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953265134 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3953265134
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/3.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_slow_rsp.1093521872
Short name	T126
Test name
Test status
Simulation time	35510489008 ps
CPU time	98.84 seconds
Started	Aug 25 12:52:11 AM UTC 24
Finished	Aug 25 12:53:55 AM UTC 24
Peak memory	212200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093521872 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.1093521872
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/3.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_zero_delays.3847555465
Short name	T34
Test name
Test status
Simulation time	124245185 ps
CPU time	4.43 seconds
Started	Aug 25 12:52:11 AM UTC 24
Finished	Aug 25 12:52:19 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847555465 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.3847555465
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/3.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_same_source.871544333
Short name	T292
Test name
Test status
Simulation time	2223207157 ps
CPU time	3.8 seconds
Started	Aug 25 12:52:11 AM UTC 24
Finished	Aug 25 12:52:29 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871544333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.871544333
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/3.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke.3123700028
Short name	T299
Test name
Test status
Simulation time	9001217 ps
CPU time	1.49 seconds
Started	Aug 25 12:52:10 AM UTC 24
Finished	Aug 25 12:52:32 AM UTC 24
Peak memory	211140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123700028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3123700028
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/3.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_large_delays.2605897168
Short name	T73
Test name
Test status
Simulation time	5436817644 ps
CPU time	10.69 seconds
Started	Aug 25 12:52:10 AM UTC 24
Finished	Aug 25 12:52:42 AM UTC 24
Peak memory	212360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605897168 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.2605897168
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/3.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.4290560181
Short name	T246
Test name
Test status
Simulation time	3858142063 ps
CPU time	7.91 seconds
Started	Aug 25 12:52:10 AM UTC 24
Finished	Aug 25 12:52:39 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290560181 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.4290560181
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/3.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.176481678
Short name	T302
Test name
Test status
Simulation time	9205183 ps
CPU time	1.62 seconds
Started	Aug 25 12:52:10 AM UTC 24
Finished	Aug 25 12:52:33 AM UTC 24
Peak memory	211228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176481678 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.176481678
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/3.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_error.898446368
Short name	T201
Test name
Test status
Simulation time	4250145346 ps
CPU time	73.67 seconds
Started	Aug 25 12:52:13 AM UTC 24
Finished	Aug 25 12:53:40 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898446368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.898446368
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/3.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.1154568213
Short name	T110
Test name
Test status
Simulation time	12314068694 ps
CPU time	149.5 seconds
Started	Aug 25 12:52:12 AM UTC 24
Finished	Aug 25 12:55:02 AM UTC 24
Peak memory	215912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154568213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.1154568213
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/3.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_unmapped_addr.1605300435
Short name	T59
Test name
Test status
Simulation time	525342352 ps
CPU time	8.19 seconds
Started	Aug 25 12:52:11 AM UTC 24
Finished	Aug 25 12:52:34 AM UTC 24
Peak memory	212240 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605300435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.1605300435
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/3.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device.3022367319
Short name	T134
Test name
Test status
Simulation time	241367347 ps
CPU time	8.76 seconds
Started	Aug 25 12:56:27 AM UTC 24
Finished	Aug 25 12:56:37 AM UTC 24
Peak memory	212200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022367319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.3022367319
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/30.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.2503293805
Short name	T242
Test name
Test status
Simulation time	49128159534 ps
CPU time	164.23 seconds
Started	Aug 25 12:56:29 AM UTC 24
Finished	Aug 25 12:59:18 AM UTC 24
Peak memory	214248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503293805 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.2503293805
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/30.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3996248160
Short name	T506
Test name
Test status
Simulation time	39213215 ps
CPU time	5.23 seconds
Started	Aug 25 12:56:33 AM UTC 24
Finished	Aug 25 12:56:39 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996248160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3996248160
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/30.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_error_random.3698293023
Short name	T549
Test name
Test status
Simulation time	257015799 ps
CPU time	7.48 seconds
Started	Aug 25 12:56:31 AM UTC 24
Finished	Aug 25 12:56:40 AM UTC 24
Peak memory	212392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698293023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3698293023
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/30.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random.1417835905
Short name	T565
Test name
Test status
Simulation time	3814669501 ps
CPU time	22.09 seconds
Started	Aug 25 12:56:26 AM UTC 24
Finished	Aug 25 12:56:49 AM UTC 24
Peak memory	211784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417835905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.1417835905
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/30.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.1583105949
Short name	T867
Test name
Test status
Simulation time	83806239721 ps
CPU time	294.28 seconds
Started	Aug 25 12:56:26 AM UTC 24
Finished	Aug 25 01:01:24 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583105949 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1583105949
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/30.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_slow_rsp.2806243762
Short name	T741
Test name
Test status
Simulation time	70349050331 ps
CPU time	137.84 seconds
Started	Aug 25 12:56:27 AM UTC 24
Finished	Aug 25 12:58:47 AM UTC 24
Peak memory	212204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806243762 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.2806243762
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/30.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_zero_delays.2706659637
Short name	T543
Test name
Test status
Simulation time	82594735 ps
CPU time	10.69 seconds
Started	Aug 25 12:56:26 AM UTC 24
Finished	Aug 25 12:56:38 AM UTC 24
Peak memory	211684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706659637 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.2706659637
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/30.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_same_source.3541961217
Short name	T541
Test name
Test status
Simulation time	36781851 ps
CPU time	4.02 seconds
Started	Aug 25 12:56:30 AM UTC 24
Finished	Aug 25 12:56:35 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541961217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.3541961217
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/30.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke.2345569899
Short name	T532
Test name
Test status
Simulation time	115463642 ps
CPU time	1.91 seconds
Started	Aug 25 12:56:23 AM UTC 24
Finished	Aug 25 12:56:26 AM UTC 24
Peak memory	211136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345569899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2345569899
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/30.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_large_delays.3204764768
Short name	T547
Test name
Test status
Simulation time	4667368737 ps
CPU time	13.62 seconds
Started	Aug 25 12:56:24 AM UTC 24
Finished	Aug 25 12:56:39 AM UTC 24
Peak memory	212388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204764768 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.3204764768
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/30.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2589329442
Short name	T539
Test name
Test status
Simulation time	969398896 ps
CPU time	7.64 seconds
Started	Aug 25 12:56:25 AM UTC 24
Finished	Aug 25 12:56:33 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589329442 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2589329442
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/30.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.4197475397
Short name	T531
Test name
Test status
Simulation time	8343679 ps
CPU time	1.67 seconds
Started	Aug 25 12:56:23 AM UTC 24
Finished	Aug 25 12:56:26 AM UTC 24
Peak memory	211132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197475397 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.4197475397
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/30.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all.1703745669
Short name	T586
Test name
Test status
Simulation time	162680993 ps
CPU time	27.63 seconds
Started	Aug 25 12:56:33 AM UTC 24
Finished	Aug 25 12:57:02 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703745669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1703745669
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/30.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_error.2343733377
Short name	T571
Test name
Test status
Simulation time	212795332 ps
CPU time	20.25 seconds
Started	Aug 25 12:56:33 AM UTC 24
Finished	Aug 25 12:56:54 AM UTC 24
Peak memory	212136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343733377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2343733377
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/30.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.4002451857
Short name	T691
Test name
Test status
Simulation time	567687555 ps
CPU time	95.78 seconds
Started	Aug 25 12:56:33 AM UTC 24
Finished	Aug 25 12:58:11 AM UTC 24
Peak memory	213928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002451857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.4002451857
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/30.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.1794849154
Short name	T833
Test name
Test status
Simulation time	25038005026 ps
CPU time	218.1 seconds
Started	Aug 25 12:56:34 AM UTC 24
Finished	Aug 25 01:00:16 AM UTC 24
Peak memory	216284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794849154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.1794849154
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/30.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_unmapped_addr.2145855081
Short name	T545
Test name
Test status
Simulation time	577823645 ps
CPU time	5.76 seconds
Started	Aug 25 12:56:32 AM UTC 24
Finished	Aug 25 12:56:38 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145855081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2145855081
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/30.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device.2767169059
Short name	T554
Test name
Test status
Simulation time	49999462 ps
CPU time	2.51 seconds
Started	Aug 25 12:56:39 AM UTC 24
Finished	Aug 25 12:56:43 AM UTC 24
Peak memory	212328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767169059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.2767169059
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/31.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2863099502
Short name	T231
Test name
Test status
Simulation time	23948857704 ps
CPU time	182.14 seconds
Started	Aug 25 12:56:39 AM UTC 24
Finished	Aug 25 12:59:44 AM UTC 24
Peak memory	214504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863099502 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.2863099502
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/31.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.4134832371
Short name	T556
Test name
Test status
Simulation time	52358431 ps
CPU time	3.05 seconds
Started	Aug 25 12:56:41 AM UTC 24
Finished	Aug 25 12:56:45 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134832371 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.4134832371
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/31.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_error_random.510758780
Short name	T560
Test name
Test status
Simulation time	166565437 ps
CPU time	5.06 seconds
Started	Aug 25 12:56:40 AM UTC 24
Finished	Aug 25 12:56:47 AM UTC 24
Peak memory	212008 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510758780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.510758780
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/31.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random.812253048
Short name	T563
Test name
Test status
Simulation time	552446433 ps
CPU time	9.24 seconds
Started	Aug 25 12:56:38 AM UTC 24
Finished	Aug 25 12:56:48 AM UTC 24
Peak memory	211884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812253048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.812253048
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/31.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_large_delays.4288929919
Short name	T606
Test name
Test status
Simulation time	5307665624 ps
CPU time	33.53 seconds
Started	Aug 25 12:56:39 AM UTC 24
Finished	Aug 25 12:57:14 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288929919 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.4288929919
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/31.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_slow_rsp.567581279
Short name	T831
Test name
Test status
Simulation time	26621628377 ps
CPU time	213.47 seconds
Started	Aug 25 12:56:39 AM UTC 24
Finished	Aug 25 01:00:16 AM UTC 24
Peak memory	212200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567581279 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.567581279
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/31.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_zero_delays.2454841357
Short name	T558
Test name
Test status
Simulation time	62195219 ps
CPU time	6.45 seconds
Started	Aug 25 12:56:38 AM UTC 24
Finished	Aug 25 12:56:45 AM UTC 24
Peak memory	211808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454841357 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.2454841357
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/31.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_same_source.3576714800
Short name	T570
Test name
Test status
Simulation time	2859090521 ps
CPU time	12.8 seconds
Started	Aug 25 12:56:40 AM UTC 24
Finished	Aug 25 12:56:54 AM UTC 24
Peak memory	211856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576714800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.3576714800
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/31.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke.3639605238
Short name	T544
Test name
Test status
Simulation time	175404512 ps
CPU time	2.41 seconds
Started	Aug 25 12:56:34 AM UTC 24
Finished	Aug 25 12:56:38 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639605238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.3639605238
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/31.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_large_delays.2342647402
Short name	T41
Test name
Test status
Simulation time	1781908272 ps
CPU time	15.09 seconds
Started	Aug 25 12:56:35 AM UTC 24
Finished	Aug 25 12:56:52 AM UTC 24
Peak memory	212136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342647402 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.2342647402
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/31.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.2916100662
Short name	T566
Test name
Test status
Simulation time	934279148 ps
CPU time	12.22 seconds
Started	Aug 25 12:56:37 AM UTC 24
Finished	Aug 25 12:56:50 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916100662 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2916100662
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/31.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.3345430577
Short name	T542
Test name
Test status
Simulation time	8600128 ps
CPU time	1.66 seconds
Started	Aug 25 12:56:34 AM UTC 24
Finished	Aug 25 12:56:37 AM UTC 24
Peak memory	211176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345430577 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.3345430577
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/31.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all.2910353688
Short name	T567
Test name
Test status
Simulation time	78465114 ps
CPU time	8.57 seconds
Started	Aug 25 12:56:41 AM UTC 24
Finished	Aug 25 12:56:50 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910353688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.2910353688
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/31.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_error.2627549102
Short name	T698
Test name
Test status
Simulation time	8495080642 ps
CPU time	93.35 seconds
Started	Aug 25 12:56:42 AM UTC 24
Finished	Aug 25 12:58:18 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627549102 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.2627549102
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/31.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.4196761901
Short name	T191
Test name
Test status
Simulation time	6303398165 ps
CPU time	177.88 seconds
Started	Aug 25 12:56:41 AM UTC 24
Finished	Aug 25 12:59:42 AM UTC 24
Peak memory	216292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196761901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.4196761901
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/31.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.3187058432
Short name	T648
Test name
Test status
Simulation time	554381364 ps
CPU time	59.39 seconds
Started	Aug 25 12:56:42 AM UTC 24
Finished	Aug 25 12:57:43 AM UTC 24
Peak memory	214172 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187058432 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.3187058432
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/31.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_unmapped_addr.851738639
Short name	T576
Test name
Test status
Simulation time	940849158 ps
CPU time	13.61 seconds
Started	Aug 25 12:56:41 AM UTC 24
Finished	Aug 25 12:56:55 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851738639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.851738639
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/31.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device.2354156461
Short name	T580
Test name
Test status
Simulation time	75047210 ps
CPU time	9.28 seconds
Started	Aug 25 12:56:47 AM UTC 24
Finished	Aug 25 12:56:57 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354156461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.2354156461
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/32.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.3915587892
Short name	T892
Test name
Test status
Simulation time	41792857051 ps
CPU time	499.22 seconds
Started	Aug 25 12:56:47 AM UTC 24
Finished	Aug 25 01:05:13 AM UTC 24
Peak memory	214244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915587892 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.3915587892
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/32.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.207425528
Short name	T578
Test name
Test status
Simulation time	303427869 ps
CPU time	5.41 seconds
Started	Aug 25 12:56:50 AM UTC 24
Finished	Aug 25 12:56:56 AM UTC 24
Peak memory	212328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207425528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.207425528
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/32.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_error_random.1138168858
Short name	T575
Test name
Test status
Simulation time	49821682 ps
CPU time	5.68 seconds
Started	Aug 25 12:56:48 AM UTC 24
Finished	Aug 25 12:56:55 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138168858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1138168858
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/32.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random.3091053670
Short name	T569
Test name
Test status
Simulation time	1014565875 ps
CPU time	6.01 seconds
Started	Aug 25 12:56:46 AM UTC 24
Finished	Aug 25 12:56:53 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091053670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.3091053670
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/32.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.101124244
Short name	T624
Test name
Test status
Simulation time	13639693859 ps
CPU time	39.14 seconds
Started	Aug 25 12:56:46 AM UTC 24
Finished	Aug 25 12:57:27 AM UTC 24
Peak memory	212184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101124244 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.101124244
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/32.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.3922522128
Short name	T825
Test name
Test status
Simulation time	18549438252 ps
CPU time	201.99 seconds
Started	Aug 25 12:56:47 AM UTC 24
Finished	Aug 25 01:00:12 AM UTC 24
Peak memory	212524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922522128 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3922522128
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/32.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_zero_delays.2989105866
Short name	T568
Test name
Test status
Simulation time	32577810 ps
CPU time	5.81 seconds
Started	Aug 25 12:56:46 AM UTC 24
Finished	Aug 25 12:56:53 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989105866 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.2989105866
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/32.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_same_source.3285247274
Short name	T572
Test name
Test status
Simulation time	192807159 ps
CPU time	5.09 seconds
Started	Aug 25 12:56:48 AM UTC 24
Finished	Aug 25 12:56:55 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285247274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3285247274
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/32.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke.4276896395
Short name	T557
Test name
Test status
Simulation time	11051670 ps
CPU time	1.61 seconds
Started	Aug 25 12:56:42 AM UTC 24
Finished	Aug 25 12:56:45 AM UTC 24
Peak memory	211136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276896395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.4276896395
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/32.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_large_delays.4101629349
Short name	T585
Test name
Test status
Simulation time	5333390874 ps
CPU time	17.33 seconds
Started	Aug 25 12:56:43 AM UTC 24
Finished	Aug 25 12:57:02 AM UTC 24
Peak memory	212200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101629349 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.4101629349
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/32.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.755398583
Short name	T582
Test name
Test status
Simulation time	9959737750 ps
CPU time	15.35 seconds
Started	Aug 25 12:56:45 AM UTC 24
Finished	Aug 25 12:57:01 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755398583 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.755398583
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/32.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.4226109032
Short name	T559
Test name
Test status
Simulation time	34355030 ps
CPU time	1.8 seconds
Started	Aug 25 12:56:43 AM UTC 24
Finished	Aug 25 12:56:46 AM UTC 24
Peak memory	211132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226109032 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.4226109032
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/32.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all.1177996406
Short name	T608
Test name
Test status
Simulation time	697720380 ps
CPU time	22.78 seconds
Started	Aug 25 12:56:51 AM UTC 24
Finished	Aug 25 12:57:15 AM UTC 24
Peak memory	214176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177996406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1177996406
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/32.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_error.4147987730
Short name	T618
Test name
Test status
Simulation time	437927230 ps
CPU time	30.01 seconds
Started	Aug 25 12:56:51 AM UTC 24
Finished	Aug 25 12:57:22 AM UTC 24
Peak memory	214180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147987730 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.4147987730
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/32.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.911717856
Short name	T742
Test name
Test status
Simulation time	3362727804 ps
CPU time	114.61 seconds
Started	Aug 25 12:56:51 AM UTC 24
Finished	Aug 25 12:58:48 AM UTC 24
Peak memory	216424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911717856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.911717856
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/32.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.4228052885
Short name	T616
Test name
Test status
Simulation time	928901626 ps
CPU time	29.33 seconds
Started	Aug 25 12:56:51 AM UTC 24
Finished	Aug 25 12:57:22 AM UTC 24
Peak memory	214172 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228052885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.4228052885
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/32.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_unmapped_addr.301216294
Short name	T579
Test name
Test status
Simulation time	44974956 ps
CPU time	6.78 seconds
Started	Aug 25 12:56:50 AM UTC 24
Finished	Aug 25 12:56:57 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301216294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.301216294
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/32.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device.580722076
Short name	T592
Test name
Test status
Simulation time	587273568 ps
CPU time	8.93 seconds
Started	Aug 25 12:56:56 AM UTC 24
Finished	Aug 25 12:57:06 AM UTC 24
Peak memory	212136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580722076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.580722076
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/33.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.3572852023
Short name	T595
Test name
Test status
Simulation time	89935279 ps
CPU time	7.32 seconds
Started	Aug 25 12:56:59 AM UTC 24
Finished	Aug 25 12:57:07 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572852023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.3572852023
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/33.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_error_random.3319661829
Short name	T594
Test name
Test status
Simulation time	330007623 ps
CPU time	8.33 seconds
Started	Aug 25 12:56:57 AM UTC 24
Finished	Aug 25 12:57:07 AM UTC 24
Peak memory	212136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319661829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3319661829
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/33.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random.706959247
Short name	T610
Test name
Test status
Simulation time	820472853 ps
CPU time	19.01 seconds
Started	Aug 25 12:56:56 AM UTC 24
Finished	Aug 25 12:57:16 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706959247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.706959247
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/33.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_large_delays.2001112459
Short name	T150
Test name
Test status
Simulation time	59284207155 ps
CPU time	307.78 seconds
Started	Aug 25 12:56:56 AM UTC 24
Finished	Aug 25 01:02:08 AM UTC 24
Peak memory	212200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001112459 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2001112459
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/33.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_slow_rsp.2363424013
Short name	T634
Test name
Test status
Simulation time	14142309318 ps
CPU time	36.58 seconds
Started	Aug 25 12:56:56 AM UTC 24
Finished	Aug 25 12:57:34 AM UTC 24
Peak memory	212460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363424013 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.2363424013
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/33.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_zero_delays.1916869001
Short name	T584
Test name
Test status
Simulation time	47484501 ps
CPU time	4.24 seconds
Started	Aug 25 12:56:56 AM UTC 24
Finished	Aug 25 12:57:01 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916869001 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.1916869001
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/33.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_same_source.656239287
Short name	T587
Test name
Test status
Simulation time	75382386 ps
CPU time	4.49 seconds
Started	Aug 25 12:56:57 AM UTC 24
Finished	Aug 25 12:57:03 AM UTC 24
Peak memory	212120 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656239287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.656239287
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/33.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke.208517130
Short name	T573
Test name
Test status
Simulation time	14130702 ps
CPU time	1.74 seconds
Started	Aug 25 12:56:52 AM UTC 24
Finished	Aug 25 12:56:55 AM UTC 24
Peak memory	211136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208517130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.208517130
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/33.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_large_delays.3214347763
Short name	T605
Test name
Test status
Simulation time	2046809875 ps
CPU time	18.63 seconds
Started	Aug 25 12:56:53 AM UTC 24
Finished	Aug 25 12:57:13 AM UTC 24
Peak memory	212328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214347763 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.3214347763
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/33.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.2566073454
Short name	T599
Test name
Test status
Simulation time	1380842556 ps
CPU time	13.52 seconds
Started	Aug 25 12:56:56 AM UTC 24
Finished	Aug 25 12:57:11 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566073454 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.2566073454
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/33.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.3826869433
Short name	T577
Test name
Test status
Simulation time	9316672 ps
CPU time	1.54 seconds
Started	Aug 25 12:56:53 AM UTC 24
Finished	Aug 25 12:56:56 AM UTC 24
Peak memory	211236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826869433 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.3826869433
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/33.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all.2889129580
Short name	T625
Test name
Test status
Simulation time	178679489 ps
CPU time	26.04 seconds
Started	Aug 25 12:57:00 AM UTC 24
Finished	Aug 25 12:57:27 AM UTC 24
Peak memory	214176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889129580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.2889129580
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/33.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_error.1327408120
Short name	T613
Test name
Test status
Simulation time	299914596 ps
CPU time	16.17 seconds
Started	Aug 25 12:57:02 AM UTC 24
Finished	Aug 25 12:57:19 AM UTC 24
Peak memory	212136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327408120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.1327408120
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/33.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.2501134181
Short name	T853
Test name
Test status
Simulation time	18386845522 ps
CPU time	212.57 seconds
Started	Aug 25 12:57:02 AM UTC 24
Finished	Aug 25 01:00:38 AM UTC 24
Peak memory	216292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501134181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.2501134181
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/33.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.2396942086
Short name	T626
Test name
Test status
Simulation time	298807381 ps
CPU time	24.14 seconds
Started	Aug 25 12:57:02 AM UTC 24
Finished	Aug 25 12:57:27 AM UTC 24
Peak memory	214176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396942086 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.2396942086
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/33.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_unmapped_addr.1172026807
Short name	T593
Test name
Test status
Simulation time	82258612 ps
CPU time	6.89 seconds
Started	Aug 25 12:56:59 AM UTC 24
Finished	Aug 25 12:57:07 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172026807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.1172026807
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/33.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device.3798685476
Short name	T632
Test name
Test status
Simulation time	1809095916 ps
CPU time	22.45 seconds
Started	Aug 25 12:57:08 AM UTC 24
Finished	Aug 25 12:57:31 AM UTC 24
Peak memory	212136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798685476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.3798685476
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/34.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.1910560098
Short name	T258
Test name
Test status
Simulation time	8925715809 ps
CPU time	86.12 seconds
Started	Aug 25 12:57:08 AM UTC 24
Finished	Aug 25 12:58:36 AM UTC 24
Peak memory	212264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910560098 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.1910560098
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/34.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.3435433433
Short name	T612
Test name
Test status
Simulation time	818413499 ps
CPU time	8.87 seconds
Started	Aug 25 12:57:09 AM UTC 24
Finished	Aug 25 12:57:19 AM UTC 24
Peak memory	212388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435433433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.3435433433
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/34.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_error_random.3294396832
Short name	T600
Test name
Test status
Simulation time	112371090 ps
CPU time	2.87 seconds
Started	Aug 25 12:57:08 AM UTC 24
Finished	Aug 25 12:57:12 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294396832 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.3294396832
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/34.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random.2599596031
Short name	T601
Test name
Test status
Simulation time	1027058220 ps
CPU time	6.14 seconds
Started	Aug 25 12:57:05 AM UTC 24
Finished	Aug 25 12:57:12 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599596031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.2599596031
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/34.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.786371576
Short name	T790
Test name
Test status
Simulation time	49006352132 ps
CPU time	154.74 seconds
Started	Aug 25 12:57:07 AM UTC 24
Finished	Aug 25 12:59:45 AM UTC 24
Peak memory	212448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786371576 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.786371576
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/34.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_slow_rsp.4165832092
Short name	T784
Test name
Test status
Simulation time	35628585736 ps
CPU time	144.03 seconds
Started	Aug 25 12:57:07 AM UTC 24
Finished	Aug 25 12:59:34 AM UTC 24
Peak memory	212524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165832092 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.4165832092
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/34.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_zero_delays.4221443797
Short name	T603
Test name
Test status
Simulation time	115854433 ps
CPU time	6.02 seconds
Started	Aug 25 12:57:06 AM UTC 24
Finished	Aug 25 12:57:13 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221443797 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.4221443797
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/34.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_same_source.577832978
Short name	T602
Test name
Test status
Simulation time	74919656 ps
CPU time	3.35 seconds
Started	Aug 25 12:57:08 AM UTC 24
Finished	Aug 25 12:57:12 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577832978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.577832978
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/34.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke.127287687
Short name	T591
Test name
Test status
Simulation time	48331941 ps
CPU time	1.97 seconds
Started	Aug 25 12:57:03 AM UTC 24
Finished	Aug 25 12:57:06 AM UTC 24
Peak memory	211244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127287687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.127287687
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/34.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_large_delays.4240380173
Short name	T623
Test name
Test status
Simulation time	5945836712 ps
CPU time	20.04 seconds
Started	Aug 25 12:57:05 AM UTC 24
Finished	Aug 25 12:57:26 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240380173 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.4240380173
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/34.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.3729076896
Short name	T619
Test name
Test status
Simulation time	1808455885 ps
CPU time	17.13 seconds
Started	Aug 25 12:57:05 AM UTC 24
Finished	Aug 25 12:57:23 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729076896 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3729076896
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/34.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.1760980685
Short name	T590
Test name
Test status
Simulation time	12685107 ps
CPU time	1.68 seconds
Started	Aug 25 12:57:03 AM UTC 24
Finished	Aug 25 12:57:06 AM UTC 24
Peak memory	211236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760980685 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.1760980685
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/34.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all.1728739501
Short name	T643
Test name
Test status
Simulation time	477750706 ps
CPU time	52.19 seconds
Started	Aug 25 12:57:09 AM UTC 24
Finished	Aug 25 12:58:03 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728739501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1728739501
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/34.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_error.1532820318
Short name	T658
Test name
Test status
Simulation time	1367553151 ps
CPU time	35.38 seconds
Started	Aug 25 12:57:11 AM UTC 24
Finished	Aug 25 12:57:48 AM UTC 24
Peak memory	212136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532820318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1532820318
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/34.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.1903524766
Short name	T722
Test name
Test status
Simulation time	456352363 ps
CPU time	82.71 seconds
Started	Aug 25 12:57:09 AM UTC 24
Finished	Aug 25 12:58:34 AM UTC 24
Peak memory	216228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903524766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.1903524766
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/34.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.1922165818
Short name	T820
Test name
Test status
Simulation time	1614564304 ps
CPU time	171.68 seconds
Started	Aug 25 12:57:12 AM UTC 24
Finished	Aug 25 01:00:06 AM UTC 24
Peak memory	216220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922165818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.1922165818
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/34.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_unmapped_addr.3831267014
Short name	T598
Test name
Test status
Simulation time	18467024 ps
CPU time	1.8 seconds
Started	Aug 25 12:57:08 AM UTC 24
Finished	Aug 25 12:57:10 AM UTC 24
Peak memory	211240 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831267014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3831267014
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/34.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device.792903230
Short name	T628
Test name
Test status
Simulation time	1432928648 ps
CPU time	12.78 seconds
Started	Aug 25 12:57:16 AM UTC 24
Finished	Aug 25 12:57:30 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792903230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.792903230
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/35.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.3956933963
Short name	T144
Test name
Test status
Simulation time	57778660352 ps
CPU time	606.79 seconds
Started	Aug 25 12:57:16 AM UTC 24
Finished	Aug 25 01:07:30 AM UTC 24
Peak memory	218204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956933963 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.3956933963
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/35.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1832036481
Short name	T615
Test name
Test status
Simulation time	26781177 ps
CPU time	2.52 seconds
Started	Aug 25 12:57:17 AM UTC 24
Finished	Aug 25 12:57:21 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832036481 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.1832036481
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/35.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_error_random.3438552177
Short name	T631
Test name
Test status
Simulation time	3365339169 ps
CPU time	13.09 seconds
Started	Aug 25 12:57:17 AM UTC 24
Finished	Aug 25 12:57:31 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438552177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3438552177
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/35.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random.1550657556
Short name	T635
Test name
Test status
Simulation time	3082704983 ps
CPU time	19.91 seconds
Started	Aug 25 12:57:13 AM UTC 24
Finished	Aug 25 12:57:34 AM UTC 24
Peak memory	212384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550657556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.1550657556
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/35.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.2565746439
Short name	T857
Test name
Test status
Simulation time	64086732292 ps
CPU time	209.39 seconds
Started	Aug 25 12:57:14 AM UTC 24
Finished	Aug 25 01:00:47 AM UTC 24
Peak memory	212388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565746439 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.2565746439
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/35.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.503163805
Short name	T209
Test name
Test status
Simulation time	17659491030 ps
CPU time	143.7 seconds
Started	Aug 25 12:57:14 AM UTC 24
Finished	Aug 25 12:59:41 AM UTC 24
Peak memory	212256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503163805 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.503163805
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/35.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_zero_delays.2769760535
Short name	T627
Test name
Test status
Simulation time	116151641 ps
CPU time	11.93 seconds
Started	Aug 25 12:57:14 AM UTC 24
Finished	Aug 25 12:57:27 AM UTC 24
Peak memory	212024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769760535 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.2769760535
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/35.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_same_source.972294431
Short name	T611
Test name
Test status
Simulation time	14840638 ps
CPU time	2.48 seconds
Started	Aug 25 12:57:16 AM UTC 24
Finished	Aug 25 12:57:19 AM UTC 24
Peak memory	212316 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972294431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.972294431
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/35.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke.2463084222
Short name	T607
Test name
Test status
Simulation time	71953914 ps
CPU time	2.12 seconds
Started	Aug 25 12:57:12 AM UTC 24
Finished	Aug 25 12:57:15 AM UTC 24
Peak memory	212384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463084222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.2463084222
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/35.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1419693711
Short name	T622
Test name
Test status
Simulation time	3209105441 ps
CPU time	10.56 seconds
Started	Aug 25 12:57:13 AM UTC 24
Finished	Aug 25 12:57:25 AM UTC 24
Peak memory	212328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419693711 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1419693711
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/35.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.2565233958
Short name	T629
Test name
Test status
Simulation time	7635937072 ps
CPU time	15.17 seconds
Started	Aug 25 12:57:13 AM UTC 24
Finished	Aug 25 12:57:30 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565233958 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.2565233958
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/35.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.3938579455
Short name	T609
Test name
Test status
Simulation time	11268441 ps
CPU time	1.73 seconds
Started	Aug 25 12:57:13 AM UTC 24
Finished	Aug 25 12:57:16 AM UTC 24
Peak memory	211176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938579455 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.3938579455
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/35.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all.2773760511
Short name	T642
Test name
Test status
Simulation time	194950095 ps
CPU time	18.6 seconds
Started	Aug 25 12:57:17 AM UTC 24
Finished	Aug 25 12:57:37 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773760511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2773760511
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/35.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_error.3140965988
Short name	T640
Test name
Test status
Simulation time	214724641 ps
CPU time	14.68 seconds
Started	Aug 25 12:57:21 AM UTC 24
Finished	Aug 25 12:57:37 AM UTC 24
Peak memory	212136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140965988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3140965988
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/35.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.2852129770
Short name	T706
Test name
Test status
Simulation time	2523485049 ps
CPU time	60.42 seconds
Started	Aug 25 12:57:21 AM UTC 24
Finished	Aug 25 12:58:23 AM UTC 24
Peak memory	214248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852129770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.2852129770
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/35.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.3052687362
Short name	T669
Test name
Test status
Simulation time	289013564 ps
CPU time	35.56 seconds
Started	Aug 25 12:57:21 AM UTC 24
Finished	Aug 25 12:57:58 AM UTC 24
Peak memory	214368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052687362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.3052687362
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/35.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_unmapped_addr.2853450327
Short name	T614
Test name
Test status
Simulation time	19132622 ps
CPU time	1.91 seconds
Started	Aug 25 12:57:17 AM UTC 24
Finished	Aug 25 12:57:20 AM UTC 24
Peak memory	211132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853450327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.2853450327
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/35.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device.1142565106
Short name	T137
Test name
Test status
Simulation time	1319293296 ps
CPU time	14.09 seconds
Started	Aug 25 12:57:26 AM UTC 24
Finished	Aug 25 12:57:41 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142565106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.1142565106
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/36.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.383585286
Short name	T894
Test name
Test status
Simulation time	46640347109 ps
CPU time	484.56 seconds
Started	Aug 25 12:57:27 AM UTC 24
Finished	Aug 25 01:05:38 AM UTC 24
Peak memory	214244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383585286 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.383585286
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/36.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.2593035129
Short name	T646
Test name
Test status
Simulation time	1467854463 ps
CPU time	12.7 seconds
Started	Aug 25 12:57:28 AM UTC 24
Finished	Aug 25 12:57:42 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593035129 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.2593035129
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/36.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_error_random.3103993916
Short name	T630
Test name
Test status
Simulation time	11499126 ps
CPU time	1.44 seconds
Started	Aug 25 12:57:28 AM UTC 24
Finished	Aug 25 12:57:31 AM UTC 24
Peak memory	211244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103993916 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.3103993916
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/36.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random.3761573373
Short name	T639
Test name
Test status
Simulation time	488590745 ps
CPU time	11.78 seconds
Started	Aug 25 12:57:23 AM UTC 24
Finished	Aug 25 12:57:36 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761573373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.3761573373
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/36.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.2397740169
Short name	T872
Test name
Test status
Simulation time	147661015840 ps
CPU time	265.28 seconds
Started	Aug 25 12:57:25 AM UTC 24
Finished	Aug 25 01:01:54 AM UTC 24
Peak memory	212456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397740169 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2397740169
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/36.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.1029272122
Short name	T139
Test name
Test status
Simulation time	29933469743 ps
CPU time	237.72 seconds
Started	Aug 25 12:57:25 AM UTC 24
Finished	Aug 25 01:01:26 AM UTC 24
Peak memory	212396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029272122 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.1029272122
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/36.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_zero_delays.3903688521
Short name	T636
Test name
Test status
Simulation time	277024012 ps
CPU time	8.97 seconds
Started	Aug 25 12:57:24 AM UTC 24
Finished	Aug 25 12:57:35 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903688521 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.3903688521
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/36.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_same_source.3557772474
Short name	T647
Test name
Test status
Simulation time	695230462 ps
CPU time	13.56 seconds
Started	Aug 25 12:57:28 AM UTC 24
Finished	Aug 25 12:57:43 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557772474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3557772474
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/36.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke.2927410571
Short name	T620
Test name
Test status
Simulation time	77019575 ps
CPU time	1.74 seconds
Started	Aug 25 12:57:21 AM UTC 24
Finished	Aug 25 12:57:24 AM UTC 24
Peak memory	211240 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927410571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.2927410571
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/36.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_large_delays.1473764196
Short name	T644
Test name
Test status
Simulation time	9680519096 ps
CPU time	17.16 seconds
Started	Aug 25 12:57:22 AM UTC 24
Finished	Aug 25 12:57:40 AM UTC 24
Peak memory	212200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473764196 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.1473764196
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/36.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.3654211220
Short name	T641
Test name
Test status
Simulation time	936463464 ps
CPU time	12.6 seconds
Started	Aug 25 12:57:23 AM UTC 24
Finished	Aug 25 12:57:37 AM UTC 24
Peak memory	212324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654211220 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3654211220
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/36.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.1478193013
Short name	T621
Test name
Test status
Simulation time	14079309 ps
CPU time	1.82 seconds
Started	Aug 25 12:57:21 AM UTC 24
Finished	Aug 25 12:57:24 AM UTC 24
Peak memory	211132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478193013 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.1478193013
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/36.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all.1801597637
Short name	T679
Test name
Test status
Simulation time	884480821 ps
CPU time	31.12 seconds
Started	Aug 25 12:57:30 AM UTC 24
Finished	Aug 25 12:58:03 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801597637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.1801597637
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/36.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_error.619431382
Short name	T694
Test name
Test status
Simulation time	3188103491 ps
CPU time	42.15 seconds
Started	Aug 25 12:57:32 AM UTC 24
Finished	Aug 25 12:58:16 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619431382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.619431382
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/36.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2107455244
Short name	T772
Test name
Test status
Simulation time	1228662361 ps
CPU time	108.76 seconds
Started	Aug 25 12:57:30 AM UTC 24
Finished	Aug 25 12:59:22 AM UTC 24
Peak memory	214180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107455244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.2107455244
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/36.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.1975556359
Short name	T685
Test name
Test status
Simulation time	789268181 ps
CPU time	35.43 seconds
Started	Aug 25 12:57:33 AM UTC 24
Finished	Aug 25 12:58:10 AM UTC 24
Peak memory	211724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975556359 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.1975556359
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/36.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_unmapped_addr.2443555078
Short name	T650
Test name
Test status
Simulation time	700660314 ps
CPU time	15.69 seconds
Started	Aug 25 12:57:28 AM UTC 24
Finished	Aug 25 12:57:45 AM UTC 24
Peak memory	212388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443555078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2443555078
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/36.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device.3084603200
Short name	T657
Test name
Test status
Simulation time	98898863 ps
CPU time	8.32 seconds
Started	Aug 25 12:57:38 AM UTC 24
Finished	Aug 25 12:57:48 AM UTC 24
Peak memory	212348 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084603200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.3084603200
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/37.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1263613618
Short name	T226
Test name
Test status
Simulation time	29194634533 ps
CPU time	220.28 seconds
Started	Aug 25 12:57:38 AM UTC 24
Finished	Aug 25 01:01:22 AM UTC 24
Peak memory	214248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263613618 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.1263613618
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/37.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.3434267981
Short name	T660
Test name
Test status
Simulation time	83814019 ps
CPU time	7.49 seconds
Started	Aug 25 12:57:41 AM UTC 24
Finished	Aug 25 12:57:50 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434267981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.3434267981
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/37.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_error_random.3289540640
Short name	T654
Test name
Test status
Simulation time	254093024 ps
CPU time	6.67 seconds
Started	Aug 25 12:57:38 AM UTC 24
Finished	Aug 25 12:57:46 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289540640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.3289540640
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/37.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random.1309979662
Short name	T171
Test name
Test status
Simulation time	1747314807 ps
CPU time	13.9 seconds
Started	Aug 25 12:57:35 AM UTC 24
Finished	Aug 25 12:57:50 AM UTC 24
Peak memory	212120 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309979662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.1309979662
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/37.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.2715764023
Short name	T149
Test name
Test status
Simulation time	49777706120 ps
CPU time	148.36 seconds
Started	Aug 25 12:57:36 AM UTC 24
Finished	Aug 25 01:00:08 AM UTC 24
Peak memory	212264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715764023 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2715764023
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/37.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.2344201481
Short name	T183
Test name
Test status
Simulation time	7875310550 ps
CPU time	30.87 seconds
Started	Aug 25 12:57:36 AM UTC 24
Finished	Aug 25 12:58:09 AM UTC 24
Peak memory	212188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344201481 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2344201481
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/37.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_zero_delays.3958640391
Short name	T649
Test name
Test status
Simulation time	41988487 ps
CPU time	5.22 seconds
Started	Aug 25 12:57:36 AM UTC 24
Finished	Aug 25 12:57:43 AM UTC 24
Peak memory	212012 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958640391 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.3958640391
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/37.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_same_source.2666485834
Short name	T663
Test name
Test status
Simulation time	2682161494 ps
CPU time	15.98 seconds
Started	Aug 25 12:57:38 AM UTC 24
Finished	Aug 25 12:57:56 AM UTC 24
Peak memory	212328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666485834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2666485834
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/37.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke.2199674573
Short name	T638
Test name
Test status
Simulation time	23659321 ps
CPU time	1.77 seconds
Started	Aug 25 12:57:33 AM UTC 24
Finished	Aug 25 12:57:36 AM UTC 24
Peak memory	210748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199674573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2199674573
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/37.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_large_delays.1422900667
Short name	T675
Test name
Test status
Simulation time	5958883180 ps
CPU time	24.68 seconds
Started	Aug 25 12:57:35 AM UTC 24
Finished	Aug 25 12:58:01 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422900667 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1422900667
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/37.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.948406997
Short name	T659
Test name
Test status
Simulation time	2857122721 ps
CPU time	13.67 seconds
Started	Aug 25 12:57:35 AM UTC 24
Finished	Aug 25 12:57:50 AM UTC 24
Peak memory	212336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948406997 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.948406997
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/37.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3313529259
Short name	T637
Test name
Test status
Simulation time	9575298 ps
CPU time	1.66 seconds
Started	Aug 25 12:57:33 AM UTC 24
Finished	Aug 25 12:57:36 AM UTC 24
Peak memory	211176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313529259 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.3313529259
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/37.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.2199630034
Short name	T690
Test name
Test status
Simulation time	1647707035 ps
CPU time	26.92 seconds
Started	Aug 25 12:57:42 AM UTC 24
Finished	Aug 25 12:58:11 AM UTC 24
Peak memory	214180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199630034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.2199630034
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/37.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_error.3092861297
Short name	T653
Test name
Test status
Simulation time	16946448 ps
CPU time	1.5 seconds
Started	Aug 25 12:57:43 AM UTC 24
Finished	Aug 25 12:57:46 AM UTC 24
Peak memory	211244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092861297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.3092861297
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/37.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.4292554141
Short name	T769
Test name
Test status
Simulation time	3108800246 ps
CPU time	93.68 seconds
Started	Aug 25 12:57:42 AM UTC 24
Finished	Aug 25 12:59:18 AM UTC 24
Peak memory	216292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292554141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.4292554141
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/37.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3737224035
Short name	T774
Test name
Test status
Simulation time	761161382 ps
CPU time	97.46 seconds
Started	Aug 25 12:57:44 AM UTC 24
Finished	Aug 25 12:59:23 AM UTC 24
Peak memory	216220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737224035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.3737224035
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/37.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_unmapped_addr.3538925462
Short name	T652
Test name
Test status
Simulation time	377877723 ps
CPU time	6.24 seconds
Started	Aug 25 12:57:38 AM UTC 24
Finished	Aug 25 12:57:46 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538925462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.3538925462
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/37.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device.2518260756
Short name	T665
Test name
Test status
Simulation time	997066663 ps
CPU time	6.41 seconds
Started	Aug 25 12:57:48 AM UTC 24
Finished	Aug 25 12:57:56 AM UTC 24
Peak memory	212136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518260756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.2518260756
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/38.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.2608679237
Short name	T888
Test name
Test status
Simulation time	30218919248 ps
CPU time	398.62 seconds
Started	Aug 25 12:57:50 AM UTC 24
Finished	Aug 25 01:04:35 AM UTC 24
Peak memory	214248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608679237 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.2608679237
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/38.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.862737516
Short name	T666
Test name
Test status
Simulation time	228462739 ps
CPU time	3.74 seconds
Started	Aug 25 12:57:51 AM UTC 24
Finished	Aug 25 12:57:56 AM UTC 24
Peak memory	212328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862737516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.862737516
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/38.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_error_random.3518296779
Short name	T671
Test name
Test status
Simulation time	1311684701 ps
CPU time	6.06 seconds
Started	Aug 25 12:57:51 AM UTC 24
Finished	Aug 25 12:57:58 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518296779 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.3518296779
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/38.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random.643997427
Short name	T670
Test name
Test status
Simulation time	1425348784 ps
CPU time	17.07 seconds
Started	Aug 25 12:57:47 AM UTC 24
Finished	Aug 25 12:58:06 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643997427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.643997427
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/38.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.3338019923
Short name	T881
Test name
Test status
Simulation time	36080315067 ps
CPU time	308.87 seconds
Started	Aug 25 12:57:47 AM UTC 24
Finished	Aug 25 01:03:01 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338019923 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.3338019923
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/38.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.3374241580
Short name	T708
Test name
Test status
Simulation time	5990901870 ps
CPU time	35.42 seconds
Started	Aug 25 12:57:48 AM UTC 24
Finished	Aug 25 12:58:25 AM UTC 24
Peak memory	212204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374241580 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.3374241580
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/38.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_zero_delays.1712593530
Short name	T661
Test name
Test status
Simulation time	13102115 ps
CPU time	2.2 seconds
Started	Aug 25 12:57:47 AM UTC 24
Finished	Aug 25 12:57:50 AM UTC 24
Peak memory	212072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712593530 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.1712593530
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/38.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_same_source.2500304892
Short name	T673
Test name
Test status
Simulation time	1514930154 ps
CPU time	8.64 seconds
Started	Aug 25 12:57:50 AM UTC 24
Finished	Aug 25 12:57:59 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500304892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.2500304892
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/38.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke.729681183
Short name	T656
Test name
Test status
Simulation time	88257047 ps
CPU time	1.98 seconds
Started	Aug 25 12:57:45 AM UTC 24
Finished	Aug 25 12:57:48 AM UTC 24
Peak memory	211140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729681183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.729681183
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/38.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_large_delays.33058896
Short name	T667
Test name
Test status
Simulation time	3772110685 ps
CPU time	9.98 seconds
Started	Aug 25 12:57:46 AM UTC 24
Finished	Aug 25 12:57:57 AM UTC 24
Peak memory	212388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33058896 -assert nopostproc +UVM_TESTNAME=xbar_base_ test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.33058896
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/38.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.1256052632
Short name	T617
Test name
Test status
Simulation time	2561504690 ps
CPU time	17.66 seconds
Started	Aug 25 12:57:47 AM UTC 24
Finished	Aug 25 12:58:06 AM UTC 24
Peak memory	212388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256052632 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.1256052632
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/38.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.2442064825
Short name	T655
Test name
Test status
Simulation time	10922495 ps
CPU time	1.62 seconds
Started	Aug 25 12:57:45 AM UTC 24
Finished	Aug 25 12:57:48 AM UTC 24
Peak memory	211232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442064825 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.2442064825
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/38.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.2862352573
Short name	T668
Test name
Test status
Simulation time	28028183 ps
CPU time	4.41 seconds
Started	Aug 25 12:57:52 AM UTC 24
Finished	Aug 25 12:57:58 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862352573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.2862352573
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/38.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.942159656
Short name	T749
Test name
Test status
Simulation time	6887954599 ps
CPU time	54.21 seconds
Started	Aug 25 12:57:56 AM UTC 24
Finished	Aug 25 12:58:53 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942159656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.942159656
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/38.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.1220469462
Short name	T730
Test name
Test status
Simulation time	1054457493 ps
CPU time	46.84 seconds
Started	Aug 25 12:57:52 AM UTC 24
Finished	Aug 25 12:58:41 AM UTC 24
Peak memory	214244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220469462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.1220469462
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/38.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.1687564398
Short name	T834
Test name
Test status
Simulation time	1429058501 ps
CPU time	138.26 seconds
Started	Aug 25 12:57:56 AM UTC 24
Finished	Aug 25 01:00:18 AM UTC 24
Peak memory	218272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687564398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.1687564398
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/38.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_unmapped_addr.4159018069
Short name	T664
Test name
Test status
Simulation time	91315309 ps
CPU time	3.71 seconds
Started	Aug 25 12:57:51 AM UTC 24
Finished	Aug 25 12:57:56 AM UTC 24
Peak memory	212324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159018069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.4159018069
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/38.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device.2882648615
Short name	T678
Test name
Test status
Simulation time	10687162 ps
CPU time	1.65 seconds
Started	Aug 25 12:58:00 AM UTC 24
Finished	Aug 25 12:58:03 AM UTC 24
Peak memory	211244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882648615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.2882648615
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/39.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1617399150
Short name	T895
Test name
Test status
Simulation time	117270931432 ps
CPU time	497.65 seconds
Started	Aug 25 12:58:00 AM UTC 24
Finished	Aug 25 01:06:25 AM UTC 24
Peak memory	214440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617399150 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.1617399150
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/39.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.2438682615
Short name	T693
Test name
Test status
Simulation time	2450244996 ps
CPU time	11.75 seconds
Started	Aug 25 12:58:03 AM UTC 24
Finished	Aug 25 12:58:15 AM UTC 24
Peak memory	212384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438682615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.2438682615
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/39.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_error_random.105892776
Short name	T692
Test name
Test status
Simulation time	166955208 ps
CPU time	8.36 seconds
Started	Aug 25 12:58:02 AM UTC 24
Finished	Aug 25 12:58:12 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105892776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.105892776
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/39.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random.3047609569
Short name	T677
Test name
Test status
Simulation time	139027960 ps
CPU time	2.69 seconds
Started	Aug 25 12:57:59 AM UTC 24
Finished	Aug 25 12:58:03 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047609569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.3047609569
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/39.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.1008680300
Short name	T883
Test name
Test status
Simulation time	110638291074 ps
CPU time	339.57 seconds
Started	Aug 25 12:57:59 AM UTC 24
Finished	Aug 25 01:03:43 AM UTC 24
Peak memory	212456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008680300 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1008680300
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/39.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.835979095
Short name	T866
Test name
Test status
Simulation time	22915405308 ps
CPU time	200.79 seconds
Started	Aug 25 12:58:00 AM UTC 24
Finished	Aug 25 01:01:24 AM UTC 24
Peak memory	212388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835979095 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.835979095
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/39.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_zero_delays.175882929
Short name	T686
Test name
Test status
Simulation time	64693258 ps
CPU time	10.1 seconds
Started	Aug 25 12:57:59 AM UTC 24
Finished	Aug 25 12:58:10 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175882929 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.175882929
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/39.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_same_source.4058794168
Short name	T684
Test name
Test status
Simulation time	229133171 ps
CPU time	7.12 seconds
Started	Aug 25 12:58:01 AM UTC 24
Finished	Aug 25 12:58:10 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058794168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.4058794168
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/39.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke.294450138
Short name	T674
Test name
Test status
Simulation time	40837386 ps
CPU time	1.88 seconds
Started	Aug 25 12:57:57 AM UTC 24
Finished	Aug 25 12:58:00 AM UTC 24
Peak memory	211244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294450138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.294450138
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/39.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_large_delays.2311693097
Short name	T681
Test name
Test status
Simulation time	1202701779 ps
CPU time	9.73 seconds
Started	Aug 25 12:57:57 AM UTC 24
Finished	Aug 25 12:58:08 AM UTC 24
Peak memory	212200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311693097 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2311693097
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/39.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.2804676291
Short name	T687
Test name
Test status
Simulation time	1154095020 ps
CPU time	11.31 seconds
Started	Aug 25 12:57:58 AM UTC 24
Finished	Aug 25 12:58:10 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804676291 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.2804676291
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/39.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.1416956912
Short name	T672
Test name
Test status
Simulation time	26026810 ps
CPU time	1.49 seconds
Started	Aug 25 12:57:57 AM UTC 24
Finished	Aug 25 12:57:59 AM UTC 24
Peak memory	211132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416956912 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.1416956912
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/39.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.2602292068
Short name	T733
Test name
Test status
Simulation time	12072066009 ps
CPU time	36.54 seconds
Started	Aug 25 12:58:04 AM UTC 24
Finished	Aug 25 12:58:42 AM UTC 24
Peak memory	214240 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602292068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.2602292068
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/39.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.3195528931
Short name	T726
Test name
Test status
Simulation time	888657371 ps
CPU time	31.5 seconds
Started	Aug 25 12:58:04 AM UTC 24
Finished	Aug 25 12:58:37 AM UTC 24
Peak memory	212136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195528931 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3195528931
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/39.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.155111824
Short name	T11
Test name
Test status
Simulation time	1771420003 ps
CPU time	241.94 seconds
Started	Aug 25 12:58:04 AM UTC 24
Finished	Aug 25 01:02:10 AM UTC 24
Peak memory	218276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155111824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.155111824
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/39.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.2984963768
Short name	T770
Test name
Test status
Simulation time	1655653037 ps
CPU time	72.94 seconds
Started	Aug 25 12:58:04 AM UTC 24
Finished	Aug 25 12:59:19 AM UTC 24
Peak memory	216224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984963768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.2984963768
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/39.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_unmapped_addr.4183480361
Short name	T697
Test name
Test status
Simulation time	667681571 ps
CPU time	13.72 seconds
Started	Aug 25 12:58:03 AM UTC 24
Finished	Aug 25 12:58:17 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183480361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.4183480361
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/39.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device.4279348153
Short name	T60
Test name
Test status
Simulation time	2743647772 ps
CPU time	10 seconds
Started	Aug 25 12:52:16 AM UTC 24
Finished	Aug 25 12:52:35 AM UTC 24
Peak memory	212384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279348153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.4279348153
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/4.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.1494925202
Short name	T297
Test name
Test status
Simulation time	9610823 ps
CPU time	0.87 seconds
Started	Aug 25 12:52:21 AM UTC 24
Finished	Aug 25 12:52:26 AM UTC 24
Peak memory	211140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494925202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.1494925202
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/4.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_error_random.2001471026
Short name	T304
Test name
Test status
Simulation time	31656498 ps
CPU time	1.84 seconds
Started	Aug 25 12:52:20 AM UTC 24
Finished	Aug 25 12:52:33 AM UTC 24
Peak memory	211136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001471026 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.2001471026
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/4.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random.2357293268
Short name	T45
Test name
Test status
Simulation time	34889196 ps
CPU time	3.53 seconds
Started	Aug 25 12:52:15 AM UTC 24
Finished	Aug 25 12:52:23 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357293268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.2357293268
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/4.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_large_delays.139423125
Short name	T72
Test name
Test status
Simulation time	4191321998 ps
CPU time	14.53 seconds
Started	Aug 25 12:52:16 AM UTC 24
Finished	Aug 25 12:52:39 AM UTC 24
Peak memory	212188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139423125 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.139423125
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/4.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_slow_rsp.959869611
Short name	T175
Test name
Test status
Simulation time	15742633576 ps
CPU time	125.86 seconds
Started	Aug 25 12:52:16 AM UTC 24
Finished	Aug 25 12:54:32 AM UTC 24
Peak memory	212452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959869611 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.959869611
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/4.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_zero_delays.762248303
Short name	T52
Test name
Test status
Simulation time	49615479 ps
CPU time	4.51 seconds
Started	Aug 25 12:52:15 AM UTC 24
Finished	Aug 25 12:52:24 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762248303 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.762248303
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/4.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_same_source.3520128229
Short name	T294
Test name
Test status
Simulation time	201865555 ps
CPU time	4.85 seconds
Started	Aug 25 12:52:20 AM UTC 24
Finished	Aug 25 12:52:36 AM UTC 24
Peak memory	212288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520128229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3520128229
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/4.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke.1077415386
Short name	T69
Test name
Test status
Simulation time	52149448 ps
CPU time	1.54 seconds
Started	Aug 25 12:52:13 AM UTC 24
Finished	Aug 25 12:52:16 AM UTC 24
Peak memory	211244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077415386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1077415386
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/4.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_large_delays.2544108363
Short name	T100
Test name
Test status
Simulation time	3556169854 ps
CPU time	11.97 seconds
Started	Aug 25 12:52:14 AM UTC 24
Finished	Aug 25 12:52:57 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544108363 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2544108363
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/4.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.2001523250
Short name	T101
Test name
Test status
Simulation time	3498739199 ps
CPU time	12.98 seconds
Started	Aug 25 12:52:14 AM UTC 24
Finished	Aug 25 12:52:58 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001523250 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2001523250
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/4.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.2844143311
Short name	T312
Test name
Test status
Simulation time	9911074 ps
CPU time	1.56 seconds
Started	Aug 25 12:52:14 AM UTC 24
Finished	Aug 25 12:52:47 AM UTC 24
Peak memory	211244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844143311 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.2844143311
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/4.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all.2295115522
Short name	T222
Test name
Test status
Simulation time	17679430797 ps
CPU time	129.56 seconds
Started	Aug 25 12:52:22 AM UTC 24
Finished	Aug 25 12:54:41 AM UTC 24
Peak memory	214500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295115522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2295115522
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/4.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_error.855581236
Short name	T290
Test name
Test status
Simulation time	186468788 ps
CPU time	16.41 seconds
Started	Aug 25 12:52:22 AM UTC 24
Finished	Aug 25 12:52:47 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855581236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.855581236
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/4.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_unmapped_addr.3740398895
Short name	T307
Test name
Test status
Simulation time	747220412 ps
CPU time	8.45 seconds
Started	Aug 25 12:52:21 AM UTC 24
Finished	Aug 25 12:52:33 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740398895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3740398895
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/4.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device.3171560437
Short name	T699
Test name
Test status
Simulation time	295361905 ps
CPU time	5.41 seconds
Started	Aug 25 12:58:11 AM UTC 24
Finished	Aug 25 12:58:18 AM UTC 24
Peak memory	212136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171560437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.3171560437
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/40.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3641796346
Short name	T898
Test name
Test status
Simulation time	47838415212 ps
CPU time	563.5 seconds
Started	Aug 25 12:58:11 AM UTC 24
Finished	Aug 25 01:07:43 AM UTC 24
Peak memory	217944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641796346 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.3641796346
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/40.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.3779186388
Short name	T704
Test name
Test status
Simulation time	571397320 ps
CPU time	9.15 seconds
Started	Aug 25 12:58:12 AM UTC 24
Finished	Aug 25 12:58:22 AM UTC 24
Peak memory	212380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779186388 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.3779186388
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/40.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_error_random.4180806658
Short name	T707
Test name
Test status
Simulation time	462416611 ps
CPU time	11.72 seconds
Started	Aug 25 12:58:12 AM UTC 24
Finished	Aug 25 12:58:25 AM UTC 24
Peak memory	212084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180806658 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.4180806658
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/40.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random.49030020
Short name	T695
Test name
Test status
Simulation time	278167460 ps
CPU time	7.06 seconds
Started	Aug 25 12:58:09 AM UTC 24
Finished	Aug 25 12:58:17 AM UTC 24
Peak memory	212136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49030020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.49030020
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/40.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.634411625
Short name	T884
Test name
Test status
Simulation time	68043847671 ps
CPU time	328.96 seconds
Started	Aug 25 12:58:10 AM UTC 24
Finished	Aug 25 01:03:43 AM UTC 24
Peak memory	212448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634411625 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.634411625
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/40.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1843524886
Short name	T758
Test name
Test status
Simulation time	7180049054 ps
CPU time	48.88 seconds
Started	Aug 25 12:58:11 AM UTC 24
Finished	Aug 25 12:59:02 AM UTC 24
Peak memory	212268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843524886 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1843524886
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/40.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_zero_delays.3761860689
Short name	T700
Test name
Test status
Simulation time	60424030 ps
CPU time	8.12 seconds
Started	Aug 25 12:58:10 AM UTC 24
Finished	Aug 25 12:58:19 AM UTC 24
Peak memory	212388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761860689 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.3761860689
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/40.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_same_source.840883813
Short name	T696
Test name
Test status
Simulation time	56517646 ps
CPU time	4.8 seconds
Started	Aug 25 12:58:12 AM UTC 24
Finished	Aug 25 12:58:17 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840883813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.840883813
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/40.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke.3746860626
Short name	T682
Test name
Test status
Simulation time	10114078 ps
CPU time	1.17 seconds
Started	Aug 25 12:58:06 AM UTC 24
Finished	Aug 25 12:58:09 AM UTC 24
Peak memory	211236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746860626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3746860626
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/40.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_large_delays.413208401
Short name	T713
Test name
Test status
Simulation time	13456406332 ps
CPU time	19.41 seconds
Started	Aug 25 12:58:08 AM UTC 24
Finished	Aug 25 12:58:28 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413208401 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.413208401
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/40.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.1135074970
Short name	T716
Test name
Test status
Simulation time	10056401382 ps
CPU time	20.45 seconds
Started	Aug 25 12:58:08 AM UTC 24
Finished	Aug 25 12:58:29 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135074970 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1135074970
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/40.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.1881073803
Short name	T688
Test name
Test status
Simulation time	9338114 ps
CPU time	1.8 seconds
Started	Aug 25 12:58:08 AM UTC 24
Finished	Aug 25 12:58:10 AM UTC 24
Peak memory	211236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881073803 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.1881073803
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/40.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.1586863744
Short name	T723
Test name
Test status
Simulation time	886206260 ps
CPU time	22.34 seconds
Started	Aug 25 12:58:12 AM UTC 24
Finished	Aug 25 12:58:35 AM UTC 24
Peak memory	214176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586863744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1586863744
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/40.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.738719549
Short name	T760
Test name
Test status
Simulation time	389979415 ps
CPU time	50.04 seconds
Started	Aug 25 12:58:13 AM UTC 24
Finished	Aug 25 12:59:05 AM UTC 24
Peak memory	214504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738719549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.738719549
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/40.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.462814966
Short name	T786
Test name
Test status
Simulation time	2142736050 ps
CPU time	83.46 seconds
Started	Aug 25 12:58:13 AM UTC 24
Finished	Aug 25 12:59:39 AM UTC 24
Peak memory	216228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462814966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.462814966
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/40.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.3546205387
Short name	T712
Test name
Test status
Simulation time	25564925 ps
CPU time	10.46 seconds
Started	Aug 25 12:58:16 AM UTC 24
Finished	Aug 25 12:58:28 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546205387 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.3546205387
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/40.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_unmapped_addr.1942407362
Short name	T710
Test name
Test status
Simulation time	1869021498 ps
CPU time	13.73 seconds
Started	Aug 25 12:58:12 AM UTC 24
Finished	Aug 25 12:58:27 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942407362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1942407362
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/40.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device.2532106857
Short name	T717
Test name
Test status
Simulation time	323797266 ps
CPU time	9.04 seconds
Started	Aug 25 12:58:21 AM UTC 24
Finished	Aug 25 12:58:31 AM UTC 24
Peak memory	212136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532106857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.2532106857
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/41.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.367987875
Short name	T896
Test name
Test status
Simulation time	59991183003 ps
CPU time	486.09 seconds
Started	Aug 25 12:58:22 AM UTC 24
Finished	Aug 25 01:06:35 AM UTC 24
Peak memory	214244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367987875 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.367987875
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/41.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.3547125839
Short name	T719
Test name
Test status
Simulation time	1825600506 ps
CPU time	6.67 seconds
Started	Aug 25 12:58:24 AM UTC 24
Finished	Aug 25 12:58:31 AM UTC 24
Peak memory	212324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547125839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.3547125839
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/41.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_error_random.4141311735
Short name	T715
Test name
Test status
Simulation time	51028831 ps
CPU time	4.06 seconds
Started	Aug 25 12:58:24 AM UTC 24
Finished	Aug 25 12:58:29 AM UTC 24
Peak memory	212136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141311735 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.4141311735
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/41.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random.1873855304
Short name	T703
Test name
Test status
Simulation time	48080614 ps
CPU time	2.05 seconds
Started	Aug 25 12:58:19 AM UTC 24
Finished	Aug 25 12:58:22 AM UTC 24
Peak memory	212120 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873855304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.1873855304
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/41.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.2734296962
Short name	T873
Test name
Test status
Simulation time	40682131408 ps
CPU time	214.97 seconds
Started	Aug 25 12:58:19 AM UTC 24
Finished	Aug 25 01:01:57 AM UTC 24
Peak memory	212456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734296962 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.2734296962
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/41.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.597593734
Short name	T854
Test name
Test status
Simulation time	19172451700 ps
CPU time	139.56 seconds
Started	Aug 25 12:58:20 AM UTC 24
Finished	Aug 25 01:00:42 AM UTC 24
Peak memory	212388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597593734 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.597593734
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/41.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_zero_delays.1695590372
Short name	T711
Test name
Test status
Simulation time	93710331 ps
CPU time	7.48 seconds
Started	Aug 25 12:58:19 AM UTC 24
Finished	Aug 25 12:58:27 AM UTC 24
Peak memory	212184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695590372 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.1695590372
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/41.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_same_source.750847645
Short name	T709
Test name
Test status
Simulation time	578413503 ps
CPU time	2.43 seconds
Started	Aug 25 12:58:22 AM UTC 24
Finished	Aug 25 12:58:26 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750847645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.750847645
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/41.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke.2127650438
Short name	T701
Test name
Test status
Simulation time	47517541 ps
CPU time	1.93 seconds
Started	Aug 25 12:58:17 AM UTC 24
Finished	Aug 25 12:58:20 AM UTC 24
Peak memory	211240 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127650438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.2127650438
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/41.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_large_delays.2115465752
Short name	T721
Test name
Test status
Simulation time	3269331440 ps
CPU time	13.25 seconds
Started	Aug 25 12:58:19 AM UTC 24
Finished	Aug 25 12:58:33 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115465752 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2115465752
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/41.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.3690775727
Short name	T728
Test name
Test status
Simulation time	1704674031 ps
CPU time	18.26 seconds
Started	Aug 25 12:58:19 AM UTC 24
Finished	Aug 25 12:58:38 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690775727 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.3690775727
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/41.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2049917883
Short name	T702
Test name
Test status
Simulation time	10592885 ps
CPU time	1.71 seconds
Started	Aug 25 12:58:19 AM UTC 24
Finished	Aug 25 12:58:21 AM UTC 24
Peak memory	211132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049917883 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2049917883
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/41.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.2132083803
Short name	T173
Test name
Test status
Simulation time	4422397647 ps
CPU time	90.34 seconds
Started	Aug 25 12:58:25 AM UTC 24
Finished	Aug 25 12:59:57 AM UTC 24
Peak memory	214500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132083803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.2132083803
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/41.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.1223638516
Short name	T738
Test name
Test status
Simulation time	3279241437 ps
CPU time	18.76 seconds
Started	Aug 25 12:58:26 AM UTC 24
Finished	Aug 25 12:58:46 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223638516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1223638516
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/41.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.3839862464
Short name	T754
Test name
Test status
Simulation time	180974497 ps
CPU time	31.51 seconds
Started	Aug 25 12:58:26 AM UTC 24
Finished	Aug 25 12:58:59 AM UTC 24
Peak memory	214180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839862464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.3839862464
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/41.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2496071928
Short name	T856
Test name
Test status
Simulation time	4563770465 ps
CPU time	136.46 seconds
Started	Aug 25 12:58:27 AM UTC 24
Finished	Aug 25 01:00:47 AM UTC 24
Peak memory	218656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496071928 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.2496071928
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/41.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_unmapped_addr.1618238620
Short name	T714
Test name
Test status
Simulation time	40558537 ps
CPU time	3.61 seconds
Started	Aug 25 12:58:24 AM UTC 24
Finished	Aug 25 12:58:29 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618238620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1618238620
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/41.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device.4100361675
Short name	T737
Test name
Test status
Simulation time	46973796 ps
CPU time	11.96 seconds
Started	Aug 25 12:58:32 AM UTC 24
Finished	Aug 25 12:58:45 AM UTC 24
Peak memory	212392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100361675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.4100361675
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/42.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.3346619958
Short name	T897
Test name
Test status
Simulation time	339769985362 ps
CPU time	528.36 seconds
Started	Aug 25 12:58:32 AM UTC 24
Finished	Aug 25 01:07:28 AM UTC 24
Peak memory	214248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346619958 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.3346619958
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/42.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.2341801340
Short name	T731
Test name
Test status
Simulation time	135191767 ps
CPU time	3.73 seconds
Started	Aug 25 12:58:37 AM UTC 24
Finished	Aug 25 12:58:41 AM UTC 24
Peak memory	212324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341801340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.2341801340
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/42.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_error_random.2674748870
Short name	T739
Test name
Test status
Simulation time	3502913734 ps
CPU time	11.21 seconds
Started	Aug 25 12:58:34 AM UTC 24
Finished	Aug 25 12:58:47 AM UTC 24
Peak memory	212200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674748870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.2674748870
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/42.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random.3580366899
Short name	T744
Test name
Test status
Simulation time	699514947 ps
CPU time	18.67 seconds
Started	Aug 25 12:58:30 AM UTC 24
Finished	Aug 25 12:58:50 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580366899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.3580366899
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/42.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.2418232162
Short name	T817
Test name
Test status
Simulation time	51369941433 ps
CPU time	90.31 seconds
Started	Aug 25 12:58:31 AM UTC 24
Finished	Aug 25 01:00:03 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418232162 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2418232162
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/42.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2431179092
Short name	T803
Test name
Test status
Simulation time	37602652037 ps
CPU time	77.13 seconds
Started	Aug 25 12:58:32 AM UTC 24
Finished	Aug 25 12:59:51 AM UTC 24
Peak memory	212204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431179092 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2431179092
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/42.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_zero_delays.2482308115
Short name	T727
Test name
Test status
Simulation time	112232759 ps
CPU time	5.33 seconds
Started	Aug 25 12:58:31 AM UTC 24
Finished	Aug 25 12:58:37 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482308115 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.2482308115
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/42.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_same_source.65224830
Short name	T724
Test name
Test status
Simulation time	13280820 ps
CPU time	1.79 seconds
Started	Aug 25 12:58:33 AM UTC 24
Finished	Aug 25 12:58:36 AM UTC 24
Peak memory	211232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65224830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.65224830
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/42.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke.2207129885
Short name	T720
Test name
Test status
Simulation time	53482422 ps
CPU time	2.32 seconds
Started	Aug 25 12:58:28 AM UTC 24
Finished	Aug 25 12:58:32 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207129885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2207129885
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/42.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_large_delays.3741944370
Short name	T574
Test name
Test status
Simulation time	7834091922 ps
CPU time	22.02 seconds
Started	Aug 25 12:58:30 AM UTC 24
Finished	Aug 25 12:58:53 AM UTC 24
Peak memory	212392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741944370 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.3741944370
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/42.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.3531099821
Short name	T735
Test name
Test status
Simulation time	3422448180 ps
CPU time	12.46 seconds
Started	Aug 25 12:58:30 AM UTC 24
Finished	Aug 25 12:58:43 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531099821 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3531099821
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/42.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.3739654241
Short name	T718
Test name
Test status
Simulation time	8142246 ps
CPU time	1.6 seconds
Started	Aug 25 12:58:28 AM UTC 24
Finished	Aug 25 12:58:31 AM UTC 24
Peak memory	211132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739654241 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.3739654241
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/42.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.2862780559
Short name	T156
Test name
Test status
Simulation time	437899923 ps
CPU time	11.11 seconds
Started	Aug 25 12:58:37 AM UTC 24
Finished	Aug 25 12:58:49 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862780559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2862780559
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/42.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.1160246839
Short name	T865
Test name
Test status
Simulation time	9899397747 ps
CPU time	152.56 seconds
Started	Aug 25 12:58:38 AM UTC 24
Finished	Aug 25 01:01:14 AM UTC 24
Peak memory	214244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160246839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.1160246839
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/42.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1027062625
Short name	T824
Test name
Test status
Simulation time	1614117834 ps
CPU time	91.71 seconds
Started	Aug 25 12:58:37 AM UTC 24
Finished	Aug 25 01:00:12 AM UTC 24
Peak memory	216232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027062625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.1027062625
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/42.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.862338281
Short name	T801
Test name
Test status
Simulation time	833177666 ps
CPU time	70.24 seconds
Started	Aug 25 12:58:38 AM UTC 24
Finished	Aug 25 12:59:50 AM UTC 24
Peak memory	214188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862338281 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.862338281
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/42.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_unmapped_addr.2975874057
Short name	T729
Test name
Test status
Simulation time	16130428 ps
CPU time	2.83 seconds
Started	Aug 25 12:58:35 AM UTC 24
Finished	Aug 25 12:58:39 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975874057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2975874057
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/42.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.2499542342
Short name	T751
Test name
Test status
Simulation time	424441987 ps
CPU time	8.61 seconds
Started	Aug 25 12:58:45 AM UTC 24
Finished	Aug 25 12:58:55 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499542342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.2499542342
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/43.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.4221686842
Short name	T879
Test name
Test status
Simulation time	26900443783 ps
CPU time	240.35 seconds
Started	Aug 25 12:58:46 AM UTC 24
Finished	Aug 25 01:02:50 AM UTC 24
Peak memory	214440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221686842 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.4221686842
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/43.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.38173562
Short name	T755
Test name
Test status
Simulation time	2487969167 ps
CPU time	9.83 seconds
Started	Aug 25 12:58:49 AM UTC 24
Finished	Aug 25 12:59:00 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38173562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.38173562
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/43.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.3085761833
Short name	T748
Test name
Test status
Simulation time	43993993 ps
CPU time	3.89 seconds
Started	Aug 25 12:58:47 AM UTC 24
Finished	Aug 25 12:58:52 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085761833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.3085761833
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/43.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random.2714406530
Short name	T743
Test name
Test status
Simulation time	192293658 ps
CPU time	6.08 seconds
Started	Aug 25 12:58:42 AM UTC 24
Finished	Aug 25 12:58:50 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714406530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.2714406530
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/43.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.345109228
Short name	T858
Test name
Test status
Simulation time	55282116514 ps
CPU time	123.24 seconds
Started	Aug 25 12:58:44 AM UTC 24
Finished	Aug 25 01:00:49 AM UTC 24
Peak memory	211844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345109228 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.345109228
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/43.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.365621184
Short name	T880
Test name
Test status
Simulation time	44537976232 ps
CPU time	250.63 seconds
Started	Aug 25 12:58:44 AM UTC 24
Finished	Aug 25 01:02:58 AM UTC 24
Peak memory	212080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365621184 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.365621184
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/43.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.2003712639
Short name	T745
Test name
Test status
Simulation time	161053484 ps
CPU time	6.76 seconds
Started	Aug 25 12:58:43 AM UTC 24
Finished	Aug 25 12:58:50 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003712639 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.2003712639
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/43.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.3499869143
Short name	T746
Test name
Test status
Simulation time	113948066 ps
CPU time	2.54 seconds
Started	Aug 25 12:58:47 AM UTC 24
Finished	Aug 25 12:58:51 AM UTC 24
Peak memory	212384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499869143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.3499869143
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/43.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke.985146931
Short name	T732
Test name
Test status
Simulation time	13620781 ps
CPU time	1.64 seconds
Started	Aug 25 12:58:39 AM UTC 24
Finished	Aug 25 12:58:42 AM UTC 24
Peak memory	211240 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985146931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.985146931
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/43.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.3427818002
Short name	T750
Test name
Test status
Simulation time	1481524850 ps
CPU time	12.03 seconds
Started	Aug 25 12:58:41 AM UTC 24
Finished	Aug 25 12:58:54 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427818002 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.3427818002
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/43.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.2282014634
Short name	T753
Test name
Test status
Simulation time	1643838898 ps
CPU time	13.5 seconds
Started	Aug 25 12:58:42 AM UTC 24
Finished	Aug 25 12:58:57 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282014634 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2282014634
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/43.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.14033371
Short name	T734
Test name
Test status
Simulation time	11843796 ps
CPU time	1.53 seconds
Started	Aug 25 12:58:40 AM UTC 24
Finished	Aug 25 12:58:43 AM UTC 24
Peak memory	211240 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14033371 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.14033371
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/43.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.4163522624
Short name	T771
Test name
Test status
Simulation time	2010921257 ps
CPU time	29.04 seconds
Started	Aug 25 12:58:49 AM UTC 24
Finished	Aug 25 12:59:19 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163522624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.4163522624
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/43.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1026090319
Short name	T855
Test name
Test status
Simulation time	11074139346 ps
CPU time	111.31 seconds
Started	Aug 25 12:58:51 AM UTC 24
Finished	Aug 25 01:00:45 AM UTC 24
Peak memory	212328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026090319 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1026090319
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/43.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.3033888555
Short name	T837
Test name
Test status
Simulation time	3857269400 ps
CPU time	87.17 seconds
Started	Aug 25 12:58:50 AM UTC 24
Finished	Aug 25 01:00:19 AM UTC 24
Peak memory	214440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033888555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.3033888555
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/43.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.1126572673
Short name	T869
Test name
Test status
Simulation time	6487116300 ps
CPU time	164.84 seconds
Started	Aug 25 12:58:51 AM UTC 24
Finished	Aug 25 01:01:39 AM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126572673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.1126572673
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/43.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.2606090265
Short name	T747
Test name
Test status
Simulation time	8727202 ps
CPU time	1.63 seconds
Started	Aug 25 12:58:49 AM UTC 24
Finished	Aug 25 12:58:51 AM UTC 24
Peak memory	211132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606090265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.2606090265
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/43.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.2977935026
Short name	T255
Test name
Test status
Simulation time	339735350 ps
CPU time	5.37 seconds
Started	Aug 25 12:58:56 AM UTC 24
Finished	Aug 25 12:59:02 AM UTC 24
Peak memory	211792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977935026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.2977935026
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/44.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.860712930
Short name	T887
Test name
Test status
Simulation time	161607059121 ps
CPU time	307.83 seconds
Started	Aug 25 12:58:56 AM UTC 24
Finished	Aug 25 01:04:08 AM UTC 24
Peak memory	214244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860712930 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.860712930
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/44.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.154002187
Short name	T767
Test name
Test status
Simulation time	514724941 ps
CPU time	11.68 seconds
Started	Aug 25 12:59:01 AM UTC 24
Finished	Aug 25 12:59:14 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154002187 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.154002187
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/44.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.2197398449
Short name	T763
Test name
Test status
Simulation time	132222722 ps
CPU time	6.82 seconds
Started	Aug 25 12:59:00 AM UTC 24
Finished	Aug 25 12:59:08 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197398449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2197398449
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/44.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random.1661921405
Short name	T759
Test name
Test status
Simulation time	1239384214 ps
CPU time	9.83 seconds
Started	Aug 25 12:58:54 AM UTC 24
Finished	Aug 25 12:59:04 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661921405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.1661921405
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/44.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.2519399376
Short name	T882
Test name
Test status
Simulation time	32788960007 ps
CPU time	277.88 seconds
Started	Aug 25 12:58:56 AM UTC 24
Finished	Aug 25 01:03:38 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519399376 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2519399376
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/44.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1150128261
Short name	T861
Test name
Test status
Simulation time	41533144871 ps
CPU time	116.17 seconds
Started	Aug 25 12:58:56 AM UTC 24
Finished	Aug 25 01:00:54 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150128261 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.1150128261
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/44.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.2172211150
Short name	T756
Test name
Test status
Simulation time	43063336 ps
CPU time	5.93 seconds
Started	Aug 25 12:58:54 AM UTC 24
Finished	Aug 25 12:59:00 AM UTC 24
Peak memory	212384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172211150 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.2172211150
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/44.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.1748081244
Short name	T757
Test name
Test status
Simulation time	22807894 ps
CPU time	2.9 seconds
Started	Aug 25 12:58:58 AM UTC 24
Finished	Aug 25 12:59:02 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748081244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1748081244
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/44.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.1233711289
Short name	T725
Test name
Test status
Simulation time	47475234 ps
CPU time	2.28 seconds
Started	Aug 25 12:58:51 AM UTC 24
Finished	Aug 25 12:58:54 AM UTC 24
Peak memory	212448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233711289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1233711289
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/44.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.4222060040
Short name	T762
Test name
Test status
Simulation time	3598375317 ps
CPU time	12.61 seconds
Started	Aug 25 12:58:52 AM UTC 24
Finished	Aug 25 12:59:06 AM UTC 24
Peak memory	212260 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222060040 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.4222060040
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/44.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.1932913527
Short name	T766
Test name
Test status
Simulation time	1262200486 ps
CPU time	15.53 seconds
Started	Aug 25 12:58:53 AM UTC 24
Finished	Aug 25 12:59:10 AM UTC 24
Peak memory	212324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932913527 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.1932913527
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/44.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.3305350122
Short name	T752
Test name
Test status
Simulation time	18666715 ps
CPU time	1.65 seconds
Started	Aug 25 12:58:52 AM UTC 24
Finished	Aug 25 12:58:55 AM UTC 24
Peak memory	211128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305350122 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.3305350122
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/44.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.823604184
Short name	T778
Test name
Test status
Simulation time	1406308475 ps
CPU time	25.31 seconds
Started	Aug 25 12:59:02 AM UTC 24
Finished	Aug 25 12:59:29 AM UTC 24
Peak memory	212264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823604184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.823604184
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/44.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.4060398122
Short name	T266
Test name
Test status
Simulation time	14177963808 ps
CPU time	86.28 seconds
Started	Aug 25 12:59:03 AM UTC 24
Finished	Aug 25 01:00:32 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060398122 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.4060398122
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/44.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.837663162
Short name	T850
Test name
Test status
Simulation time	1630936793 ps
CPU time	88.22 seconds
Started	Aug 25 12:59:06 AM UTC 24
Finished	Aug 25 01:00:36 AM UTC 24
Peak memory	216300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837663162 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.837663162
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/44.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.2091352211
Short name	T213
Test name
Test status
Simulation time	1007305025 ps
CPU time	7.7 seconds
Started	Aug 25 12:59:00 AM UTC 24
Finished	Aug 25 12:59:09 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091352211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2091352211
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/44.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.1989644431
Short name	T785
Test name
Test status
Simulation time	2413665905 ps
CPU time	19.39 seconds
Started	Aug 25 12:59:14 AM UTC 24
Finished	Aug 25 12:59:35 AM UTC 24
Peak memory	212200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989644431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.1989644431
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/45.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1709103648
Short name	T265
Test name
Test status
Simulation time	27572386274 ps
CPU time	111.16 seconds
Started	Aug 25 12:59:16 AM UTC 24
Finished	Aug 25 01:01:09 AM UTC 24
Peak memory	212392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709103648 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.1709103648
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/45.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.3599581509
Short name	T777
Test name
Test status
Simulation time	69330404 ps
CPU time	5.93 seconds
Started	Aug 25 12:59:20 AM UTC 24
Finished	Aug 25 12:59:27 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599581509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.3599581509
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/45.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.1778263047
Short name	T781
Test name
Test status
Simulation time	573115498 ps
CPU time	10.54 seconds
Started	Aug 25 12:59:19 AM UTC 24
Finished	Aug 25 12:59:31 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778263047 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.1778263047
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/45.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random.141817652
Short name	T212
Test name
Test status
Simulation time	665898983 ps
CPU time	14.7 seconds
Started	Aug 25 12:59:09 AM UTC 24
Finished	Aug 25 12:59:25 AM UTC 24
Peak memory	212256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141817652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.141817652
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/45.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.2340300982
Short name	T875
Test name
Test status
Simulation time	23289687885 ps
CPU time	180.61 seconds
Started	Aug 25 12:59:10 AM UTC 24
Finished	Aug 25 01:02:14 AM UTC 24
Peak memory	212392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340300982 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2340300982
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/45.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3336776200
Short name	T818
Test name
Test status
Simulation time	3725705160 ps
CPU time	51.36 seconds
Started	Aug 25 12:59:11 AM UTC 24
Finished	Aug 25 01:00:04 AM UTC 24
Peak memory	212268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336776200 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3336776200
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/45.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.2787665499
Short name	T773
Test name
Test status
Simulation time	70673409 ps
CPU time	12.6 seconds
Started	Aug 25 12:59:09 AM UTC 24
Finished	Aug 25 12:59:23 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787665499 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2787665499
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/45.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.1764313
Short name	T775
Test name
Test status
Simulation time	27201102 ps
CPU time	4.61 seconds
Started	Aug 25 12:59:19 AM UTC 24
Finished	Aug 25 12:59:25 AM UTC 24
Peak memory	212384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_T EST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-si m-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1764313
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/45.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.3701147032
Short name	T765
Test name
Test status
Simulation time	9904025 ps
CPU time	1.57 seconds
Started	Aug 25 12:59:06 AM UTC 24
Finished	Aug 25 12:59:08 AM UTC 24
Peak memory	211132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701147032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.3701147032
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/45.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.3951087111
Short name	T776
Test name
Test status
Simulation time	2145755031 ps
CPU time	18.87 seconds
Started	Aug 25 12:59:07 AM UTC 24
Finished	Aug 25 12:59:27 AM UTC 24
Peak memory	212392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951087111 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.3951087111
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/45.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1439570238
Short name	T782
Test name
Test status
Simulation time	3098574310 ps
CPU time	20.23 seconds
Started	Aug 25 12:59:09 AM UTC 24
Finished	Aug 25 12:59:31 AM UTC 24
Peak memory	212084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439570238 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1439570238
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/45.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.439186895
Short name	T764
Test name
Test status
Simulation time	8408867 ps
CPU time	1.49 seconds
Started	Aug 25 12:59:06 AM UTC 24
Finished	Aug 25 12:59:08 AM UTC 24
Peak memory	211140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439186895 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.439186895
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/45.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.4247680311
Short name	T795
Test name
Test status
Simulation time	1417841672 ps
CPU time	25.71 seconds
Started	Aug 25 12:59:20 AM UTC 24
Finished	Aug 25 12:59:47 AM UTC 24
Peak memory	214180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247680311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.4247680311
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/45.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.3068176480
Short name	T832
Test name
Test status
Simulation time	2760935645 ps
CPU time	51.1 seconds
Started	Aug 25 12:59:24 AM UTC 24
Finished	Aug 25 01:00:16 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068176480 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.3068176480
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/45.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.2917860188
Short name	T876
Test name
Test status
Simulation time	838687955 ps
CPU time	167.23 seconds
Started	Aug 25 12:59:23 AM UTC 24
Finished	Aug 25 01:02:14 AM UTC 24
Peak memory	216232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917860188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.2917860188
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/45.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1327784155
Short name	T802
Test name
Test status
Simulation time	116227195 ps
CPU time	24.13 seconds
Started	Aug 25 12:59:25 AM UTC 24
Finished	Aug 25 12:59:50 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327784155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.1327784155
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/45.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.3041415359
Short name	T783
Test name
Test status
Simulation time	516451925 ps
CPU time	10.16 seconds
Started	Aug 25 12:59:20 AM UTC 24
Finished	Aug 25 12:59:31 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041415359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3041415359
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/45.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.191106016
Short name	T791
Test name
Test status
Simulation time	92869144 ps
CPU time	12.17 seconds
Started	Aug 25 12:59:32 AM UTC 24
Finished	Aug 25 12:59:45 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191106016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.191106016
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/46.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.3105995602
Short name	T900
Test name
Test status
Simulation time	60578744952 ps
CPU time	674.13 seconds
Started	Aug 25 12:59:33 AM UTC 24
Finished	Aug 25 01:10:56 AM UTC 24
Peak memory	217944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105995602 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.3105995602
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/46.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2283381848
Short name	T792
Test name
Test status
Simulation time	254120879 ps
CPU time	5.49 seconds
Started	Aug 25 12:59:39 AM UTC 24
Finished	Aug 25 12:59:46 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283381848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.2283381848
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/46.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.635746840
Short name	T806
Test name
Test status
Simulation time	1596890793 ps
CPU time	19.12 seconds
Started	Aug 25 12:59:35 AM UTC 24
Finished	Aug 25 12:59:55 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635746840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.635746840
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/46.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random.1495051403
Short name	T788
Test name
Test status
Simulation time	121562316 ps
CPU time	9.49 seconds
Started	Aug 25 12:59:29 AM UTC 24
Finished	Aug 25 12:59:40 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495051403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.1495051403
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/46.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.2599925626
Short name	T886
Test name
Test status
Simulation time	84077974077 ps
CPU time	260.91 seconds
Started	Aug 25 12:59:30 AM UTC 24
Finished	Aug 25 01:03:56 AM UTC 24
Peak memory	212392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599925626 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.2599925626
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/46.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.1977577522
Short name	T823
Test name
Test status
Simulation time	19308329005 ps
CPU time	37.52 seconds
Started	Aug 25 12:59:32 AM UTC 24
Finished	Aug 25 01:00:11 AM UTC 24
Peak memory	212204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977577522 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1977577522
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/46.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.2445198738
Short name	T787
Test name
Test status
Simulation time	277587705 ps
CPU time	8.48 seconds
Started	Aug 25 12:59:29 AM UTC 24
Finished	Aug 25 12:59:39 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445198738 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.2445198738
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/46.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.1509605318
Short name	T793
Test name
Test status
Simulation time	1154616015 ps
CPU time	11.61 seconds
Started	Aug 25 12:59:33 AM UTC 24
Finished	Aug 25 12:59:46 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509605318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1509605318
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/46.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.3237066076
Short name	T780
Test name
Test status
Simulation time	105976919 ps
CPU time	2.25 seconds
Started	Aug 25 12:59:26 AM UTC 24
Finished	Aug 25 12:59:29 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237066076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3237066076
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/46.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1408871864
Short name	T800
Test name
Test status
Simulation time	4162860206 ps
CPU time	20.57 seconds
Started	Aug 25 12:59:28 AM UTC 24
Finished	Aug 25 12:59:50 AM UTC 24
Peak memory	212200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408871864 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1408871864
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/46.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.917479538
Short name	T804
Test name
Test status
Simulation time	4127577155 ps
CPU time	22.73 seconds
Started	Aug 25 12:59:28 AM UTC 24
Finished	Aug 25 12:59:52 AM UTC 24
Peak memory	212452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917479538 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.917479538
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/46.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.403288385
Short name	T779
Test name
Test status
Simulation time	9744300 ps
CPU time	1.65 seconds
Started	Aug 25 12:59:26 AM UTC 24
Finished	Aug 25 12:59:29 AM UTC 24
Peak memory	211240 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403288385 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.403288385
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/46.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.1778537309
Short name	T798
Test name
Test status
Simulation time	95340559 ps
CPU time	7.35 seconds
Started	Aug 25 12:59:40 AM UTC 24
Finished	Aug 25 12:59:49 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778537309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1778537309
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/46.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.3238337128
Short name	T851
Test name
Test status
Simulation time	1209904802 ps
CPU time	53.8 seconds
Started	Aug 25 12:59:41 AM UTC 24
Finished	Aug 25 01:00:37 AM UTC 24
Peak memory	212328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238337128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.3238337128
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/46.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.2769287264
Short name	T870
Test name
Test status
Simulation time	856113422 ps
CPU time	117.75 seconds
Started	Aug 25 12:59:41 AM UTC 24
Finished	Aug 25 01:01:42 AM UTC 24
Peak memory	216296 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769287264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.2769287264
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/46.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.705264436
Short name	T816
Test name
Test status
Simulation time	257910902 ps
CPU time	19.37 seconds
Started	Aug 25 12:59:41 AM UTC 24
Finished	Aug 25 01:00:02 AM UTC 24
Peak memory	212268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705264436 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.705264436
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/46.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.2285581629
Short name	T789
Test name
Test status
Simulation time	103061871 ps
CPU time	4.04 seconds
Started	Aug 25 12:59:36 AM UTC 24
Finished	Aug 25 12:59:41 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285581629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.2285581629
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/46.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.3658567795
Short name	T811
Test name
Test status
Simulation time	54139364 ps
CPU time	8.87 seconds
Started	Aug 25 12:59:48 AM UTC 24
Finished	Aug 25 12:59:58 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658567795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.3658567795
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/47.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.737469591
Short name	T263
Test name
Test status
Simulation time	86324763259 ps
CPU time	232.15 seconds
Started	Aug 25 12:59:49 AM UTC 24
Finished	Aug 25 01:03:45 AM UTC 24
Peak memory	214312 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737469591 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.737469591
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/47.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.4192233442
Short name	T819
Test name
Test status
Simulation time	544459586 ps
CPU time	12.38 seconds
Started	Aug 25 12:59:52 AM UTC 24
Finished	Aug 25 01:00:05 AM UTC 24
Peak memory	211864 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192233442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.4192233442
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/47.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.1428426905
Short name	T813
Test name
Test status
Simulation time	1457610816 ps
CPU time	7.76 seconds
Started	Aug 25 12:59:51 AM UTC 24
Finished	Aug 25 12:59:59 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428426905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1428426905
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/47.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random.446424830
Short name	T810
Test name
Test status
Simulation time	66639312 ps
CPU time	9.52 seconds
Started	Aug 25 12:59:47 AM UTC 24
Finished	Aug 25 12:59:58 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446424830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.446424830
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/47.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.1152132014
Short name	T889
Test name
Test status
Simulation time	38045162483 ps
CPU time	292.07 seconds
Started	Aug 25 12:59:48 AM UTC 24
Finished	Aug 25 01:04:45 AM UTC 24
Peak memory	212020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152132014 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1152132014
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/47.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.353789295
Short name	T860
Test name
Test status
Simulation time	5214582931 ps
CPU time	61.23 seconds
Started	Aug 25 12:59:48 AM UTC 24
Finished	Aug 25 01:00:51 AM UTC 24
Peak memory	212328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353789295 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.353789295
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/47.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.1044054069
Short name	T799
Test name
Test status
Simulation time	17907873 ps
CPU time	1.73 seconds
Started	Aug 25 12:59:47 AM UTC 24
Finished	Aug 25 12:59:50 AM UTC 24
Peak memory	211136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044054069 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.1044054069
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/47.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.338421531
Short name	T807
Test name
Test status
Simulation time	498822192 ps
CPU time	5.3 seconds
Started	Aug 25 12:59:49 AM UTC 24
Finished	Aug 25 12:59:56 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338421531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.338421531
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/47.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.3906897961
Short name	T794
Test name
Test status
Simulation time	403247284 ps
CPU time	2.36 seconds
Started	Aug 25 12:59:44 AM UTC 24
Finished	Aug 25 12:59:47 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906897961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.3906897961
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/47.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2966697894
Short name	T821
Test name
Test status
Simulation time	2841285345 ps
CPU time	22.82 seconds
Started	Aug 25 12:59:46 AM UTC 24
Finished	Aug 25 01:00:10 AM UTC 24
Peak memory	211860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966697894 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2966697894
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/47.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.1051875234
Short name	T814
Test name
Test status
Simulation time	1309768187 ps
CPU time	13.49 seconds
Started	Aug 25 12:59:46 AM UTC 24
Finished	Aug 25 01:00:01 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051875234 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1051875234
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/47.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.879434301
Short name	T796
Test name
Test status
Simulation time	9055725 ps
CPU time	1.53 seconds
Started	Aug 25 12:59:45 AM UTC 24
Finished	Aug 25 12:59:47 AM UTC 24
Peak memory	211140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879434301 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.879434301
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/47.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.2739672603
Short name	T852
Test name
Test status
Simulation time	2147717713 ps
CPU time	44.03 seconds
Started	Aug 25 12:59:52 AM UTC 24
Finished	Aug 25 01:00:38 AM UTC 24
Peak memory	213860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739672603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2739672603
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/47.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3256556878
Short name	T848
Test name
Test status
Simulation time	605549994 ps
CPU time	38.44 seconds
Started	Aug 25 12:59:52 AM UTC 24
Finished	Aug 25 01:00:32 AM UTC 24
Peak memory	212328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256556878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3256556878
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/47.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.3969205766
Short name	T846
Test name
Test status
Simulation time	181647549 ps
CPU time	36.74 seconds
Started	Aug 25 12:59:52 AM UTC 24
Finished	Aug 25 01:00:30 AM UTC 24
Peak memory	214252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969205766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.3969205766
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/47.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.258838574
Short name	T809
Test name
Test status
Simulation time	15634592 ps
CPU time	3.44 seconds
Started	Aug 25 12:59:53 AM UTC 24
Finished	Aug 25 12:59:58 AM UTC 24
Peak memory	212204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258838574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.258838574
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/47.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.1084156943
Short name	T805
Test name
Test status
Simulation time	11551338 ps
CPU time	1.91 seconds
Started	Aug 25 12:59:51 AM UTC 24
Finished	Aug 25 12:59:53 AM UTC 24
Peak memory	211120 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084156943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.1084156943
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/47.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.3237620953
Short name	T829
Test name
Test status
Simulation time	712560666 ps
CPU time	9.3 seconds
Started	Aug 25 01:00:00 AM UTC 24
Finished	Aug 25 01:00:14 AM UTC 24
Peak memory	211436 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237620953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.3237620953
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/48.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2676506206
Short name	T143
Test name
Test status
Simulation time	29945689192 ps
CPU time	347.49 seconds
Started	Aug 25 01:00:00 AM UTC 24
Finished	Aug 25 01:05:57 AM UTC 24
Peak memory	213716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676506206 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.2676506206
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/48.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.1427111247
Short name	T839
Test name
Test status
Simulation time	1386552550 ps
CPU time	12.75 seconds
Started	Aug 25 01:00:06 AM UTC 24
Finished	Aug 25 01:00:20 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427111247 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.1427111247
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/48.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.328904020
Short name	T827
Test name
Test status
Simulation time	64962032 ps
CPU time	5.97 seconds
Started	Aug 25 01:00:06 AM UTC 24
Finished	Aug 25 01:00:13 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328904020 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.328904020
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/48.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random.1719098394
Short name	T835
Test name
Test status
Simulation time	1856008004 ps
CPU time	18.28 seconds
Started	Aug 25 12:59:59 AM UTC 24
Finished	Aug 25 01:00:18 AM UTC 24
Peak memory	212112 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719098394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.1719098394
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/48.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.2050595103
Short name	T874
Test name
Test status
Simulation time	28849583147 ps
CPU time	122.06 seconds
Started	Aug 25 12:59:59 AM UTC 24
Finished	Aug 25 01:02:03 AM UTC 24
Peak memory	212200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050595103 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2050595103
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/48.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.312380568
Short name	T871
Test name
Test status
Simulation time	35420014553 ps
CPU time	105.64 seconds
Started	Aug 25 01:00:00 AM UTC 24
Finished	Aug 25 01:01:52 AM UTC 24
Peak memory	212388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312380568 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.312380568
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/48.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.2976514449
Short name	T815
Test name
Test status
Simulation time	17397790 ps
CPU time	1.78 seconds
Started	Aug 25 12:59:59 AM UTC 24
Finished	Aug 25 01:00:01 AM UTC 24
Peak memory	211240 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976514449 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.2976514449
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/48.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.1057589635
Short name	T826
Test name
Test status
Simulation time	895534469 ps
CPU time	7.18 seconds
Started	Aug 25 01:00:02 AM UTC 24
Finished	Aug 25 01:00:13 AM UTC 24
Peak memory	212384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057589635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1057589635
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/48.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.1494775380
Short name	T808
Test name
Test status
Simulation time	135212839 ps
CPU time	2.05 seconds
Started	Aug 25 12:59:54 AM UTC 24
Finished	Aug 25 12:59:57 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494775380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.1494775380
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/48.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1569465764
Short name	T822
Test name
Test status
Simulation time	2591424592 ps
CPU time	13.22 seconds
Started	Aug 25 12:59:56 AM UTC 24
Finished	Aug 25 01:00:11 AM UTC 24
Peak memory	212392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569465764 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.1569465764
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/48.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.1903010658
Short name	T842
Test name
Test status
Simulation time	12067423981 ps
CPU time	22.51 seconds
Started	Aug 25 12:59:59 AM UTC 24
Finished	Aug 25 01:00:22 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903010658 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.1903010658
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/48.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.334442602
Short name	T812
Test name
Test status
Simulation time	9987125 ps
CPU time	1.91 seconds
Started	Aug 25 12:59:56 AM UTC 24
Finished	Aug 25 12:59:59 AM UTC 24
Peak memory	211244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334442602 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.334442602
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/48.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.337173670
Short name	T862
Test name
Test status
Simulation time	2470005953 ps
CPU time	47.8 seconds
Started	Aug 25 01:00:06 AM UTC 24
Finished	Aug 25 01:00:56 AM UTC 24
Peak memory	214568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337173670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.337173670
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/48.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1231079174
Short name	T877
Test name
Test status
Simulation time	50069271650 ps
CPU time	128.49 seconds
Started	Aug 25 01:00:08 AM UTC 24
Finished	Aug 25 01:02:19 AM UTC 24
Peak memory	214440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231079174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.1231079174
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/48.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3823445821
Short name	T859
Test name
Test status
Simulation time	202600670 ps
CPU time	42.54 seconds
Started	Aug 25 01:00:06 AM UTC 24
Finished	Aug 25 01:00:51 AM UTC 24
Peak memory	214376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823445821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.3823445821
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/48.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.2403647911
Short name	T844
Test name
Test status
Simulation time	282481906 ps
CPU time	13.54 seconds
Started	Aug 25 01:00:09 AM UTC 24
Finished	Aug 25 01:00:24 AM UTC 24
Peak memory	212452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403647911 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.2403647911
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/48.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.1720839520
Short name	T204
Test name
Test status
Simulation time	2171465780 ps
CPU time	11.3 seconds
Started	Aug 25 01:00:06 AM UTC 24
Finished	Aug 25 01:00:19 AM UTC 24
Peak memory	212260 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720839520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.1720839520
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/48.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.2327235321
Short name	T138
Test name
Test status
Simulation time	1315734460 ps
CPU time	16.33 seconds
Started	Aug 25 01:00:15 AM UTC 24
Finished	Aug 25 01:00:32 AM UTC 24
Peak memory	212136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327235321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.2327235321
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/49.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2922851097
Short name	T899
Test name
Test status
Simulation time	230137990610 ps
CPU time	632.97 seconds
Started	Aug 25 01:00:15 AM UTC 24
Finished	Aug 25 01:10:56 AM UTC 24
Peak memory	220188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922851097 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.2922851097
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/49.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2331054367
Short name	T838
Test name
Test status
Simulation time	12077551 ps
CPU time	1.46 seconds
Started	Aug 25 01:00:17 AM UTC 24
Finished	Aug 25 01:00:20 AM UTC 24
Peak memory	211236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331054367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.2331054367
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/49.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.4036861842
Short name	T843
Test name
Test status
Simulation time	278766635 ps
CPU time	4.86 seconds
Started	Aug 25 01:00:17 AM UTC 24
Finished	Aug 25 01:00:23 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036861842 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.4036861842
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/49.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random.726978529
Short name	T836
Test name
Test status
Simulation time	671609404 ps
CPU time	5.6 seconds
Started	Aug 25 01:00:12 AM UTC 24
Finished	Aug 25 01:00:19 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726978529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.726978529
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/49.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.1341392277
Short name	T203
Test name
Test status
Simulation time	30902214640 ps
CPU time	197.92 seconds
Started	Aug 25 01:00:14 AM UTC 24
Finished	Aug 25 01:03:35 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341392277 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.1341392277
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/49.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.744677768
Short name	T890
Test name
Test status
Simulation time	34477823524 ps
CPU time	266.28 seconds
Started	Aug 25 01:00:15 AM UTC 24
Finished	Aug 25 01:04:45 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744677768 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.744677768
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/49.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.1884293152
Short name	T840
Test name
Test status
Simulation time	90774141 ps
CPU time	6.44 seconds
Started	Aug 25 01:00:14 AM UTC 24
Finished	Aug 25 01:00:21 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884293152 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.1884293152
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/49.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.1524639746
Short name	T845
Test name
Test status
Simulation time	1205331737 ps
CPU time	7.93 seconds
Started	Aug 25 01:00:15 AM UTC 24
Finished	Aug 25 01:00:24 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524639746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1524639746
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/49.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.1501083613
Short name	T830
Test name
Test status
Simulation time	128837403 ps
CPU time	2.33 seconds
Started	Aug 25 01:00:11 AM UTC 24
Finished	Aug 25 01:00:14 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501083613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1501083613
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/49.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3146078111
Short name	T849
Test name
Test status
Simulation time	2933936122 ps
CPU time	19.48 seconds
Started	Aug 25 01:00:12 AM UTC 24
Finished	Aug 25 01:00:33 AM UTC 24
Peak memory	212384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146078111 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3146078111
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/49.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.428368029
Short name	T841
Test name
Test status
Simulation time	1320277188 ps
CPU time	7.83 seconds
Started	Aug 25 01:00:12 AM UTC 24
Finished	Aug 25 01:00:21 AM UTC 24
Peak memory	212324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428368029 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.428368029
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/49.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1243855157
Short name	T828
Test name
Test status
Simulation time	14524844 ps
CPU time	1.64 seconds
Started	Aug 25 01:00:11 AM UTC 24
Finished	Aug 25 01:00:14 AM UTC 24
Peak memory	211236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243855157 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.1243855157
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/49.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.364536877
Short name	T864
Test name
Test status
Simulation time	250164729 ps
CPU time	42.72 seconds
Started	Aug 25 01:00:19 AM UTC 24
Finished	Aug 25 01:01:04 AM UTC 24
Peak memory	214164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364536877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.364536877
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/49.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.1678819060
Short name	T863
Test name
Test status
Simulation time	3268832318 ps
CPU time	41.58 seconds
Started	Aug 25 01:00:20 AM UTC 24
Finished	Aug 25 01:01:03 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678819060 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.1678819060
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/49.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.636486328
Short name	T885
Test name
Test status
Simulation time	6376153189 ps
CPU time	207.88 seconds
Started	Aug 25 01:00:20 AM UTC 24
Finished	Aug 25 01:03:51 AM UTC 24
Peak memory	216292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636486328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.636486328
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/49.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.4002081245
Short name	T868
Test name
Test status
Simulation time	3892976889 ps
CPU time	68.16 seconds
Started	Aug 25 01:00:20 AM UTC 24
Finished	Aug 25 01:01:30 AM UTC 24
Peak memory	214236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002081245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.4002081245
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/49.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.2452101265
Short name	T214
Test name
Test status
Simulation time	1019135165 ps
CPU time	21.56 seconds
Started	Aug 25 01:00:17 AM UTC 24
Finished	Aug 25 01:00:40 AM UTC 24
Peak memory	212324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452101265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2452101265
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/49.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device.1721779275
Short name	T71
Test name
Test status
Simulation time	131072424 ps
CPU time	8.55 seconds
Started	Aug 25 12:52:26 AM UTC 24
Finished	Aug 25 12:52:39 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721779275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1721779275
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/5.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.3689749107
Short name	T306
Test name
Test status
Simulation time	37349717 ps
CPU time	3.54 seconds
Started	Aug 25 12:52:27 AM UTC 24
Finished	Aug 25 12:52:33 AM UTC 24
Peak memory	212200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689749107 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.3689749107
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/5.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_error_random.1475577816
Short name	T303
Test name
Test status
Simulation time	146153332 ps
CPU time	3.26 seconds
Started	Aug 25 12:52:27 AM UTC 24
Finished	Aug 25 12:52:33 AM UTC 24
Peak memory	212388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475577816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1475577816
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/5.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_large_delays.955106018
Short name	T145
Test name
Test status
Simulation time	51891403577 ps
CPU time	190.8 seconds
Started	Aug 25 12:52:25 AM UTC 24
Finished	Aug 25 12:55:59 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955106018 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.955106018
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/5.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_slow_rsp.132998152
Short name	T375
Test name
Test status
Simulation time	21021099089 ps
CPU time	73.2 seconds
Started	Aug 25 12:52:26 AM UTC 24
Finished	Aug 25 12:53:45 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132998152 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.132998152
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/5.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_zero_delays.242487611
Short name	T56
Test name
Test status
Simulation time	29482609 ps
CPU time	1.71 seconds
Started	Aug 25 12:52:24 AM UTC 24
Finished	Aug 25 12:52:27 AM UTC 24
Peak memory	211140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242487611 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.242487611
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/5.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_same_source.1158453699
Short name	T5
Test name
Test status
Simulation time	46503402 ps
CPU time	4.76 seconds
Started	Aug 25 12:52:27 AM UTC 24
Finished	Aug 25 12:52:34 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158453699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.1158453699
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/5.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke.1981021991
Short name	T54
Test name
Test status
Simulation time	9385593 ps
CPU time	1.07 seconds
Started	Aug 25 12:52:23 AM UTC 24
Finished	Aug 25 12:52:26 AM UTC 24
Peak memory	211140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981021991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.1981021991
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/5.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_large_delays.4183357283
Short name	T61
Test name
Test status
Simulation time	5921480988 ps
CPU time	13.62 seconds
Started	Aug 25 12:52:24 AM UTC 24
Finished	Aug 25 12:52:39 AM UTC 24
Peak memory	211600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183357283 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.4183357283
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/5.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.1922194215
Short name	T264
Test name
Test status
Simulation time	1092966273 ps
CPU time	7.75 seconds
Started	Aug 25 12:52:24 AM UTC 24
Finished	Aug 25 12:52:33 AM UTC 24
Peak memory	212040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922194215 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1922194215
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/5.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.1482110100
Short name	T55
Test name
Test status
Simulation time	13480975 ps
CPU time	1.29 seconds
Started	Aug 25 12:52:24 AM UTC 24
Finished	Aug 25 12:52:27 AM UTC 24
Peak memory	211236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482110100 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.1482110100
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/5.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all.2740936363
Short name	T326
Test name
Test status
Simulation time	468923119 ps
CPU time	37.47 seconds
Started	Aug 25 12:52:28 AM UTC 24
Finished	Aug 25 12:53:08 AM UTC 24
Peak memory	214176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740936363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.2740936363
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/5.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_error.4083868494
Short name	T296
Test name
Test status
Simulation time	157543544 ps
CPU time	16.93 seconds
Started	Aug 25 12:52:28 AM UTC 24
Finished	Aug 25 12:52:47 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083868494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.4083868494
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/5.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.543390215
Short name	T278
Test name
Test status
Simulation time	5984036568 ps
CPU time	130.43 seconds
Started	Aug 25 12:52:28 AM UTC 24
Finished	Aug 25 12:54:42 AM UTC 24
Peak memory	214240 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543390215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.543390215
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/5.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.1049994486
Short name	T6
Test name
Test status
Simulation time	231702582 ps
CPU time	45.48 seconds
Started	Aug 25 12:52:29 AM UTC 24
Finished	Aug 25 12:53:17 AM UTC 24
Peak memory	214172 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049994486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.1049994486
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/5.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_unmapped_addr.2519878326
Short name	T308
Test name
Test status
Simulation time	383681999 ps
CPU time	6.44 seconds
Started	Aug 25 12:52:27 AM UTC 24
Finished	Aug 25 12:52:36 AM UTC 24
Peak memory	212324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519878326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.2519878326
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/5.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device.2570635416
Short name	T95
Test name
Test status
Simulation time	447524736 ps
CPU time	9.76 seconds
Started	Aug 25 12:52:34 AM UTC 24
Finished	Aug 25 12:52:55 AM UTC 24
Peak memory	212388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570635416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2570635416
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/6.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.323520372
Short name	T241
Test name
Test status
Simulation time	30827036346 ps
CPU time	285.7 seconds
Started	Aug 25 12:52:34 AM UTC 24
Finished	Aug 25 12:57:35 AM UTC 24
Peak memory	214244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323520372 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.323520372
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/6.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.3408418649
Short name	T314
Test name
Test status
Simulation time	117300981 ps
CPU time	4.02 seconds
Started	Aug 25 12:52:34 AM UTC 24
Finished	Aug 25 12:52:50 AM UTC 24
Peak memory	212392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408418649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.3408418649
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/6.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_error_random.2244061778
Short name	T316
Test name
Test status
Simulation time	195942284 ps
CPU time	4.54 seconds
Started	Aug 25 12:52:34 AM UTC 24
Finished	Aug 25 12:52:50 AM UTC 24
Peak memory	212324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244061778 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2244061778
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/6.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random.1936111045
Short name	T319
Test name
Test status
Simulation time	421965802 ps
CPU time	6.95 seconds
Started	Aug 25 12:52:33 AM UTC 24
Finished	Aug 25 12:52:51 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936111045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.1936111045
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/6.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_large_delays.2824775260
Short name	T455
Test name
Test status
Simulation time	56058783516 ps
CPU time	156.01 seconds
Started	Aug 25 12:52:33 AM UTC 24
Finished	Aug 25 12:55:23 AM UTC 24
Peak memory	212256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824775260 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2824775260
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/6.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_slow_rsp.1831745586
Short name	T371
Test name
Test status
Simulation time	4496258217 ps
CPU time	57.41 seconds
Started	Aug 25 12:52:33 AM UTC 24
Finished	Aug 25 12:53:43 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831745586 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.1831745586
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/6.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_zero_delays.3457355434
Short name	T94
Test name
Test status
Simulation time	68008652 ps
CPU time	9.53 seconds
Started	Aug 25 12:52:33 AM UTC 24
Finished	Aug 25 12:52:55 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457355434 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.3457355434
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/6.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_same_source.1915591765
Short name	T295
Test name
Test status
Simulation time	34176780 ps
CPU time	3.28 seconds
Started	Aug 25 12:52:34 AM UTC 24
Finished	Aug 25 12:52:49 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915591765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.1915591765
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/6.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke.434183508
Short name	T300
Test name
Test status
Simulation time	13521746 ps
CPU time	1.48 seconds
Started	Aug 25 12:52:29 AM UTC 24
Finished	Aug 25 12:52:32 AM UTC 24
Peak memory	211092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434183508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.434183508
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/6.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_large_delays.411745201
Short name	T186
Test name
Test status
Simulation time	14448572130 ps
CPU time	14.37 seconds
Started	Aug 25 12:52:33 AM UTC 24
Finished	Aug 25 12:52:59 AM UTC 24
Peak memory	212384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411745201 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.411745201
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/6.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.3327517706
Short name	T97
Test name
Test status
Simulation time	3845332028 ps
CPU time	11.36 seconds
Started	Aug 25 12:52:33 AM UTC 24
Finished	Aug 25 12:52:56 AM UTC 24
Peak memory	212384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327517706 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3327517706
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/6.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.2555245626
Short name	T305
Test name
Test status
Simulation time	23649213 ps
CPU time	1.49 seconds
Started	Aug 25 12:52:31 AM UTC 24
Finished	Aug 25 12:52:33 AM UTC 24
Peak memory	211132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555245626 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.2555245626
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/6.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all.999976478
Short name	T221
Test name
Test status
Simulation time	4906932624 ps
CPU time	90.18 seconds
Started	Aug 25 12:52:34 AM UTC 24
Finished	Aug 25 12:54:17 AM UTC 24
Peak memory	214244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999976478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.999976478
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/6.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_error.1531363129
Short name	T195
Test name
Test status
Simulation time	604130075 ps
CPU time	48.95 seconds
Started	Aug 25 12:52:34 AM UTC 24
Finished	Aug 25 12:53:35 AM UTC 24
Peak memory	214184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531363129 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.1531363129
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/6.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.909180039
Short name	T81
Test name
Test status
Simulation time	224361477 ps
CPU time	21.76 seconds
Started	Aug 25 12:52:34 AM UTC 24
Finished	Aug 25 12:53:08 AM UTC 24
Peak memory	214176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909180039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.909180039
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/6.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.744534433
Short name	T277
Test name
Test status
Simulation time	249844439 ps
CPU time	29.31 seconds
Started	Aug 25 12:52:35 AM UTC 24
Finished	Aug 25 12:53:15 AM UTC 24
Peak memory	214180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744534433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.744534433
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/6.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_unmapped_addr.3508578137
Short name	T66
Test name
Test status
Simulation time	747194429 ps
CPU time	11.63 seconds
Started	Aug 25 12:52:34 AM UTC 24
Finished	Aug 25 12:52:57 AM UTC 24
Peak memory	212132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508578137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3508578137
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/6.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device.3917957450
Short name	T98
Test name
Test status
Simulation time	2281242994 ps
CPU time	16.13 seconds
Started	Aug 25 12:52:36 AM UTC 24
Finished	Aug 25 12:52:56 AM UTC 24
Peak memory	212188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917957450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.3917957450
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/7.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.3828947808
Short name	T240
Test name
Test status
Simulation time	118987538457 ps
CPU time	577.33 seconds
Started	Aug 25 12:52:36 AM UTC 24
Finished	Aug 25 01:02:24 AM UTC 24
Peak memory	217944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828947808 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.3828947808
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/7.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.719318804
Short name	T76
Test name
Test status
Simulation time	484406617 ps
CPU time	4.99 seconds
Started	Aug 25 12:52:37 AM UTC 24
Finished	Aug 25 12:52:44 AM UTC 24
Peak memory	212200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719318804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.719318804
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/7.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_error_random.2898116022
Short name	T317
Test name
Test status
Simulation time	331240158 ps
CPU time	9.68 seconds
Started	Aug 25 12:52:36 AM UTC 24
Finished	Aug 25 12:52:50 AM UTC 24
Peak memory	212324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898116022 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.2898116022
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/7.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random.1669119180
Short name	T75
Test name
Test status
Simulation time	73624613 ps
CPU time	3.34 seconds
Started	Aug 25 12:52:36 AM UTC 24
Finished	Aug 25 12:52:43 AM UTC 24
Peak memory	212120 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669119180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.1669119180
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/7.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_large_delays.2472982864
Short name	T379
Test name
Test status
Simulation time	30111111653 ps
CPU time	68.38 seconds
Started	Aug 25 12:52:36 AM UTC 24
Finished	Aug 25 12:53:49 AM UTC 24
Peak memory	212016 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472982864 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2472982864
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/7.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_slow_rsp.1586621984
Short name	T413
Test name
Test status
Simulation time	35802513368 ps
CPU time	104.3 seconds
Started	Aug 25 12:52:36 AM UTC 24
Finished	Aug 25 12:54:26 AM UTC 24
Peak memory	212180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586621984 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.1586621984
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/7.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_zero_delays.825209062
Short name	T310
Test name
Test status
Simulation time	226420502 ps
CPU time	5.43 seconds
Started	Aug 25 12:52:36 AM UTC 24
Finished	Aug 25 12:52:45 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825209062 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.825209062
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/7.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_same_source.3963009634
Short name	T77
Test name
Test status
Simulation time	36013848 ps
CPU time	5.01 seconds
Started	Aug 25 12:52:36 AM UTC 24
Finished	Aug 25 12:52:45 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963009634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3963009634
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/7.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke.47460459
Short name	T309
Test name
Test status
Simulation time	10753219 ps
CPU time	1.59 seconds
Started	Aug 25 12:52:35 AM UTC 24
Finished	Aug 25 12:52:47 AM UTC 24
Peak memory	211244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47460459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.47460459
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/7.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_large_delays.2630688841
Short name	T325
Test name
Test status
Simulation time	8546167078 ps
CPU time	21.53 seconds
Started	Aug 25 12:52:35 AM UTC 24
Finished	Aug 25 12:53:08 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630688841 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2630688841
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/7.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.758387598
Short name	T185
Test name
Test status
Simulation time	3803687301 ps
CPU time	12.73 seconds
Started	Aug 25 12:52:35 AM UTC 24
Finished	Aug 25 12:52:59 AM UTC 24
Peak memory	212188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758387598 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.758387598
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/7.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.1367414372
Short name	T313
Test name
Test status
Simulation time	10334082 ps
CPU time	1.92 seconds
Started	Aug 25 12:52:35 AM UTC 24
Finished	Aug 25 12:52:48 AM UTC 24
Peak memory	211128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367414372 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.1367414372
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/7.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_error.3291976996
Short name	T207
Test name
Test status
Simulation time	245280565 ps
CPU time	20.57 seconds
Started	Aug 25 12:52:39 AM UTC 24
Finished	Aug 25 12:53:01 AM UTC 24
Peak memory	210808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291976996 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3291976996
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/7.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.3346878068
Short name	T179
Test name
Test status
Simulation time	738612390 ps
CPU time	112.25 seconds
Started	Aug 25 12:52:39 AM UTC 24
Finished	Aug 25 12:54:34 AM UTC 24
Peak memory	216552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346878068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.3346878068
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/7.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.57676730
Short name	T270
Test name
Test status
Simulation time	733399633 ps
CPU time	135.62 seconds
Started	Aug 25 12:52:39 AM UTC 24
Finished	Aug 25 12:54:58 AM UTC 24
Peak memory	218272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57676730 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.57676730
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/7.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_unmapped_addr.2786835296
Short name	T318
Test name
Test status
Simulation time	597188981 ps
CPU time	11.11 seconds
Started	Aug 25 12:52:37 AM UTC 24
Finished	Aug 25 12:52:50 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786835296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2786835296
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/7.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device.3485662048
Short name	T184
Test name
Test status
Simulation time	732145027 ps
CPU time	13.4 seconds
Started	Aug 25 12:52:43 AM UTC 24
Finished	Aug 25 12:52:59 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485662048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.3485662048
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/8.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.335210703
Short name	T234
Test name
Test status
Simulation time	36425502207 ps
CPU time	240.86 seconds
Started	Aug 25 12:52:44 AM UTC 24
Finished	Aug 25 12:56:49 AM UTC 24
Peak memory	214304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335210703 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.335210703
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/8.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.3390292264
Short name	T322
Test name
Test status
Simulation time	25330974 ps
CPU time	2.74 seconds
Started	Aug 25 12:52:45 AM UTC 24
Finished	Aug 25 12:52:52 AM UTC 24
Peak memory	212136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390292264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.3390292264
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/8.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random.1330003083
Short name	T323
Test name
Test status
Simulation time	80308349 ps
CPU time	6.53 seconds
Started	Aug 25 12:52:42 AM UTC 24
Finished	Aug 25 12:52:53 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330003083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.1330003083
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/8.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_large_delays.2485147367
Short name	T88
Test name
Test status
Simulation time	46641506278 ps
CPU time	82.61 seconds
Started	Aug 25 12:52:43 AM UTC 24
Finished	Aug 25 12:54:08 AM UTC 24
Peak memory	212188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485147367 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2485147367
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/8.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_slow_rsp.583647141
Short name	T473
Test name
Test status
Simulation time	32554040325 ps
CPU time	170.2 seconds
Started	Aug 25 12:52:43 AM UTC 24
Finished	Aug 25 12:55:37 AM UTC 24
Peak memory	212196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583647141 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.583647141
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/8.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_zero_delays.1845510245
Short name	T315
Test name
Test status
Simulation time	39005781 ps
CPU time	3.78 seconds
Started	Aug 25 12:52:42 AM UTC 24
Finished	Aug 25 12:52:50 AM UTC 24
Peak memory	212312 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845510245 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.1845510245
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/8.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_same_source.3944841959
Short name	T67
Test name
Test status
Simulation time	1751120738 ps
CPU time	13.68 seconds
Started	Aug 25 12:52:44 AM UTC 24
Finished	Aug 25 12:52:59 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944841959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.3944841959
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/8.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke.1460280639
Short name	T64
Test name
Test status
Simulation time	282271328 ps
CPU time	2.48 seconds
Started	Aug 25 12:52:41 AM UTC 24
Finished	Aug 25 12:52:47 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460280639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1460280639
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/8.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_large_delays.2576829754
Short name	T187
Test name
Test status
Simulation time	9462364301 ps
CPU time	15.21 seconds
Started	Aug 25 12:52:41 AM UTC 24
Finished	Aug 25 12:53:00 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576829754 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.2576829754
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/8.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2854056266
Short name	T96
Test name
Test status
Simulation time	1019265998 ps
CPU time	11.47 seconds
Started	Aug 25 12:52:41 AM UTC 24
Finished	Aug 25 12:52:56 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854056266 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2854056266
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/8.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.610826510
Short name	T311
Test name
Test status
Simulation time	13137173 ps
CPU time	1.47 seconds
Started	Aug 25 12:52:41 AM UTC 24
Finished	Aug 25 12:52:46 AM UTC 24
Peak memory	211124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610826510 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.610826510
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/8.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all.3015539438
Short name	T193
Test name
Test status
Simulation time	885947942 ps
CPU time	44.52 seconds
Started	Aug 25 12:52:45 AM UTC 24
Finished	Aug 25 12:53:35 AM UTC 24
Peak memory	214180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015539438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.3015539438
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/8.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_error.2698862687
Short name	T397
Test name
Test status
Simulation time	12466971489 ps
CPU time	77.35 seconds
Started	Aug 25 12:52:47 AM UTC 24
Finished	Aug 25 12:54:14 AM UTC 24
Peak memory	214248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698862687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.2698862687
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/8.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.843142553
Short name	T286
Test name
Test status
Simulation time	9998017164 ps
CPU time	123.12 seconds
Started	Aug 25 12:52:47 AM UTC 24
Finished	Aug 25 12:55:00 AM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843142553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.843142553
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/8.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.3229948629
Short name	T287
Test name
Test status
Simulation time	3056892220 ps
CPU time	188.38 seconds
Started	Aug 25 12:52:47 AM UTC 24
Finished	Aug 25 12:56:13 AM UTC 24
Peak memory	216480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229948629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.3229948629
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/8.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_unmapped_addr.2033394662
Short name	T78
Test name
Test status
Simulation time	616058983 ps
CPU time	9.17 seconds
Started	Aug 25 12:52:45 AM UTC 24
Finished	Aug 25 12:52:59 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033394662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2033394662
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/8.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device.1840176524
Short name	T219
Test name
Test status
Simulation time	2822723103 ps
CPU time	22.96 seconds
Started	Aug 25 12:52:50 AM UTC 24
Finished	Aug 25 12:53:18 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840176524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1840176524
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/9.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.622923292
Short name	T233
Test name
Test status
Simulation time	22003226012 ps
CPU time	177.59 seconds
Started	Aug 25 12:52:50 AM UTC 24
Finished	Aug 25 12:55:54 AM UTC 24
Peak memory	212320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622923292 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.622923292
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/9.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.710202871
Short name	T331
Test name
Test status
Simulation time	1016078578 ps
CPU time	8.63 seconds
Started	Aug 25 12:52:52 AM UTC 24
Finished	Aug 25 12:53:09 AM UTC 24
Peak memory	212136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710202871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.710202871
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/9.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_error_random.552654374
Short name	T327
Test name
Test status
Simulation time	165574123 ps
CPU time	8.05 seconds
Started	Aug 25 12:52:52 AM UTC 24
Finished	Aug 25 12:53:08 AM UTC 24
Peak memory	212136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552654374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.552654374
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/9.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random.51756150
Short name	T324
Test name
Test status
Simulation time	122502047 ps
CPU time	3.99 seconds
Started	Aug 25 12:52:48 AM UTC 24
Finished	Aug 25 12:52:53 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51756150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.51756150
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/9.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_large_delays.3676680304
Short name	T676
Test name
Test status
Simulation time	39547880523 ps
CPU time	297.98 seconds
Started	Aug 25 12:52:49 AM UTC 24
Finished	Aug 25 12:58:02 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676680304 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.3676680304
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/9.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_slow_rsp.1609414336
Short name	T452
Test name
Test status
Simulation time	11633233760 ps
CPU time	138.49 seconds
Started	Aug 25 12:52:49 AM UTC 24
Finished	Aug 25 12:55:21 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609414336 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1609414336
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/9.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_zero_delays.1506313466
Short name	T106
Test name
Test status
Simulation time	34349258 ps
CPU time	4.78 seconds
Started	Aug 25 12:52:49 AM UTC 24
Finished	Aug 25 12:53:05 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506313466 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.1506313466
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/9.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_same_source.116262743
Short name	T99
Test name
Test status
Simulation time	66768109 ps
CPU time	2.34 seconds
Started	Aug 25 12:52:50 AM UTC 24
Finished	Aug 25 12:52:57 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116262743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.116262743
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/9.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke.2525148506
Short name	T321
Test name
Test status
Simulation time	9499872 ps
CPU time	1.93 seconds
Started	Aug 25 12:52:48 AM UTC 24
Finished	Aug 25 12:52:52 AM UTC 24
Peak memory	211140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525148506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2525148506
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/9.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_large_delays.332773914
Short name	T68
Test name
Test status
Simulation time	5570784759 ps
CPU time	9.46 seconds
Started	Aug 25 12:52:48 AM UTC 24
Finished	Aug 25 12:52:59 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332773914 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.332773914
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/9.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.645502940
Short name	T351
Test name
Test status
Simulation time	1459505350 ps
CPU time	19.07 seconds
Started	Aug 25 12:52:48 AM UTC 24
Finished	Aug 25 12:53:19 AM UTC 24
Peak memory	212372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645502940 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.645502940
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/9.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.3381551476
Short name	T320
Test name
Test status
Simulation time	18458743 ps
CPU time	1.82 seconds
Started	Aug 25 12:52:48 AM UTC 24
Finished	Aug 25 12:52:52 AM UTC 24
Peak memory	211232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381551476 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.3381551476
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/9.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_error.3381346734
Short name	T124
Test name
Test status
Simulation time	2564752162 ps
CPU time	20.87 seconds
Started	Aug 25 12:52:53 AM UTC 24
Finished	Aug 25 12:53:23 AM UTC 24
Peak memory	212392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381346734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3381346734
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/9.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.4202883939
Short name	T147
Test name
Test status
Simulation time	12796254119 ps
CPU time	244.1 seconds
Started	Aug 25 12:52:52 AM UTC 24
Finished	Aug 25 12:57:08 AM UTC 24
Peak memory	216292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202883939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.4202883939
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/9.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.3800450594
Short name	T343
Test name
Test status
Simulation time	68546783 ps
CPU time	11.84 seconds
Started	Aug 25 12:52:53 AM UTC 24
Finished	Aug 25 12:53:14 AM UTC 24
Peak memory	212324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800450594 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.3800450594
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/9.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_unmapped_addr.3002213474
Short name	T82
Test name
Test status
Simulation time	947800999 ps
CPU time	11.13 seconds
Started	Aug 25 12:52:52 AM UTC 24
Finished	Aug 25 12:53:11 AM UTC 24
Peak memory	212128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002213474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3002213474
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/9.xbar_unmapped_addr/latest