Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	404	1			T46	1		T110	1		T53	1
all_values[1]	437	1			T46	2		T110	1		T81	1
all_values[2]	416	1			T44	2		T229	2		T139	1
all_values[3]	419	1			T44	1		T47	1		T229	1
all_values[4]	417	1			T44	1		T46	2		T53	1
all_values[5]	394	1			T47	1		T81	2		T139	4
all_values[6]	446	1			T81	1		T288	1		T139	1
all_values[7]	439	1			T229	1		T139	2		T178	1
all_values[8]	405	1			T44	1		T47	1		T229	1
all_values[9]	401	1			T44	2		T47	1		T139	1
all_values[10]	432	1			T46	2		T110	2		T81	1
all_values[11]	424	1			T44	1		T229	1		T81	3
all_values[12]	387	1			T229	1		T53	1		T81	1
all_values[13]	394	1			T44	1		T46	1		T47	1
all_values[14]	414	1			T46	1		T110	1		T81	1
all_values[15]	415	1			T110	1		T47	2		T53	2
all_values[16]	413	1			T110	2		T47	2		T229	1
all_values[17]	399	1			T47	1		T229	1		T139	3
all_values[18]	369	1			T44	1		T229	2		T53	1
all_values[19]	419	1			T44	2		T46	1		T47	1
all_values[20]	388	1			T44	1		T81	2		T288	1
all_values[21]	395	1			T47	1		T81	1		T139	1
all_values[22]	417	1			T44	1		T46	2		T110	1
all_values[23]	432	1			T47	1		T81	1		T139	1
all_values[24]	383	1			T44	1		T47	1		T53	1
all_values[25]	460	1			T53	1		T81	1		T139	4
all_values[26]	433	1			T229	1		T53	3		T81	2