Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	493	1			T31	1		T154	6		T60	1
all_values[1]	454	1			T256	1		T43	1		T154	2
all_values[2]	466	1			T31	1		T154	7		T60	1
all_values[3]	485	1			T44	1		T31	1		T43	1
all_values[4]	481	1			T31	1		T43	1		T154	2
all_values[5]	460	1			T31	1		T154	6		T88	2
all_values[6]	457	1			T31	1		T43	1		T154	3
all_values[7]	493	1			T21	1		T154	5		T88	1
all_values[8]	460	1			T44	1		T43	1		T154	3
all_values[9]	479	1			T44	3		T31	2		T154	3
all_values[10]	490	1			T43	1		T154	4		T60	1
all_values[11]	465	1			T44	1		T256	1		T154	1
all_values[12]	505	1			T31	3		T154	5		T88	1
all_values[13]	494	1			T44	1		T256	1		T43	4
all_values[14]	454	1			T256	1		T43	1		T154	3
all_values[15]	471	1			T44	1		T31	1		T256	1
all_values[16]	492	1			T31	1		T154	2		T60	1
all_values[17]	483	1			T43	1		T154	3		T60	1
all_values[18]	474	1			T154	2		T88	3		T324	2
all_values[19]	474	1			T44	4		T154	4		T88	4
all_values[20]	461	1			T154	1		T60	2		T88	1
all_values[21]	444	1			T154	3		T60	2		T62	1
all_values[22]	501	1			T154	2		T60	2		T193	1
all_values[23]	480	1			T44	1		T31	1		T154	5
all_values[24]	509	1			T21	1		T31	1		T43	2
all_values[25]	461	1			T154	3		T60	1		T88	2
all_values[26]	518	1			T154	4		T155	1		T62	1