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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.30 100.00 95.80 100.00 100.00 100.00 100.00


Total test records in report: 900
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T776 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.599608120 Aug 28 07:19:33 PM UTC 24 Aug 28 07:19:49 PM UTC 24 2875365052 ps
T777 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.722657499 Aug 28 07:15:58 PM UTC 24 Aug 28 07:19:49 PM UTC 24 273552367533 ps
T778 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.2858554548 Aug 28 07:19:46 PM UTC 24 Aug 28 07:19:50 PM UTC 24 62126306 ps
T779 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.1282379489 Aug 28 07:19:47 PM UTC 24 Aug 28 07:19:50 PM UTC 24 13036339 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.632399754 Aug 28 07:19:44 PM UTC 24 Aug 28 07:19:51 PM UTC 24 223942620 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.2173709659 Aug 28 07:13:31 PM UTC 24 Aug 28 07:19:52 PM UTC 24 67551438057 ps
T780 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.249118961 Aug 28 07:19:42 PM UTC 24 Aug 28 07:19:52 PM UTC 24 191738474 ps
T781 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.2229922471 Aug 28 07:18:06 PM UTC 24 Aug 28 07:19:55 PM UTC 24 3886475737 ps
T782 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.3300725848 Aug 28 07:19:54 PM UTC 24 Aug 28 07:19:56 PM UTC 24 13887082 ps
T783 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.764106132 Aug 28 07:19:53 PM UTC 24 Aug 28 07:19:56 PM UTC 24 127176853 ps
T784 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.1739877690 Aug 28 07:19:42 PM UTC 24 Aug 28 07:19:58 PM UTC 24 2200663000 ps
T785 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.2892407184 Aug 28 07:19:28 PM UTC 24 Aug 28 07:19:59 PM UTC 24 263377714 ps
T786 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.3828194225 Aug 28 07:19:41 PM UTC 24 Aug 28 07:19:59 PM UTC 24 2103087477 ps
T787 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random.2176772293 Aug 28 07:19:42 PM UTC 24 Aug 28 07:19:59 PM UTC 24 1396895326 ps
T788 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.1817752683 Aug 28 07:17:18 PM UTC 24 Aug 28 07:20:01 PM UTC 24 689618983 ps
T789 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.3479566049 Aug 28 07:18:56 PM UTC 24 Aug 28 07:20:01 PM UTC 24 1778350022 ps
T790 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.1887656729 Aug 28 07:19:46 PM UTC 24 Aug 28 07:20:01 PM UTC 24 1795135868 ps
T791 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.2360520114 Aug 28 07:19:46 PM UTC 24 Aug 28 07:20:03 PM UTC 24 666012465 ps
T792 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random.1953665235 Aug 28 07:19:58 PM UTC 24 Aug 28 07:20:03 PM UTC 24 53112098 ps
T793 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.162766767 Aug 28 07:19:41 PM UTC 24 Aug 28 07:20:04 PM UTC 24 129582554 ps
T794 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.2273809476 Aug 28 07:19:58 PM UTC 24 Aug 28 07:20:06 PM UTC 24 40217022 ps
T795 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.1230094704 Aug 28 07:19:54 PM UTC 24 Aug 28 07:20:06 PM UTC 24 1677924727 ps
T796 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.3223579346 Aug 28 07:20:02 PM UTC 24 Aug 28 07:20:06 PM UTC 24 407464478 ps
T797 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.840916676 Aug 28 07:20:02 PM UTC 24 Aug 28 07:20:10 PM UTC 24 429875798 ps
T798 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.294760693 Aug 28 07:19:20 PM UTC 24 Aug 28 07:20:11 PM UTC 24 19034112480 ps
T799 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.1043652209 Aug 28 07:20:04 PM UTC 24 Aug 28 07:20:11 PM UTC 24 99037988 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.2007009120 Aug 28 07:19:50 PM UTC 24 Aug 28 07:20:11 PM UTC 24 123194027 ps
T800 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.1346267752 Aug 28 07:20:08 PM UTC 24 Aug 28 07:20:12 PM UTC 24 246768231 ps
T801 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.2915675187 Aug 28 07:19:56 PM UTC 24 Aug 28 07:20:12 PM UTC 24 1482768473 ps
T802 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.930881200 Aug 28 07:20:12 PM UTC 24 Aug 28 07:20:15 PM UTC 24 16978048 ps
T803 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.2246673068 Aug 28 07:20:04 PM UTC 24 Aug 28 07:20:15 PM UTC 24 447663233 ps
T804 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.1371497641 Aug 28 07:20:02 PM UTC 24 Aug 28 07:20:17 PM UTC 24 1050934849 ps
T805 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.583070465 Aug 28 07:20:14 PM UTC 24 Aug 28 07:20:18 PM UTC 24 14039648 ps
T806 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.843924896 Aug 28 07:20:01 PM UTC 24 Aug 28 07:20:19 PM UTC 24 708173253 ps
T807 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_slow_rsp.1170430652 Aug 28 07:15:14 PM UTC 24 Aug 28 07:20:22 PM UTC 24 20267845871 ps
T808 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.2769291836 Aug 28 07:20:17 PM UTC 24 Aug 28 07:20:25 PM UTC 24 117578953 ps
T809 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.1000639537 Aug 28 07:17:40 PM UTC 24 Aug 28 07:20:26 PM UTC 24 902248684 ps
T810 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2511868503 Aug 28 07:19:22 PM UTC 24 Aug 28 07:20:26 PM UTC 24 14203759792 ps
T811 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.2723165872 Aug 28 07:20:12 PM UTC 24 Aug 28 07:20:26 PM UTC 24 1605407392 ps
T812 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.878898773 Aug 28 07:20:23 PM UTC 24 Aug 28 07:20:27 PM UTC 24 24308410 ps
T813 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random.510241023 Aug 28 07:20:12 PM UTC 24 Aug 28 07:20:27 PM UTC 24 784808392 ps
T814 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.643575035 Aug 28 07:19:38 PM UTC 24 Aug 28 07:20:27 PM UTC 24 2988332885 ps
T815 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.2041275627 Aug 28 07:20:21 PM UTC 24 Aug 28 07:20:28 PM UTC 24 388978146 ps
T816 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.3244246587 Aug 28 07:18:04 PM UTC 24 Aug 28 07:20:28 PM UTC 24 3690653042 ps
T817 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.1878277013 Aug 28 07:20:19 PM UTC 24 Aug 28 07:20:28 PM UTC 24 75045099 ps
T818 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1214576672 Aug 28 07:20:28 PM UTC 24 Aug 28 07:20:30 PM UTC 24 8029871 ps
T819 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.439708550 Aug 28 07:20:12 PM UTC 24 Aug 28 07:20:30 PM UTC 24 2616939080 ps
T820 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.3955830487 Aug 28 07:18:27 PM UTC 24 Aug 28 07:20:31 PM UTC 24 21868624778 ps
T821 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.429807763 Aug 28 07:20:07 PM UTC 24 Aug 28 07:20:31 PM UTC 24 438828514 ps
T822 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.1956983886 Aug 28 07:19:50 PM UTC 24 Aug 28 07:20:31 PM UTC 24 699655626 ps
T823 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.2741507035 Aug 28 07:20:28 PM UTC 24 Aug 28 07:20:31 PM UTC 24 54456747 ps
T824 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.434953939 Aug 28 07:20:24 PM UTC 24 Aug 28 07:20:31 PM UTC 24 1254182455 ps
T825 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.4169153022 Aug 28 07:20:30 PM UTC 24 Aug 28 07:20:36 PM UTC 24 27770889 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.1026365654 Aug 28 07:17:45 PM UTC 24 Aug 28 07:20:37 PM UTC 24 57060377764 ps
T826 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.2565112368 Aug 28 07:20:33 PM UTC 24 Aug 28 07:20:38 PM UTC 24 77384971 ps
T827 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random.704507723 Aug 28 07:20:30 PM UTC 24 Aug 28 07:20:38 PM UTC 24 149371104 ps
T828 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.1801518392 Aug 28 07:20:30 PM UTC 24 Aug 28 07:20:39 PM UTC 24 861361031 ps
T829 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.774280202 Aug 28 07:20:33 PM UTC 24 Aug 28 07:20:39 PM UTC 24 806997412 ps
T830 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.692714863 Aug 28 07:20:36 PM UTC 24 Aug 28 07:20:40 PM UTC 24 20615073 ps
T831 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.3276588145 Aug 28 07:20:33 PM UTC 24 Aug 28 07:20:43 PM UTC 24 204950605 ps
T832 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.3383294441 Aug 28 07:20:30 PM UTC 24 Aug 28 07:20:43 PM UTC 24 1166543724 ps
T833 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2562908683 Aug 28 07:19:52 PM UTC 24 Aug 28 07:20:43 PM UTC 24 304303733 ps
T834 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.295613194 Aug 28 07:20:41 PM UTC 24 Aug 28 07:20:44 PM UTC 24 7930700 ps
T835 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.2315152346 Aug 28 07:20:33 PM UTC 24 Aug 28 07:20:44 PM UTC 24 232989243 ps
T836 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.2819479342 Aug 28 07:20:41 PM UTC 24 Aug 28 07:20:44 PM UTC 24 91389589 ps
T837 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random.298928036 Aug 28 07:20:44 PM UTC 24 Aug 28 07:20:47 PM UTC 24 20524769 ps
T838 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.1093205398 Aug 28 07:20:44 PM UTC 24 Aug 28 07:20:49 PM UTC 24 73236167 ps
T839 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.2670829208 Aug 28 07:19:12 PM UTC 24 Aug 28 07:20:51 PM UTC 24 4470743550 ps
T840 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.2893892356 Aug 28 07:20:48 PM UTC 24 Aug 28 07:20:51 PM UTC 24 122501595 ps
T841 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.3032491885 Aug 28 07:19:25 PM UTC 24 Aug 28 07:20:58 PM UTC 24 796094173 ps
T842 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2351553054 Aug 28 07:18:20 PM UTC 24 Aug 28 07:21:00 PM UTC 24 2189624143 ps
T843 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.978209348 Aug 28 07:20:26 PM UTC 24 Aug 28 07:21:00 PM UTC 24 325613713 ps
T844 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1160034395 Aug 28 07:20:44 PM UTC 24 Aug 28 07:21:01 PM UTC 24 2322350007 ps
T845 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.3327487404 Aug 28 07:19:00 PM UTC 24 Aug 28 07:21:01 PM UTC 24 8542346560 ps
T846 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.16500796 Aug 28 07:20:44 PM UTC 24 Aug 28 07:21:02 PM UTC 24 6874454957 ps
T847 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.2531803660 Aug 28 07:19:44 PM UTC 24 Aug 28 07:21:03 PM UTC 24 19325342094 ps
T848 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.1612128418 Aug 28 07:20:41 PM UTC 24 Aug 28 07:21:05 PM UTC 24 36591381 ps
T849 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.1191473659 Aug 28 07:21:03 PM UTC 24 Aug 28 07:21:06 PM UTC 24 44349663 ps
T850 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.2650798776 Aug 28 07:20:57 PM UTC 24 Aug 28 07:21:06 PM UTC 24 132982305 ps
T851 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.3156253743 Aug 28 07:21:04 PM UTC 24 Aug 28 07:21:07 PM UTC 24 12468424 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.2650264195 Aug 28 07:17:26 PM UTC 24 Aug 28 07:21:08 PM UTC 24 55210360456 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.3997322801 Aug 28 07:17:26 PM UTC 24 Aug 28 07:21:09 PM UTC 24 37751766650 ps
T852 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.587952919 Aug 28 07:20:53 PM UTC 24 Aug 28 07:21:10 PM UTC 24 962085418 ps
T853 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.2898874227 Aug 28 07:20:53 PM UTC 24 Aug 28 07:21:11 PM UTC 24 903874737 ps
T854 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.3210000042 Aug 28 07:20:28 PM UTC 24 Aug 28 07:21:12 PM UTC 24 3324672330 ps
T855 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random.3540680068 Aug 28 07:21:08 PM UTC 24 Aug 28 07:21:13 PM UTC 24 27947440 ps
T856 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.2162250926 Aug 28 07:21:01 PM UTC 24 Aug 28 07:21:13 PM UTC 24 502435209 ps
T857 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.1446825554 Aug 28 07:21:08 PM UTC 24 Aug 28 07:21:13 PM UTC 24 32307488 ps
T858 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.2624525417 Aug 28 07:21:12 PM UTC 24 Aug 28 07:21:15 PM UTC 24 16862665 ps
T859 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.4241545241 Aug 28 07:20:59 PM UTC 24 Aug 28 07:21:16 PM UTC 24 1583492284 ps
T860 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1702324083 Aug 28 07:21:06 PM UTC 24 Aug 28 07:21:18 PM UTC 24 1887119960 ps
T861 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.1378894444 Aug 28 07:18:41 PM UTC 24 Aug 28 07:21:19 PM UTC 24 7966532888 ps
T862 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.1410088034 Aug 28 07:19:38 PM UTC 24 Aug 28 07:21:19 PM UTC 24 22566343524 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.4055604011 Aug 28 07:19:13 PM UTC 24 Aug 28 07:21:21 PM UTC 24 8622804008 ps
T863 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.912229961 Aug 28 07:21:09 PM UTC 24 Aug 28 07:21:21 PM UTC 24 597895231 ps
T864 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.1962533189 Aug 28 07:20:01 PM UTC 24 Aug 28 07:21:22 PM UTC 24 19088452867 ps
T865 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.3857190189 Aug 28 07:21:14 PM UTC 24 Aug 28 07:21:23 PM UTC 24 364859873 ps
T866 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.4258247508 Aug 28 07:20:39 PM UTC 24 Aug 28 07:21:24 PM UTC 24 7279236220 ps
T867 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3712368 Aug 28 07:21:06 PM UTC 24 Aug 28 07:21:26 PM UTC 24 3036120157 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.3121698149 Aug 28 07:18:49 PM UTC 24 Aug 28 07:21:26 PM UTC 24 41559740088 ps
T868 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.1467850710 Aug 28 07:21:14 PM UTC 24 Aug 28 07:21:28 PM UTC 24 2562103520 ps
T869 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.3698206640 Aug 28 07:21:14 PM UTC 24 Aug 28 07:21:30 PM UTC 24 744199266 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.1954879704 Aug 28 07:18:11 PM UTC 24 Aug 28 07:21:30 PM UTC 24 238062978156 ps
T870 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1038404693 Aug 28 07:21:01 PM UTC 24 Aug 28 07:21:36 PM UTC 24 902203673 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.81836398 Aug 28 07:10:53 PM UTC 24 Aug 28 07:21:37 PM UTC 24 103399274342 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.2640048834 Aug 28 07:20:46 PM UTC 24 Aug 28 07:21:39 PM UTC 24 7835483158 ps
T871 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.925971843 Aug 28 07:20:05 PM UTC 24 Aug 28 07:21:40 PM UTC 24 5794989316 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2706535864 Aug 28 07:16:17 PM UTC 24 Aug 28 07:21:40 PM UTC 24 107850843691 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.1542052965 Aug 28 07:19:00 PM UTC 24 Aug 28 07:21:41 PM UTC 24 1098860185 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1113181720 Aug 28 07:19:38 PM UTC 24 Aug 28 07:21:42 PM UTC 24 3118084630 ps
T872 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.649166832 Aug 28 07:18:49 PM UTC 24 Aug 28 07:21:46 PM UTC 24 101195598175 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.548078811 Aug 28 07:20:50 PM UTC 24 Aug 28 07:21:48 PM UTC 24 8152470154 ps
T873 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.3496952723 Aug 28 07:19:15 PM UTC 24 Aug 28 07:21:50 PM UTC 24 761641711 ps
T874 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.1281460475 Aug 28 07:21:19 PM UTC 24 Aug 28 07:21:51 PM UTC 24 440472490 ps
T875 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.2386810149 Aug 28 07:18:22 PM UTC 24 Aug 28 07:21:53 PM UTC 24 11629522900 ps
T876 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2578298480 Aug 28 07:19:20 PM UTC 24 Aug 28 07:21:54 PM UTC 24 45495340668 ps
T877 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.1497010466 Aug 28 07:21:17 PM UTC 24 Aug 28 07:21:59 PM UTC 24 705003031 ps
T878 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.2115928827 Aug 28 07:20:28 PM UTC 24 Aug 28 07:22:00 PM UTC 24 3466793714 ps
T879 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3989819353 Aug 28 07:21:01 PM UTC 24 Aug 28 07:22:02 PM UTC 24 488690911 ps
T880 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2801696760 Aug 28 07:20:39 PM UTC 24 Aug 28 07:22:04 PM UTC 24 496328096 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.852152037 Aug 28 07:20:33 PM UTC 24 Aug 28 07:22:05 PM UTC 24 64051038537 ps
T881 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.70339964 Aug 28 07:19:33 PM UTC 24 Aug 28 07:22:14 PM UTC 24 20298514892 ps
T882 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3800458680 Aug 28 07:21:09 PM UTC 24 Aug 28 07:22:16 PM UTC 24 12027516852 ps
T883 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.3585754604 Aug 28 07:18:29 PM UTC 24 Aug 28 07:22:19 PM UTC 24 163349891131 ps
T884 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.841785391 Aug 28 07:19:44 PM UTC 24 Aug 28 07:22:25 PM UTC 24 20772163633 ps
T885 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3339641851 Aug 28 07:19:08 PM UTC 24 Aug 28 07:22:25 PM UTC 24 109755412602 ps
T886 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.3482010718 Aug 28 07:20:01 PM UTC 24 Aug 28 07:22:33 PM UTC 24 40896649332 ps
T887 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.3507532316 Aug 28 07:19:07 PM UTC 24 Aug 28 07:23:03 PM UTC 24 22525699336 ps
T888 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.2775459924 Aug 28 07:20:46 PM UTC 24 Aug 28 07:23:05 PM UTC 24 13805940035 ps
T889 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.356761691 Aug 28 07:20:14 PM UTC 24 Aug 28 07:23:10 PM UTC 24 44964225539 ps
T890 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.2378476037 Aug 28 07:21:03 PM UTC 24 Aug 28 07:23:18 PM UTC 24 1032097750 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.2270159816 Aug 28 07:20:38 PM UTC 24 Aug 28 07:23:24 PM UTC 24 14044308201 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.4274101232 Aug 28 07:18:15 PM UTC 24 Aug 28 07:23:25 PM UTC 24 37533319830 ps
T891 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3907022878 Aug 28 07:20:07 PM UTC 24 Aug 28 07:23:26 PM UTC 24 6452641184 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.1294733291 Aug 28 07:21:15 PM UTC 24 Aug 28 07:23:26 PM UTC 24 54300960647 ps
T892 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.545066267 Aug 28 07:20:28 PM UTC 24 Aug 28 07:23:27 PM UTC 24 5936940808 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.978937302 Aug 28 07:17:45 PM UTC 24 Aug 28 07:23:31 PM UTC 24 43036194634 ps
T893 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1683284055 Aug 28 07:21:17 PM UTC 24 Aug 28 07:23:43 PM UTC 24 467001635 ps
T894 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.3550076691 Aug 28 07:21:08 PM UTC 24 Aug 28 07:23:49 PM UTC 24 27713098064 ps
T895 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.4094928519 Aug 28 07:20:17 PM UTC 24 Aug 28 07:24:04 PM UTC 24 178284554951 ps
T896 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.1406280524 Aug 28 07:20:33 PM UTC 24 Aug 28 07:24:33 PM UTC 24 114777136451 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1358647176 Aug 28 07:20:33 PM UTC 24 Aug 28 07:24:34 PM UTC 24 33377801655 ps
T897 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.2070099742 Aug 28 07:19:59 PM UTC 24 Aug 28 07:24:36 PM UTC 24 265727638363 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3165133416 Aug 28 07:18:00 PM UTC 24 Aug 28 07:25:24 PM UTC 24 83765343781 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.2392490909 Aug 28 07:18:31 PM UTC 24 Aug 28 07:25:34 PM UTC 24 86083427700 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.1406695697 Aug 28 07:18:51 PM UTC 24 Aug 28 07:26:04 PM UTC 24 142858925990 ps
T898 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3289503514 Aug 28 07:21:12 PM UTC 24 Aug 28 07:26:21 PM UTC 24 48549347789 ps
T899 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3909921451 Aug 28 07:19:34 PM UTC 24 Aug 28 07:26:50 PM UTC 24 91940640095 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1312030455 Aug 28 07:20:18 PM UTC 24 Aug 28 07:26:52 PM UTC 24 42940915685 ps
T900 /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.2289607034 Aug 28 07:19:44 PM UTC 24 Aug 28 07:26:52 PM UTC 24 157521670719 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_error_random.2462722998
Short name T4
Test name
Test status
Simulation time 271319892 ps
CPU time 3.35 seconds
Started Aug 28 07:05:56 PM UTC 24
Finished Aug 28 07:06:00 PM UTC 24
Peak memory 212112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462722998 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.2462722998
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/0.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.3515220767
Short name T119
Test name
Test status
Simulation time 90800912208 ps
CPU time 732.82 seconds
Started Aug 28 07:05:56 PM UTC 24
Finished Aug 28 07:18:19 PM UTC 24
Peak memory 214504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515220767 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.3515220767
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/0.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.33493170
Short name T282
Test name
Test status
Simulation time 25446700414 ps
CPU time 254.27 seconds
Started Aug 28 07:12:57 PM UTC 24
Finished Aug 28 07:17:15 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33493170 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.33493170
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/20.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_unmapped_addr.4091310735
Short name T19
Test name
Test status
Simulation time 55941788 ps
CPU time 5.35 seconds
Started Aug 28 07:05:56 PM UTC 24
Finished Aug 28 07:06:02 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091310735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.4091310735
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/0.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.1482960294
Short name T278
Test name
Test status
Simulation time 69816986663 ps
CPU time 384.18 seconds
Started Aug 28 07:07:53 PM UTC 24
Finished Aug 28 07:14:22 PM UTC 24
Peak memory 214504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482960294 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.1482960294
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/4.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2836494561
Short name T275
Test name
Test status
Simulation time 22993670143 ps
CPU time 203.48 seconds
Started Aug 28 07:15:16 PM UTC 24
Finished Aug 28 07:18:43 PM UTC 24
Peak memory 214240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836494561 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.2836494561
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/27.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.3657136358
Short name T77
Test name
Test status
Simulation time 3587918446 ps
CPU time 97.63 seconds
Started Aug 28 07:06:57 PM UTC 24
Finished Aug 28 07:08:36 PM UTC 24
Peak memory 216424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657136358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.3657136358
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/2.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_large_delays.3745590676
Short name T53
Test name
Test status
Simulation time 3383857812 ps
CPU time 18.21 seconds
Started Aug 28 07:06:04 PM UTC 24
Finished Aug 28 07:06:24 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745590676 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3745590676
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/1.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.2632398184
Short name T96
Test name
Test status
Simulation time 48842047981 ps
CPU time 211.34 seconds
Started Aug 28 07:08:45 PM UTC 24
Finished Aug 28 07:12:21 PM UTC 24
Peak memory 214440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632398184 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.2632398184
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/7.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all.2608331241
Short name T62
Test name
Test status
Simulation time 25255780571 ps
CPU time 86.38 seconds
Started Aug 28 07:06:24 PM UTC 24
Finished Aug 28 07:07:53 PM UTC 24
Peak memory 214236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608331241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2608331241
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/1.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1253986911
Short name T280
Test name
Test status
Simulation time 151043433671 ps
CPU time 463.45 seconds
Started Aug 28 07:09:52 PM UTC 24
Finished Aug 28 07:17:42 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253986911 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.1253986911
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/10.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.81836398
Short name T125
Test name
Test status
Simulation time 103399274342 ps
CPU time 635.25 seconds
Started Aug 28 07:10:53 PM UTC 24
Finished Aug 28 07:21:37 PM UTC 24
Peak memory 216296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81836398 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.81836398
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/13.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_slow_rsp.2922969897
Short name T153
Test name
Test status
Simulation time 19950423998 ps
CPU time 53.22 seconds
Started Aug 28 07:06:12 PM UTC 24
Finished Aug 28 07:07:07 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922969897 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2922969897
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/1.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_error.179722381
Short name T271
Test name
Test status
Simulation time 5603030400 ps
CPU time 102.58 seconds
Started Aug 28 07:11:20 PM UTC 24
Finished Aug 28 07:13:05 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179722381 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.179722381
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/14.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.1968570533
Short name T8
Test name
Test status
Simulation time 1929361141 ps
CPU time 86.18 seconds
Started Aug 28 07:10:01 PM UTC 24
Finished Aug 28 07:11:29 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968570533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.1968570533
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/10.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.328330999
Short name T263
Test name
Test status
Simulation time 32099949007 ps
CPU time 59.62 seconds
Started Aug 28 07:12:12 PM UTC 24
Finished Aug 28 07:13:13 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328330999 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.328330999
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/17.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.301639715
Short name T12
Test name
Test status
Simulation time 1994258121 ps
CPU time 113.85 seconds
Started Aug 28 07:13:54 PM UTC 24
Finished Aug 28 07:15:51 PM UTC 24
Peak memory 216232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301639715 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.301639715
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/23.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.1155021122
Short name T14
Test name
Test status
Simulation time 547856578 ps
CPU time 65.56 seconds
Started Aug 28 07:16:39 PM UTC 24
Finished Aug 28 07:17:47 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155021122 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.1155021122
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/32.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.1542052965
Short name T13
Test name
Test status
Simulation time 1098860185 ps
CPU time 158.61 seconds
Started Aug 28 07:19:00 PM UTC 24
Finished Aug 28 07:21:41 PM UTC 24
Peak memory 216232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542052965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.1542052965
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/40.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.127050270
Short name T9
Test name
Test status
Simulation time 8000598653 ps
CPU time 163.57 seconds
Started Aug 28 07:15:28 PM UTC 24
Finished Aug 28 07:18:15 PM UTC 24
Peak memory 216548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127050270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.127050270
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/27.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.2392490909
Short name T131
Test name
Test status
Simulation time 86083427700 ps
CPU time 416.34 seconds
Started Aug 28 07:18:31 PM UTC 24
Finished Aug 28 07:25:34 PM UTC 24
Peak memory 214500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392490909 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.2392490909
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/39.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device.890100452
Short name T43
Test name
Test status
Simulation time 999597594 ps
CPU time 19.7 seconds
Started Aug 28 07:06:45 PM UTC 24
Finished Aug 28 07:07:06 PM UTC 24
Peak memory 212452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890100452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.890100452
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/2.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.221429205
Short name T198
Test name
Test status
Simulation time 594507393 ps
CPU time 77.79 seconds
Started Aug 28 07:07:07 PM UTC 24
Finished Aug 28 07:08:27 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221429205 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.221429205
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/2.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.1406695697
Short name T289
Test name
Test status
Simulation time 142858925990 ps
CPU time 425.02 seconds
Started Aug 28 07:18:51 PM UTC 24
Finished Aug 28 07:26:04 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406695697 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.1406695697
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/40.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.1936717748
Short name T322
Test name
Test status
Simulation time 310351466 ps
CPU time 30.92 seconds
Started Aug 28 07:11:22 PM UTC 24
Finished Aug 28 07:11:54 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936717748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.1936717748
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/14.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.3178218283
Short name T286
Test name
Test status
Simulation time 3758054149 ps
CPU time 93.72 seconds
Started Aug 28 07:12:36 PM UTC 24
Finished Aug 28 07:14:12 PM UTC 24
Peak memory 216296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178218283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.3178218283
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/18.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_slow_rsp.3329011033
Short name T75
Test name
Test status
Simulation time 34497799961 ps
CPU time 152.87 seconds
Started Aug 28 07:05:56 PM UTC 24
Finished Aug 28 07:08:31 PM UTC 24
Peak memory 212452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329011033 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.3329011033
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/0.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.3244246587
Short name T816
Test name
Test status
Simulation time 3690653042 ps
CPU time 140.91 seconds
Started Aug 28 07:18:04 PM UTC 24
Finished Aug 28 07:20:28 PM UTC 24
Peak memory 216488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244246587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.3244246587
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/37.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all.2752826455
Short name T61
Test name
Test status
Simulation time 2750590382 ps
CPU time 52.45 seconds
Started Aug 28 07:06:57 PM UTC 24
Finished Aug 28 07:07:51 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752826455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.2752826455
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/2.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all.460401806
Short name T219
Test name
Test status
Simulation time 808587677 ps
CPU time 19.59 seconds
Started Aug 28 07:10:00 PM UTC 24
Finished Aug 28 07:10:21 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460401806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.460401806
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/10.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.2173709659
Short name T299
Test name
Test status
Simulation time 67551438057 ps
CPU time 375.34 seconds
Started Aug 28 07:13:31 PM UTC 24
Finished Aug 28 07:19:52 PM UTC 24
Peak memory 214240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173709659 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.2173709659
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/22.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.3435746275
Short name T20
Test name
Test status
Simulation time 46936204 ps
CPU time 5.86 seconds
Started Aug 28 07:05:57 PM UTC 24
Finished Aug 28 07:06:04 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435746275 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.3435746275
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/0.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_large_delays.3340016716
Short name T104
Test name
Test status
Simulation time 63761772117 ps
CPU time 113.44 seconds
Started Aug 28 07:10:31 PM UTC 24
Finished Aug 28 07:12:27 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340016716 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3340016716
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/12.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device.3712686441
Short name T21
Test name
Test status
Simulation time 58043132 ps
CPU time 2.51 seconds
Started Aug 28 07:05:56 PM UTC 24
Finished Aug 28 07:05:59 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712686441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.3712686441
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/0.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random.524781752
Short name T23
Test name
Test status
Simulation time 207533233 ps
CPU time 11.25 seconds
Started Aug 28 07:05:54 PM UTC 24
Finished Aug 28 07:06:07 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524781752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.524781752
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/0.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_large_delays.2290141295
Short name T66
Test name
Test status
Simulation time 23973090077 ps
CPU time 136.04 seconds
Started Aug 28 07:05:56 PM UTC 24
Finished Aug 28 07:08:14 PM UTC 24
Peak memory 212244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290141295 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.2290141295
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/0.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_zero_delays.3976099464
Short name T22
Test name
Test status
Simulation time 70660520 ps
CPU time 7.47 seconds
Started Aug 28 07:05:55 PM UTC 24
Finished Aug 28 07:06:04 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976099464 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.3976099464
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/0.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_same_source.2880612699
Short name T25
Test name
Test status
Simulation time 613172805 ps
CPU time 13.35 seconds
Started Aug 28 07:05:56 PM UTC 24
Finished Aug 28 07:06:10 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880612699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2880612699
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/0.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke.322234436
Short name T1
Test name
Test status
Simulation time 38258589 ps
CPU time 2.16 seconds
Started Aug 28 07:05:53 PM UTC 24
Finished Aug 28 07:05:57 PM UTC 24
Peak memory 212380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322234436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.322234436
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/0.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_large_delays.816056681
Short name T18
Test name
Test status
Simulation time 2541810088 ps
CPU time 14.36 seconds
Started Aug 28 07:05:54 PM UTC 24
Finished Aug 28 07:06:10 PM UTC 24
Peak memory 212268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816056681 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.816056681
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/0.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.1741782243
Short name T26
Test name
Test status
Simulation time 1327263910 ps
CPU time 15.83 seconds
Started Aug 28 07:05:54 PM UTC 24
Finished Aug 28 07:06:12 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741782243 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1741782243
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/0.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.1207553829
Short name T3
Test name
Test status
Simulation time 8821714 ps
CPU time 1.69 seconds
Started Aug 28 07:05:54 PM UTC 24
Finished Aug 28 07:05:58 PM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207553829 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.1207553829
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/0.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all.406067653
Short name T31
Test name
Test status
Simulation time 276289704 ps
CPU time 27.44 seconds
Started Aug 28 07:05:58 PM UTC 24
Finished Aug 28 07:06:27 PM UTC 24
Peak memory 214368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406067653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.406067653
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/0.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_error.370797716
Short name T256
Test name
Test status
Simulation time 5439299740 ps
CPU time 51.89 seconds
Started Aug 28 07:06:01 PM UTC 24
Finished Aug 28 07:06:55 PM UTC 24
Peak memory 212204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370797716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.370797716
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/0.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1871189315
Short name T6
Test name
Test status
Simulation time 858008681 ps
CPU time 176.01 seconds
Started Aug 28 07:06:00 PM UTC 24
Finished Aug 28 07:09:01 PM UTC 24
Peak memory 216232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871189315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.1871189315
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/0.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.163521656
Short name T154
Test name
Test status
Simulation time 508939517 ps
CPU time 66.21 seconds
Started Aug 28 07:06:03 PM UTC 24
Finished Aug 28 07:07:12 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163521656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.163521656
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/0.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device.4143826104
Short name T44
Test name
Test status
Simulation time 99181505 ps
CPU time 8.22 seconds
Started Aug 28 07:06:13 PM UTC 24
Finished Aug 28 07:06:22 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143826104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.4143826104
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/1.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.3612048833
Short name T145
Test name
Test status
Simulation time 12353985565 ps
CPU time 134.21 seconds
Started Aug 28 07:06:13 PM UTC 24
Finished Aug 28 07:08:30 PM UTC 24
Peak memory 212456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612048833 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.3612048833
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/1.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.2526580494
Short name T56
Test name
Test status
Simulation time 1912753112 ps
CPU time 12.86 seconds
Started Aug 28 07:06:23 PM UTC 24
Finished Aug 28 07:06:37 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526580494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.2526580494
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/1.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_error_random.245812517
Short name T54
Test name
Test status
Simulation time 164336731 ps
CPU time 3.19 seconds
Started Aug 28 07:06:20 PM UTC 24
Finished Aug 28 07:06:24 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245812517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.245812517
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/1.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random.3912546792
Short name T29
Test name
Test status
Simulation time 436387265 ps
CPU time 13.83 seconds
Started Aug 28 07:06:09 PM UTC 24
Finished Aug 28 07:06:24 PM UTC 24
Peak memory 211880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912546792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.3912546792
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/1.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_large_delays.904032029
Short name T32
Test name
Test status
Simulation time 6642418513 ps
CPU time 34.48 seconds
Started Aug 28 07:06:12 PM UTC 24
Finished Aug 28 07:06:48 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904032029 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.904032029
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/1.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_zero_delays.4064355720
Short name T27
Test name
Test status
Simulation time 23696037 ps
CPU time 2.4 seconds
Started Aug 28 07:06:09 PM UTC 24
Finished Aug 28 07:06:12 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064355720 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.4064355720
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/1.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_same_source.2718871403
Short name T30
Test name
Test status
Simulation time 578536080 ps
CPU time 9.71 seconds
Started Aug 28 07:06:13 PM UTC 24
Finished Aug 28 07:06:24 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718871403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2718871403
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/1.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke.2070748752
Short name T24
Test name
Test status
Simulation time 60076049 ps
CPU time 2.36 seconds
Started Aug 28 07:06:04 PM UTC 24
Finished Aug 28 07:06:08 PM UTC 24
Peak memory 211000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070748752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.2070748752
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/1.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.4261291864
Short name T28
Test name
Test status
Simulation time 1152892126 ps
CPU time 10.18 seconds
Started Aug 28 07:06:08 PM UTC 24
Finished Aug 28 07:06:20 PM UTC 24
Peak memory 211828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261291864 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.4261291864
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/1.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1820757781
Short name T5
Test name
Test status
Simulation time 9900753 ps
CPU time 2.05 seconds
Started Aug 28 07:06:04 PM UTC 24
Finished Aug 28 07:06:08 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820757781 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.1820757781
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/1.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_error.3186905501
Short name T91
Test name
Test status
Simulation time 4113831671 ps
CPU time 95.06 seconds
Started Aug 28 07:06:25 PM UTC 24
Finished Aug 28 07:08:03 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186905501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.3186905501
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/1.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.2992777801
Short name T310
Test name
Test status
Simulation time 4261121979 ps
CPU time 134.42 seconds
Started Aug 28 07:06:25 PM UTC 24
Finished Aug 28 07:08:42 PM UTC 24
Peak memory 216296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992777801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.2992777801
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/1.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.4255809356
Short name T321
Test name
Test status
Simulation time 1307497478 ps
CPU time 210.18 seconds
Started Aug 28 07:06:25 PM UTC 24
Finished Aug 28 07:09:59 PM UTC 24
Peak memory 220048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255809356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.4255809356
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/1.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_unmapped_addr.1093425878
Short name T55
Test name
Test status
Simulation time 1181684220 ps
CPU time 6.4 seconds
Started Aug 28 07:06:21 PM UTC 24
Finished Aug 28 07:06:29 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093425878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1093425878
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/1.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device.1160767968
Short name T281
Test name
Test status
Simulation time 809864423 ps
CPU time 16.52 seconds
Started Aug 28 07:09:51 PM UTC 24
Finished Aug 28 07:10:09 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160767968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.1160767968
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/10.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.1991452218
Short name T214
Test name
Test status
Simulation time 1100264704 ps
CPU time 11.08 seconds
Started Aug 28 07:10:00 PM UTC 24
Finished Aug 28 07:10:12 PM UTC 24
Peak memory 211892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991452218 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.1991452218
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/10.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_error_random.3614179599
Short name T366
Test name
Test status
Simulation time 140507300 ps
CPU time 2.91 seconds
Started Aug 28 07:09:55 PM UTC 24
Finished Aug 28 07:09:59 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614179599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.3614179599
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/10.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random.3163315502
Short name T86
Test name
Test status
Simulation time 3114970689 ps
CPU time 22.69 seconds
Started Aug 28 07:09:45 PM UTC 24
Finished Aug 28 07:10:09 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163315502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.3163315502
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/10.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_large_delays.3922185674
Short name T459
Test name
Test status
Simulation time 53321031334 ps
CPU time 206.54 seconds
Started Aug 28 07:09:47 PM UTC 24
Finished Aug 28 07:13:17 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922185674 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3922185674
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/10.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_slow_rsp.855276498
Short name T384
Test name
Test status
Simulation time 11981887047 ps
CPU time 72.99 seconds
Started Aug 28 07:09:48 PM UTC 24
Finished Aug 28 07:11:03 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855276498 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.855276498
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/10.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_zero_delays.344159322
Short name T361
Test name
Test status
Simulation time 54454014 ps
CPU time 3.95 seconds
Started Aug 28 07:09:45 PM UTC 24
Finished Aug 28 07:09:50 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344159322 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.344159322
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/10.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_same_source.2969371684
Short name T367
Test name
Test status
Simulation time 485528827 ps
CPU time 4.25 seconds
Started Aug 28 07:09:55 PM UTC 24
Finished Aug 28 07:10:01 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969371684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2969371684
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/10.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke.2561221115
Short name T132
Test name
Test status
Simulation time 109428467 ps
CPU time 2.16 seconds
Started Aug 28 07:09:39 PM UTC 24
Finished Aug 28 07:09:42 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561221115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2561221115
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/10.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_large_delays.923493447
Short name T85
Test name
Test status
Simulation time 2982247422 ps
CPU time 13.5 seconds
Started Aug 28 07:09:43 PM UTC 24
Finished Aug 28 07:09:58 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923493447 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.923493447
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/10.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.2090484141
Short name T368
Test name
Test status
Simulation time 1607573793 ps
CPU time 15.9 seconds
Started Aug 28 07:09:45 PM UTC 24
Finished Aug 28 07:10:02 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090484141 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.2090484141
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/10.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.2747082474
Short name T252
Test name
Test status
Simulation time 14509261 ps
CPU time 1.73 seconds
Started Aug 28 07:09:42 PM UTC 24
Finished Aug 28 07:09:44 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747082474 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.2747082474
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/10.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_error.1350691278
Short name T381
Test name
Test status
Simulation time 1279869269 ps
CPU time 56.6 seconds
Started Aug 28 07:10:01 PM UTC 24
Finished Aug 28 07:10:59 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350691278 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.1350691278
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/10.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.739024035
Short name T311
Test name
Test status
Simulation time 775657993 ps
CPU time 61.35 seconds
Started Aug 28 07:10:02 PM UTC 24
Finished Aug 28 07:11:05 PM UTC 24
Peak memory 214188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739024035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.739024035
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/10.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_unmapped_addr.1694689849
Short name T370
Test name
Test status
Simulation time 199255572 ps
CPU time 8.39 seconds
Started Aug 28 07:09:58 PM UTC 24
Finished Aug 28 07:10:08 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694689849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1694689849
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/10.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device.1139402073
Short name T306
Test name
Test status
Simulation time 261653905 ps
CPU time 8.34 seconds
Started Aug 28 07:10:15 PM UTC 24
Finished Aug 28 07:10:25 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139402073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.1139402073
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/11.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.1617663363
Short name T264
Test name
Test status
Simulation time 55154114895 ps
CPU time 236.72 seconds
Started Aug 28 07:10:15 PM UTC 24
Finished Aug 28 07:14:16 PM UTC 24
Peak memory 214240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617663363 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.1617663363
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/11.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.1290162194
Short name T373
Test name
Test status
Simulation time 90721070 ps
CPU time 3.99 seconds
Started Aug 28 07:10:21 PM UTC 24
Finished Aug 28 07:10:26 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290162194 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.1290162194
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/11.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_error_random.3974483727
Short name T221
Test name
Test status
Simulation time 49396266 ps
CPU time 4.39 seconds
Started Aug 28 07:10:17 PM UTC 24
Finished Aug 28 07:10:23 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974483727 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3974483727
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/11.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random.3679169361
Short name T218
Test name
Test status
Simulation time 355972434 ps
CPU time 5.13 seconds
Started Aug 28 07:10:10 PM UTC 24
Finished Aug 28 07:10:17 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679169361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.3679169361
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/11.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_large_delays.3888577587
Short name T87
Test name
Test status
Simulation time 2749360058 ps
CPU time 15.93 seconds
Started Aug 28 07:10:13 PM UTC 24
Finished Aug 28 07:10:30 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888577587 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.3888577587
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/11.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_slow_rsp.107993296
Short name T105
Test name
Test status
Simulation time 34830607600 ps
CPU time 154.97 seconds
Started Aug 28 07:10:13 PM UTC 24
Finished Aug 28 07:12:51 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107993296 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.107993296
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/11.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_zero_delays.3455013940
Short name T217
Test name
Test status
Simulation time 18823359 ps
CPU time 2.52 seconds
Started Aug 28 07:10:10 PM UTC 24
Finished Aug 28 07:10:15 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455013940 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.3455013940
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/11.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_same_source.1972984647
Short name T220
Test name
Test status
Simulation time 136680887 ps
CPU time 3.32 seconds
Started Aug 28 07:10:16 PM UTC 24
Finished Aug 28 07:10:21 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972984647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.1972984647
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/11.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke.332851179
Short name T369
Test name
Test status
Simulation time 67197692 ps
CPU time 2.52 seconds
Started Aug 28 07:10:03 PM UTC 24
Finished Aug 28 07:10:07 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332851179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.332851179
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/11.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_large_delays.577730038
Short name T371
Test name
Test status
Simulation time 2725922815 ps
CPU time 14.57 seconds
Started Aug 28 07:10:09 PM UTC 24
Finished Aug 28 07:10:25 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577730038 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.577730038
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/11.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.1260655212
Short name T372
Test name
Test status
Simulation time 2500614331 ps
CPU time 12.85 seconds
Started Aug 28 07:10:10 PM UTC 24
Finished Aug 28 07:10:25 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260655212 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.1260655212
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/11.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.849438786
Short name T213
Test name
Test status
Simulation time 8000436 ps
CPU time 1.71 seconds
Started Aug 28 07:10:07 PM UTC 24
Finished Aug 28 07:10:10 PM UTC 24
Peak memory 211172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849438786 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.849438786
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/11.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all.2440156250
Short name T226
Test name
Test status
Simulation time 868702261 ps
CPU time 14.48 seconds
Started Aug 28 07:10:22 PM UTC 24
Finished Aug 28 07:10:38 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440156250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2440156250
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/11.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_error.3809908872
Short name T378
Test name
Test status
Simulation time 1086519389 ps
CPU time 25.36 seconds
Started Aug 28 07:10:24 PM UTC 24
Finished Aug 28 07:10:51 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809908872 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.3809908872
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/11.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.3811458932
Short name T185
Test name
Test status
Simulation time 979420006 ps
CPU time 123.5 seconds
Started Aug 28 07:10:23 PM UTC 24
Finished Aug 28 07:12:30 PM UTC 24
Peak memory 218472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811458932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.3811458932
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/11.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.1162532709
Short name T312
Test name
Test status
Simulation time 1730648464 ps
CPU time 153.94 seconds
Started Aug 28 07:10:25 PM UTC 24
Finished Aug 28 07:13:03 PM UTC 24
Peak memory 218280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162532709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.1162532709
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/11.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_unmapped_addr.481720799
Short name T374
Test name
Test status
Simulation time 207702184 ps
CPU time 7.57 seconds
Started Aug 28 07:10:18 PM UTC 24
Finished Aug 28 07:10:27 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481720799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.481720799
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/11.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device.4207954888
Short name T170
Test name
Test status
Simulation time 54852830 ps
CPU time 8.78 seconds
Started Aug 28 07:10:34 PM UTC 24
Finished Aug 28 07:10:44 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207954888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.4207954888
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/12.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.339608356
Short name T287
Test name
Test status
Simulation time 39269879554 ps
CPU time 293.41 seconds
Started Aug 28 07:10:34 PM UTC 24
Finished Aug 28 07:15:32 PM UTC 24
Peak memory 214504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339608356 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.339608356
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/12.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.1355645851
Short name T173
Test name
Test status
Simulation time 206579500 ps
CPU time 5.13 seconds
Started Aug 28 07:10:40 PM UTC 24
Finished Aug 28 07:10:46 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355645851 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.1355645851
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/12.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_error_random.180640200
Short name T382
Test name
Test status
Simulation time 962931361 ps
CPU time 22.86 seconds
Started Aug 28 07:10:37 PM UTC 24
Finished Aug 28 07:11:02 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180640200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.180640200
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/12.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random.2701617210
Short name T224
Test name
Test status
Simulation time 199670121 ps
CPU time 2.01 seconds
Started Aug 28 07:10:30 PM UTC 24
Finished Aug 28 07:10:33 PM UTC 24
Peak memory 211232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701617210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.2701617210
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/12.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_slow_rsp.4290500412
Short name T447
Test name
Test status
Simulation time 19639419498 ps
CPU time 142.84 seconds
Started Aug 28 07:10:31 PM UTC 24
Finished Aug 28 07:12:57 PM UTC 24
Peak memory 212256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290500412 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.4290500412
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/12.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_zero_delays.115967400
Short name T169
Test name
Test status
Simulation time 155209688 ps
CPU time 11.35 seconds
Started Aug 28 07:10:31 PM UTC 24
Finished Aug 28 07:10:44 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115967400 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.115967400
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/12.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_same_source.1577362699
Short name T172
Test name
Test status
Simulation time 969855037 ps
CPU time 8.46 seconds
Started Aug 28 07:10:35 PM UTC 24
Finished Aug 28 07:10:45 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577362699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1577362699
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/12.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke.3543481666
Short name T375
Test name
Test status
Simulation time 29543111 ps
CPU time 1.34 seconds
Started Aug 28 07:10:27 PM UTC 24
Finished Aug 28 07:10:29 PM UTC 24
Peak memory 211128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543481666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.3543481666
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/12.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_large_delays.1502112037
Short name T171
Test name
Test status
Simulation time 2624756775 ps
CPU time 15.7 seconds
Started Aug 28 07:10:28 PM UTC 24
Finished Aug 28 07:10:45 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502112037 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.1502112037
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/12.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.3289803331
Short name T36
Test name
Test status
Simulation time 2084799269 ps
CPU time 7.35 seconds
Started Aug 28 07:10:28 PM UTC 24
Finished Aug 28 07:10:36 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289803331 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.3289803331
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/12.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.1473350340
Short name T222
Test name
Test status
Simulation time 15287475 ps
CPU time 1.81 seconds
Started Aug 28 07:10:27 PM UTC 24
Finished Aug 28 07:10:30 PM UTC 24
Peak memory 211180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473350340 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.1473350340
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/12.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all.732211224
Short name T175
Test name
Test status
Simulation time 19124121 ps
CPU time 2.93 seconds
Started Aug 28 07:10:44 PM UTC 24
Finished Aug 28 07:10:48 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732211224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.732211224
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/12.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_error.1677531892
Short name T210
Test name
Test status
Simulation time 4162817816 ps
CPU time 59.88 seconds
Started Aug 28 07:10:45 PM UTC 24
Finished Aug 28 07:11:47 PM UTC 24
Peak memory 216296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677531892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1677531892
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/12.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.1549292512
Short name T181
Test name
Test status
Simulation time 4135326832 ps
CPU time 149.72 seconds
Started Aug 28 07:10:45 PM UTC 24
Finished Aug 28 07:13:18 PM UTC 24
Peak memory 216296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549292512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.1549292512
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/12.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.2844031174
Short name T377
Test name
Test status
Simulation time 88704242 ps
CPU time 5.45 seconds
Started Aug 28 07:10:45 PM UTC 24
Finished Aug 28 07:10:51 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844031174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.2844031174
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/12.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_unmapped_addr.3000352690
Short name T174
Test name
Test status
Simulation time 40040601 ps
CPU time 6.26 seconds
Started Aug 28 07:10:39 PM UTC 24
Finished Aug 28 07:10:46 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000352690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.3000352690
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/12.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device.3100528375
Short name T194
Test name
Test status
Simulation time 173138432 ps
CPU time 4.46 seconds
Started Aug 28 07:10:53 PM UTC 24
Finished Aug 28 07:10:58 PM UTC 24
Peak memory 212028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100528375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.3100528375
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/13.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.2222720683
Short name T383
Test name
Test status
Simulation time 74126964 ps
CPU time 3.15 seconds
Started Aug 28 07:10:59 PM UTC 24
Finished Aug 28 07:11:03 PM UTC 24
Peak memory 212396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222720683 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.2222720683
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/13.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_error_random.1625276139
Short name T389
Test name
Test status
Simulation time 296501441 ps
CPU time 9.18 seconds
Started Aug 28 07:10:58 PM UTC 24
Finished Aug 28 07:11:08 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625276139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.1625276139
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/13.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random.1579341282
Short name T391
Test name
Test status
Simulation time 3783284669 ps
CPU time 21.81 seconds
Started Aug 28 07:10:48 PM UTC 24
Finished Aug 28 07:11:12 PM UTC 24
Peak memory 212184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579341282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.1579341282
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/13.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_large_delays.2487423185
Short name T206
Test name
Test status
Simulation time 17361334045 ps
CPU time 51.03 seconds
Started Aug 28 07:10:49 PM UTC 24
Finished Aug 28 07:11:42 PM UTC 24
Peak memory 211872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487423185 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2487423185
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/13.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_slow_rsp.1548803661
Short name T405
Test name
Test status
Simulation time 4832147101 ps
CPU time 35.6 seconds
Started Aug 28 07:10:52 PM UTC 24
Finished Aug 28 07:11:29 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548803661 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.1548803661
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/13.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_zero_delays.1015168403
Short name T379
Test name
Test status
Simulation time 56473468 ps
CPU time 4.41 seconds
Started Aug 28 07:10:49 PM UTC 24
Finished Aug 28 07:10:55 PM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015168403 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.1015168403
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/13.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_same_source.1402547987
Short name T385
Test name
Test status
Simulation time 439314265 ps
CPU time 7.48 seconds
Started Aug 28 07:10:56 PM UTC 24
Finished Aug 28 07:11:04 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402547987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1402547987
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/13.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke.186916956
Short name T176
Test name
Test status
Simulation time 10925805 ps
CPU time 1.53 seconds
Started Aug 28 07:10:46 PM UTC 24
Finished Aug 28 07:10:49 PM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186916956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.186916956
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/13.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_large_delays.2252947465
Short name T390
Test name
Test status
Simulation time 4047591660 ps
CPU time 22.37 seconds
Started Aug 28 07:10:47 PM UTC 24
Finished Aug 28 07:11:11 PM UTC 24
Peak memory 211984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252947465 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2252947465
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/13.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.3552627305
Short name T37
Test name
Test status
Simulation time 1955840909 ps
CPU time 13.84 seconds
Started Aug 28 07:10:47 PM UTC 24
Finished Aug 28 07:11:02 PM UTC 24
Peak memory 211904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552627305 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.3552627305
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/13.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.3341442145
Short name T376
Test name
Test status
Simulation time 9087549 ps
CPU time 1.56 seconds
Started Aug 28 07:10:46 PM UTC 24
Finished Aug 28 07:10:49 PM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341442145 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.3341442145
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/13.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all.2722672395
Short name T266
Test name
Test status
Simulation time 3219625855 ps
CPU time 74.76 seconds
Started Aug 28 07:11:00 PM UTC 24
Finished Aug 28 07:12:17 PM UTC 24
Peak memory 214236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722672395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.2722672395
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/13.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_error.2250273440
Short name T184
Test name
Test status
Simulation time 8707860882 ps
CPU time 83.52 seconds
Started Aug 28 07:11:03 PM UTC 24
Finished Aug 28 07:12:29 PM UTC 24
Peak memory 214504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250273440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2250273440
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/13.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.1437494231
Short name T208
Test name
Test status
Simulation time 199058156 ps
CPU time 39.45 seconds
Started Aug 28 07:11:02 PM UTC 24
Finished Aug 28 07:11:43 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437494231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.1437494231
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/13.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.4014345340
Short name T317
Test name
Test status
Simulation time 109678278 ps
CPU time 21.59 seconds
Started Aug 28 07:11:05 PM UTC 24
Finished Aug 28 07:11:27 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014345340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.4014345340
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/13.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_unmapped_addr.3381925012
Short name T386
Test name
Test status
Simulation time 259092942 ps
CPU time 6.85 seconds
Started Aug 28 07:10:59 PM UTC 24
Finished Aug 28 07:11:07 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381925012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3381925012
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/13.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device.2634863793
Short name T398
Test name
Test status
Simulation time 58949965 ps
CPU time 10.53 seconds
Started Aug 28 07:11:11 PM UTC 24
Finished Aug 28 07:11:23 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634863793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.2634863793
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/14.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.1951963463
Short name T276
Test name
Test status
Simulation time 300421640881 ps
CPU time 495.14 seconds
Started Aug 28 07:11:11 PM UTC 24
Finished Aug 28 07:19:33 PM UTC 24
Peak memory 214240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951963463 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.1951963463
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/14.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.689139558
Short name T396
Test name
Test status
Simulation time 47512678 ps
CPU time 2.75 seconds
Started Aug 28 07:11:16 PM UTC 24
Finished Aug 28 07:11:20 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689139558 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.689139558
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/14.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_error_random.2751444483
Short name T399
Test name
Test status
Simulation time 101346154 ps
CPU time 8.5 seconds
Started Aug 28 07:11:14 PM UTC 24
Finished Aug 28 07:11:23 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751444483 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2751444483
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/14.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random.2486699320
Short name T392
Test name
Test status
Simulation time 338695818 ps
CPU time 5.38 seconds
Started Aug 28 07:11:08 PM UTC 24
Finished Aug 28 07:11:14 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486699320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.2486699320
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/14.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_large_delays.2489075121
Short name T404
Test name
Test status
Simulation time 3012395711 ps
CPU time 19.08 seconds
Started Aug 28 07:11:08 PM UTC 24
Finished Aug 28 07:11:28 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489075121 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.2489075121
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/14.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_slow_rsp.2301916876
Short name T433
Test name
Test status
Simulation time 8904780081 ps
CPU time 91.05 seconds
Started Aug 28 07:11:09 PM UTC 24
Finished Aug 28 07:12:42 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301916876 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.2301916876
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/14.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_zero_delays.2909048069
Short name T393
Test name
Test status
Simulation time 118025876 ps
CPU time 5.72 seconds
Started Aug 28 07:11:08 PM UTC 24
Finished Aug 28 07:11:15 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909048069 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2909048069
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/14.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_same_source.2515586966
Short name T395
Test name
Test status
Simulation time 35575572 ps
CPU time 2.68 seconds
Started Aug 28 07:11:12 PM UTC 24
Finished Aug 28 07:11:16 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515586966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.2515586966
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/14.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke.1989446588
Short name T387
Test name
Test status
Simulation time 11976041 ps
CPU time 1.54 seconds
Started Aug 28 07:11:05 PM UTC 24
Finished Aug 28 07:11:07 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989446588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.1989446588
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/14.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_large_delays.2164639847
Short name T401
Test name
Test status
Simulation time 3809544605 ps
CPU time 19.75 seconds
Started Aug 28 07:11:06 PM UTC 24
Finished Aug 28 07:11:27 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164639847 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2164639847
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/14.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.3269217227
Short name T400
Test name
Test status
Simulation time 1733593839 ps
CPU time 18.33 seconds
Started Aug 28 07:11:07 PM UTC 24
Finished Aug 28 07:11:27 PM UTC 24
Peak memory 212316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269217227 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.3269217227
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/14.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.3029059624
Short name T388
Test name
Test status
Simulation time 8082260 ps
CPU time 1.68 seconds
Started Aug 28 07:11:05 PM UTC 24
Finished Aug 28 07:11:07 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029059624 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.3029059624
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/14.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all.574446344
Short name T411
Test name
Test status
Simulation time 3554863669 ps
CPU time 36.34 seconds
Started Aug 28 07:11:17 PM UTC 24
Finished Aug 28 07:11:55 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574446344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.574446344
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/14.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.4086284754
Short name T421
Test name
Test status
Simulation time 310544186 ps
CPU time 48.13 seconds
Started Aug 28 07:11:17 PM UTC 24
Finished Aug 28 07:12:07 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086284754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.4086284754
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/14.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_unmapped_addr.1654803669
Short name T397
Test name
Test status
Simulation time 26340570 ps
CPU time 4.46 seconds
Started Aug 28 07:11:16 PM UTC 24
Finished Aug 28 07:11:21 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654803669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1654803669
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/14.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device.4126545235
Short name T209
Test name
Test status
Simulation time 292007053 ps
CPU time 13.22 seconds
Started Aug 28 07:11:30 PM UTC 24
Finished Aug 28 07:11:44 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126545235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.4126545235
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/15.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.2726297329
Short name T297
Test name
Test status
Simulation time 76202440161 ps
CPU time 359.52 seconds
Started Aug 28 07:11:30 PM UTC 24
Finished Aug 28 07:17:35 PM UTC 24
Peak memory 214240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726297329 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.2726297329
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/15.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.2907654310
Short name T413
Test name
Test status
Simulation time 488300206 ps
CPU time 13.06 seconds
Started Aug 28 07:11:42 PM UTC 24
Finished Aug 28 07:11:57 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907654310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2907654310
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/15.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_error_random.3492703941
Short name T410
Test name
Test status
Simulation time 856699117 ps
CPU time 20.18 seconds
Started Aug 28 07:11:33 PM UTC 24
Finished Aug 28 07:11:54 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492703941 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3492703941
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/15.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random.899207055
Short name T205
Test name
Test status
Simulation time 676647506 ps
CPU time 12.8 seconds
Started Aug 28 07:11:27 PM UTC 24
Finished Aug 28 07:11:41 PM UTC 24
Peak memory 212116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899207055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.899207055
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/15.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_large_delays.3919439139
Short name T422
Test name
Test status
Simulation time 7053541555 ps
CPU time 36.9 seconds
Started Aug 28 07:11:29 PM UTC 24
Finished Aug 28 07:12:07 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919439139 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.3919439139
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/15.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_slow_rsp.3344763032
Short name T139
Test name
Test status
Simulation time 4033935645 ps
CPU time 43.34 seconds
Started Aug 28 07:11:30 PM UTC 24
Finished Aug 28 07:12:15 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344763032 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3344763032
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/15.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_zero_delays.4267567738
Short name T203
Test name
Test status
Simulation time 81648605 ps
CPU time 4.01 seconds
Started Aug 28 07:11:27 PM UTC 24
Finished Aug 28 07:11:32 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267567738 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.4267567738
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/15.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_same_source.3925856576
Short name T406
Test name
Test status
Simulation time 842541748 ps
CPU time 14.51 seconds
Started Aug 28 07:11:33 PM UTC 24
Finished Aug 28 07:11:49 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925856576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.3925856576
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/15.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke.3350109483
Short name T402
Test name
Test status
Simulation time 10077482 ps
CPU time 1.84 seconds
Started Aug 28 07:11:24 PM UTC 24
Finished Aug 28 07:11:27 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350109483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3350109483
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/15.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_large_delays.2704361573
Short name T207
Test name
Test status
Simulation time 4220681341 ps
CPU time 14.51 seconds
Started Aug 28 07:11:27 PM UTC 24
Finished Aug 28 07:11:43 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704361573 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2704361573
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/15.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.2135591017
Short name T409
Test name
Test status
Simulation time 2455700653 ps
CPU time 24.17 seconds
Started Aug 28 07:11:27 PM UTC 24
Finished Aug 28 07:11:53 PM UTC 24
Peak memory 212448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135591017 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.2135591017
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/15.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.2665475388
Short name T403
Test name
Test status
Simulation time 10096433 ps
CPU time 1.86 seconds
Started Aug 28 07:11:24 PM UTC 24
Finished Aug 28 07:11:27 PM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665475388 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.2665475388
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/15.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all.611927975
Short name T448
Test name
Test status
Simulation time 3358090955 ps
CPU time 74.25 seconds
Started Aug 28 07:11:43 PM UTC 24
Finished Aug 28 07:13:00 PM UTC 24
Peak memory 214500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611927975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.611927975
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/15.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_error.868728434
Short name T233
Test name
Test status
Simulation time 5117810929 ps
CPU time 102.38 seconds
Started Aug 28 07:11:44 PM UTC 24
Finished Aug 28 07:13:30 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868728434 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.868728434
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/15.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3203136499
Short name T408
Test name
Test status
Simulation time 53034468 ps
CPU time 6.78 seconds
Started Aug 28 07:11:44 PM UTC 24
Finished Aug 28 07:11:53 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203136499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.3203136499
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/15.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.2305096299
Short name T136
Test name
Test status
Simulation time 249949159 ps
CPU time 25.32 seconds
Started Aug 28 07:11:45 PM UTC 24
Finished Aug 28 07:12:11 PM UTC 24
Peak memory 214376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305096299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.2305096299
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/15.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_unmapped_addr.3770536273
Short name T380
Test name
Test status
Simulation time 109925350 ps
CPU time 4.05 seconds
Started Aug 28 07:11:38 PM UTC 24
Finished Aug 28 07:11:44 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770536273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3770536273
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/15.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device.1482351217
Short name T102
Test name
Test status
Simulation time 856329006 ps
CPU time 27.83 seconds
Started Aug 28 07:11:55 PM UTC 24
Finished Aug 28 07:12:25 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482351217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.1482351217
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/16.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3579801447
Short name T284
Test name
Test status
Simulation time 34865755501 ps
CPU time 245.8 seconds
Started Aug 28 07:11:55 PM UTC 24
Finished Aug 28 07:16:06 PM UTC 24
Peak memory 214436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579801447 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.3579801447
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/16.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.167361935
Short name T420
Test name
Test status
Simulation time 79366748 ps
CPU time 4.54 seconds
Started Aug 28 07:12:00 PM UTC 24
Finished Aug 28 07:12:05 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167361935 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.167361935
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/16.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_error_random.560377876
Short name T423
Test name
Test status
Simulation time 1114740972 ps
CPU time 18.7 seconds
Started Aug 28 07:11:58 PM UTC 24
Finished Aug 28 07:12:18 PM UTC 24
Peak memory 211264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560377876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.560377876
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/16.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random.1092571539
Short name T414
Test name
Test status
Simulation time 55765646 ps
CPU time 5.79 seconds
Started Aug 28 07:11:52 PM UTC 24
Finished Aug 28 07:11:59 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092571539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.1092571539
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/16.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_large_delays.849918630
Short name T582
Test name
Test status
Simulation time 100855219886 ps
CPU time 270.04 seconds
Started Aug 28 07:11:53 PM UTC 24
Finished Aug 28 07:16:27 PM UTC 24
Peak memory 212396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849918630 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.849918630
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/16.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_slow_rsp.2213560933
Short name T631
Test name
Test status
Simulation time 83041424863 ps
CPU time 330.72 seconds
Started Aug 28 07:11:54 PM UTC 24
Finished Aug 28 07:17:30 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213560933 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2213560933
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/16.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_zero_delays.1472550271
Short name T412
Test name
Test status
Simulation time 14926820 ps
CPU time 2 seconds
Started Aug 28 07:11:53 PM UTC 24
Finished Aug 28 07:11:56 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472550271 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.1472550271
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/16.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_same_source.3231739967
Short name T417
Test name
Test status
Simulation time 52316438 ps
CPU time 5.64 seconds
Started Aug 28 07:11:55 PM UTC 24
Finished Aug 28 07:12:03 PM UTC 24
Peak memory 212256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231739967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.3231739967
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/16.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke.295305009
Short name T211
Test name
Test status
Simulation time 13576308 ps
CPU time 1.7 seconds
Started Aug 28 07:11:46 PM UTC 24
Finished Aug 28 07:11:49 PM UTC 24
Peak memory 211180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295305009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.295305009
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/16.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_large_delays.3916730618
Short name T94
Test name
Test status
Simulation time 1888913780 ps
CPU time 15.71 seconds
Started Aug 28 07:11:50 PM UTC 24
Finished Aug 28 07:12:07 PM UTC 24
Peak memory 212032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916730618 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3916730618
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/16.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.2792489934
Short name T419
Test name
Test status
Simulation time 1123128265 ps
CPU time 14.28 seconds
Started Aug 28 07:11:50 PM UTC 24
Finished Aug 28 07:12:05 PM UTC 24
Peak memory 212208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792489934 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2792489934
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/16.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.3255384065
Short name T407
Test name
Test status
Simulation time 12591069 ps
CPU time 1.72 seconds
Started Aug 28 07:11:48 PM UTC 24
Finished Aug 28 07:11:51 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255384065 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.3255384065
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/16.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all.3500863805
Short name T309
Test name
Test status
Simulation time 1132239434 ps
CPU time 18.15 seconds
Started Aug 28 07:12:01 PM UTC 24
Finished Aug 28 07:12:21 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500863805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3500863805
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/16.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_error.3793193631
Short name T100
Test name
Test status
Simulation time 268791909 ps
CPU time 19.72 seconds
Started Aug 28 07:12:03 PM UTC 24
Finished Aug 28 07:12:24 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793193631 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.3793193631
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/16.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.1005820977
Short name T320
Test name
Test status
Simulation time 9549809449 ps
CPU time 98.41 seconds
Started Aug 28 07:12:01 PM UTC 24
Finished Aug 28 07:13:42 PM UTC 24
Peak memory 216360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005820977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.1005820977
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/16.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.186970100
Short name T231
Test name
Test status
Simulation time 4948521335 ps
CPU time 82.86 seconds
Started Aug 28 07:12:04 PM UTC 24
Finished Aug 28 07:13:29 PM UTC 24
Peak memory 216296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186970100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.186970100
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/16.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_unmapped_addr.3444744520
Short name T416
Test name
Test status
Simulation time 11554757 ps
CPU time 1.59 seconds
Started Aug 28 07:11:58 PM UTC 24
Finished Aug 28 07:12:00 PM UTC 24
Peak memory 211140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444744520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3444744520
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/16.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device.1557518114
Short name T141
Test name
Test status
Simulation time 1023568315 ps
CPU time 4.66 seconds
Started Aug 28 07:12:10 PM UTC 24
Finished Aug 28 07:12:16 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557518114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.1557518114
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/17.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.182499214
Short name T183
Test name
Test status
Simulation time 509608139 ps
CPU time 11.11 seconds
Started Aug 28 07:12:16 PM UTC 24
Finished Aug 28 07:12:29 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182499214 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.182499214
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/17.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_error_random.2510180610
Short name T424
Test name
Test status
Simulation time 70540259 ps
CPU time 2.85 seconds
Started Aug 28 07:12:14 PM UTC 24
Finished Aug 28 07:12:18 PM UTC 24
Peak memory 212080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510180610 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2510180610
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/17.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random.2899946227
Short name T137
Test name
Test status
Simulation time 37808125 ps
CPU time 4.99 seconds
Started Aug 28 07:12:07 PM UTC 24
Finished Aug 28 07:12:13 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899946227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.2899946227
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/17.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_large_delays.3971297413
Short name T103
Test name
Test status
Simulation time 10595395127 ps
CPU time 14.1 seconds
Started Aug 28 07:12:10 PM UTC 24
Finished Aug 28 07:12:25 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971297413 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3971297413
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/17.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_slow_rsp.3469600406
Short name T474
Test name
Test status
Simulation time 9694863587 ps
CPU time 90.51 seconds
Started Aug 28 07:12:10 PM UTC 24
Finished Aug 28 07:13:42 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469600406 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3469600406
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/17.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_zero_delays.1724352528
Short name T138
Test name
Test status
Simulation time 32720626 ps
CPU time 3.89 seconds
Started Aug 28 07:12:09 PM UTC 24
Finished Aug 28 07:12:14 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724352528 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.1724352528
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/17.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_same_source.3453208423
Short name T99
Test name
Test status
Simulation time 379132157 ps
CPU time 7.84 seconds
Started Aug 28 07:12:14 PM UTC 24
Finished Aug 28 07:12:23 PM UTC 24
Peak memory 212172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453208423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3453208423
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/17.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke.992977336
Short name T135
Test name
Test status
Simulation time 15254993 ps
CPU time 1.91 seconds
Started Aug 28 07:12:06 PM UTC 24
Finished Aug 28 07:12:09 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992977336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.992977336
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/17.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_large_delays.904696541
Short name T97
Test name
Test status
Simulation time 2006623245 ps
CPU time 14.16 seconds
Started Aug 28 07:12:07 PM UTC 24
Finished Aug 28 07:12:23 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904696541 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.904696541
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/17.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.2297747927
Short name T140
Test name
Test status
Simulation time 472281027 ps
CPU time 7.03 seconds
Started Aug 28 07:12:07 PM UTC 24
Finished Aug 28 07:12:16 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297747927 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2297747927
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/17.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.3013797023
Short name T133
Test name
Test status
Simulation time 8840883 ps
CPU time 1.56 seconds
Started Aug 28 07:12:06 PM UTC 24
Finished Aug 28 07:12:09 PM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013797023 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.3013797023
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/17.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all.3851121938
Short name T434
Test name
Test status
Simulation time 541967656 ps
CPU time 24.84 seconds
Started Aug 28 07:12:16 PM UTC 24
Finished Aug 28 07:12:43 PM UTC 24
Peak memory 214372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851121938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3851121938
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/17.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_error.479308867
Short name T182
Test name
Test status
Simulation time 152151172 ps
CPU time 8.53 seconds
Started Aug 28 07:12:18 PM UTC 24
Finished Aug 28 07:12:28 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479308867 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.479308867
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/17.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.2958882036
Short name T314
Test name
Test status
Simulation time 10305467477 ps
CPU time 196.84 seconds
Started Aug 28 07:12:18 PM UTC 24
Finished Aug 28 07:15:39 PM UTC 24
Peak memory 216296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958882036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.2958882036
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/17.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.2456057607
Short name T431
Test name
Test status
Simulation time 145294050 ps
CPU time 20.67 seconds
Started Aug 28 07:12:19 PM UTC 24
Finished Aug 28 07:12:40 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456057607 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.2456057607
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/17.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_unmapped_addr.46242668
Short name T425
Test name
Test status
Simulation time 11975346 ps
CPU time 2.03 seconds
Started Aug 28 07:12:15 PM UTC 24
Finished Aug 28 07:12:18 PM UTC 24
Peak memory 212316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46242668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.46242668
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/17.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device.2762632816
Short name T186
Test name
Test status
Simulation time 20897414 ps
CPU time 4.57 seconds
Started Aug 28 07:12:25 PM UTC 24
Finished Aug 28 07:12:31 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762632816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.2762632816
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/18.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.404281593
Short name T273
Test name
Test status
Simulation time 42764988055 ps
CPU time 161.09 seconds
Started Aug 28 07:12:26 PM UTC 24
Finished Aug 28 07:15:11 PM UTC 24
Peak memory 214248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404281593 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.404281593
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/18.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.176444411
Short name T426
Test name
Test status
Simulation time 872670252 ps
CPU time 8.11 seconds
Started Aug 28 07:12:30 PM UTC 24
Finished Aug 28 07:12:39 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176444411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.176444411
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/18.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_error_random.3604537291
Short name T187
Test name
Test status
Simulation time 28649184 ps
CPU time 2.49 seconds
Started Aug 28 07:12:28 PM UTC 24
Finished Aug 28 07:12:32 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604537291 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3604537291
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/18.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random.1375504340
Short name T180
Test name
Test status
Simulation time 589115266 ps
CPU time 13.01 seconds
Started Aug 28 07:12:24 PM UTC 24
Finished Aug 28 07:12:38 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375504340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.1375504340
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/18.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_large_delays.4082408426
Short name T575
Test name
Test status
Simulation time 51810926559 ps
CPU time 231.94 seconds
Started Aug 28 07:12:25 PM UTC 24
Finished Aug 28 07:16:21 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082408426 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.4082408426
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/18.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_slow_rsp.201162362
Short name T571
Test name
Test status
Simulation time 61429412324 ps
CPU time 226.35 seconds
Started Aug 28 07:12:25 PM UTC 24
Finished Aug 28 07:16:15 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201162362 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.201162362
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/18.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_zero_delays.1006854811
Short name T188
Test name
Test status
Simulation time 117338891 ps
CPU time 9.95 seconds
Started Aug 28 07:12:24 PM UTC 24
Finished Aug 28 07:12:35 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006854811 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.1006854811
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/18.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_same_source.3398948858
Short name T228
Test name
Test status
Simulation time 2925887173 ps
CPU time 11.48 seconds
Started Aug 28 07:12:28 PM UTC 24
Finished Aug 28 07:12:41 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398948858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3398948858
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/18.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke.10881020
Short name T98
Test name
Test status
Simulation time 389772242 ps
CPU time 2.31 seconds
Started Aug 28 07:12:20 PM UTC 24
Finished Aug 28 07:12:23 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10881020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs
/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.10881020
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/18.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_large_delays.2646672507
Short name T432
Test name
Test status
Simulation time 2695727773 ps
CPU time 18.04 seconds
Started Aug 28 07:12:22 PM UTC 24
Finished Aug 28 07:12:41 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646672507 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.2646672507
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/18.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.1723412752
Short name T189
Test name
Test status
Simulation time 5417531610 ps
CPU time 11.56 seconds
Started Aug 28 07:12:24 PM UTC 24
Finished Aug 28 07:12:37 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723412752 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.1723412752
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/18.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.3079148157
Short name T101
Test name
Test status
Simulation time 9192423 ps
CPU time 1.88 seconds
Started Aug 28 07:12:22 PM UTC 24
Finished Aug 28 07:12:25 PM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079148157 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.3079148157
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/18.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all.1571449377
Short name T230
Test name
Test status
Simulation time 447028388 ps
CPU time 55.46 seconds
Started Aug 28 07:12:31 PM UTC 24
Finished Aug 28 07:13:29 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571449377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.1571449377
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/18.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_error.550617869
Short name T302
Test name
Test status
Simulation time 5941029840 ps
CPU time 51.83 seconds
Started Aug 28 07:12:33 PM UTC 24
Finished Aug 28 07:13:27 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550617869 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.550617869
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/18.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.510267154
Short name T429
Test name
Test status
Simulation time 97952402 ps
CPU time 7.18 seconds
Started Aug 28 07:12:32 PM UTC 24
Finished Aug 28 07:12:40 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510267154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.510267154
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/18.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_unmapped_addr.2588538078
Short name T427
Test name
Test status
Simulation time 92204889 ps
CPU time 8.92 seconds
Started Aug 28 07:12:30 PM UTC 24
Finished Aug 28 07:12:40 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588538078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.2588538078
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/18.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device.1577351894
Short name T435
Test name
Test status
Simulation time 99788494 ps
CPU time 2.46 seconds
Started Aug 28 07:12:42 PM UTC 24
Finished Aug 28 07:12:45 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577351894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.1577351894
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/19.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.3368879040
Short name T294
Test name
Test status
Simulation time 31908003457 ps
CPU time 56.77 seconds
Started Aug 28 07:12:42 PM UTC 24
Finished Aug 28 07:13:40 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368879040 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.3368879040
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/19.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.2926297134
Short name T438
Test name
Test status
Simulation time 17225235 ps
CPU time 2.66 seconds
Started Aug 28 07:12:44 PM UTC 24
Finished Aug 28 07:12:48 PM UTC 24
Peak memory 212332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926297134 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.2926297134
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/19.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_error_random.2307782311
Short name T441
Test name
Test status
Simulation time 56578405 ps
CPU time 7.6 seconds
Started Aug 28 07:12:42 PM UTC 24
Finished Aug 28 07:12:50 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307782311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.2307782311
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/19.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random.2243993630
Short name T439
Test name
Test status
Simulation time 306240200 ps
CPU time 7.52 seconds
Started Aug 28 07:12:40 PM UTC 24
Finished Aug 28 07:12:49 PM UTC 24
Peak memory 212316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243993630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.2243993630
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/19.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_large_delays.1875010420
Short name T443
Test name
Test status
Simulation time 2239025391 ps
CPU time 10.2 seconds
Started Aug 28 07:12:40 PM UTC 24
Finished Aug 28 07:12:52 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875010420 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1875010420
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/19.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_slow_rsp.3887159365
Short name T470
Test name
Test status
Simulation time 8764686885 ps
CPU time 51.59 seconds
Started Aug 28 07:12:42 PM UTC 24
Finished Aug 28 07:13:35 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887159365 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.3887159365
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/19.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_zero_delays.1012117329
Short name T437
Test name
Test status
Simulation time 52354601 ps
CPU time 6.31 seconds
Started Aug 28 07:12:40 PM UTC 24
Finished Aug 28 07:12:48 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012117329 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.1012117329
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/19.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_same_source.2453694385
Short name T445
Test name
Test status
Simulation time 758493489 ps
CPU time 13.41 seconds
Started Aug 28 07:12:42 PM UTC 24
Finished Aug 28 07:12:56 PM UTC 24
Peak memory 211968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453694385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.2453694385
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/19.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke.1865336438
Short name T430
Test name
Test status
Simulation time 97104223 ps
CPU time 2.37 seconds
Started Aug 28 07:12:37 PM UTC 24
Finished Aug 28 07:12:40 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865336438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.1865336438
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/19.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3579104653
Short name T436
Test name
Test status
Simulation time 1719566350 ps
CPU time 8.05 seconds
Started Aug 28 07:12:38 PM UTC 24
Finished Aug 28 07:12:47 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579104653 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3579104653
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/19.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.4153673928
Short name T449
Test name
Test status
Simulation time 5746616312 ps
CPU time 18.66 seconds
Started Aug 28 07:12:39 PM UTC 24
Finished Aug 28 07:13:00 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153673928 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.4153673928
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/19.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.803194014
Short name T428
Test name
Test status
Simulation time 21274898 ps
CPU time 1.88 seconds
Started Aug 28 07:12:37 PM UTC 24
Finished Aug 28 07:12:40 PM UTC 24
Peak memory 211128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803194014 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.803194014
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/19.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all.3385238803
Short name T236
Test name
Test status
Simulation time 2330264241 ps
CPU time 46.6 seconds
Started Aug 28 07:12:46 PM UTC 24
Finished Aug 28 07:13:34 PM UTC 24
Peak memory 214236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385238803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.3385238803
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/19.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_error.2946782247
Short name T303
Test name
Test status
Simulation time 490774959 ps
CPU time 6.52 seconds
Started Aug 28 07:12:48 PM UTC 24
Finished Aug 28 07:12:56 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946782247 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.2946782247
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/19.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.4053414009
Short name T117
Test name
Test status
Simulation time 4100704846 ps
CPU time 109.46 seconds
Started Aug 28 07:12:48 PM UTC 24
Finished Aug 28 07:14:40 PM UTC 24
Peak memory 216296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053414009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.4053414009
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/19.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.10908016
Short name T514
Test name
Test status
Simulation time 1048481616 ps
CPU time 133.59 seconds
Started Aug 28 07:12:49 PM UTC 24
Finished Aug 28 07:15:06 PM UTC 24
Peak memory 216236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10908016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.10908016
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/19.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_unmapped_addr.3075922622
Short name T440
Test name
Test status
Simulation time 39955193 ps
CPU time 5.78 seconds
Started Aug 28 07:12:43 PM UTC 24
Finished Aug 28 07:12:50 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075922622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3075922622
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/19.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.482703116
Short name T155
Test name
Test status
Simulation time 8468819536 ps
CPU time 31.86 seconds
Started Aug 28 07:06:45 PM UTC 24
Finished Aug 28 07:07:18 PM UTC 24
Peak memory 212452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482703116 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.482703116
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/2.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.3720315821
Short name T257
Test name
Test status
Simulation time 611313980 ps
CPU time 8.98 seconds
Started Aug 28 07:06:55 PM UTC 24
Finished Aug 28 07:07:06 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720315821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.3720315821
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/2.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_error_random.2685098294
Short name T259
Test name
Test status
Simulation time 356422985 ps
CPU time 5.98 seconds
Started Aug 28 07:06:48 PM UTC 24
Finished Aug 28 07:06:55 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685098294 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2685098294
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/2.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random.2523674800
Short name T47
Test name
Test status
Simulation time 75638924 ps
CPU time 6.49 seconds
Started Aug 28 07:06:32 PM UTC 24
Finished Aug 28 07:06:40 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523674800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.2523674800
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/2.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_large_delays.2021162237
Short name T347
Test name
Test status
Simulation time 30338840468 ps
CPU time 149.45 seconds
Started Aug 28 07:06:38 PM UTC 24
Finished Aug 28 07:09:11 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021162237 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2021162237
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/2.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_slow_rsp.2839434931
Short name T301
Test name
Test status
Simulation time 21890882938 ps
CPU time 153.34 seconds
Started Aug 28 07:06:40 PM UTC 24
Finished Aug 28 07:09:16 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839434931 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2839434931
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/2.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_zero_delays.3312057192
Short name T48
Test name
Test status
Simulation time 67945748 ps
CPU time 8.19 seconds
Started Aug 28 07:06:37 PM UTC 24
Finished Aug 28 07:06:46 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312057192 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.3312057192
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/2.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_same_source.1817174359
Short name T42
Test name
Test status
Simulation time 1555306935 ps
CPU time 17.05 seconds
Started Aug 28 07:06:47 PM UTC 24
Finished Aug 28 07:07:06 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817174359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.1817174359
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/2.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke.1996664911
Short name T45
Test name
Test status
Simulation time 11241702 ps
CPU time 1.62 seconds
Started Aug 28 07:06:27 PM UTC 24
Finished Aug 28 07:06:30 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996664911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.1996664911
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/2.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_large_delays.4275890271
Short name T260
Test name
Test status
Simulation time 1298645426 ps
CPU time 13.07 seconds
Started Aug 28 07:06:30 PM UTC 24
Finished Aug 28 07:06:44 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275890271 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.4275890271
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/2.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.548867657
Short name T33
Test name
Test status
Simulation time 2244024655 ps
CPU time 19.73 seconds
Started Aug 28 07:06:31 PM UTC 24
Finished Aug 28 07:06:52 PM UTC 24
Peak memory 212456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548867657 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.548867657
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/2.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.2060946912
Short name T46
Test name
Test status
Simulation time 27834644 ps
CPU time 1.67 seconds
Started Aug 28 07:06:29 PM UTC 24
Finished Aug 28 07:06:31 PM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060946912 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.2060946912
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/2.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_error.1850301014
Short name T88
Test name
Test status
Simulation time 366953302 ps
CPU time 45.04 seconds
Started Aug 28 07:07:06 PM UTC 24
Finished Aug 28 07:07:52 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850301014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1850301014
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/2.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_unmapped_addr.1430357585
Short name T49
Test name
Test status
Simulation time 16419824 ps
CPU time 2.52 seconds
Started Aug 28 07:06:52 PM UTC 24
Finished Aug 28 07:06:56 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430357585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.1430357585
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/2.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device.3000832029
Short name T461
Test name
Test status
Simulation time 1125016949 ps
CPU time 20.52 seconds
Started Aug 28 07:12:57 PM UTC 24
Finished Aug 28 07:13:19 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000832029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.3000832029
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/20.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1165688078
Short name T456
Test name
Test status
Simulation time 115849609 ps
CPU time 8.59 seconds
Started Aug 28 07:13:01 PM UTC 24
Finished Aug 28 07:13:11 PM UTC 24
Peak memory 212332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165688078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.1165688078
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/20.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_error_random.3570308394
Short name T452
Test name
Test status
Simulation time 400032146 ps
CPU time 8.74 seconds
Started Aug 28 07:12:58 PM UTC 24
Finished Aug 28 07:13:08 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570308394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3570308394
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/20.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random.4114576156
Short name T444
Test name
Test status
Simulation time 11643273 ps
CPU time 2.06 seconds
Started Aug 28 07:12:53 PM UTC 24
Finished Aug 28 07:12:56 PM UTC 24
Peak memory 212316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114576156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.4114576156
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/20.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_large_delays.1908075446
Short name T107
Test name
Test status
Simulation time 31281108294 ps
CPU time 144.54 seconds
Started Aug 28 07:12:54 PM UTC 24
Finished Aug 28 07:15:21 PM UTC 24
Peak memory 211980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908075446 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1908075446
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/20.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_slow_rsp.3151486312
Short name T469
Test name
Test status
Simulation time 16402325542 ps
CPU time 36.49 seconds
Started Aug 28 07:12:57 PM UTC 24
Finished Aug 28 07:13:35 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151486312 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3151486312
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/20.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_zero_delays.2409220613
Short name T446
Test name
Test status
Simulation time 9338256 ps
CPU time 1.86 seconds
Started Aug 28 07:12:54 PM UTC 24
Finished Aug 28 07:12:57 PM UTC 24
Peak memory 210956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409220613 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2409220613
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/20.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_same_source.3919342570
Short name T450
Test name
Test status
Simulation time 51588387 ps
CPU time 3.34 seconds
Started Aug 28 07:12:58 PM UTC 24
Finished Aug 28 07:13:02 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919342570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3919342570
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/20.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke.3530969362
Short name T442
Test name
Test status
Simulation time 81358367 ps
CPU time 1.92 seconds
Started Aug 28 07:12:50 PM UTC 24
Finished Aug 28 07:12:53 PM UTC 24
Peak memory 211128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530969362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.3530969362
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/20.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_large_delays.609380652
Short name T458
Test name
Test status
Simulation time 2840715542 ps
CPU time 20.97 seconds
Started Aug 28 07:12:51 PM UTC 24
Finished Aug 28 07:13:14 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609380652 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.609380652
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/20.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.2817279172
Short name T451
Test name
Test status
Simulation time 1783674322 ps
CPU time 14.13 seconds
Started Aug 28 07:12:51 PM UTC 24
Finished Aug 28 07:13:07 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817279172 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2817279172
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/20.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.518216485
Short name T134
Test name
Test status
Simulation time 9856836 ps
CPU time 1.76 seconds
Started Aug 28 07:12:50 PM UTC 24
Finished Aug 28 07:12:53 PM UTC 24
Peak memory 211232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518216485 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.518216485
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/20.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all.2758505101
Short name T453
Test name
Test status
Simulation time 203801241 ps
CPU time 5.74 seconds
Started Aug 28 07:13:01 PM UTC 24
Finished Aug 28 07:13:08 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758505101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2758505101
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/20.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_error.1574286661
Short name T463
Test name
Test status
Simulation time 1119915156 ps
CPU time 15.99 seconds
Started Aug 28 07:13:04 PM UTC 24
Finished Aug 28 07:13:21 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574286661 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1574286661
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/20.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.680228873
Short name T561
Test name
Test status
Simulation time 10688328951 ps
CPU time 180.11 seconds
Started Aug 28 07:13:03 PM UTC 24
Finished Aug 28 07:16:07 PM UTC 24
Peak memory 218596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680228873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.680228873
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/20.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.3214623619
Short name T465
Test name
Test status
Simulation time 9738448 ps
CPU time 18.53 seconds
Started Aug 28 07:13:06 PM UTC 24
Finished Aug 28 07:13:25 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214623619 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.3214623619
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/20.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_unmapped_addr.1087714153
Short name T454
Test name
Test status
Simulation time 451177024 ps
CPU time 10.62 seconds
Started Aug 28 07:12:59 PM UTC 24
Finished Aug 28 07:13:11 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087714153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1087714153
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/20.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device.208558662
Short name T149
Test name
Test status
Simulation time 471815970 ps
CPU time 11.9 seconds
Started Aug 28 07:13:14 PM UTC 24
Finished Aug 28 07:13:27 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208558662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.208558662
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/21.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.81301473
Short name T300
Test name
Test status
Simulation time 12500369645 ps
CPU time 60.3 seconds
Started Aug 28 07:13:17 PM UTC 24
Finished Aug 28 07:14:20 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81301473 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.81301473
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/21.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.1502365786
Short name T466
Test name
Test status
Simulation time 346781086 ps
CPU time 4.68 seconds
Started Aug 28 07:13:20 PM UTC 24
Finished Aug 28 07:13:26 PM UTC 24
Peak memory 212236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502365786 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.1502365786
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/21.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_error_random.927106994
Short name T229
Test name
Test status
Simulation time 371853633 ps
CPU time 8 seconds
Started Aug 28 07:13:19 PM UTC 24
Finished Aug 28 07:13:28 PM UTC 24
Peak memory 212332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927106994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.927106994
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/21.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random.3285551300
Short name T462
Test name
Test status
Simulation time 61187447 ps
CPU time 6.04 seconds
Started Aug 28 07:13:12 PM UTC 24
Finished Aug 28 07:13:19 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285551300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.3285551300
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/21.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_large_delays.832337168
Short name T239
Test name
Test status
Simulation time 21574388854 ps
CPU time 145.89 seconds
Started Aug 28 07:13:13 PM UTC 24
Finished Aug 28 07:15:42 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832337168 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.832337168
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/21.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_slow_rsp.849110567
Short name T164
Test name
Test status
Simulation time 12877422619 ps
CPU time 82.46 seconds
Started Aug 28 07:13:14 PM UTC 24
Finished Aug 28 07:14:39 PM UTC 24
Peak memory 212448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849110567 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.849110567
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/21.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_zero_delays.1884304408
Short name T460
Test name
Test status
Simulation time 53784067 ps
CPU time 4.62 seconds
Started Aug 28 07:13:12 PM UTC 24
Finished Aug 28 07:13:18 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884304408 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.1884304408
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/21.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_same_source.2058391301
Short name T468
Test name
Test status
Simulation time 42639311 ps
CPU time 6.84 seconds
Started Aug 28 07:13:19 PM UTC 24
Finished Aug 28 07:13:27 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058391301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2058391301
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/21.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke.42225500
Short name T455
Test name
Test status
Simulation time 9631825 ps
CPU time 1.7 seconds
Started Aug 28 07:13:08 PM UTC 24
Finished Aug 28 07:13:11 PM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42225500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs
/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.42225500
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/21.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_large_delays.2392237844
Short name T467
Test name
Test status
Simulation time 13408478212 ps
CPU time 15.13 seconds
Started Aug 28 07:13:09 PM UTC 24
Finished Aug 28 07:13:26 PM UTC 24
Peak memory 212024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392237844 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2392237844
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/21.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.20847560
Short name T464
Test name
Test status
Simulation time 1853273147 ps
CPU time 10.6 seconds
Started Aug 28 07:13:12 PM UTC 24
Finished Aug 28 07:13:24 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20847560 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.20847560
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/21.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.1623723395
Short name T457
Test name
Test status
Simulation time 10213591 ps
CPU time 1.64 seconds
Started Aug 28 07:13:09 PM UTC 24
Finished Aug 28 07:13:12 PM UTC 24
Peak memory 210908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623723395 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.1623723395
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/21.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all.4063620063
Short name T508
Test name
Test status
Simulation time 4901456736 ps
CPU time 95.8 seconds
Started Aug 28 07:13:22 PM UTC 24
Finished Aug 28 07:15:00 PM UTC 24
Peak memory 216280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063620063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.4063620063
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/21.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_error.4054632556
Short name T479
Test name
Test status
Simulation time 1033750023 ps
CPU time 15.66 seconds
Started Aug 28 07:13:26 PM UTC 24
Finished Aug 28 07:13:43 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054632556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.4054632556
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/21.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.3086889154
Short name T247
Test name
Test status
Simulation time 244855571 ps
CPU time 25.97 seconds
Started Aug 28 07:13:25 PM UTC 24
Finished Aug 28 07:13:53 PM UTC 24
Peak memory 214376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086889154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.3086889154
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/21.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.1110511080
Short name T114
Test name
Test status
Simulation time 565103152 ps
CPU time 118.08 seconds
Started Aug 28 07:13:26 PM UTC 24
Finished Aug 28 07:15:27 PM UTC 24
Peak memory 216488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110511080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.1110511080
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/21.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_unmapped_addr.2980740630
Short name T234
Test name
Test status
Simulation time 677986027 ps
CPU time 9.15 seconds
Started Aug 28 07:13:20 PM UTC 24
Finished Aug 28 07:13:30 PM UTC 24
Peak memory 212056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980740630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.2980740630
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/21.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device.75687734
Short name T305
Test name
Test status
Simulation time 248190128 ps
CPU time 5.7 seconds
Started Aug 28 07:13:30 PM UTC 24
Finished Aug 28 07:13:37 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75687734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.75687734
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/22.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.1881792593
Short name T482
Test name
Test status
Simulation time 78890089 ps
CPU time 9.45 seconds
Started Aug 28 07:13:35 PM UTC 24
Finished Aug 28 07:13:46 PM UTC 24
Peak memory 212140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881792593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.1881792593
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/22.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_error_random.1177600722
Short name T476
Test name
Test status
Simulation time 552493336 ps
CPU time 10.97 seconds
Started Aug 28 07:13:31 PM UTC 24
Finished Aug 28 07:13:43 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177600722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1177600722
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/22.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random.2084555967
Short name T473
Test name
Test status
Simulation time 176722157 ps
CPU time 11.55 seconds
Started Aug 28 07:13:28 PM UTC 24
Finished Aug 28 07:13:41 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084555967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.2084555967
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/22.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_large_delays.207307418
Short name T167
Test name
Test status
Simulation time 37976302318 ps
CPU time 223.68 seconds
Started Aug 28 07:13:30 PM UTC 24
Finished Aug 28 07:17:17 PM UTC 24
Peak memory 212264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207307418 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.207307418
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/22.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_slow_rsp.3248564249
Short name T610
Test name
Test status
Simulation time 65816307128 ps
CPU time 207.61 seconds
Started Aug 28 07:13:30 PM UTC 24
Finished Aug 28 07:17:01 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248564249 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.3248564249
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/22.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_zero_delays.3120726797
Short name T237
Test name
Test status
Simulation time 82049696 ps
CPU time 4.59 seconds
Started Aug 28 07:13:28 PM UTC 24
Finished Aug 28 07:13:34 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120726797 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.3120726797
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/22.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_same_source.2373750269
Short name T472
Test name
Test status
Simulation time 72534127 ps
CPU time 7.91 seconds
Started Aug 28 07:13:31 PM UTC 24
Finished Aug 28 07:13:40 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373750269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.2373750269
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/22.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke.2516633202
Short name T232
Test name
Test status
Simulation time 19696094 ps
CPU time 1.73 seconds
Started Aug 28 07:13:26 PM UTC 24
Finished Aug 28 07:13:29 PM UTC 24
Peak memory 211128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516633202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2516633202
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/22.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_large_delays.4061520920
Short name T480
Test name
Test status
Simulation time 3385836783 ps
CPU time 15.88 seconds
Started Aug 28 07:13:27 PM UTC 24
Finished Aug 28 07:13:45 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061520920 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.4061520920
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/22.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.1484705753
Short name T471
Test name
Test status
Simulation time 2996775179 ps
CPU time 6.64 seconds
Started Aug 28 07:13:28 PM UTC 24
Finished Aug 28 07:13:36 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484705753 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.1484705753
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/22.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.569094606
Short name T235
Test name
Test status
Simulation time 10211465 ps
CPU time 1.81 seconds
Started Aug 28 07:13:27 PM UTC 24
Finished Aug 28 07:13:30 PM UTC 24
Peak memory 211232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569094606 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.569094606
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/22.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all.1972444682
Short name T272
Test name
Test status
Simulation time 1059730738 ps
CPU time 22.42 seconds
Started Aug 28 07:13:35 PM UTC 24
Finished Aug 28 07:13:59 PM UTC 24
Peak memory 214176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972444682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.1972444682
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/22.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_error.92618150
Short name T509
Test name
Test status
Simulation time 14306649681 ps
CPU time 81.66 seconds
Started Aug 28 07:13:37 PM UTC 24
Finished Aug 28 07:15:01 PM UTC 24
Peak memory 214444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92618150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.92618150
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/22.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.480271787
Short name T111
Test name
Test status
Simulation time 8700840811 ps
CPU time 106.96 seconds
Started Aug 28 07:13:36 PM UTC 24
Finished Aug 28 07:15:26 PM UTC 24
Peak memory 216288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480271787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.480271787
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/22.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.1581259692
Short name T495
Test name
Test status
Simulation time 250853612 ps
CPU time 24.9 seconds
Started Aug 28 07:13:37 PM UTC 24
Finished Aug 28 07:14:04 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581259692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.1581259692
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/22.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_unmapped_addr.3390072344
Short name T475
Test name
Test status
Simulation time 113231413 ps
CPU time 6.23 seconds
Started Aug 28 07:13:35 PM UTC 24
Finished Aug 28 07:13:42 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390072344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3390072344
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/22.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device.1590476063
Short name T483
Test name
Test status
Simulation time 95599632 ps
CPU time 5.32 seconds
Started Aug 28 07:13:44 PM UTC 24
Finished Aug 28 07:13:51 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590476063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.1590476063
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/23.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.2469707132
Short name T279
Test name
Test status
Simulation time 21025951448 ps
CPU time 216.9 seconds
Started Aug 28 07:13:44 PM UTC 24
Finished Aug 28 07:17:25 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469707132 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.2469707132
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/23.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.4029267418
Short name T497
Test name
Test status
Simulation time 565202396 ps
CPU time 16.25 seconds
Started Aug 28 07:13:52 PM UTC 24
Finished Aug 28 07:14:09 PM UTC 24
Peak memory 212140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029267418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.4029267418
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/23.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_error_random.819978896
Short name T487
Test name
Test status
Simulation time 271511191 ps
CPU time 5.64 seconds
Started Aug 28 07:13:46 PM UTC 24
Finished Aug 28 07:13:53 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819978896 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.819978896
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/23.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random.2438421858
Short name T488
Test name
Test status
Simulation time 578862024 ps
CPU time 9.74 seconds
Started Aug 28 07:13:43 PM UTC 24
Finished Aug 28 07:13:54 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438421858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.2438421858
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/23.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_large_delays.2675307783
Short name T512
Test name
Test status
Simulation time 24320165734 ps
CPU time 78.97 seconds
Started Aug 28 07:13:44 PM UTC 24
Finished Aug 28 07:15:05 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675307783 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2675307783
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/23.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_slow_rsp.83956808
Short name T577
Test name
Test status
Simulation time 23182593191 ps
CPU time 158.16 seconds
Started Aug 28 07:13:44 PM UTC 24
Finished Aug 28 07:16:25 PM UTC 24
Peak memory 212452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83956808 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.83956808
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/23.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_zero_delays.533728825
Short name T486
Test name
Test status
Simulation time 55486097 ps
CPU time 8.23 seconds
Started Aug 28 07:13:43 PM UTC 24
Finished Aug 28 07:13:52 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533728825 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.533728825
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/23.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_same_source.235403365
Short name T484
Test name
Test status
Simulation time 208347637 ps
CPU time 5.31 seconds
Started Aug 28 07:13:45 PM UTC 24
Finished Aug 28 07:13:52 PM UTC 24
Peak memory 212112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235403365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.235403365
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/23.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke.1935645327
Short name T477
Test name
Test status
Simulation time 10979483 ps
CPU time 1.68 seconds
Started Aug 28 07:13:41 PM UTC 24
Finished Aug 28 07:13:43 PM UTC 24
Peak memory 210956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935645327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.1935645327
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/23.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_large_delays.3794313962
Short name T485
Test name
Test status
Simulation time 1444280190 ps
CPU time 9.51 seconds
Started Aug 28 07:13:42 PM UTC 24
Finished Aug 28 07:13:52 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794313962 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.3794313962
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/23.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.2479586624
Short name T493
Test name
Test status
Simulation time 1419248152 ps
CPU time 15.18 seconds
Started Aug 28 07:13:43 PM UTC 24
Finished Aug 28 07:13:59 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479586624 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.2479586624
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/23.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.1793808241
Short name T478
Test name
Test status
Simulation time 12606813 ps
CPU time 1.67 seconds
Started Aug 28 07:13:41 PM UTC 24
Finished Aug 28 07:13:43 PM UTC 24
Peak memory 210844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793808241 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.1793808241
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/23.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all.1532824353
Short name T500
Test name
Test status
Simulation time 697069126 ps
CPU time 17.37 seconds
Started Aug 28 07:13:53 PM UTC 24
Finished Aug 28 07:14:11 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532824353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1532824353
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/23.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_error.1777230117
Short name T489
Test name
Test status
Simulation time 61863870 ps
CPU time 1.94 seconds
Started Aug 28 07:13:53 PM UTC 24
Finished Aug 28 07:13:56 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777230117 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1777230117
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/23.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.470572840
Short name T241
Test name
Test status
Simulation time 295008446 ps
CPU time 51.95 seconds
Started Aug 28 07:13:53 PM UTC 24
Finished Aug 28 07:14:46 PM UTC 24
Peak memory 218468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470572840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.470572840
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/23.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_unmapped_addr.1665536769
Short name T490
Test name
Test status
Simulation time 66557932 ps
CPU time 6.53 seconds
Started Aug 28 07:13:48 PM UTC 24
Finished Aug 28 07:13:56 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665536769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1665536769
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/23.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device.3238983445
Short name T116
Test name
Test status
Simulation time 3184642193 ps
CPU time 22.42 seconds
Started Aug 28 07:14:03 PM UTC 24
Finished Aug 28 07:14:26 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238983445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.3238983445
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/24.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.1309946696
Short name T179
Test name
Test status
Simulation time 15983764519 ps
CPU time 99.67 seconds
Started Aug 28 07:14:05 PM UTC 24
Finished Aug 28 07:15:47 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309946696 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.1309946696
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/24.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.815629896
Short name T505
Test name
Test status
Simulation time 1050482640 ps
CPU time 11.05 seconds
Started Aug 28 07:14:11 PM UTC 24
Finished Aug 28 07:14:23 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815629896 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.815629896
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/24.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_error_random.2453079254
Short name T503
Test name
Test status
Simulation time 374636785 ps
CPU time 8.8 seconds
Started Aug 28 07:14:10 PM UTC 24
Finished Aug 28 07:14:20 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453079254 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.2453079254
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/24.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random.3624549510
Short name T38
Test name
Test status
Simulation time 179533767 ps
CPU time 5.52 seconds
Started Aug 28 07:13:58 PM UTC 24
Finished Aug 28 07:14:05 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624549510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.3624549510
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/24.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_large_delays.2344922478
Short name T115
Test name
Test status
Simulation time 33371310740 ps
CPU time 86.86 seconds
Started Aug 28 07:13:59 PM UTC 24
Finished Aug 28 07:15:29 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344922478 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.2344922478
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/24.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_slow_rsp.3545931606
Short name T557
Test name
Test status
Simulation time 44201964363 ps
CPU time 120.62 seconds
Started Aug 28 07:14:01 PM UTC 24
Finished Aug 28 07:16:04 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545931606 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.3545931606
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/24.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_zero_delays.1816268830
Short name T494
Test name
Test status
Simulation time 21746230 ps
CPU time 2.36 seconds
Started Aug 28 07:13:58 PM UTC 24
Finished Aug 28 07:14:02 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816268830 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.1816268830
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/24.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_same_source.223735810
Short name T498
Test name
Test status
Simulation time 29880255 ps
CPU time 3.23 seconds
Started Aug 28 07:14:06 PM UTC 24
Finished Aug 28 07:14:10 PM UTC 24
Peak memory 212116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223735810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.223735810
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/24.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke.3588594666
Short name T491
Test name
Test status
Simulation time 48194553 ps
CPU time 1.95 seconds
Started Aug 28 07:13:54 PM UTC 24
Finished Aug 28 07:13:57 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588594666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3588594666
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/24.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_large_delays.753980619
Short name T481
Test name
Test status
Simulation time 12843859145 ps
CPU time 12.9 seconds
Started Aug 28 07:13:56 PM UTC 24
Finished Aug 28 07:14:10 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753980619 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.753980619
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/24.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.1435381190
Short name T496
Test name
Test status
Simulation time 1411279010 ps
CPU time 10.52 seconds
Started Aug 28 07:13:57 PM UTC 24
Finished Aug 28 07:14:09 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435381190 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.1435381190
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/24.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1196181765
Short name T492
Test name
Test status
Simulation time 13061860 ps
CPU time 1.76 seconds
Started Aug 28 07:13:55 PM UTC 24
Finished Aug 28 07:13:58 PM UTC 24
Peak memory 211180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196181765 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1196181765
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/24.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all.2006255798
Short name T510
Test name
Test status
Simulation time 415455967 ps
CPU time 50.37 seconds
Started Aug 28 07:14:11 PM UTC 24
Finished Aug 28 07:15:03 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006255798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2006255798
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/24.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_error.3203844915
Short name T501
Test name
Test status
Simulation time 70040673 ps
CPU time 3.33 seconds
Started Aug 28 07:14:13 PM UTC 24
Finished Aug 28 07:14:18 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203844915 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3203844915
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/24.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.77728899
Short name T523
Test name
Test status
Simulation time 885206360 ps
CPU time 75.22 seconds
Started Aug 28 07:14:12 PM UTC 24
Finished Aug 28 07:15:30 PM UTC 24
Peak memory 214368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77728899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.77728899
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/24.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.1730807773
Short name T10
Test name
Test status
Simulation time 1981655127 ps
CPU time 153.52 seconds
Started Aug 28 07:14:17 PM UTC 24
Finished Aug 28 07:16:54 PM UTC 24
Peak memory 218280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730807773 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.1730807773
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/24.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_unmapped_addr.1975110988
Short name T502
Test name
Test status
Simulation time 188895498 ps
CPU time 8.42 seconds
Started Aug 28 07:14:10 PM UTC 24
Finished Aug 28 07:14:19 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975110988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1975110988
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/24.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device.4285307884
Short name T165
Test name
Test status
Simulation time 611194532 ps
CPU time 14.88 seconds
Started Aug 28 07:14:27 PM UTC 24
Finished Aug 28 07:14:43 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285307884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.4285307884
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/25.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.1589964190
Short name T277
Test name
Test status
Simulation time 243861677428 ps
CPU time 311.52 seconds
Started Aug 28 07:14:27 PM UTC 24
Finished Aug 28 07:19:44 PM UTC 24
Peak memory 214436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589964190 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.1589964190
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/25.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.2065934509
Short name T166
Test name
Test status
Simulation time 185365558 ps
CPU time 6.48 seconds
Started Aug 28 07:14:37 PM UTC 24
Finished Aug 28 07:14:45 PM UTC 24
Peak memory 212332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065934509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.2065934509
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/25.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_error_random.3897472808
Short name T162
Test name
Test status
Simulation time 146458925 ps
CPU time 4.91 seconds
Started Aug 28 07:14:32 PM UTC 24
Finished Aug 28 07:14:38 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897472808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.3897472808
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/25.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random.2164622474
Short name T506
Test name
Test status
Simulation time 46565751 ps
CPU time 2.35 seconds
Started Aug 28 07:14:23 PM UTC 24
Finished Aug 28 07:14:26 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164622474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.2164622474
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/25.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_large_delays.1978969273
Short name T565
Test name
Test status
Simulation time 20814096599 ps
CPU time 104.81 seconds
Started Aug 28 07:14:24 PM UTC 24
Finished Aug 28 07:16:11 PM UTC 24
Peak memory 212264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978969273 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.1978969273
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/25.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_slow_rsp.3351419360
Short name T244
Test name
Test status
Simulation time 4598886190 ps
CPU time 25.47 seconds
Started Aug 28 07:14:24 PM UTC 24
Finished Aug 28 07:14:51 PM UTC 24
Peak memory 212344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351419360 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.3351419360
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/25.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_zero_delays.621438877
Short name T159
Test name
Test status
Simulation time 42621385 ps
CPU time 7.83 seconds
Started Aug 28 07:14:23 PM UTC 24
Finished Aug 28 07:14:32 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621438877 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.621438877
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/25.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_same_source.3325027482
Short name T161
Test name
Test status
Simulation time 30608095 ps
CPU time 3.47 seconds
Started Aug 28 07:14:31 PM UTC 24
Finished Aug 28 07:14:36 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325027482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3325027482
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/25.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke.3192034046
Short name T499
Test name
Test status
Simulation time 52279187 ps
CPU time 2.29 seconds
Started Aug 28 07:14:18 PM UTC 24
Finished Aug 28 07:14:22 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192034046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.3192034046
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/25.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_large_delays.1445969249
Short name T163
Test name
Test status
Simulation time 3082789663 ps
CPU time 16.44 seconds
Started Aug 28 07:14:21 PM UTC 24
Finished Aug 28 07:14:38 PM UTC 24
Peak memory 212152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445969249 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.1445969249
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/25.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.448736662
Short name T160
Test name
Test status
Simulation time 853400724 ps
CPU time 9.97 seconds
Started Aug 28 07:14:21 PM UTC 24
Finished Aug 28 07:14:32 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448736662 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.448736662
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/25.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.2517576374
Short name T504
Test name
Test status
Simulation time 7849601 ps
CPU time 1.53 seconds
Started Aug 28 07:14:21 PM UTC 24
Finished Aug 28 07:14:23 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517576374 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.2517576374
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/25.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all.675419479
Short name T295
Test name
Test status
Simulation time 3012300888 ps
CPU time 29.04 seconds
Started Aug 28 07:14:39 PM UTC 24
Finished Aug 28 07:15:10 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675419479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.675419479
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/25.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_error.1617999986
Short name T515
Test name
Test status
Simulation time 2119113648 ps
CPU time 25.16 seconds
Started Aug 28 07:14:40 PM UTC 24
Finished Aug 28 07:15:06 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617999986 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1617999986
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/25.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.1172873283
Short name T313
Test name
Test status
Simulation time 414339301 ps
CPU time 53.78 seconds
Started Aug 28 07:14:39 PM UTC 24
Finished Aug 28 07:15:35 PM UTC 24
Peak memory 216092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172873283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.1172873283
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/25.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.526942818
Short name T11
Test name
Test status
Simulation time 1311598284 ps
CPU time 164.41 seconds
Started Aug 28 07:14:41 PM UTC 24
Finished Aug 28 07:17:28 PM UTC 24
Peak memory 216236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526942818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.526942818
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/25.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_unmapped_addr.2488206767
Short name T240
Test name
Test status
Simulation time 600544361 ps
CPU time 12.39 seconds
Started Aug 28 07:14:32 PM UTC 24
Finished Aug 28 07:14:46 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488206767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.2488206767
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/25.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device.1695362878
Short name T108
Test name
Test status
Simulation time 9253567603 ps
CPU time 25.35 seconds
Started Aug 28 07:14:55 PM UTC 24
Finished Aug 28 07:15:22 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695362878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.1695362878
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/26.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.1485067639
Short name T274
Test name
Test status
Simulation time 15063420624 ps
CPU time 72.81 seconds
Started Aug 28 07:15:00 PM UTC 24
Finished Aug 28 07:16:15 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485067639 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.1485067639
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/26.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.572800152
Short name T521
Test name
Test status
Simulation time 76924932 ps
CPU time 8.71 seconds
Started Aug 28 07:15:05 PM UTC 24
Finished Aug 28 07:15:15 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572800152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.572800152
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/26.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_error_random.1264497866
Short name T516
Test name
Test status
Simulation time 27282033 ps
CPU time 2.82 seconds
Started Aug 28 07:15:03 PM UTC 24
Finished Aug 28 07:15:06 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264497866 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.1264497866
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/26.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random.818755237
Short name T245
Test name
Test status
Simulation time 36110767 ps
CPU time 3.08 seconds
Started Aug 28 07:14:47 PM UTC 24
Finished Aug 28 07:14:51 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818755237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.818755237
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/26.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_large_delays.1572073965
Short name T513
Test name
Test status
Simulation time 1873794942 ps
CPU time 12.94 seconds
Started Aug 28 07:14:51 PM UTC 24
Finished Aug 28 07:15:05 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572073965 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1572073965
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/26.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_slow_rsp.1813354117
Short name T586
Test name
Test status
Simulation time 18670038715 ps
CPU time 94.12 seconds
Started Aug 28 07:14:52 PM UTC 24
Finished Aug 28 07:16:29 PM UTC 24
Peak memory 212256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813354117 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1813354117
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/26.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_zero_delays.248128129
Short name T507
Test name
Test status
Simulation time 64184833 ps
CPU time 9.45 seconds
Started Aug 28 07:14:49 PM UTC 24
Finished Aug 28 07:15:00 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248128129 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.248128129
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/26.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_same_source.3981132670
Short name T517
Test name
Test status
Simulation time 277241790 ps
CPU time 4.97 seconds
Started Aug 28 07:15:02 PM UTC 24
Finished Aug 28 07:15:08 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981132670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.3981132670
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/26.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke.4148428101
Short name T242
Test name
Test status
Simulation time 12130000 ps
CPU time 1.69 seconds
Started Aug 28 07:14:44 PM UTC 24
Finished Aug 28 07:14:46 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148428101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.4148428101
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/26.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_large_delays.1428918241
Short name T511
Test name
Test status
Simulation time 2375341077 ps
CPU time 15.43 seconds
Started Aug 28 07:14:47 PM UTC 24
Finished Aug 28 07:15:04 PM UTC 24
Peak memory 212260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428918241 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1428918241
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/26.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.1150442416
Short name T246
Test name
Test status
Simulation time 836104675 ps
CPU time 6.98 seconds
Started Aug 28 07:14:47 PM UTC 24
Finished Aug 28 07:14:55 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150442416 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1150442416
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/26.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.3995918404
Short name T243
Test name
Test status
Simulation time 14689413 ps
CPU time 1.76 seconds
Started Aug 28 07:14:46 PM UTC 24
Finished Aug 28 07:14:49 PM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995918404 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.3995918404
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/26.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all.3177682597
Short name T112
Test name
Test status
Simulation time 222493299 ps
CPU time 19.1 seconds
Started Aug 28 07:15:06 PM UTC 24
Finished Aug 28 07:15:26 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177682597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3177682597
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/26.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1471981927
Short name T540
Test name
Test status
Simulation time 346657008 ps
CPU time 40.69 seconds
Started Aug 28 07:15:06 PM UTC 24
Finished Aug 28 07:15:48 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471981927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1471981927
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/26.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.2963610857
Short name T667
Test name
Test status
Simulation time 7850705715 ps
CPU time 176.3 seconds
Started Aug 28 07:15:06 PM UTC 24
Finished Aug 28 07:18:06 PM UTC 24
Peak memory 216488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963610857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.2963610857
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/26.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.2201581914
Short name T531
Test name
Test status
Simulation time 225602920 ps
CPU time 30.03 seconds
Started Aug 28 07:15:07 PM UTC 24
Finished Aug 28 07:15:39 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201581914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.2201581914
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/26.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_unmapped_addr.1904793054
Short name T520
Test name
Test status
Simulation time 326578929 ps
CPU time 6.46 seconds
Started Aug 28 07:15:04 PM UTC 24
Finished Aug 28 07:15:11 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904793054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.1904793054
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/26.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device.1357059284
Short name T527
Test name
Test status
Simulation time 6440956699 ps
CPU time 18.35 seconds
Started Aug 28 07:15:16 PM UTC 24
Finished Aug 28 07:15:36 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357059284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.1357059284
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/27.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.250026212
Short name T528
Test name
Test status
Simulation time 421787114 ps
CPU time 9.47 seconds
Started Aug 28 07:15:25 PM UTC 24
Finished Aug 28 07:15:36 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250026212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.250026212
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/27.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_error_random.4021244295
Short name T535
Test name
Test status
Simulation time 1241119268 ps
CPU time 21.17 seconds
Started Aug 28 07:15:22 PM UTC 24
Finished Aug 28 07:15:45 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021244295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.4021244295
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/27.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random.3090800349
Short name T524
Test name
Test status
Simulation time 821764230 ps
CPU time 16.86 seconds
Started Aug 28 07:15:12 PM UTC 24
Finished Aug 28 07:15:30 PM UTC 24
Peak memory 212380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090800349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.3090800349
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/27.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_large_delays.2174155099
Short name T701
Test name
Test status
Simulation time 34876203053 ps
CPU time 206.91 seconds
Started Aug 28 07:15:13 PM UTC 24
Finished Aug 28 07:18:43 PM UTC 24
Peak memory 212260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174155099 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2174155099
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/27.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_slow_rsp.1170430652
Short name T807
Test name
Test status
Simulation time 20267845871 ps
CPU time 303.23 seconds
Started Aug 28 07:15:14 PM UTC 24
Finished Aug 28 07:20:22 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170430652 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.1170430652
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/27.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_zero_delays.1170289872
Short name T522
Test name
Test status
Simulation time 15821523 ps
CPU time 2.45 seconds
Started Aug 28 07:15:12 PM UTC 24
Finished Aug 28 07:15:15 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170289872 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.1170289872
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/27.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_same_source.2330297189
Short name T110
Test name
Test status
Simulation time 75526080 ps
CPU time 5 seconds
Started Aug 28 07:15:19 PM UTC 24
Finished Aug 28 07:15:25 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330297189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.2330297189
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/27.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke.3741315527
Short name T518
Test name
Test status
Simulation time 14711412 ps
CPU time 1.89 seconds
Started Aug 28 07:15:07 PM UTC 24
Finished Aug 28 07:15:10 PM UTC 24
Peak memory 211232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741315527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3741315527
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/27.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_large_delays.974847820
Short name T113
Test name
Test status
Simulation time 5725565343 ps
CPU time 14.29 seconds
Started Aug 28 07:15:12 PM UTC 24
Finished Aug 28 07:15:27 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974847820 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.974847820
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/27.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.385086046
Short name T109
Test name
Test status
Simulation time 5217840417 ps
CPU time 11.41 seconds
Started Aug 28 07:15:12 PM UTC 24
Finished Aug 28 07:15:24 PM UTC 24
Peak memory 212452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385086046 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.385086046
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/27.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.1406550221
Short name T519
Test name
Test status
Simulation time 12730663 ps
CPU time 1.46 seconds
Started Aug 28 07:15:08 PM UTC 24
Finished Aug 28 07:15:11 PM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406550221 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.1406550221
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/27.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all.680378021
Short name T567
Test name
Test status
Simulation time 312530833 ps
CPU time 45.55 seconds
Started Aug 28 07:15:26 PM UTC 24
Finished Aug 28 07:16:13 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680378021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.680378021
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/27.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_error.2714979566
Short name T585
Test name
Test status
Simulation time 4913531646 ps
CPU time 59.2 seconds
Started Aug 28 07:15:28 PM UTC 24
Finished Aug 28 07:16:28 PM UTC 24
Peak memory 212264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714979566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2714979566
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/27.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.2568837837
Short name T542
Test name
Test status
Simulation time 152514609 ps
CPU time 21.5 seconds
Started Aug 28 07:15:28 PM UTC 24
Finished Aug 28 07:15:50 PM UTC 24
Peak memory 214440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568837837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.2568837837
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/27.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_unmapped_addr.2768657413
Short name T533
Test name
Test status
Simulation time 4324894605 ps
CPU time 16.52 seconds
Started Aug 28 07:15:23 PM UTC 24
Finished Aug 28 07:15:41 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768657413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2768657413
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/27.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device.1244098648
Short name T543
Test name
Test status
Simulation time 188586690 ps
CPU time 14.35 seconds
Started Aug 28 07:15:37 PM UTC 24
Finished Aug 28 07:15:52 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244098648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.1244098648
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/28.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.1014135223
Short name T121
Test name
Test status
Simulation time 22599142617 ps
CPU time 206.02 seconds
Started Aug 28 07:15:37 PM UTC 24
Finished Aug 28 07:19:06 PM UTC 24
Peak memory 214308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014135223 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.1014135223
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/28.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.1515469371
Short name T545
Test name
Test status
Simulation time 534835775 ps
CPU time 11.6 seconds
Started Aug 28 07:15:40 PM UTC 24
Finished Aug 28 07:15:53 PM UTC 24
Peak memory 212052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515469371 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.1515469371
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/28.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_error_random.3399494147
Short name T538
Test name
Test status
Simulation time 373462014 ps
CPU time 7.63 seconds
Started Aug 28 07:15:39 PM UTC 24
Finished Aug 28 07:15:47 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399494147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3399494147
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/28.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random.2999883199
Short name T529
Test name
Test status
Simulation time 25658198 ps
CPU time 2.62 seconds
Started Aug 28 07:15:32 PM UTC 24
Finished Aug 28 07:15:36 PM UTC 24
Peak memory 212380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999883199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.2999883199
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/28.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_large_delays.3869672514
Short name T581
Test name
Test status
Simulation time 9059321001 ps
CPU time 52.12 seconds
Started Aug 28 07:15:33 PM UTC 24
Finished Aug 28 07:16:27 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869672514 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.3869672514
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/28.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_slow_rsp.896777613
Short name T584
Test name
Test status
Simulation time 25869093960 ps
CPU time 50.63 seconds
Started Aug 28 07:15:35 PM UTC 24
Finished Aug 28 07:16:28 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896777613 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.896777613
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/28.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_zero_delays.3434719178
Short name T530
Test name
Test status
Simulation time 52451679 ps
CPU time 4.31 seconds
Started Aug 28 07:15:33 PM UTC 24
Finished Aug 28 07:15:39 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434719178 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.3434719178
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/28.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_same_source.64856014
Short name T534
Test name
Test status
Simulation time 1463877942 ps
CPU time 4.62 seconds
Started Aug 28 07:15:37 PM UTC 24
Finished Aug 28 07:15:42 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64856014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.64856014
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/28.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke.146901303
Short name T525
Test name
Test status
Simulation time 10126044 ps
CPU time 1.68 seconds
Started Aug 28 07:15:29 PM UTC 24
Finished Aug 28 07:15:32 PM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146901303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.146901303
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/28.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_large_delays.1785001611
Short name T539
Test name
Test status
Simulation time 2465242610 ps
CPU time 16.03 seconds
Started Aug 28 07:15:31 PM UTC 24
Finished Aug 28 07:15:48 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785001611 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.1785001611
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/28.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.2295374039
Short name T532
Test name
Test status
Simulation time 744844469 ps
CPU time 8.38 seconds
Started Aug 28 07:15:31 PM UTC 24
Finished Aug 28 07:15:41 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295374039 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.2295374039
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/28.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.239363203
Short name T526
Test name
Test status
Simulation time 8226498 ps
CPU time 1.56 seconds
Started Aug 28 07:15:30 PM UTC 24
Finished Aug 28 07:15:33 PM UTC 24
Peak memory 211128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239363203 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.239363203
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/28.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all.542784592
Short name T558
Test name
Test status
Simulation time 376872864 ps
CPU time 23.4 seconds
Started Aug 28 07:15:40 PM UTC 24
Finished Aug 28 07:16:05 PM UTC 24
Peak memory 212036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542784592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.542784592
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/28.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_error.3084114016
Short name T668
Test name
Test status
Simulation time 19146182237 ps
CPU time 143.38 seconds
Started Aug 28 07:15:40 PM UTC 24
Finished Aug 28 07:18:07 PM UTC 24
Peak memory 214440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084114016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.3084114016
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/28.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.2932785600
Short name T547
Test name
Test status
Simulation time 87449753 ps
CPU time 13.6 seconds
Started Aug 28 07:15:40 PM UTC 24
Finished Aug 28 07:15:55 PM UTC 24
Peak memory 214376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932785600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.2932785600
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/28.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.2336693226
Short name T323
Test name
Test status
Simulation time 414507682 ps
CPU time 40.88 seconds
Started Aug 28 07:15:41 PM UTC 24
Finished Aug 28 07:16:24 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336693226 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.2336693226
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/28.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_unmapped_addr.3801393025
Short name T541
Test name
Test status
Simulation time 117946677 ps
CPU time 9.73 seconds
Started Aug 28 07:15:39 PM UTC 24
Finished Aug 28 07:15:50 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801393025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3801393025
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/28.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device.1879470853
Short name T142
Test name
Test status
Simulation time 302709646 ps
CPU time 6.88 seconds
Started Aug 28 07:15:49 PM UTC 24
Finished Aug 28 07:15:57 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879470853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.1879470853
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/29.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.160005132
Short name T285
Test name
Test status
Simulation time 14865279538 ps
CPU time 67.43 seconds
Started Aug 28 07:15:49 PM UTC 24
Finished Aug 28 07:16:58 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160005132 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.160005132
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/29.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.536524447
Short name T548
Test name
Test status
Simulation time 254904926 ps
CPU time 3.99 seconds
Started Aug 28 07:15:51 PM UTC 24
Finished Aug 28 07:15:56 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536524447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.536524447
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/29.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_error_random.2448305937
Short name T546
Test name
Test status
Simulation time 25220240 ps
CPU time 3.02 seconds
Started Aug 28 07:15:50 PM UTC 24
Finished Aug 28 07:15:54 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448305937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.2448305937
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/29.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random.2101710862
Short name T544
Test name
Test status
Simulation time 68588014 ps
CPU time 5.54 seconds
Started Aug 28 07:15:46 PM UTC 24
Finished Aug 28 07:15:52 PM UTC 24
Peak memory 211928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101710862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.2101710862
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/29.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_large_delays.1717774497
Short name T725
Test name
Test status
Simulation time 115592201918 ps
CPU time 194.42 seconds
Started Aug 28 07:15:48 PM UTC 24
Finished Aug 28 07:19:06 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717774497 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.1717774497
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/29.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_slow_rsp.331360371
Short name T611
Test name
Test status
Simulation time 38263611372 ps
CPU time 72.59 seconds
Started Aug 28 07:15:48 PM UTC 24
Finished Aug 28 07:17:02 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331360371 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.331360371
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/29.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_zero_delays.236384210
Short name T552
Test name
Test status
Simulation time 65961097 ps
CPU time 9.44 seconds
Started Aug 28 07:15:47 PM UTC 24
Finished Aug 28 07:15:57 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236384210 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.236384210
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/29.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_same_source.2317809859
Short name T551
Test name
Test status
Simulation time 48269741 ps
CPU time 6.03 seconds
Started Aug 28 07:15:50 PM UTC 24
Finished Aug 28 07:15:57 PM UTC 24
Peak memory 212452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317809859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.2317809859
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/29.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke.2247991594
Short name T537
Test name
Test status
Simulation time 51754432 ps
CPU time 2.2 seconds
Started Aug 28 07:15:42 PM UTC 24
Finished Aug 28 07:15:46 PM UTC 24
Peak memory 212148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247991594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2247991594
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/29.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_large_delays.3404991904
Short name T553
Test name
Test status
Simulation time 4049255486 ps
CPU time 14.22 seconds
Started Aug 28 07:15:43 PM UTC 24
Finished Aug 28 07:15:59 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404991904 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3404991904
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/29.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.3931610981
Short name T550
Test name
Test status
Simulation time 2795318160 ps
CPU time 9.87 seconds
Started Aug 28 07:15:46 PM UTC 24
Finished Aug 28 07:15:57 PM UTC 24
Peak memory 212068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931610981 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.3931610981
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/29.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.1058439648
Short name T536
Test name
Test status
Simulation time 9443535 ps
CPU time 1.7 seconds
Started Aug 28 07:15:42 PM UTC 24
Finished Aug 28 07:15:45 PM UTC 24
Peak memory 211084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058439648 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.1058439648
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/29.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all.1353126338
Short name T556
Test name
Test status
Simulation time 597943492 ps
CPU time 9.47 seconds
Started Aug 28 07:15:53 PM UTC 24
Finished Aug 28 07:16:03 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353126338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.1353126338
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/29.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_error.3397616433
Short name T595
Test name
Test status
Simulation time 298693833 ps
CPU time 38.7 seconds
Started Aug 28 07:15:54 PM UTC 24
Finished Aug 28 07:16:34 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397616433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3397616433
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/29.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.2477481368
Short name T315
Test name
Test status
Simulation time 2335689281 ps
CPU time 60.38 seconds
Started Aug 28 07:15:54 PM UTC 24
Finished Aug 28 07:16:56 PM UTC 24
Peak memory 216296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477481368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.2477481368
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/29.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.3019330813
Short name T755
Test name
Test status
Simulation time 1202636289 ps
CPU time 211.56 seconds
Started Aug 28 07:15:55 PM UTC 24
Finished Aug 28 07:19:30 PM UTC 24
Peak memory 232336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019330813 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.3019330813
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/29.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_unmapped_addr.4248026757
Short name T549
Test name
Test status
Simulation time 575573119 ps
CPU time 4.08 seconds
Started Aug 28 07:15:51 PM UTC 24
Finished Aug 28 07:15:57 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248026757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.4248026757
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/29.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device.1265883759
Short name T60
Test name
Test status
Simulation time 5603302143 ps
CPU time 23.81 seconds
Started Aug 28 07:07:18 PM UTC 24
Finished Aug 28 07:07:44 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265883759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.1265883759
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/3.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.2391391152
Short name T193
Test name
Test status
Simulation time 4814636899 ps
CPU time 59.84 seconds
Started Aug 28 07:07:19 PM UTC 24
Finished Aug 28 07:08:21 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391391152 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.2391391152
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/3.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.4205111714
Short name T71
Test name
Test status
Simulation time 98719602 ps
CPU time 5.51 seconds
Started Aug 28 07:07:27 PM UTC 24
Finished Aug 28 07:07:34 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205111714 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.4205111714
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/3.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_error_random.371620960
Short name T70
Test name
Test status
Simulation time 353903753 ps
CPU time 5.27 seconds
Started Aug 28 07:07:26 PM UTC 24
Finished Aug 28 07:07:33 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371620960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.371620960
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/3.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random.3990785497
Short name T34
Test name
Test status
Simulation time 1532039843 ps
CPU time 17.34 seconds
Started Aug 28 07:07:11 PM UTC 24
Finished Aug 28 07:07:30 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990785497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.3990785497
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/3.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_large_delays.3011659129
Short name T326
Test name
Test status
Simulation time 14197876475 ps
CPU time 55.26 seconds
Started Aug 28 07:07:18 PM UTC 24
Finished Aug 28 07:08:15 PM UTC 24
Peak memory 212004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011659129 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3011659129
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/3.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_slow_rsp.2553556052
Short name T59
Test name
Test status
Simulation time 2977280518 ps
CPU time 17.98 seconds
Started Aug 28 07:07:18 PM UTC 24
Finished Aug 28 07:07:38 PM UTC 24
Peak memory 211824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553556052 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.2553556052
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/3.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_zero_delays.3218271381
Short name T51
Test name
Test status
Simulation time 73645809 ps
CPU time 4.04 seconds
Started Aug 28 07:07:12 PM UTC 24
Finished Aug 28 07:07:17 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218271381 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.3218271381
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/3.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_same_source.3218483678
Short name T157
Test name
Test status
Simulation time 33982155 ps
CPU time 4.08 seconds
Started Aug 28 07:07:20 PM UTC 24
Finished Aug 28 07:07:25 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218483678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.3218483678
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/3.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke.2656065805
Short name T57
Test name
Test status
Simulation time 262158700 ps
CPU time 2.82 seconds
Started Aug 28 07:07:07 PM UTC 24
Finished Aug 28 07:07:11 PM UTC 24
Peak memory 212076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656065805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2656065805
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/3.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_large_delays.2605163078
Short name T156
Test name
Test status
Simulation time 4563014926 ps
CPU time 15.36 seconds
Started Aug 28 07:07:08 PM UTC 24
Finished Aug 28 07:07:25 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605163078 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.2605163078
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/3.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1007618818
Short name T58
Test name
Test status
Simulation time 6034981432 ps
CPU time 13.68 seconds
Started Aug 28 07:07:11 PM UTC 24
Finished Aug 28 07:07:26 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007618818 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1007618818
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/3.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.4034825128
Short name T50
Test name
Test status
Simulation time 17500232 ps
CPU time 1.91 seconds
Started Aug 28 07:07:07 PM UTC 24
Finished Aug 28 07:07:10 PM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034825128 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.4034825128
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/3.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all.1364675198
Short name T324
Test name
Test status
Simulation time 1022634706 ps
CPU time 44.19 seconds
Started Aug 28 07:07:29 PM UTC 24
Finished Aug 28 07:08:15 PM UTC 24
Peak memory 214176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364675198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.1364675198
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/3.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_error.205683520
Short name T291
Test name
Test status
Simulation time 5535686407 ps
CPU time 103.99 seconds
Started Aug 28 07:07:34 PM UTC 24
Finished Aug 28 07:09:21 PM UTC 24
Peak memory 214316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205683520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.205683520
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/3.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.194097886
Short name T7
Test name
Test status
Simulation time 11775496501 ps
CPU time 187.37 seconds
Started Aug 28 07:07:31 PM UTC 24
Finished Aug 28 07:10:43 PM UTC 24
Peak memory 216296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194097886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.194097886
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/3.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1213978846
Short name T261
Test name
Test status
Simulation time 4058564262 ps
CPU time 88.97 seconds
Started Aug 28 07:07:35 PM UTC 24
Finished Aug 28 07:09:06 PM UTC 24
Peak memory 214136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213978846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.1213978846
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/3.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_unmapped_addr.534967250
Short name T52
Test name
Test status
Simulation time 50869464 ps
CPU time 6.21 seconds
Started Aug 28 07:07:26 PM UTC 24
Finished Aug 28 07:07:34 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534967250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.534967250
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/3.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device.3261019297
Short name T564
Test name
Test status
Simulation time 849278989 ps
CPU time 9.71 seconds
Started Aug 28 07:15:59 PM UTC 24
Finished Aug 28 07:16:11 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261019297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.3261019297
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/30.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.3048413619
Short name T637
Test name
Test status
Simulation time 11805873091 ps
CPU time 95.4 seconds
Started Aug 28 07:16:01 PM UTC 24
Finished Aug 28 07:17:39 PM UTC 24
Peak memory 212260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048413619 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.3048413619
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/30.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.2240184592
Short name T563
Test name
Test status
Simulation time 60163871 ps
CPU time 2.45 seconds
Started Aug 28 07:16:07 PM UTC 24
Finished Aug 28 07:16:10 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240184592 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.2240184592
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/30.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_error_random.879943930
Short name T570
Test name
Test status
Simulation time 358183617 ps
CPU time 8.61 seconds
Started Aug 28 07:16:05 PM UTC 24
Finished Aug 28 07:16:15 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879943930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.879943930
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/30.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random.1352596519
Short name T560
Test name
Test status
Simulation time 45543907 ps
CPU time 6.23 seconds
Started Aug 28 07:15:58 PM UTC 24
Finished Aug 28 07:16:06 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352596519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.1352596519
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/30.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.722657499
Short name T777
Test name
Test status
Simulation time 273552367533 ps
CPU time 226.96 seconds
Started Aug 28 07:15:58 PM UTC 24
Finished Aug 28 07:19:49 PM UTC 24
Peak memory 212204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722657499 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.722657499
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/30.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1087886688
Short name T642
Test name
Test status
Simulation time 13824372600 ps
CPU time 100.59 seconds
Started Aug 28 07:15:59 PM UTC 24
Finished Aug 28 07:17:43 PM UTC 24
Peak memory 212380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087886688 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1087886688
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/30.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_zero_delays.1108797288
Short name T559
Test name
Test status
Simulation time 108776953 ps
CPU time 6.15 seconds
Started Aug 28 07:15:58 PM UTC 24
Finished Aug 28 07:16:05 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108797288 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.1108797288
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/30.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_same_source.1707622939
Short name T566
Test name
Test status
Simulation time 50184254 ps
CPU time 6.06 seconds
Started Aug 28 07:16:05 PM UTC 24
Finished Aug 28 07:16:12 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707622939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.1707622939
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/30.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke.1927631967
Short name T554
Test name
Test status
Simulation time 10664908 ps
CPU time 1.68 seconds
Started Aug 28 07:15:56 PM UTC 24
Finished Aug 28 07:15:59 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927631967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1927631967
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/30.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_large_delays.3579760263
Short name T573
Test name
Test status
Simulation time 3810769573 ps
CPU time 21.63 seconds
Started Aug 28 07:15:57 PM UTC 24
Finished Aug 28 07:16:20 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579760263 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.3579760263
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/30.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2122192975
Short name T562
Test name
Test status
Simulation time 927669337 ps
CPU time 11.07 seconds
Started Aug 28 07:15:57 PM UTC 24
Finished Aug 28 07:16:09 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122192975 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2122192975
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/30.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.1511774677
Short name T555
Test name
Test status
Simulation time 10886348 ps
CPU time 1.77 seconds
Started Aug 28 07:15:57 PM UTC 24
Finished Aug 28 07:16:00 PM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511774677 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.1511774677
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/30.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all.2096931655
Short name T695
Test name
Test status
Simulation time 13714302938 ps
CPU time 144.35 seconds
Started Aug 28 07:16:07 PM UTC 24
Finished Aug 28 07:18:34 PM UTC 24
Peak memory 214432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096931655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2096931655
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/30.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_error.3188197381
Short name T593
Test name
Test status
Simulation time 1055663797 ps
CPU time 23.84 seconds
Started Aug 28 07:16:08 PM UTC 24
Finished Aug 28 07:16:33 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188197381 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3188197381
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/30.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.3794860909
Short name T617
Test name
Test status
Simulation time 359487974 ps
CPU time 57.45 seconds
Started Aug 28 07:16:07 PM UTC 24
Finished Aug 28 07:17:06 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794860909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.3794860909
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/30.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.1579814316
Short name T730
Test name
Test status
Simulation time 13020449163 ps
CPU time 178.22 seconds
Started Aug 28 07:16:10 PM UTC 24
Finished Aug 28 07:19:12 PM UTC 24
Peak memory 218344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579814316 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.1579814316
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/30.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_unmapped_addr.1412880178
Short name T572
Test name
Test status
Simulation time 2069372306 ps
CPU time 11.37 seconds
Started Aug 28 07:16:06 PM UTC 24
Finished Aug 28 07:16:18 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412880178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1412880178
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/30.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device.1487814913
Short name T580
Test name
Test status
Simulation time 61698705 ps
CPU time 8.98 seconds
Started Aug 28 07:16:16 PM UTC 24
Finished Aug 28 07:16:26 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487814913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.1487814913
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/31.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2706535864
Short name T308
Test name
Test status
Simulation time 107850843691 ps
CPU time 317.61 seconds
Started Aug 28 07:16:17 PM UTC 24
Finished Aug 28 07:21:40 PM UTC 24
Peak memory 214240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706535864 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.2706535864
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/31.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.378105223
Short name T589
Test name
Test status
Simulation time 488931645 ps
CPU time 9.68 seconds
Started Aug 28 07:16:21 PM UTC 24
Finished Aug 28 07:16:32 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378105223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.378105223
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/31.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_error_random.2737241898
Short name T591
Test name
Test status
Simulation time 65247031 ps
CPU time 10.36 seconds
Started Aug 28 07:16:21 PM UTC 24
Finished Aug 28 07:16:33 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737241898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.2737241898
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/31.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random.977131487
Short name T592
Test name
Test status
Simulation time 627453792 ps
CPU time 17.16 seconds
Started Aug 28 07:16:15 PM UTC 24
Finished Aug 28 07:16:33 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977131487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.977131487
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/31.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_large_delays.467949093
Short name T615
Test name
Test status
Simulation time 8434872979 ps
CPU time 47.9 seconds
Started Aug 28 07:16:16 PM UTC 24
Finished Aug 28 07:17:05 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467949093 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.467949093
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/31.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_slow_rsp.908656695
Short name T661
Test name
Test status
Simulation time 18197616205 ps
CPU time 101.04 seconds
Started Aug 28 07:16:16 PM UTC 24
Finished Aug 28 07:17:59 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908656695 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.908656695
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/31.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_zero_delays.739265809
Short name T574
Test name
Test status
Simulation time 39305791 ps
CPU time 4.39 seconds
Started Aug 28 07:16:15 PM UTC 24
Finished Aug 28 07:16:20 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739265809 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.739265809
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/31.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_same_source.3159607233
Short name T579
Test name
Test status
Simulation time 35153127 ps
CPU time 5.72 seconds
Started Aug 28 07:16:19 PM UTC 24
Finished Aug 28 07:16:26 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159607233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.3159607233
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/31.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke.3114559478
Short name T569
Test name
Test status
Simulation time 20573649 ps
CPU time 1.63 seconds
Started Aug 28 07:16:11 PM UTC 24
Finished Aug 28 07:16:14 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114559478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.3114559478
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/31.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_large_delays.240007685
Short name T578
Test name
Test status
Simulation time 1501556564 ps
CPU time 11.65 seconds
Started Aug 28 07:16:12 PM UTC 24
Finished Aug 28 07:16:25 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240007685 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.240007685
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/31.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.214981891
Short name T576
Test name
Test status
Simulation time 867352243 ps
CPU time 9.85 seconds
Started Aug 28 07:16:12 PM UTC 24
Finished Aug 28 07:16:23 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214981891 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.214981891
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/31.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.3409529053
Short name T568
Test name
Test status
Simulation time 8849440 ps
CPU time 1.53 seconds
Started Aug 28 07:16:11 PM UTC 24
Finished Aug 28 07:16:14 PM UTC 24
Peak memory 211180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409529053 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.3409529053
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/31.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all.3483850847
Short name T606
Test name
Test status
Simulation time 1603289808 ps
CPU time 28.38 seconds
Started Aug 28 07:16:24 PM UTC 24
Finished Aug 28 07:16:54 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483850847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3483850847
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/31.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_error.3173345128
Short name T621
Test name
Test status
Simulation time 10485130719 ps
CPU time 46.81 seconds
Started Aug 28 07:16:25 PM UTC 24
Finished Aug 28 07:17:14 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173345128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3173345128
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/31.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.3594952177
Short name T645
Test name
Test status
Simulation time 321487510 ps
CPU time 78.72 seconds
Started Aug 28 07:16:24 PM UTC 24
Finished Aug 28 07:17:45 PM UTC 24
Peak memory 216232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594952177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.3594952177
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/31.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.3098634709
Short name T619
Test name
Test status
Simulation time 1480498076 ps
CPU time 39.52 seconds
Started Aug 28 07:16:27 PM UTC 24
Finished Aug 28 07:17:08 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098634709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.3098634709
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/31.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_unmapped_addr.3767251466
Short name T583
Test name
Test status
Simulation time 250313223 ps
CPU time 5.51 seconds
Started Aug 28 07:16:21 PM UTC 24
Finished Aug 28 07:16:28 PM UTC 24
Peak memory 212452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767251466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.3767251466
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/31.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device.1764702589
Short name T596
Test name
Test status
Simulation time 31854103 ps
CPU time 7.14 seconds
Started Aug 28 07:16:30 PM UTC 24
Finished Aug 28 07:16:38 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764702589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.1764702589
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/32.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.3446026329
Short name T267
Test name
Test status
Simulation time 6406752085 ps
CPU time 43.5 seconds
Started Aug 28 07:16:31 PM UTC 24
Finished Aug 28 07:17:16 PM UTC 24
Peak memory 212452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446026329 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.3446026329
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/32.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.1715581319
Short name T604
Test name
Test status
Simulation time 1078721737 ps
CPU time 15.86 seconds
Started Aug 28 07:16:35 PM UTC 24
Finished Aug 28 07:16:52 PM UTC 24
Peak memory 212204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715581319 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.1715581319
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/32.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_error_random.4253849359
Short name T598
Test name
Test status
Simulation time 110769951 ps
CPU time 3.91 seconds
Started Aug 28 07:16:33 PM UTC 24
Finished Aug 28 07:16:39 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253849359 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.4253849359
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/32.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random.998903429
Short name T594
Test name
Test status
Simulation time 49726728 ps
CPU time 4.03 seconds
Started Aug 28 07:16:29 PM UTC 24
Finished Aug 28 07:16:34 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998903429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.998903429
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/32.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.3765679662
Short name T254
Test name
Test status
Simulation time 6965076460 ps
CPU time 51.94 seconds
Started Aug 28 07:16:29 PM UTC 24
Finished Aug 28 07:17:23 PM UTC 24
Peak memory 212452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765679662 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3765679662
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/32.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.1813582992
Short name T733
Test name
Test status
Simulation time 59391771007 ps
CPU time 160.25 seconds
Started Aug 28 07:16:30 PM UTC 24
Finished Aug 28 07:19:14 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813582992 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.1813582992
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/32.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_zero_delays.3652593033
Short name T590
Test name
Test status
Simulation time 81677709 ps
CPU time 2.55 seconds
Started Aug 28 07:16:29 PM UTC 24
Finished Aug 28 07:16:33 PM UTC 24
Peak memory 211840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652593033 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.3652593033
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/32.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_same_source.4247086886
Short name T597
Test name
Test status
Simulation time 766273675 ps
CPU time 4.95 seconds
Started Aug 28 07:16:32 PM UTC 24
Finished Aug 28 07:16:38 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247086886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.4247086886
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/32.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke.3168196203
Short name T587
Test name
Test status
Simulation time 12397655 ps
CPU time 1.61 seconds
Started Aug 28 07:16:27 PM UTC 24
Finished Aug 28 07:16:29 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168196203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3168196203
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/32.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_large_delays.1855714568
Short name T599
Test name
Test status
Simulation time 4705907797 ps
CPU time 11.23 seconds
Started Aug 28 07:16:28 PM UTC 24
Finished Aug 28 07:16:40 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855714568 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.1855714568
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/32.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.2179777661
Short name T603
Test name
Test status
Simulation time 3161961099 ps
CPU time 21.37 seconds
Started Aug 28 07:16:29 PM UTC 24
Finished Aug 28 07:16:52 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179777661 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2179777661
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/32.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.4176914
Short name T588
Test name
Test status
Simulation time 11967321 ps
CPU time 1.84 seconds
Started Aug 28 07:16:28 PM UTC 24
Finished Aug 28 07:16:31 PM UTC 24
Peak memory 210532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176914 -assert nopostproc +UVM_TESTNAME=xbar_b
ase_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.4176914
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/32.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all.1483522896
Short name T638
Test name
Test status
Simulation time 1744844026 ps
CPU time 63.06 seconds
Started Aug 28 07:16:35 PM UTC 24
Finished Aug 28 07:17:40 PM UTC 24
Peak memory 214368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483522896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1483522896
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/32.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1425166951
Short name T607
Test name
Test status
Simulation time 202978938 ps
CPU time 18.27 seconds
Started Aug 28 07:16:35 PM UTC 24
Finished Aug 28 07:16:54 PM UTC 24
Peak memory 214248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425166951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1425166951
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/32.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.221448305
Short name T686
Test name
Test status
Simulation time 711022465 ps
CPU time 108.7 seconds
Started Aug 28 07:16:35 PM UTC 24
Finished Aug 28 07:18:26 PM UTC 24
Peak memory 216224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221448305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.221448305
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/32.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_unmapped_addr.1463712014
Short name T212
Test name
Test status
Simulation time 1281034416 ps
CPU time 7.19 seconds
Started Aug 28 07:16:33 PM UTC 24
Finished Aug 28 07:16:42 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463712014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1463712014
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/32.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device.1758308022
Short name T612
Test name
Test status
Simulation time 60708588 ps
CPU time 10.24 seconds
Started Aug 28 07:16:52 PM UTC 24
Finished Aug 28 07:17:04 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758308022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.1758308022
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/33.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.1470407681
Short name T283
Test name
Test status
Simulation time 13229484592 ps
CPU time 49.35 seconds
Started Aug 28 07:16:54 PM UTC 24
Finished Aug 28 07:17:45 PM UTC 24
Peak memory 212452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470407681 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.1470407681
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/33.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.3167700982
Short name T613
Test name
Test status
Simulation time 571154411 ps
CPU time 8.3 seconds
Started Aug 28 07:16:55 PM UTC 24
Finished Aug 28 07:17:04 PM UTC 24
Peak memory 212332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167700982 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.3167700982
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/33.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_error_random.3553533776
Short name T622
Test name
Test status
Simulation time 872807414 ps
CPU time 18.39 seconds
Started Aug 28 07:16:55 PM UTC 24
Finished Aug 28 07:17:15 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553533776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3553533776
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/33.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random.2331063807
Short name T191
Test name
Test status
Simulation time 538508400 ps
CPU time 8.64 seconds
Started Aug 28 07:16:43 PM UTC 24
Finished Aug 28 07:16:53 PM UTC 24
Peak memory 212444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331063807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.2331063807
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/33.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_large_delays.2962840786
Short name T717
Test name
Test status
Simulation time 26956825637 ps
CPU time 127.94 seconds
Started Aug 28 07:16:48 PM UTC 24
Finished Aug 28 07:18:59 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962840786 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2962840786
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/33.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_slow_rsp.337378668
Short name T715
Test name
Test status
Simulation time 13221188857 ps
CPU time 122.64 seconds
Started Aug 28 07:16:52 PM UTC 24
Finished Aug 28 07:18:58 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337378668 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.337378668
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/33.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_zero_delays.1733233842
Short name T602
Test name
Test status
Simulation time 87594839 ps
CPU time 3.4 seconds
Started Aug 28 07:16:43 PM UTC 24
Finished Aug 28 07:16:48 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733233842 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.1733233842
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/33.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_same_source.3115008712
Short name T608
Test name
Test status
Simulation time 187412518 ps
CPU time 3.52 seconds
Started Aug 28 07:16:54 PM UTC 24
Finished Aug 28 07:16:58 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115008712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3115008712
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/33.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke.1588234497
Short name T600
Test name
Test status
Simulation time 369467559 ps
CPU time 2.35 seconds
Started Aug 28 07:16:39 PM UTC 24
Finished Aug 28 07:16:42 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588234497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1588234497
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/33.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_large_delays.717820338
Short name T605
Test name
Test status
Simulation time 4709023613 ps
CPU time 10.01 seconds
Started Aug 28 07:16:41 PM UTC 24
Finished Aug 28 07:16:53 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717820338 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.717820338
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/33.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.3298557299
Short name T618
Test name
Test status
Simulation time 4422111299 ps
CPU time 22.37 seconds
Started Aug 28 07:16:43 PM UTC 24
Finished Aug 28 07:17:07 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298557299 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.3298557299
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/33.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.1715642830
Short name T601
Test name
Test status
Simulation time 14046912 ps
CPU time 1.45 seconds
Started Aug 28 07:16:40 PM UTC 24
Finished Aug 28 07:16:42 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715642830 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.1715642830
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/33.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all.558901231
Short name T620
Test name
Test status
Simulation time 604076413 ps
CPU time 13 seconds
Started Aug 28 07:16:57 PM UTC 24
Finished Aug 28 07:17:11 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558901231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.558901231
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/33.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_error.1673527253
Short name T700
Test name
Test status
Simulation time 6168536463 ps
CPU time 99.5 seconds
Started Aug 28 07:16:59 PM UTC 24
Finished Aug 28 07:18:41 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673527253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.1673527253
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/33.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.1672916360
Short name T702
Test name
Test status
Simulation time 2604338635 ps
CPU time 102.41 seconds
Started Aug 28 07:16:59 PM UTC 24
Finished Aug 28 07:18:44 PM UTC 24
Peak memory 216488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672916360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.1672916360
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/33.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.4119137666
Short name T665
Test name
Test status
Simulation time 565941020 ps
CPU time 61.37 seconds
Started Aug 28 07:17:00 PM UTC 24
Finished Aug 28 07:18:03 PM UTC 24
Peak memory 216488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119137666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.4119137666
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/33.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_unmapped_addr.3138431304
Short name T609
Test name
Test status
Simulation time 796701930 ps
CPU time 3.91 seconds
Started Aug 28 07:16:55 PM UTC 24
Finished Aug 28 07:17:00 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138431304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3138431304
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/33.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device.2435469264
Short name T634
Test name
Test status
Simulation time 929706570 ps
CPU time 24.9 seconds
Started Aug 28 07:17:08 PM UTC 24
Finished Aug 28 07:17:34 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435469264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.2435469264
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/34.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.2844695060
Short name T192
Test name
Test status
Simulation time 21979343889 ps
CPU time 132.71 seconds
Started Aug 28 07:17:08 PM UTC 24
Finished Aug 28 07:19:24 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844695060 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.2844695060
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/34.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.2809656685
Short name T629
Test name
Test status
Simulation time 342700848 ps
CPU time 8.68 seconds
Started Aug 28 07:17:15 PM UTC 24
Finished Aug 28 07:17:25 PM UTC 24
Peak memory 212140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809656685 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.2809656685
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/34.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_error_random.3226198394
Short name T630
Test name
Test status
Simulation time 478874452 ps
CPU time 10.23 seconds
Started Aug 28 07:17:15 PM UTC 24
Finished Aug 28 07:17:27 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226198394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.3226198394
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/34.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random.3258111441
Short name T626
Test name
Test status
Simulation time 1033296475 ps
CPU time 16.73 seconds
Started Aug 28 07:17:06 PM UTC 24
Finished Aug 28 07:17:24 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258111441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.3258111441
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/34.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.1885017102
Short name T659
Test name
Test status
Simulation time 47752822190 ps
CPU time 50.26 seconds
Started Aug 28 07:17:07 PM UTC 24
Finished Aug 28 07:17:59 PM UTC 24
Peak memory 212264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885017102 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1885017102
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/34.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_slow_rsp.932261567
Short name T676
Test name
Test status
Simulation time 12169357109 ps
CPU time 66.12 seconds
Started Aug 28 07:17:07 PM UTC 24
Finished Aug 28 07:18:15 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932261567 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.932261567
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/34.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_zero_delays.1748668036
Short name T623
Test name
Test status
Simulation time 186052548 ps
CPU time 8.01 seconds
Started Aug 28 07:17:07 PM UTC 24
Finished Aug 28 07:17:16 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748668036 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.1748668036
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/34.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_same_source.210037880
Short name T633
Test name
Test status
Simulation time 2336115444 ps
CPU time 17.23 seconds
Started Aug 28 07:17:12 PM UTC 24
Finished Aug 28 07:17:31 PM UTC 24
Peak memory 212436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210037880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.210037880
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/34.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke.614963160
Short name T614
Test name
Test status
Simulation time 11811859 ps
CPU time 1.57 seconds
Started Aug 28 07:17:02 PM UTC 24
Finished Aug 28 07:17:05 PM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614963160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.614963160
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/34.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_large_delays.1587139057
Short name T39
Test name
Test status
Simulation time 8045637858 ps
CPU time 14.14 seconds
Started Aug 28 07:17:04 PM UTC 24
Finished Aug 28 07:17:20 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587139057 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.1587139057
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/34.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.3933714695
Short name T625
Test name
Test status
Simulation time 1356978842 ps
CPU time 13.81 seconds
Started Aug 28 07:17:06 PM UTC 24
Finished Aug 28 07:17:21 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933714695 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3933714695
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/34.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.2712662966
Short name T616
Test name
Test status
Simulation time 9878604 ps
CPU time 1.7 seconds
Started Aug 28 07:17:03 PM UTC 24
Finished Aug 28 07:17:06 PM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712662966 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.2712662966
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/34.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all.1175162098
Short name T643
Test name
Test status
Simulation time 1459686144 ps
CPU time 25.82 seconds
Started Aug 28 07:17:17 PM UTC 24
Finished Aug 28 07:17:44 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175162098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1175162098
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/34.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_error.1112135647
Short name T644
Test name
Test status
Simulation time 2633850253 ps
CPU time 25.91 seconds
Started Aug 28 07:17:18 PM UTC 24
Finished Aug 28 07:17:45 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112135647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1112135647
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/34.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.1817752683
Short name T788
Test name
Test status
Simulation time 689618983 ps
CPU time 159.92 seconds
Started Aug 28 07:17:18 PM UTC 24
Finished Aug 28 07:20:01 PM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817752683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.1817752683
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/34.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.2949771194
Short name T764
Test name
Test status
Simulation time 862717536 ps
CPU time 133.5 seconds
Started Aug 28 07:17:21 PM UTC 24
Finished Aug 28 07:19:37 PM UTC 24
Peak memory 216232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949771194 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.2949771194
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/34.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_unmapped_addr.833176230
Short name T624
Test name
Test status
Simulation time 33726007 ps
CPU time 4.39 seconds
Started Aug 28 07:17:15 PM UTC 24
Finished Aug 28 07:17:21 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833176230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.833176230
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/34.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device.1703759096
Short name T654
Test name
Test status
Simulation time 1947305186 ps
CPU time 26.76 seconds
Started Aug 28 07:17:27 PM UTC 24
Finished Aug 28 07:17:56 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703759096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.1703759096
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/35.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.783831891
Short name T682
Test name
Test status
Simulation time 8390301729 ps
CPU time 49.16 seconds
Started Aug 28 07:17:30 PM UTC 24
Finished Aug 28 07:18:21 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783831891 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.783831891
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/35.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1191928419
Short name T649
Test name
Test status
Simulation time 929068765 ps
CPU time 13.32 seconds
Started Aug 28 07:17:35 PM UTC 24
Finished Aug 28 07:17:49 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191928419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.1191928419
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/35.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_error_random.1682542882
Short name T636
Test name
Test status
Simulation time 55090610 ps
CPU time 5.88 seconds
Started Aug 28 07:17:32 PM UTC 24
Finished Aug 28 07:17:39 PM UTC 24
Peak memory 212180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682542882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.1682542882
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/35.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random.676163802
Short name T632
Test name
Test status
Simulation time 169973523 ps
CPU time 4.17 seconds
Started Aug 28 07:17:25 PM UTC 24
Finished Aug 28 07:17:31 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676163802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.676163802
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/35.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.2650264195
Short name T143
Test name
Test status
Simulation time 55210360456 ps
CPU time 217.99 seconds
Started Aug 28 07:17:26 PM UTC 24
Finished Aug 28 07:21:08 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650264195 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.2650264195
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/35.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.3997322801
Short name T177
Test name
Test status
Simulation time 37751766650 ps
CPU time 218.53 seconds
Started Aug 28 07:17:26 PM UTC 24
Finished Aug 28 07:21:09 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997322801 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3997322801
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/35.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_zero_delays.734552664
Short name T40
Test name
Test status
Simulation time 64555979 ps
CPU time 10 seconds
Started Aug 28 07:17:26 PM UTC 24
Finished Aug 28 07:17:37 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734552664 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.734552664
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/35.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_same_source.517649248
Short name T639
Test name
Test status
Simulation time 1160404420 ps
CPU time 8.39 seconds
Started Aug 28 07:17:31 PM UTC 24
Finished Aug 28 07:17:40 PM UTC 24
Peak memory 212244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517649248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.517649248
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/35.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke.321575378
Short name T628
Test name
Test status
Simulation time 230364863 ps
CPU time 2.17 seconds
Started Aug 28 07:17:22 PM UTC 24
Finished Aug 28 07:17:25 PM UTC 24
Peak memory 211828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321575378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.321575378
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/35.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_large_delays.2540393508
Short name T635
Test name
Test status
Simulation time 2101215918 ps
CPU time 13.01 seconds
Started Aug 28 07:17:24 PM UTC 24
Finished Aug 28 07:17:38 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540393508 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.2540393508
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/35.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.3094510040
Short name T646
Test name
Test status
Simulation time 2719144360 ps
CPU time 21.39 seconds
Started Aug 28 07:17:24 PM UTC 24
Finished Aug 28 07:17:47 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094510040 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.3094510040
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/35.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.2927718403
Short name T627
Test name
Test status
Simulation time 9149230 ps
CPU time 1.48 seconds
Started Aug 28 07:17:22 PM UTC 24
Finished Aug 28 07:17:24 PM UTC 24
Peak memory 210872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927718403 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.2927718403
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/35.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all.1927927063
Short name T660
Test name
Test status
Simulation time 867458866 ps
CPU time 22.27 seconds
Started Aug 28 07:17:35 PM UTC 24
Finished Aug 28 07:17:59 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927927063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.1927927063
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/35.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_error.294805203
Short name T653
Test name
Test status
Simulation time 2801023277 ps
CPU time 14.43 seconds
Started Aug 28 07:17:39 PM UTC 24
Finished Aug 28 07:17:55 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294805203 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.294805203
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/35.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.3473475766
Short name T122
Test name
Test status
Simulation time 14325570457 ps
CPU time 113.65 seconds
Started Aug 28 07:17:38 PM UTC 24
Finished Aug 28 07:19:35 PM UTC 24
Peak memory 216296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473475766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.3473475766
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/35.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.1000639537
Short name T809
Test name
Test status
Simulation time 902248684 ps
CPU time 162.31 seconds
Started Aug 28 07:17:40 PM UTC 24
Finished Aug 28 07:20:26 PM UTC 24
Peak memory 216232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000639537 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.1000639537
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/35.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_unmapped_addr.705305318
Short name T640
Test name
Test status
Simulation time 439312565 ps
CPU time 7.49 seconds
Started Aug 28 07:17:32 PM UTC 24
Finished Aug 28 07:17:41 PM UTC 24
Peak memory 212012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705305318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.705305318
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/35.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device.1905678357
Short name T658
Test name
Test status
Simulation time 309074563 ps
CPU time 11.4 seconds
Started Aug 28 07:17:45 PM UTC 24
Finished Aug 28 07:17:58 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905678357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.1905678357
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/36.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.1026365654
Short name T124
Test name
Test status
Simulation time 57060377764 ps
CPU time 168.39 seconds
Started Aug 28 07:17:45 PM UTC 24
Finished Aug 28 07:20:37 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026365654 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.1026365654
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/36.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.4247058005
Short name T650
Test name
Test status
Simulation time 38459072 ps
CPU time 4.37 seconds
Started Aug 28 07:17:48 PM UTC 24
Finished Aug 28 07:17:53 PM UTC 24
Peak memory 212396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247058005 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.4247058005
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/36.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_error_random.3884540974
Short name T651
Test name
Test status
Simulation time 79765136 ps
CPU time 5.69 seconds
Started Aug 28 07:17:46 PM UTC 24
Finished Aug 28 07:17:53 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884540974 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.3884540974
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/36.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random.2911053103
Short name T647
Test name
Test status
Simulation time 33888153 ps
CPU time 3.89 seconds
Started Aug 28 07:17:43 PM UTC 24
Finished Aug 28 07:17:48 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911053103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.2911053103
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/36.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.2497552731
Short name T681
Test name
Test status
Simulation time 11279395123 ps
CPU time 34.02 seconds
Started Aug 28 07:17:44 PM UTC 24
Finished Aug 28 07:18:19 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497552731 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2497552731
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/36.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.978937302
Short name T128
Test name
Test status
Simulation time 43036194634 ps
CPU time 340.61 seconds
Started Aug 28 07:17:45 PM UTC 24
Finished Aug 28 07:23:31 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978937302 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.978937302
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/36.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_zero_delays.2148119057
Short name T648
Test name
Test status
Simulation time 38030947 ps
CPU time 4.41 seconds
Started Aug 28 07:17:44 PM UTC 24
Finished Aug 28 07:17:49 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148119057 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.2148119057
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/36.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_same_source.2011822849
Short name T663
Test name
Test status
Simulation time 1334943782 ps
CPU time 14.14 seconds
Started Aug 28 07:17:45 PM UTC 24
Finished Aug 28 07:18:00 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011822849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2011822849
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/36.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke.4225521242
Short name T41
Test name
Test status
Simulation time 146841242 ps
CPU time 2.37 seconds
Started Aug 28 07:17:40 PM UTC 24
Finished Aug 28 07:17:44 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225521242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.4225521242
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/36.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_large_delays.3824511220
Short name T664
Test name
Test status
Simulation time 5326786776 ps
CPU time 18.57 seconds
Started Aug 28 07:17:42 PM UTC 24
Finished Aug 28 07:18:01 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824511220 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.3824511220
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/36.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.1613208468
Short name T655
Test name
Test status
Simulation time 3651510364 ps
CPU time 13.08 seconds
Started Aug 28 07:17:42 PM UTC 24
Finished Aug 28 07:17:56 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613208468 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.1613208468
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/36.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.1026106469
Short name T641
Test name
Test status
Simulation time 12915374 ps
CPU time 1.47 seconds
Started Aug 28 07:17:40 PM UTC 24
Finished Aug 28 07:17:43 PM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026106469 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.1026106469
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/36.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all.1989285339
Short name T738
Test name
Test status
Simulation time 4141264290 ps
CPU time 87.48 seconds
Started Aug 28 07:17:48 PM UTC 24
Finished Aug 28 07:19:17 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989285339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.1989285339
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/36.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_error.1093566028
Short name T705
Test name
Test status
Simulation time 4777847143 ps
CPU time 55.53 seconds
Started Aug 28 07:17:50 PM UTC 24
Finished Aug 28 07:18:47 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093566028 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1093566028
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/36.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.13023201
Short name T202
Test name
Test status
Simulation time 3253914645 ps
CPU time 104.44 seconds
Started Aug 28 07:17:49 PM UTC 24
Finished Aug 28 07:19:35 PM UTC 24
Peak memory 216292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13023201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.13023201
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/36.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3303674113
Short name T680
Test name
Test status
Simulation time 154533456 ps
CPU time 27.54 seconds
Started Aug 28 07:17:50 PM UTC 24
Finished Aug 28 07:18:19 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303674113 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.3303674113
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/36.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_unmapped_addr.1797964951
Short name T652
Test name
Test status
Simulation time 410090988 ps
CPU time 7.4 seconds
Started Aug 28 07:17:46 PM UTC 24
Finished Aug 28 07:17:55 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797964951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1797964951
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/36.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device.212262172
Short name T690
Test name
Test status
Simulation time 2028302015 ps
CPU time 28.02 seconds
Started Aug 28 07:17:58 PM UTC 24
Finished Aug 28 07:18:28 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212262172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.212262172
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/37.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3165133416
Short name T130
Test name
Test status
Simulation time 83765343781 ps
CPU time 438 seconds
Started Aug 28 07:18:00 PM UTC 24
Finished Aug 28 07:25:24 PM UTC 24
Peak memory 214436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165133416 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.3165133416
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/37.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.2659111954
Short name T672
Test name
Test status
Simulation time 47681651 ps
CPU time 5.05 seconds
Started Aug 28 07:18:02 PM UTC 24
Finished Aug 28 07:18:08 PM UTC 24
Peak memory 212140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659111954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.2659111954
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/37.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_error_random.2958282325
Short name T678
Test name
Test status
Simulation time 6521367230 ps
CPU time 16.65 seconds
Started Aug 28 07:18:00 PM UTC 24
Finished Aug 28 07:18:18 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958282325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2958282325
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/37.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random.1818138946
Short name T662
Test name
Test status
Simulation time 28470162 ps
CPU time 3.03 seconds
Started Aug 28 07:17:56 PM UTC 24
Finished Aug 28 07:18:00 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818138946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.1818138946
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/37.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.3958598549
Short name T726
Test name
Test status
Simulation time 17200954375 ps
CPU time 67.5 seconds
Started Aug 28 07:17:57 PM UTC 24
Finished Aug 28 07:19:07 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958598549 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.3958598549
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/37.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.2117460387
Short name T737
Test name
Test status
Simulation time 10054556346 ps
CPU time 77.56 seconds
Started Aug 28 07:17:57 PM UTC 24
Finished Aug 28 07:19:17 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117460387 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2117460387
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/37.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_zero_delays.201040573
Short name T669
Test name
Test status
Simulation time 148334620 ps
CPU time 8.57 seconds
Started Aug 28 07:17:57 PM UTC 24
Finished Aug 28 07:18:07 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201040573 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.201040573
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/37.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_same_source.1840330234
Short name T666
Test name
Test status
Simulation time 51724798 ps
CPU time 3.43 seconds
Started Aug 28 07:18:00 PM UTC 24
Finished Aug 28 07:18:04 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840330234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.1840330234
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/37.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke.3962713913
Short name T656
Test name
Test status
Simulation time 11012180 ps
CPU time 1.59 seconds
Started Aug 28 07:17:54 PM UTC 24
Finished Aug 28 07:17:57 PM UTC 24
Peak memory 211228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962713913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.3962713913
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/37.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_large_delays.4160292521
Short name T670
Test name
Test status
Simulation time 1894930093 ps
CPU time 10.25 seconds
Started Aug 28 07:17:56 PM UTC 24
Finished Aug 28 07:18:07 PM UTC 24
Peak memory 211936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160292521 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.4160292521
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/37.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.67501327
Short name T671
Test name
Test status
Simulation time 2049490456 ps
CPU time 10.66 seconds
Started Aug 28 07:17:56 PM UTC 24
Finished Aug 28 07:18:08 PM UTC 24
Peak memory 212068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67501327 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.67501327
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/37.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.425086174
Short name T657
Test name
Test status
Simulation time 21935154 ps
CPU time 1.92 seconds
Started Aug 28 07:17:54 PM UTC 24
Finished Aug 28 07:17:57 PM UTC 24
Peak memory 211232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425086174 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.425086174
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/37.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.1133660322
Short name T711
Test name
Test status
Simulation time 8141147882 ps
CPU time 49.73 seconds
Started Aug 28 07:18:02 PM UTC 24
Finished Aug 28 07:18:53 PM UTC 24
Peak memory 214496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133660322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.1133660322
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/37.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_error.3561135716
Short name T683
Test name
Test status
Simulation time 136227562 ps
CPU time 14.7 seconds
Started Aug 28 07:18:05 PM UTC 24
Finished Aug 28 07:18:21 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561135716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.3561135716
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/37.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.2229922471
Short name T781
Test name
Test status
Simulation time 3886475737 ps
CPU time 105.81 seconds
Started Aug 28 07:18:06 PM UTC 24
Finished Aug 28 07:19:55 PM UTC 24
Peak memory 216616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229922471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.2229922471
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/37.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_unmapped_addr.717393627
Short name T673
Test name
Test status
Simulation time 283508732 ps
CPU time 7.45 seconds
Started Aug 28 07:18:01 PM UTC 24
Finished Aug 28 07:18:09 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717393627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.717393627
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/37.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device.1581884237
Short name T120
Test name
Test status
Simulation time 519574601 ps
CPU time 8.37 seconds
Started Aug 28 07:18:15 PM UTC 24
Finished Aug 28 07:18:25 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581884237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.1581884237
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/38.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.4274101232
Short name T304
Test name
Test status
Simulation time 37533319830 ps
CPU time 304.1 seconds
Started Aug 28 07:18:15 PM UTC 24
Finished Aug 28 07:23:25 PM UTC 24
Peak memory 214436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274101232 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.4274101232
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/38.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.3805004923
Short name T688
Test name
Test status
Simulation time 63848753 ps
CPU time 5.17 seconds
Started Aug 28 07:18:20 PM UTC 24
Finished Aug 28 07:18:27 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805004923 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.3805004923
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/38.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_error_random.4079353304
Short name T697
Test name
Test status
Simulation time 942696976 ps
CPU time 19.58 seconds
Started Aug 28 07:18:18 PM UTC 24
Finished Aug 28 07:18:39 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079353304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.4079353304
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/38.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random.1826950360
Short name T687
Test name
Test status
Simulation time 3880614759 ps
CPU time 16.39 seconds
Started Aug 28 07:18:09 PM UTC 24
Finished Aug 28 07:18:26 PM UTC 24
Peak memory 212184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826950360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.1826950360
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/38.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.1954879704
Short name T152
Test name
Test status
Simulation time 238062978156 ps
CPU time 195.95 seconds
Started Aug 28 07:18:11 PM UTC 24
Finished Aug 28 07:21:30 PM UTC 24
Peak memory 211924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954879704 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.1954879704
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/38.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.1961002166
Short name T709
Test name
Test status
Simulation time 3830591762 ps
CPU time 37.34 seconds
Started Aug 28 07:18:11 PM UTC 24
Finished Aug 28 07:18:50 PM UTC 24
Peak memory 212512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961002166 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.1961002166
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/38.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_zero_delays.946673242
Short name T677
Test name
Test status
Simulation time 51684416 ps
CPU time 6.27 seconds
Started Aug 28 07:18:10 PM UTC 24
Finished Aug 28 07:18:17 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946673242 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.946673242
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/38.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_same_source.200957573
Short name T685
Test name
Test status
Simulation time 43115708 ps
CPU time 4.34 seconds
Started Aug 28 07:18:18 PM UTC 24
Finished Aug 28 07:18:24 PM UTC 24
Peak memory 212112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200957573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.200957573
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/38.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke.2081313797
Short name T674
Test name
Test status
Simulation time 8577179 ps
CPU time 1.65 seconds
Started Aug 28 07:18:08 PM UTC 24
Finished Aug 28 07:18:10 PM UTC 24
Peak memory 211128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081313797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2081313797
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/38.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_large_delays.1912830877
Short name T684
Test name
Test status
Simulation time 5516264213 ps
CPU time 13.27 seconds
Started Aug 28 07:18:09 PM UTC 24
Finished Aug 28 07:18:23 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912830877 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.1912830877
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/38.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.4078459505
Short name T679
Test name
Test status
Simulation time 992914175 ps
CPU time 8.5 seconds
Started Aug 28 07:18:09 PM UTC 24
Finished Aug 28 07:18:18 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078459505 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.4078459505
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/38.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.2240816096
Short name T675
Test name
Test status
Simulation time 9561269 ps
CPU time 1.89 seconds
Started Aug 28 07:18:08 PM UTC 24
Finished Aug 28 07:18:10 PM UTC 24
Peak memory 211180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240816096 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.2240816096
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/38.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.2760354017
Short name T716
Test name
Test status
Simulation time 506624711 ps
CPU time 36.63 seconds
Started Aug 28 07:18:20 PM UTC 24
Finished Aug 28 07:18:59 PM UTC 24
Peak memory 214168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760354017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.2760354017
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/38.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.2823821524
Short name T712
Test name
Test status
Simulation time 240876586 ps
CPU time 30.26 seconds
Started Aug 28 07:18:22 PM UTC 24
Finished Aug 28 07:18:53 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823821524 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2823821524
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/38.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2351553054
Short name T842
Test name
Test status
Simulation time 2189624143 ps
CPU time 155.75 seconds
Started Aug 28 07:18:20 PM UTC 24
Finished Aug 28 07:21:00 PM UTC 24
Peak memory 214504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351553054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.2351553054
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/38.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.2386810149
Short name T875
Test name
Test status
Simulation time 11629522900 ps
CPU time 207.61 seconds
Started Aug 28 07:18:22 PM UTC 24
Finished Aug 28 07:21:53 PM UTC 24
Peak memory 218568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386810149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.2386810149
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/38.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_unmapped_addr.1170235969
Short name T693
Test name
Test status
Simulation time 559424278 ps
CPU time 9.9 seconds
Started Aug 28 07:18:20 PM UTC 24
Finished Aug 28 07:18:31 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170235969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1170235969
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/38.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device.830604998
Short name T694
Test name
Test status
Simulation time 11620521 ps
CPU time 2.28 seconds
Started Aug 28 07:18:29 PM UTC 24
Finished Aug 28 07:18:32 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830604998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.830604998
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/39.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.4231033045
Short name T713
Test name
Test status
Simulation time 1363813052 ps
CPU time 11.57 seconds
Started Aug 28 07:18:41 PM UTC 24
Finished Aug 28 07:18:54 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231033045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.4231033045
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/39.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_error_random.3488096425
Short name T710
Test name
Test status
Simulation time 753302594 ps
CPU time 16.83 seconds
Started Aug 28 07:18:34 PM UTC 24
Finished Aug 28 07:18:52 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488096425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.3488096425
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/39.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random.1035870269
Short name T696
Test name
Test status
Simulation time 585314238 ps
CPU time 10.46 seconds
Started Aug 28 07:18:27 PM UTC 24
Finished Aug 28 07:18:39 PM UTC 24
Peak memory 212316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035870269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.1035870269
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/39.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.3955830487
Short name T820
Test name
Test status
Simulation time 21868624778 ps
CPU time 120.75 seconds
Started Aug 28 07:18:27 PM UTC 24
Finished Aug 28 07:20:31 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955830487 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.3955830487
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/39.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.3585754604
Short name T883
Test name
Test status
Simulation time 163349891131 ps
CPU time 226.04 seconds
Started Aug 28 07:18:29 PM UTC 24
Finished Aug 28 07:22:19 PM UTC 24
Peak memory 212448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585754604 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3585754604
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/39.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_zero_delays.642278594
Short name T692
Test name
Test status
Simulation time 14663748 ps
CPU time 2.11 seconds
Started Aug 28 07:18:27 PM UTC 24
Finished Aug 28 07:18:31 PM UTC 24
Peak memory 212452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642278594 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.642278594
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/39.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_same_source.1920880463
Short name T704
Test name
Test status
Simulation time 898708833 ps
CPU time 12.32 seconds
Started Aug 28 07:18:33 PM UTC 24
Finished Aug 28 07:18:46 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920880463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.1920880463
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/39.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke.1497359435
Short name T689
Test name
Test status
Simulation time 12968623 ps
CPU time 1.66 seconds
Started Aug 28 07:18:24 PM UTC 24
Finished Aug 28 07:18:27 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497359435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.1497359435
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/39.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_large_delays.517678508
Short name T703
Test name
Test status
Simulation time 6038748442 ps
CPU time 19.07 seconds
Started Aug 28 07:18:26 PM UTC 24
Finished Aug 28 07:18:46 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517678508 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.517678508
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/39.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.3834752894
Short name T698
Test name
Test status
Simulation time 1222453301 ps
CPU time 11.37 seconds
Started Aug 28 07:18:27 PM UTC 24
Finished Aug 28 07:18:40 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834752894 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.3834752894
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/39.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.3055029388
Short name T691
Test name
Test status
Simulation time 10977006 ps
CPU time 1.72 seconds
Started Aug 28 07:18:25 PM UTC 24
Finished Aug 28 07:18:28 PM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055029388 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.3055029388
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/39.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.570185931
Short name T708
Test name
Test status
Simulation time 30700791 ps
CPU time 6.3 seconds
Started Aug 28 07:18:41 PM UTC 24
Finished Aug 28 07:18:49 PM UTC 24
Peak memory 212284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570185931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.570185931
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/39.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.1378894444
Short name T861
Test name
Test status
Simulation time 7966532888 ps
CPU time 154.29 seconds
Started Aug 28 07:18:41 PM UTC 24
Finished Aug 28 07:21:19 PM UTC 24
Peak memory 214204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378894444 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.1378894444
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/39.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.316367138
Short name T714
Test name
Test status
Simulation time 94530262 ps
CPU time 12.27 seconds
Started Aug 28 07:18:41 PM UTC 24
Finished Aug 28 07:18:55 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316367138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.316367138
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/39.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.1403771787
Short name T743
Test name
Test status
Simulation time 214463119 ps
CPU time 35.26 seconds
Started Aug 28 07:18:43 PM UTC 24
Finished Aug 28 07:19:19 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403771787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.1403771787
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/39.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_unmapped_addr.1258162129
Short name T699
Test name
Test status
Simulation time 40387697 ps
CPU time 4.13 seconds
Started Aug 28 07:18:35 PM UTC 24
Finished Aug 28 07:18:40 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258162129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1258162129
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/39.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device.1627782238
Short name T65
Test name
Test status
Simulation time 462181057 ps
CPU time 10.43 seconds
Started Aug 28 07:07:52 PM UTC 24
Finished Aug 28 07:08:03 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627782238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.1627782238
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/4.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.2702685355
Short name T258
Test name
Test status
Simulation time 805648857 ps
CPU time 13.28 seconds
Started Aug 28 07:07:59 PM UTC 24
Finished Aug 28 07:08:14 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702685355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.2702685355
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/4.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_error_random.1961535586
Short name T307
Test name
Test status
Simulation time 3496937445 ps
CPU time 16.56 seconds
Started Aug 28 07:07:54 PM UTC 24
Finished Aug 28 07:08:12 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961535586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.1961535586
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/4.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random.1843511555
Short name T74
Test name
Test status
Simulation time 132591795 ps
CPU time 3.78 seconds
Started Aug 28 07:07:44 PM UTC 24
Finished Aug 28 07:07:50 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843511555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.1843511555
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/4.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_large_delays.346823071
Short name T68
Test name
Test status
Simulation time 4197648438 ps
CPU time 29.95 seconds
Started Aug 28 07:07:48 PM UTC 24
Finished Aug 28 07:08:20 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346823071 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.346823071
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/4.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_slow_rsp.1185137031
Short name T418
Test name
Test status
Simulation time 87953292260 ps
CPU time 248.32 seconds
Started Aug 28 07:07:51 PM UTC 24
Finished Aug 28 07:12:03 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185137031 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1185137031
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/4.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_zero_delays.1008783101
Short name T89
Test name
Test status
Simulation time 73803395 ps
CPU time 9.91 seconds
Started Aug 28 07:07:45 PM UTC 24
Finished Aug 28 07:07:57 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008783101 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.1008783101
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/4.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_same_source.1907803369
Short name T64
Test name
Test status
Simulation time 625826823 ps
CPU time 8.07 seconds
Started Aug 28 07:07:54 PM UTC 24
Finished Aug 28 07:08:03 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907803369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1907803369
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/4.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke.1917908613
Short name T72
Test name
Test status
Simulation time 126355125 ps
CPU time 2.67 seconds
Started Aug 28 07:07:35 PM UTC 24
Finished Aug 28 07:07:39 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917908613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1917908613
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/4.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_large_delays.1687824545
Short name T90
Test name
Test status
Simulation time 2297464691 ps
CPU time 17.83 seconds
Started Aug 28 07:07:39 PM UTC 24
Finished Aug 28 07:07:58 PM UTC 24
Peak memory 212380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687824545 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1687824545
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/4.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.2381623141
Short name T63
Test name
Test status
Simulation time 1221298883 ps
CPU time 14.86 seconds
Started Aug 28 07:07:41 PM UTC 24
Finished Aug 28 07:07:58 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381623141 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2381623141
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/4.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.395283415
Short name T73
Test name
Test status
Simulation time 20278102 ps
CPU time 1.6 seconds
Started Aug 28 07:07:38 PM UTC 24
Finished Aug 28 07:07:41 PM UTC 24
Peak memory 211184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395283415 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.395283415
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/4.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all.1858555645
Short name T69
Test name
Test status
Simulation time 1326681928 ps
CPU time 27.9 seconds
Started Aug 28 07:07:59 PM UTC 24
Finished Aug 28 07:08:28 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858555645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1858555645
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/4.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_error.1897862079
Short name T328
Test name
Test status
Simulation time 691727536 ps
CPU time 16.24 seconds
Started Aug 28 07:08:02 PM UTC 24
Finished Aug 28 07:08:20 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897862079 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1897862079
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/4.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.662447703
Short name T215
Test name
Test status
Simulation time 1601372030 ps
CPU time 130.23 seconds
Started Aug 28 07:08:00 PM UTC 24
Finished Aug 28 07:10:13 PM UTC 24
Peak memory 216424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662447703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.662447703
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/4.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.1088906095
Short name T338
Test name
Test status
Simulation time 2765778177 ps
CPU time 47.28 seconds
Started Aug 28 07:08:03 PM UTC 24
Finished Aug 28 07:08:52 PM UTC 24
Peak memory 214048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088906095 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.1088906095
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/4.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_unmapped_addr.614191065
Short name T150
Test name
Test status
Simulation time 102155708 ps
CPU time 7.46 seconds
Started Aug 28 07:07:58 PM UTC 24
Finished Aug 28 07:08:07 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614191065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.614191065
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/4.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device.368779235
Short name T729
Test name
Test status
Simulation time 1067032195 ps
CPU time 19.2 seconds
Started Aug 28 07:18:50 PM UTC 24
Finished Aug 28 07:19:11 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368779235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.368779235
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/40.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.3973496935
Short name T719
Test name
Test status
Simulation time 352576120 ps
CPU time 4.48 seconds
Started Aug 28 07:18:56 PM UTC 24
Finished Aug 28 07:19:01 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973496935 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.3973496935
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/40.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_error_random.1460441077
Short name T728
Test name
Test status
Simulation time 885891498 ps
CPU time 13.14 seconds
Started Aug 28 07:18:54 PM UTC 24
Finished Aug 28 07:19:09 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460441077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.1460441077
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/40.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random.4197071341
Short name T721
Test name
Test status
Simulation time 1305102862 ps
CPU time 14.24 seconds
Started Aug 28 07:18:47 PM UTC 24
Finished Aug 28 07:19:02 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197071341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.4197071341
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/40.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.3121698149
Short name T238
Test name
Test status
Simulation time 41559740088 ps
CPU time 153.82 seconds
Started Aug 28 07:18:49 PM UTC 24
Finished Aug 28 07:21:26 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121698149 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.3121698149
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/40.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.649166832
Short name T872
Test name
Test status
Simulation time 101195598175 ps
CPU time 172.56 seconds
Started Aug 28 07:18:49 PM UTC 24
Finished Aug 28 07:21:46 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649166832 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.649166832
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/40.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_zero_delays.566663419
Short name T718
Test name
Test status
Simulation time 60870686 ps
CPU time 8.04 seconds
Started Aug 28 07:18:49 PM UTC 24
Finished Aug 28 07:18:59 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566663419 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.566663419
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/40.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_same_source.2081380189
Short name T732
Test name
Test status
Simulation time 1308102232 ps
CPU time 19.22 seconds
Started Aug 28 07:18:53 PM UTC 24
Finished Aug 28 07:19:13 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081380189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2081380189
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/40.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke.1402017409
Short name T707
Test name
Test status
Simulation time 66563249 ps
CPU time 1.95 seconds
Started Aug 28 07:18:44 PM UTC 24
Finished Aug 28 07:18:48 PM UTC 24
Peak memory 210744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402017409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.1402017409
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/40.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_large_delays.3944493209
Short name T722
Test name
Test status
Simulation time 2059435502 ps
CPU time 16.1 seconds
Started Aug 28 07:18:45 PM UTC 24
Finished Aug 28 07:19:03 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944493209 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.3944493209
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/40.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.2558561889
Short name T727
Test name
Test status
Simulation time 1998310848 ps
CPU time 19.04 seconds
Started Aug 28 07:18:47 PM UTC 24
Finished Aug 28 07:19:07 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558561889 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.2558561889
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/40.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.702271913
Short name T706
Test name
Test status
Simulation time 8962812 ps
CPU time 1.65 seconds
Started Aug 28 07:18:44 PM UTC 24
Finished Aug 28 07:18:47 PM UTC 24
Peak memory 210612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702271913 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.702271913
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/40.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.3479566049
Short name T789
Test name
Test status
Simulation time 1778350022 ps
CPU time 63.47 seconds
Started Aug 28 07:18:56 PM UTC 24
Finished Aug 28 07:20:01 PM UTC 24
Peak memory 216416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479566049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3479566049
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/40.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.4191599379
Short name T742
Test name
Test status
Simulation time 498565308 ps
CPU time 18.42 seconds
Started Aug 28 07:19:00 PM UTC 24
Finished Aug 28 07:19:19 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191599379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.4191599379
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/40.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.3327487404
Short name T845
Test name
Test status
Simulation time 8542346560 ps
CPU time 119.06 seconds
Started Aug 28 07:19:00 PM UTC 24
Finished Aug 28 07:21:01 PM UTC 24
Peak memory 216296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327487404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.3327487404
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/40.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_unmapped_addr.2760234447
Short name T720
Test name
Test status
Simulation time 163742103 ps
CPU time 6.08 seconds
Started Aug 28 07:18:54 PM UTC 24
Finished Aug 28 07:19:02 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760234447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2760234447
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/40.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device.1913935177
Short name T741
Test name
Test status
Simulation time 544807801 ps
CPU time 11.2 seconds
Started Aug 28 07:19:07 PM UTC 24
Finished Aug 28 07:19:19 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913935177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.1913935177
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/41.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3339641851
Short name T885
Test name
Test status
Simulation time 109755412602 ps
CPU time 193.79 seconds
Started Aug 28 07:19:08 PM UTC 24
Finished Aug 28 07:22:25 PM UTC 24
Peak memory 214192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339641851 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.3339641851
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/41.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.2104039697
Short name T744
Test name
Test status
Simulation time 1958194104 ps
CPU time 9.29 seconds
Started Aug 28 07:19:10 PM UTC 24
Finished Aug 28 07:19:20 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104039697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.2104039697
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/41.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_error_random.1980542774
Short name T736
Test name
Test status
Simulation time 62158842 ps
CPU time 5.96 seconds
Started Aug 28 07:19:08 PM UTC 24
Finished Aug 28 07:19:16 PM UTC 24
Peak memory 212176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980542774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.1980542774
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/41.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random.3861994446
Short name T750
Test name
Test status
Simulation time 3705703218 ps
CPU time 21.58 seconds
Started Aug 28 07:19:04 PM UTC 24
Finished Aug 28 07:19:27 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861994446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.3861994446
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/41.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.2127640339
Short name T745
Test name
Test status
Simulation time 2192823371 ps
CPU time 14.38 seconds
Started Aug 28 07:19:05 PM UTC 24
Finished Aug 28 07:19:21 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127640339 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.2127640339
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/41.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.3507532316
Short name T887
Test name
Test status
Simulation time 22525699336 ps
CPU time 232.22 seconds
Started Aug 28 07:19:07 PM UTC 24
Finished Aug 28 07:23:03 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507532316 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.3507532316
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/41.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_zero_delays.2353756165
Short name T731
Test name
Test status
Simulation time 84708980 ps
CPU time 8.03 seconds
Started Aug 28 07:19:04 PM UTC 24
Finished Aug 28 07:19:13 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353756165 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.2353756165
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/41.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_same_source.2359253727
Short name T753
Test name
Test status
Simulation time 942381710 ps
CPU time 18.36 seconds
Started Aug 28 07:19:08 PM UTC 24
Finished Aug 28 07:19:28 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359253727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.2359253727
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/41.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke.1036427090
Short name T723
Test name
Test status
Simulation time 114240918 ps
CPU time 1.89 seconds
Started Aug 28 07:19:01 PM UTC 24
Finished Aug 28 07:19:04 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036427090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1036427090
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/41.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_large_delays.2443788838
Short name T735
Test name
Test status
Simulation time 2073888736 ps
CPU time 10.51 seconds
Started Aug 28 07:19:02 PM UTC 24
Finished Aug 28 07:19:14 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443788838 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2443788838
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/41.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.3437339321
Short name T734
Test name
Test status
Simulation time 736636930 ps
CPU time 8.87 seconds
Started Aug 28 07:19:04 PM UTC 24
Finished Aug 28 07:19:14 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437339321 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.3437339321
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/41.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2743006815
Short name T724
Test name
Test status
Simulation time 9157974 ps
CPU time 1.61 seconds
Started Aug 28 07:19:02 PM UTC 24
Finished Aug 28 07:19:05 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743006815 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2743006815
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/41.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.2670829208
Short name T839
Test name
Test status
Simulation time 4470743550 ps
CPU time 97.1 seconds
Started Aug 28 07:19:12 PM UTC 24
Finished Aug 28 07:20:51 PM UTC 24
Peak memory 214236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670829208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.2670829208
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/41.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.1987524180
Short name T763
Test name
Test status
Simulation time 362668948 ps
CPU time 20.18 seconds
Started Aug 28 07:19:15 PM UTC 24
Finished Aug 28 07:19:37 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987524180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1987524180
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/41.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.4055604011
Short name T158
Test name
Test status
Simulation time 8622804008 ps
CPU time 125.05 seconds
Started Aug 28 07:19:13 PM UTC 24
Finished Aug 28 07:21:21 PM UTC 24
Peak memory 216296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055604011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.4055604011
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/41.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.3496952723
Short name T873
Test name
Test status
Simulation time 761641711 ps
CPU time 151.54 seconds
Started Aug 28 07:19:15 PM UTC 24
Finished Aug 28 07:21:50 PM UTC 24
Peak memory 218268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496952723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.3496952723
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/41.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_unmapped_addr.1757299071
Short name T746
Test name
Test status
Simulation time 1144840622 ps
CPU time 11.95 seconds
Started Aug 28 07:19:08 PM UTC 24
Finished Aug 28 07:19:22 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757299071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1757299071
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/41.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device.1049547831
Short name T752
Test name
Test status
Simulation time 20985105 ps
CPU time 4.78 seconds
Started Aug 28 07:19:22 PM UTC 24
Finished Aug 28 07:19:28 PM UTC 24
Peak memory 212260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049547831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.1049547831
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/42.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2511868503
Short name T810
Test name
Test status
Simulation time 14203759792 ps
CPU time 62.29 seconds
Started Aug 28 07:19:22 PM UTC 24
Finished Aug 28 07:20:26 PM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511868503 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.2511868503
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/42.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.878228511
Short name T759
Test name
Test status
Simulation time 114415182 ps
CPU time 7.79 seconds
Started Aug 28 07:19:23 PM UTC 24
Finished Aug 28 07:19:33 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878228511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.878228511
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/42.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_error_random.1507909592
Short name T749
Test name
Test status
Simulation time 8832085 ps
CPU time 1.62 seconds
Started Aug 28 07:19:22 PM UTC 24
Finished Aug 28 07:19:25 PM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507909592 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.1507909592
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/42.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random.3576813014
Short name T762
Test name
Test status
Simulation time 1063496152 ps
CPU time 16.32 seconds
Started Aug 28 07:19:18 PM UTC 24
Finished Aug 28 07:19:36 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576813014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.3576813014
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/42.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.294760693
Short name T798
Test name
Test status
Simulation time 19034112480 ps
CPU time 49.51 seconds
Started Aug 28 07:19:20 PM UTC 24
Finished Aug 28 07:20:11 PM UTC 24
Peak memory 212172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294760693 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.294760693
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/42.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2578298480
Short name T876
Test name
Test status
Simulation time 45495340668 ps
CPU time 151.47 seconds
Started Aug 28 07:19:20 PM UTC 24
Finished Aug 28 07:21:54 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578298480 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2578298480
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/42.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_zero_delays.3403354192
Short name T748
Test name
Test status
Simulation time 36751057 ps
CPU time 4.3 seconds
Started Aug 28 07:19:18 PM UTC 24
Finished Aug 28 07:19:24 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403354192 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.3403354192
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/42.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_same_source.933881215
Short name T751
Test name
Test status
Simulation time 188168911 ps
CPU time 4.55 seconds
Started Aug 28 07:19:22 PM UTC 24
Finished Aug 28 07:19:28 PM UTC 24
Peak memory 212116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933881215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.933881215
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/42.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke.4111555823
Short name T740
Test name
Test status
Simulation time 66726161 ps
CPU time 2.62 seconds
Started Aug 28 07:19:16 PM UTC 24
Finished Aug 28 07:19:19 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111555823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.4111555823
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/42.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1234745613
Short name T756
Test name
Test status
Simulation time 4493886739 ps
CPU time 14.68 seconds
Started Aug 28 07:19:16 PM UTC 24
Finished Aug 28 07:19:31 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234745613 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1234745613
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/42.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.859924507
Short name T754
Test name
Test status
Simulation time 2387067012 ps
CPU time 11.76 seconds
Started Aug 28 07:19:17 PM UTC 24
Finished Aug 28 07:19:30 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859924507 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.859924507
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/42.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.3988084265
Short name T739
Test name
Test status
Simulation time 8056890 ps
CPU time 1.59 seconds
Started Aug 28 07:19:16 PM UTC 24
Finished Aug 28 07:19:18 PM UTC 24
Peak memory 211180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988084265 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.3988084265
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/42.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.1355671831
Short name T766
Test name
Test status
Simulation time 305439162 ps
CPU time 11.91 seconds
Started Aug 28 07:19:25 PM UTC 24
Finished Aug 28 07:19:38 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355671831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1355671831
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/42.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3023707332
Short name T769
Test name
Test status
Simulation time 355028436 ps
CPU time 14.08 seconds
Started Aug 28 07:19:26 PM UTC 24
Finished Aug 28 07:19:42 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023707332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3023707332
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/42.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.3032491885
Short name T841
Test name
Test status
Simulation time 796094173 ps
CPU time 90.62 seconds
Started Aug 28 07:19:25 PM UTC 24
Finished Aug 28 07:20:58 PM UTC 24
Peak memory 216232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032491885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.3032491885
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/42.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.2892407184
Short name T785
Test name
Test status
Simulation time 263377714 ps
CPU time 29.74 seconds
Started Aug 28 07:19:28 PM UTC 24
Finished Aug 28 07:19:59 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892407184 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.2892407184
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/42.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_unmapped_addr.2864726337
Short name T760
Test name
Test status
Simulation time 1283484503 ps
CPU time 10.89 seconds
Started Aug 28 07:19:22 PM UTC 24
Finished Aug 28 07:19:34 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864726337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2864726337
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/42.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.3356341166
Short name T768
Test name
Test status
Simulation time 34555726 ps
CPU time 6.16 seconds
Started Aug 28 07:19:33 PM UTC 24
Finished Aug 28 07:19:40 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356341166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.3356341166
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/43.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3909921451
Short name T899
Test name
Test status
Simulation time 91940640095 ps
CPU time 429.83 seconds
Started Aug 28 07:19:34 PM UTC 24
Finished Aug 28 07:26:50 PM UTC 24
Peak memory 214436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909921451 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.3909921451
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/43.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.3726270732
Short name T771
Test name
Test status
Simulation time 485593815 ps
CPU time 6.15 seconds
Started Aug 28 07:19:36 PM UTC 24
Finished Aug 28 07:19:43 PM UTC 24
Peak memory 212396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726270732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.3726270732
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/43.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.650756462
Short name T15
Test name
Test status
Simulation time 126094435 ps
CPU time 3.76 seconds
Started Aug 28 07:19:36 PM UTC 24
Finished Aug 28 07:19:41 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650756462 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.650756462
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/43.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random.3718617193
Short name T761
Test name
Test status
Simulation time 613637256 ps
CPU time 3.66 seconds
Started Aug 28 07:19:31 PM UTC 24
Finished Aug 28 07:19:35 PM UTC 24
Peak memory 212316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718617193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.3718617193
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/43.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.599608120
Short name T776
Test name
Test status
Simulation time 2875365052 ps
CPU time 14.52 seconds
Started Aug 28 07:19:33 PM UTC 24
Finished Aug 28 07:19:49 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599608120 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.599608120
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/43.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.70339964
Short name T881
Test name
Test status
Simulation time 20298514892 ps
CPU time 158.03 seconds
Started Aug 28 07:19:33 PM UTC 24
Finished Aug 28 07:22:14 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70339964 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.70339964
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/43.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.444240369
Short name T765
Test name
Test status
Simulation time 49599467 ps
CPU time 4.12 seconds
Started Aug 28 07:19:33 PM UTC 24
Finished Aug 28 07:19:38 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444240369 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.444240369
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/43.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.2154953988
Short name T773
Test name
Test status
Simulation time 482038333 ps
CPU time 8.24 seconds
Started Aug 28 07:19:34 PM UTC 24
Finished Aug 28 07:19:43 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154953988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.2154953988
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/43.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke.52143204
Short name T757
Test name
Test status
Simulation time 11760262 ps
CPU time 1.31 seconds
Started Aug 28 07:19:29 PM UTC 24
Finished Aug 28 07:19:32 PM UTC 24
Peak memory 211244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52143204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs
/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.52143204
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/43.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.1500720295
Short name T775
Test name
Test status
Simulation time 4464471282 ps
CPU time 16.08 seconds
Started Aug 28 07:19:29 PM UTC 24
Finished Aug 28 07:19:47 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500720295 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1500720295
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/43.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.899901901
Short name T774
Test name
Test status
Simulation time 807667408 ps
CPU time 13.04 seconds
Started Aug 28 07:19:29 PM UTC 24
Finished Aug 28 07:19:44 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899901901 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.899901901
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/43.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.2761091204
Short name T758
Test name
Test status
Simulation time 9020748 ps
CPU time 1.56 seconds
Started Aug 28 07:19:29 PM UTC 24
Finished Aug 28 07:19:32 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761091204 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.2761091204
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/43.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.1410088034
Short name T862
Test name
Test status
Simulation time 22566343524 ps
CPU time 98.95 seconds
Started Aug 28 07:19:38 PM UTC 24
Finished Aug 28 07:21:19 PM UTC 24
Peak memory 214496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410088034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.1410088034
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/43.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.643575035
Short name T814
Test name
Test status
Simulation time 2988332885 ps
CPU time 47.47 seconds
Started Aug 28 07:19:38 PM UTC 24
Finished Aug 28 07:20:27 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643575035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.643575035
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/43.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1113181720
Short name T178
Test name
Test status
Simulation time 3118084630 ps
CPU time 121.11 seconds
Started Aug 28 07:19:38 PM UTC 24
Finished Aug 28 07:21:42 PM UTC 24
Peak memory 216296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113181720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.1113181720
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/43.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.162766767
Short name T793
Test name
Test status
Simulation time 129582554 ps
CPU time 22.29 seconds
Started Aug 28 07:19:41 PM UTC 24
Finished Aug 28 07:20:04 PM UTC 24
Peak memory 212140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162766767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.162766767
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/43.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.1922911697
Short name T767
Test name
Test status
Simulation time 24022952 ps
CPU time 2.06 seconds
Started Aug 28 07:19:36 PM UTC 24
Finished Aug 28 07:19:39 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922911697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1922911697
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/43.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.632399754
Short name T123
Test name
Test status
Simulation time 223942620 ps
CPU time 5.51 seconds
Started Aug 28 07:19:44 PM UTC 24
Finished Aug 28 07:19:51 PM UTC 24
Peak memory 211948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632399754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.632399754
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/44.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.2289607034
Short name T900
Test name
Test status
Simulation time 157521670719 ps
CPU time 421.98 seconds
Started Aug 28 07:19:44 PM UTC 24
Finished Aug 28 07:26:52 PM UTC 24
Peak memory 216484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289607034 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.2289607034
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/44.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.1282379489
Short name T779
Test name
Test status
Simulation time 13036339 ps
CPU time 1.97 seconds
Started Aug 28 07:19:47 PM UTC 24
Finished Aug 28 07:19:50 PM UTC 24
Peak memory 211248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282379489 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.1282379489
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/44.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.2360520114
Short name T791
Test name
Test status
Simulation time 666012465 ps
CPU time 15.38 seconds
Started Aug 28 07:19:46 PM UTC 24
Finished Aug 28 07:20:03 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360520114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2360520114
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/44.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random.2176772293
Short name T787
Test name
Test status
Simulation time 1396895326 ps
CPU time 15.77 seconds
Started Aug 28 07:19:42 PM UTC 24
Finished Aug 28 07:19:59 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176772293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.2176772293
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/44.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.2531803660
Short name T847
Test name
Test status
Simulation time 19325342094 ps
CPU time 77.12 seconds
Started Aug 28 07:19:44 PM UTC 24
Finished Aug 28 07:21:03 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531803660 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2531803660
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/44.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.841785391
Short name T884
Test name
Test status
Simulation time 20772163633 ps
CPU time 157.21 seconds
Started Aug 28 07:19:44 PM UTC 24
Finished Aug 28 07:22:25 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841785391 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.841785391
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/44.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.249118961
Short name T780
Test name
Test status
Simulation time 191738474 ps
CPU time 8.92 seconds
Started Aug 28 07:19:42 PM UTC 24
Finished Aug 28 07:19:52 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249118961 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.249118961
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/44.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.1887656729
Short name T790
Test name
Test status
Simulation time 1795135868 ps
CPU time 14.02 seconds
Started Aug 28 07:19:46 PM UTC 24
Finished Aug 28 07:20:01 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887656729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1887656729
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/44.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.2116947909
Short name T770
Test name
Test status
Simulation time 10777735 ps
CPU time 1.62 seconds
Started Aug 28 07:19:41 PM UTC 24
Finished Aug 28 07:19:43 PM UTC 24
Peak memory 211128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116947909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.2116947909
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/44.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.3828194225
Short name T786
Test name
Test status
Simulation time 2103087477 ps
CPU time 16.96 seconds
Started Aug 28 07:19:41 PM UTC 24
Finished Aug 28 07:19:59 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828194225 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.3828194225
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/44.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.1739877690
Short name T784
Test name
Test status
Simulation time 2200663000 ps
CPU time 14.92 seconds
Started Aug 28 07:19:42 PM UTC 24
Finished Aug 28 07:19:58 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739877690 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.1739877690
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/44.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.1102233365
Short name T772
Test name
Test status
Simulation time 8899543 ps
CPU time 1.7 seconds
Started Aug 28 07:19:41 PM UTC 24
Finished Aug 28 07:19:43 PM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102233365 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.1102233365
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/44.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.1956983886
Short name T822
Test name
Test status
Simulation time 699655626 ps
CPU time 39.13 seconds
Started Aug 28 07:19:50 PM UTC 24
Finished Aug 28 07:20:31 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956983886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1956983886
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/44.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.4076775460
Short name T747
Test name
Test status
Simulation time 1354930875 ps
CPU time 30.23 seconds
Started Aug 28 07:19:52 PM UTC 24
Finished Aug 28 07:20:23 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076775460 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.4076775460
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/44.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.2007009120
Short name T16
Test name
Test status
Simulation time 123194027 ps
CPU time 19.74 seconds
Started Aug 28 07:19:50 PM UTC 24
Finished Aug 28 07:20:11 PM UTC 24
Peak memory 214248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007009120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.2007009120
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/44.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2562908683
Short name T833
Test name
Test status
Simulation time 304303733 ps
CPU time 49.56 seconds
Started Aug 28 07:19:52 PM UTC 24
Finished Aug 28 07:20:43 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562908683 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.2562908683
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/44.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.2858554548
Short name T778
Test name
Test status
Simulation time 62126306 ps
CPU time 2.95 seconds
Started Aug 28 07:19:46 PM UTC 24
Finished Aug 28 07:19:50 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858554548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2858554548
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/44.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.843924896
Short name T806
Test name
Test status
Simulation time 708173253 ps
CPU time 17.31 seconds
Started Aug 28 07:20:01 PM UTC 24
Finished Aug 28 07:20:19 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843924896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.843924896
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/45.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.3482010718
Short name T886
Test name
Test status
Simulation time 40896649332 ps
CPU time 149.37 seconds
Started Aug 28 07:20:01 PM UTC 24
Finished Aug 28 07:22:33 PM UTC 24
Peak memory 214240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482010718 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.3482010718
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/45.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.1043652209
Short name T799
Test name
Test status
Simulation time 99037988 ps
CPU time 6.13 seconds
Started Aug 28 07:20:04 PM UTC 24
Finished Aug 28 07:20:11 PM UTC 24
Peak memory 212332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043652209 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.1043652209
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/45.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.840916676
Short name T797
Test name
Test status
Simulation time 429875798 ps
CPU time 6.8 seconds
Started Aug 28 07:20:02 PM UTC 24
Finished Aug 28 07:20:10 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840916676 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.840916676
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/45.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random.1953665235
Short name T792
Test name
Test status
Simulation time 53112098 ps
CPU time 4.17 seconds
Started Aug 28 07:19:58 PM UTC 24
Finished Aug 28 07:20:03 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953665235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.1953665235
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/45.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.2070099742
Short name T897
Test name
Test status
Simulation time 265727638363 ps
CPU time 273.1 seconds
Started Aug 28 07:19:59 PM UTC 24
Finished Aug 28 07:24:36 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070099742 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2070099742
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/45.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.1962533189
Short name T864
Test name
Test status
Simulation time 19088452867 ps
CPU time 79.15 seconds
Started Aug 28 07:20:01 PM UTC 24
Finished Aug 28 07:21:22 PM UTC 24
Peak memory 212168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962533189 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.1962533189
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/45.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.2273809476
Short name T794
Test name
Test status
Simulation time 40217022 ps
CPU time 6.87 seconds
Started Aug 28 07:19:58 PM UTC 24
Finished Aug 28 07:20:06 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273809476 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2273809476
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/45.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.1371497641
Short name T804
Test name
Test status
Simulation time 1050934849 ps
CPU time 13.35 seconds
Started Aug 28 07:20:02 PM UTC 24
Finished Aug 28 07:20:17 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371497641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1371497641
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/45.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.764106132
Short name T783
Test name
Test status
Simulation time 127176853 ps
CPU time 1.65 seconds
Started Aug 28 07:19:53 PM UTC 24
Finished Aug 28 07:19:56 PM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764106132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.764106132
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/45.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.1230094704
Short name T795
Test name
Test status
Simulation time 1677924727 ps
CPU time 11.39 seconds
Started Aug 28 07:19:54 PM UTC 24
Finished Aug 28 07:20:06 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230094704 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.1230094704
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/45.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.2915675187
Short name T801
Test name
Test status
Simulation time 1482768473 ps
CPU time 15.19 seconds
Started Aug 28 07:19:56 PM UTC 24
Finished Aug 28 07:20:12 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915675187 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.2915675187
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/45.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.3300725848
Short name T782
Test name
Test status
Simulation time 13887082 ps
CPU time 1.57 seconds
Started Aug 28 07:19:54 PM UTC 24
Finished Aug 28 07:19:56 PM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300725848 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.3300725848
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/45.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.2246673068
Short name T803
Test name
Test status
Simulation time 447663233 ps
CPU time 9.98 seconds
Started Aug 28 07:20:04 PM UTC 24
Finished Aug 28 07:20:15 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246673068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.2246673068
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/45.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.429807763
Short name T821
Test name
Test status
Simulation time 438828514 ps
CPU time 22.38 seconds
Started Aug 28 07:20:07 PM UTC 24
Finished Aug 28 07:20:31 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429807763 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.429807763
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/45.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.925971843
Short name T871
Test name
Test status
Simulation time 5794989316 ps
CPU time 92.06 seconds
Started Aug 28 07:20:05 PM UTC 24
Finished Aug 28 07:21:40 PM UTC 24
Peak memory 216296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925971843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.925971843
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/45.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3907022878
Short name T891
Test name
Test status
Simulation time 6452641184 ps
CPU time 195.23 seconds
Started Aug 28 07:20:07 PM UTC 24
Finished Aug 28 07:23:26 PM UTC 24
Peak memory 218344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907022878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.3907022878
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/45.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.3223579346
Short name T796
Test name
Test status
Simulation time 407464478 ps
CPU time 2.82 seconds
Started Aug 28 07:20:02 PM UTC 24
Finished Aug 28 07:20:06 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223579346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3223579346
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/45.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.2769291836
Short name T808
Test name
Test status
Simulation time 117578953 ps
CPU time 6.86 seconds
Started Aug 28 07:20:17 PM UTC 24
Finished Aug 28 07:20:25 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769291836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2769291836
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/46.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1312030455
Short name T290
Test name
Test status
Simulation time 42940915685 ps
CPU time 388.31 seconds
Started Aug 28 07:20:18 PM UTC 24
Finished Aug 28 07:26:52 PM UTC 24
Peak memory 214240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312030455 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.1312030455
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/46.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.434953939
Short name T824
Test name
Test status
Simulation time 1254182455 ps
CPU time 5.68 seconds
Started Aug 28 07:20:24 PM UTC 24
Finished Aug 28 07:20:31 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434953939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.434953939
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/46.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.2041275627
Short name T815
Test name
Test status
Simulation time 388978146 ps
CPU time 6.24 seconds
Started Aug 28 07:20:21 PM UTC 24
Finished Aug 28 07:20:28 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041275627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2041275627
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/46.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random.510241023
Short name T813
Test name
Test status
Simulation time 784808392 ps
CPU time 13.17 seconds
Started Aug 28 07:20:12 PM UTC 24
Finished Aug 28 07:20:27 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510241023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.510241023
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/46.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.356761691
Short name T889
Test name
Test status
Simulation time 44964225539 ps
CPU time 171.72 seconds
Started Aug 28 07:20:14 PM UTC 24
Finished Aug 28 07:23:10 PM UTC 24
Peak memory 212204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356761691 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.356761691
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/46.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.4094928519
Short name T895
Test name
Test status
Simulation time 178284554951 ps
CPU time 222.91 seconds
Started Aug 28 07:20:17 PM UTC 24
Finished Aug 28 07:24:04 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094928519 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.4094928519
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/46.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.583070465
Short name T805
Test name
Test status
Simulation time 14039648 ps
CPU time 2.58 seconds
Started Aug 28 07:20:14 PM UTC 24
Finished Aug 28 07:20:18 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583070465 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.583070465
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/46.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.1878277013
Short name T817
Test name
Test status
Simulation time 75045099 ps
CPU time 7.55 seconds
Started Aug 28 07:20:19 PM UTC 24
Finished Aug 28 07:20:28 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878277013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1878277013
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/46.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.1346267752
Short name T800
Test name
Test status
Simulation time 246768231 ps
CPU time 2.44 seconds
Started Aug 28 07:20:08 PM UTC 24
Finished Aug 28 07:20:12 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346267752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.1346267752
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/46.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.439708550
Short name T819
Test name
Test status
Simulation time 2616939080 ps
CPU time 16.87 seconds
Started Aug 28 07:20:12 PM UTC 24
Finished Aug 28 07:20:30 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439708550 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.439708550
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/46.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.2723165872
Short name T811
Test name
Test status
Simulation time 1605407392 ps
CPU time 12.72 seconds
Started Aug 28 07:20:12 PM UTC 24
Finished Aug 28 07:20:26 PM UTC 24
Peak memory 212228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723165872 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.2723165872
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/46.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.930881200
Short name T802
Test name
Test status
Simulation time 16978048 ps
CPU time 1.89 seconds
Started Aug 28 07:20:12 PM UTC 24
Finished Aug 28 07:20:15 PM UTC 24
Peak memory 211172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930881200 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.930881200
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/46.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.978209348
Short name T843
Test name
Test status
Simulation time 325613713 ps
CPU time 33 seconds
Started Aug 28 07:20:26 PM UTC 24
Finished Aug 28 07:21:00 PM UTC 24
Peak memory 214176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978209348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.978209348
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/46.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.3210000042
Short name T854
Test name
Test status
Simulation time 3324672330 ps
CPU time 42.18 seconds
Started Aug 28 07:20:28 PM UTC 24
Finished Aug 28 07:21:12 PM UTC 24
Peak memory 212456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210000042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.3210000042
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/46.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.2115928827
Short name T878
Test name
Test status
Simulation time 3466793714 ps
CPU time 89.71 seconds
Started Aug 28 07:20:28 PM UTC 24
Finished Aug 28 07:22:00 PM UTC 24
Peak memory 216296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115928827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.2115928827
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/46.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.545066267
Short name T892
Test name
Test status
Simulation time 5936940808 ps
CPU time 176.05 seconds
Started Aug 28 07:20:28 PM UTC 24
Finished Aug 28 07:23:27 PM UTC 24
Peak memory 216364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545066267 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.545066267
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/46.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.878898773
Short name T812
Test name
Test status
Simulation time 24308410 ps
CPU time 2.49 seconds
Started Aug 28 07:20:23 PM UTC 24
Finished Aug 28 07:20:27 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878898773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.878898773
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/46.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.774280202
Short name T829
Test name
Test status
Simulation time 806997412 ps
CPU time 4.37 seconds
Started Aug 28 07:20:33 PM UTC 24
Finished Aug 28 07:20:39 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774280202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.774280202
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/47.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.852152037
Short name T288
Test name
Test status
Simulation time 64051038537 ps
CPU time 89.45 seconds
Started Aug 28 07:20:33 PM UTC 24
Finished Aug 28 07:22:05 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852152037 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.852152037
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/47.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.692714863
Short name T830
Test name
Test status
Simulation time 20615073 ps
CPU time 2.47 seconds
Started Aug 28 07:20:36 PM UTC 24
Finished Aug 28 07:20:40 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692714863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.692714863
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/47.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.2565112368
Short name T826
Test name
Test status
Simulation time 77384971 ps
CPU time 3.31 seconds
Started Aug 28 07:20:33 PM UTC 24
Finished Aug 28 07:20:38 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565112368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.2565112368
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/47.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random.704507723
Short name T827
Test name
Test status
Simulation time 149371104 ps
CPU time 6.75 seconds
Started Aug 28 07:20:30 PM UTC 24
Finished Aug 28 07:20:38 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704507723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.704507723
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/47.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.1406280524
Short name T896
Test name
Test status
Simulation time 114777136451 ps
CPU time 235.77 seconds
Started Aug 28 07:20:33 PM UTC 24
Finished Aug 28 07:24:33 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406280524 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1406280524
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/47.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1358647176
Short name T129
Test name
Test status
Simulation time 33377801655 ps
CPU time 237.27 seconds
Started Aug 28 07:20:33 PM UTC 24
Finished Aug 28 07:24:34 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358647176 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1358647176
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/47.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.4169153022
Short name T825
Test name
Test status
Simulation time 27770889 ps
CPU time 4.02 seconds
Started Aug 28 07:20:30 PM UTC 24
Finished Aug 28 07:20:36 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169153022 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.4169153022
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/47.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.3276588145
Short name T831
Test name
Test status
Simulation time 204950605 ps
CPU time 8.3 seconds
Started Aug 28 07:20:33 PM UTC 24
Finished Aug 28 07:20:43 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276588145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.3276588145
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/47.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.2741507035
Short name T823
Test name
Test status
Simulation time 54456747 ps
CPU time 2.05 seconds
Started Aug 28 07:20:28 PM UTC 24
Finished Aug 28 07:20:31 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741507035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.2741507035
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/47.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.3383294441
Short name T832
Test name
Test status
Simulation time 1166543724 ps
CPU time 11.12 seconds
Started Aug 28 07:20:30 PM UTC 24
Finished Aug 28 07:20:43 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383294441 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.3383294441
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/47.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.1801518392
Short name T828
Test name
Test status
Simulation time 861361031 ps
CPU time 6.99 seconds
Started Aug 28 07:20:30 PM UTC 24
Finished Aug 28 07:20:39 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801518392 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1801518392
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/47.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1214576672
Short name T818
Test name
Test status
Simulation time 8029871 ps
CPU time 1.27 seconds
Started Aug 28 07:20:28 PM UTC 24
Finished Aug 28 07:20:30 PM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214576672 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.1214576672
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/47.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.2270159816
Short name T126
Test name
Test status
Simulation time 14044308201 ps
CPU time 162.66 seconds
Started Aug 28 07:20:38 PM UTC 24
Finished Aug 28 07:23:24 PM UTC 24
Peak memory 216480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270159816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2270159816
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/47.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.4258247508
Short name T866
Test name
Test status
Simulation time 7279236220 ps
CPU time 43.34 seconds
Started Aug 28 07:20:39 PM UTC 24
Finished Aug 28 07:21:24 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258247508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.4258247508
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/47.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2801696760
Short name T880
Test name
Test status
Simulation time 496328096 ps
CPU time 82.4 seconds
Started Aug 28 07:20:39 PM UTC 24
Finished Aug 28 07:22:04 PM UTC 24
Peak memory 214380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801696760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.2801696760
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/47.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.1612128418
Short name T848
Test name
Test status
Simulation time 36591381 ps
CPU time 22.59 seconds
Started Aug 28 07:20:41 PM UTC 24
Finished Aug 28 07:21:05 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612128418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.1612128418
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/47.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.2315152346
Short name T835
Test name
Test status
Simulation time 232989243 ps
CPU time 9.6 seconds
Started Aug 28 07:20:33 PM UTC 24
Finished Aug 28 07:20:44 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315152346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2315152346
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/47.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.2893892356
Short name T840
Test name
Test status
Simulation time 122501595 ps
CPU time 2.28 seconds
Started Aug 28 07:20:48 PM UTC 24
Finished Aug 28 07:20:51 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893892356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.2893892356
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/48.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.548078811
Short name T201
Test name
Test status
Simulation time 8152470154 ps
CPU time 55.87 seconds
Started Aug 28 07:20:50 PM UTC 24
Finished Aug 28 07:21:48 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548078811 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.548078811
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/48.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.4241545241
Short name T859
Test name
Test status
Simulation time 1583492284 ps
CPU time 15.29 seconds
Started Aug 28 07:20:59 PM UTC 24
Finished Aug 28 07:21:16 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241545241 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.4241545241
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/48.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.2898874227
Short name T853
Test name
Test status
Simulation time 903874737 ps
CPU time 17.07 seconds
Started Aug 28 07:20:53 PM UTC 24
Finished Aug 28 07:21:11 PM UTC 24
Peak memory 212096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898874227 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2898874227
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/48.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random.298928036
Short name T837
Test name
Test status
Simulation time 20524769 ps
CPU time 2.09 seconds
Started Aug 28 07:20:44 PM UTC 24
Finished Aug 28 07:20:47 PM UTC 24
Peak memory 212380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298928036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.298928036
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/48.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.2640048834
Short name T255
Test name
Test status
Simulation time 7835483158 ps
CPU time 51.16 seconds
Started Aug 28 07:20:46 PM UTC 24
Finished Aug 28 07:21:39 PM UTC 24
Peak memory 212260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640048834 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2640048834
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/48.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.2775459924
Short name T888
Test name
Test status
Simulation time 13805940035 ps
CPU time 136.56 seconds
Started Aug 28 07:20:46 PM UTC 24
Finished Aug 28 07:23:05 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775459924 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.2775459924
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/48.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.1093205398
Short name T838
Test name
Test status
Simulation time 73236167 ps
CPU time 3.72 seconds
Started Aug 28 07:20:44 PM UTC 24
Finished Aug 28 07:20:49 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093205398 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.1093205398
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/48.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.587952919
Short name T852
Test name
Test status
Simulation time 962085418 ps
CPU time 16.49 seconds
Started Aug 28 07:20:53 PM UTC 24
Finished Aug 28 07:21:10 PM UTC 24
Peak memory 211984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587952919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.587952919
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/48.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.2819479342
Short name T836
Test name
Test status
Simulation time 91389589 ps
CPU time 2.1 seconds
Started Aug 28 07:20:41 PM UTC 24
Finished Aug 28 07:20:44 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819479342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.2819479342
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/48.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1160034395
Short name T844
Test name
Test status
Simulation time 2322350007 ps
CPU time 15.25 seconds
Started Aug 28 07:20:44 PM UTC 24
Finished Aug 28 07:21:01 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160034395 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.1160034395
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/48.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.16500796
Short name T846
Test name
Test status
Simulation time 6874454957 ps
CPU time 16.86 seconds
Started Aug 28 07:20:44 PM UTC 24
Finished Aug 28 07:21:02 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16500796 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.16500796
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/48.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.295613194
Short name T834
Test name
Test status
Simulation time 7930700 ps
CPU time 1.54 seconds
Started Aug 28 07:20:41 PM UTC 24
Finished Aug 28 07:20:44 PM UTC 24
Peak memory 211128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295613194 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.295613194
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/48.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.2162250926
Short name T856
Test name
Test status
Simulation time 502435209 ps
CPU time 10.75 seconds
Started Aug 28 07:21:01 PM UTC 24
Finished Aug 28 07:21:13 PM UTC 24
Peak memory 214116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162250926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.2162250926
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/48.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1038404693
Short name T870
Test name
Test status
Simulation time 902203673 ps
CPU time 33.01 seconds
Started Aug 28 07:21:01 PM UTC 24
Finished Aug 28 07:21:36 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038404693 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.1038404693
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/48.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3989819353
Short name T879
Test name
Test status
Simulation time 488690911 ps
CPU time 58.9 seconds
Started Aug 28 07:21:01 PM UTC 24
Finished Aug 28 07:22:02 PM UTC 24
Peak memory 216012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989819353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.3989819353
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/48.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.2378476037
Short name T890
Test name
Test status
Simulation time 1032097750 ps
CPU time 132.09 seconds
Started Aug 28 07:21:03 PM UTC 24
Finished Aug 28 07:23:18 PM UTC 24
Peak memory 218280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378476037 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.2378476037
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/48.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.2650798776
Short name T850
Test name
Test status
Simulation time 132982305 ps
CPU time 8.07 seconds
Started Aug 28 07:20:57 PM UTC 24
Finished Aug 28 07:21:06 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650798776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2650798776
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/48.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.912229961
Short name T863
Test name
Test status
Simulation time 597895231 ps
CPU time 10.59 seconds
Started Aug 28 07:21:09 PM UTC 24
Finished Aug 28 07:21:21 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912229961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.912229961
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/49.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3289503514
Short name T898
Test name
Test status
Simulation time 48549347789 ps
CPU time 304.22 seconds
Started Aug 28 07:21:12 PM UTC 24
Finished Aug 28 07:26:21 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289503514 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.3289503514
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/49.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.3857190189
Short name T865
Test name
Test status
Simulation time 364859873 ps
CPU time 8.5 seconds
Started Aug 28 07:21:14 PM UTC 24
Finished Aug 28 07:21:23 PM UTC 24
Peak memory 212140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857190189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.3857190189
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/49.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.3698206640
Short name T869
Test name
Test status
Simulation time 744199266 ps
CPU time 14.99 seconds
Started Aug 28 07:21:14 PM UTC 24
Finished Aug 28 07:21:30 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698206640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3698206640
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/49.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random.3540680068
Short name T855
Test name
Test status
Simulation time 27947440 ps
CPU time 3.93 seconds
Started Aug 28 07:21:08 PM UTC 24
Finished Aug 28 07:21:13 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540680068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.3540680068
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/49.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.3550076691
Short name T894
Test name
Test status
Simulation time 27713098064 ps
CPU time 158.27 seconds
Started Aug 28 07:21:08 PM UTC 24
Finished Aug 28 07:23:49 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550076691 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.3550076691
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/49.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3800458680
Short name T882
Test name
Test status
Simulation time 12027516852 ps
CPU time 65.18 seconds
Started Aug 28 07:21:09 PM UTC 24
Finished Aug 28 07:22:16 PM UTC 24
Peak memory 212448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800458680 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3800458680
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/49.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.1446825554
Short name T857
Test name
Test status
Simulation time 32307488 ps
CPU time 4.45 seconds
Started Aug 28 07:21:08 PM UTC 24
Finished Aug 28 07:21:13 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446825554 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.1446825554
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/49.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.2624525417
Short name T858
Test name
Test status
Simulation time 16862665 ps
CPU time 2.06 seconds
Started Aug 28 07:21:12 PM UTC 24
Finished Aug 28 07:21:15 PM UTC 24
Peak memory 212448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624525417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2624525417
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/49.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.1191473659
Short name T849
Test name
Test status
Simulation time 44349663 ps
CPU time 2.1 seconds
Started Aug 28 07:21:03 PM UTC 24
Finished Aug 28 07:21:06 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191473659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1191473659
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/49.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3712368
Short name T867
Test name
Test status
Simulation time 3036120157 ps
CPU time 18.32 seconds
Started Aug 28 07:21:06 PM UTC 24
Finished Aug 28 07:21:26 PM UTC 24
Peak memory 212204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712368 -assert nopostproc +UVM_TESTNAME=xbar_base_t
est +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3712368
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/49.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1702324083
Short name T860
Test name
Test status
Simulation time 1887119960 ps
CPU time 11.16 seconds
Started Aug 28 07:21:06 PM UTC 24
Finished Aug 28 07:21:18 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702324083 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.1702324083
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/49.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.3156253743
Short name T851
Test name
Test status
Simulation time 12468424 ps
CPU time 1.52 seconds
Started Aug 28 07:21:04 PM UTC 24
Finished Aug 28 07:21:07 PM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156253743 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.3156253743
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/49.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.1294733291
Short name T127
Test name
Test status
Simulation time 54300960647 ps
CPU time 128.41 seconds
Started Aug 28 07:21:15 PM UTC 24
Finished Aug 28 07:23:26 PM UTC 24
Peak memory 214236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294733291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1294733291
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/49.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.1497010466
Short name T877
Test name
Test status
Simulation time 705003031 ps
CPU time 40.52 seconds
Started Aug 28 07:21:17 PM UTC 24
Finished Aug 28 07:21:59 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497010466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.1497010466
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/49.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1683284055
Short name T893
Test name
Test status
Simulation time 467001635 ps
CPU time 143.17 seconds
Started Aug 28 07:21:17 PM UTC 24
Finished Aug 28 07:23:43 PM UTC 24
Peak memory 216424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683284055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.1683284055
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/49.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.1281460475
Short name T874
Test name
Test status
Simulation time 440472490 ps
CPU time 30.2 seconds
Started Aug 28 07:21:19 PM UTC 24
Finished Aug 28 07:21:51 PM UTC 24
Peak memory 214376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281460475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.1281460475
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/49.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.1467850710
Short name T868
Test name
Test status
Simulation time 2562103520 ps
CPU time 12.84 seconds
Started Aug 28 07:21:14 PM UTC 24
Finished Aug 28 07:21:28 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467850710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.1467850710
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/49.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device.2846356528
Short name T196
Test name
Test status
Simulation time 88888714 ps
CPU time 11.9 seconds
Started Aug 28 07:08:12 PM UTC 24
Finished Aug 28 07:08:25 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846356528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.2846356528
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/5.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.2853702851
Short name T265
Test name
Test status
Simulation time 46885158339 ps
CPU time 439.8 seconds
Started Aug 28 07:08:13 PM UTC 24
Finished Aug 28 07:15:39 PM UTC 24
Peak memory 214248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853702851 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.2853702851
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/5.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.757814621
Short name T330
Test name
Test status
Simulation time 44304284 ps
CPU time 4.01 seconds
Started Aug 28 07:08:16 PM UTC 24
Finished Aug 28 07:08:21 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757814621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.757814621
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/5.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_error_random.3336387583
Short name T146
Test name
Test status
Simulation time 2635691352 ps
CPU time 13.73 seconds
Started Aug 28 07:08:15 PM UTC 24
Finished Aug 28 07:08:30 PM UTC 24
Peak memory 212452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336387583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.3336387583
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/5.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random.2424230512
Short name T67
Test name
Test status
Simulation time 895704712 ps
CPU time 9.1 seconds
Started Aug 28 07:08:08 PM UTC 24
Finished Aug 28 07:08:18 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424230512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.2424230512
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/5.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_large_delays.3403170016
Short name T225
Test name
Test status
Simulation time 42544801274 ps
CPU time 140.35 seconds
Started Aug 28 07:08:11 PM UTC 24
Finished Aug 28 07:10:34 PM UTC 24
Peak memory 212396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403170016 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3403170016
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/5.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_slow_rsp.1822919299
Short name T190
Test name
Test status
Simulation time 27189353909 ps
CPU time 82.93 seconds
Started Aug 28 07:08:12 PM UTC 24
Finished Aug 28 07:09:37 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822919299 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.1822919299
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/5.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_zero_delays.4143695494
Short name T325
Test name
Test status
Simulation time 9619982 ps
CPU time 1.59 seconds
Started Aug 28 07:08:09 PM UTC 24
Finished Aug 28 07:08:11 PM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143695494 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.4143695494
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/5.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_same_source.1731897372
Short name T329
Test name
Test status
Simulation time 438824701 ps
CPU time 6.07 seconds
Started Aug 28 07:08:14 PM UTC 24
Finished Aug 28 07:08:21 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731897372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.1731897372
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/5.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke.4092447449
Short name T92
Test name
Test status
Simulation time 9885867 ps
CPU time 1.93 seconds
Started Aug 28 07:08:03 PM UTC 24
Finished Aug 28 07:08:06 PM UTC 24
Peak memory 211088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092447449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.4092447449
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/5.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_large_delays.4171223231
Short name T327
Test name
Test status
Simulation time 1941028970 ps
CPU time 11.74 seconds
Started Aug 28 07:08:04 PM UTC 24
Finished Aug 28 07:08:17 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171223231 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.4171223231
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/5.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.1976953775
Short name T296
Test name
Test status
Simulation time 1079041449 ps
CPU time 11.13 seconds
Started Aug 28 07:08:08 PM UTC 24
Finished Aug 28 07:08:20 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976953775 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1976953775
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/5.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.196418871
Short name T151
Test name
Test status
Simulation time 14244642 ps
CPU time 1.86 seconds
Started Aug 28 07:08:04 PM UTC 24
Finished Aug 28 07:08:07 PM UTC 24
Peak memory 211076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196418871 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.196418871
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/5.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all.2535081071
Short name T197
Test name
Test status
Simulation time 37750261 ps
CPU time 5.69 seconds
Started Aug 28 07:08:18 PM UTC 24
Finished Aug 28 07:08:25 PM UTC 24
Peak memory 211784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535081071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.2535081071
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/5.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_error.1842065682
Short name T335
Test name
Test status
Simulation time 1092466845 ps
CPU time 27.73 seconds
Started Aug 28 07:08:20 PM UTC 24
Finished Aug 28 07:08:50 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842065682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.1842065682
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/5.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.460645609
Short name T82
Test name
Test status
Simulation time 2286387478 ps
CPU time 64.95 seconds
Started Aug 28 07:08:18 PM UTC 24
Finished Aug 28 07:09:25 PM UTC 24
Peak memory 216292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460645609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.460645609
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/5.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.3200876009
Short name T316
Test name
Test status
Simulation time 283806363 ps
CPU time 49.9 seconds
Started Aug 28 07:08:21 PM UTC 24
Finished Aug 28 07:09:12 PM UTC 24
Peak memory 214376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200876009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.3200876009
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/5.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_unmapped_addr.2960921824
Short name T2
Test name
Test status
Simulation time 259870675 ps
CPU time 7.42 seconds
Started Aug 28 07:08:16 PM UTC 24
Finished Aug 28 07:08:25 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960921824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.2960921824
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/5.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device.507979776
Short name T144
Test name
Test status
Simulation time 11546380 ps
CPU time 2.67 seconds
Started Aug 28 07:08:26 PM UTC 24
Finished Aug 28 07:08:30 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507979776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.507979776
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/6.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.576493590
Short name T106
Test name
Test status
Simulation time 121442829650 ps
CPU time 405.17 seconds
Started Aug 28 07:08:27 PM UTC 24
Finished Aug 28 07:15:18 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576493590 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.576493590
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/6.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.2683514732
Short name T332
Test name
Test status
Simulation time 535425692 ps
CPU time 8.44 seconds
Started Aug 28 07:08:31 PM UTC 24
Finished Aug 28 07:08:40 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683514732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.2683514732
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/6.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_error_random.2146739932
Short name T147
Test name
Test status
Simulation time 9279223 ps
CPU time 1.7 seconds
Started Aug 28 07:08:28 PM UTC 24
Finished Aug 28 07:08:31 PM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146739932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2146739932
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/6.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random.1106762389
Short name T199
Test name
Test status
Simulation time 92493046 ps
CPU time 2.43 seconds
Started Aug 28 07:08:24 PM UTC 24
Finished Aug 28 07:08:27 PM UTC 24
Peak memory 212316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106762389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.1106762389
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/6.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_large_delays.2785690094
Short name T394
Test name
Test status
Simulation time 42416601411 ps
CPU time 166.51 seconds
Started Aug 28 07:08:26 PM UTC 24
Finished Aug 28 07:11:15 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785690094 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2785690094
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/6.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_slow_rsp.2814637706
Short name T292
Test name
Test status
Simulation time 11877387444 ps
CPU time 148.21 seconds
Started Aug 28 07:08:26 PM UTC 24
Finished Aug 28 07:10:57 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814637706 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2814637706
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/6.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_zero_delays.3136345148
Short name T200
Test name
Test status
Simulation time 11691049 ps
CPU time 1.96 seconds
Started Aug 28 07:08:25 PM UTC 24
Finished Aug 28 07:08:28 PM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136345148 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.3136345148
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/6.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_same_source.2283252307
Short name T334
Test name
Test status
Simulation time 1107854808 ps
CPU time 14.28 seconds
Started Aug 28 07:08:28 PM UTC 24
Finished Aug 28 07:08:44 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283252307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2283252307
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/6.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke.2911657291
Short name T195
Test name
Test status
Simulation time 27434392 ps
CPU time 1.5 seconds
Started Aug 28 07:08:21 PM UTC 24
Finished Aug 28 07:08:23 PM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911657291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2911657291
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/6.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_large_delays.950501578
Short name T148
Test name
Test status
Simulation time 2394873468 ps
CPU time 10.41 seconds
Started Aug 28 07:08:22 PM UTC 24
Finished Aug 28 07:08:33 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950501578 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.950501578
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/6.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.3735738819
Short name T78
Test name
Test status
Simulation time 3806122456 ps
CPU time 13.26 seconds
Started Aug 28 07:08:23 PM UTC 24
Finished Aug 28 07:08:37 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735738819 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3735738819
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/6.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.1863355007
Short name T17
Test name
Test status
Simulation time 9925913 ps
CPU time 1.74 seconds
Started Aug 28 07:08:22 PM UTC 24
Finished Aug 28 07:08:24 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863355007 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.1863355007
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/6.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all.1294484771
Short name T83
Test name
Test status
Simulation time 2974959973 ps
CPU time 61.29 seconds
Started Aug 28 07:08:31 PM UTC 24
Finished Aug 28 07:09:34 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294484771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1294484771
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/6.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_error.3040201393
Short name T298
Test name
Test status
Simulation time 2763861497 ps
CPU time 25.72 seconds
Started Aug 28 07:08:32 PM UTC 24
Finished Aug 28 07:08:59 PM UTC 24
Peak memory 212456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040201393 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3040201393
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/6.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.2142652246
Short name T80
Test name
Test status
Simulation time 274189394 ps
CPU time 34.31 seconds
Started Aug 28 07:08:31 PM UTC 24
Finished Aug 28 07:09:07 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142652246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.2142652246
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/6.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1375087227
Short name T262
Test name
Test status
Simulation time 3205086994 ps
CPU time 34.04 seconds
Started Aug 28 07:08:32 PM UTC 24
Finished Aug 28 07:09:07 PM UTC 24
Peak memory 214440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375087227 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.1375087227
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/6.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_unmapped_addr.3731939125
Short name T76
Test name
Test status
Simulation time 279042046 ps
CPU time 5.59 seconds
Started Aug 28 07:08:30 PM UTC 24
Finished Aug 28 07:08:36 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731939125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3731939125
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/6.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device.1134922938
Short name T340
Test name
Test status
Simulation time 75734747 ps
CPU time 12.74 seconds
Started Aug 28 07:08:44 PM UTC 24
Finished Aug 28 07:08:58 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134922938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.1134922938
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/7.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.4261261712
Short name T341
Test name
Test status
Simulation time 93494166 ps
CPU time 7.01 seconds
Started Aug 28 07:08:53 PM UTC 24
Finished Aug 28 07:09:01 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261261712 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.4261261712
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/7.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_error_random.904529056
Short name T346
Test name
Test status
Simulation time 1468544833 ps
CPU time 16.05 seconds
Started Aug 28 07:08:51 PM UTC 24
Finished Aug 28 07:09:09 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904529056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.904529056
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/7.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random.710139635
Short name T333
Test name
Test status
Simulation time 18866049 ps
CPU time 3.36 seconds
Started Aug 28 07:08:38 PM UTC 24
Finished Aug 28 07:08:43 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710139635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.710139635
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/7.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_large_delays.2169590615
Short name T227
Test name
Test status
Simulation time 36994120576 ps
CPU time 115 seconds
Started Aug 28 07:08:41 PM UTC 24
Finished Aug 28 07:10:39 PM UTC 24
Peak memory 212396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169590615 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2169590615
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/7.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_slow_rsp.3068705044
Short name T362
Test name
Test status
Simulation time 8673396656 ps
CPU time 65.34 seconds
Started Aug 28 07:08:44 PM UTC 24
Finished Aug 28 07:09:51 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068705044 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.3068705044
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/7.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_zero_delays.705993694
Short name T337
Test name
Test status
Simulation time 94329557 ps
CPU time 10.38 seconds
Started Aug 28 07:08:40 PM UTC 24
Finished Aug 28 07:08:52 PM UTC 24
Peak memory 212112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705993694 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.705993694
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/7.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_same_source.4052032777
Short name T339
Test name
Test status
Simulation time 107979714 ps
CPU time 3.49 seconds
Started Aug 28 07:08:51 PM UTC 24
Finished Aug 28 07:08:56 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052032777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.4052032777
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/7.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke.2219431369
Short name T79
Test name
Test status
Simulation time 409566700 ps
CPU time 2.55 seconds
Started Aug 28 07:08:34 PM UTC 24
Finished Aug 28 07:08:38 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219431369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.2219431369
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/7.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_large_delays.2909003410
Short name T336
Test name
Test status
Simulation time 6632360263 ps
CPU time 12.02 seconds
Started Aug 28 07:08:37 PM UTC 24
Finished Aug 28 07:08:50 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909003410 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2909003410
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/7.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.776305830
Short name T344
Test name
Test status
Simulation time 2508002947 ps
CPU time 24.81 seconds
Started Aug 28 07:08:38 PM UTC 24
Finished Aug 28 07:09:04 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776305830 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.776305830
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/7.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.4280630674
Short name T331
Test name
Test status
Simulation time 8900464 ps
CPU time 1.88 seconds
Started Aug 28 07:08:37 PM UTC 24
Finished Aug 28 07:08:40 PM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280630674 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.4280630674
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/7.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all.2150402228
Short name T365
Test name
Test status
Simulation time 484147236 ps
CPU time 62.08 seconds
Started Aug 28 07:08:54 PM UTC 24
Finished Aug 28 07:09:58 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150402228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2150402228
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/7.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_error.4292848584
Short name T223
Test name
Test status
Simulation time 16413779577 ps
CPU time 94.79 seconds
Started Aug 28 07:08:56 PM UTC 24
Finished Aug 28 07:10:33 PM UTC 24
Peak memory 214248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292848584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.4292848584
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/7.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.3740262527
Short name T318
Test name
Test status
Simulation time 1093092636 ps
CPU time 188.93 seconds
Started Aug 28 07:08:54 PM UTC 24
Finished Aug 28 07:12:07 PM UTC 24
Peak memory 216424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740262527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.3740262527
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/7.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.2481304095
Short name T319
Test name
Test status
Simulation time 2096079386 ps
CPU time 121.71 seconds
Started Aug 28 07:08:58 PM UTC 24
Finished Aug 28 07:11:03 PM UTC 24
Peak memory 218472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481304095 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.2481304095
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/7.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_unmapped_addr.1440467961
Short name T342
Test name
Test status
Simulation time 76566160 ps
CPU time 8.22 seconds
Started Aug 28 07:08:53 PM UTC 24
Finished Aug 28 07:09:02 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440467961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1440467961
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/7.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device.3765163468
Short name T348
Test name
Test status
Simulation time 22508884 ps
CPU time 2.59 seconds
Started Aug 28 07:09:07 PM UTC 24
Finished Aug 28 07:09:11 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765163468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.3765163468
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/8.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.1918465756
Short name T168
Test name
Test status
Simulation time 10043108101 ps
CPU time 92.98 seconds
Started Aug 28 07:09:08 PM UTC 24
Finished Aug 28 07:10:44 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918465756 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.1918465756
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/8.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.1593269850
Short name T356
Test name
Test status
Simulation time 1095888109 ps
CPU time 12.93 seconds
Started Aug 28 07:09:12 PM UTC 24
Finished Aug 28 07:09:26 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593269850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.1593269850
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/8.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_error_random.936478462
Short name T352
Test name
Test status
Simulation time 839747302 ps
CPU time 8.99 seconds
Started Aug 28 07:09:12 PM UTC 24
Finished Aug 28 07:09:22 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936478462 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.936478462
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/8.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random.3279174494
Short name T354
Test name
Test status
Simulation time 1146038731 ps
CPU time 16.88 seconds
Started Aug 28 07:09:04 PM UTC 24
Finished Aug 28 07:09:22 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279174494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.3279174494
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/8.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_large_delays.2680606669
Short name T248
Test name
Test status
Simulation time 12185867936 ps
CPU time 27.7 seconds
Started Aug 28 07:09:06 PM UTC 24
Finished Aug 28 07:09:35 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680606669 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2680606669
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/8.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_slow_rsp.1644873005
Short name T95
Test name
Test status
Simulation time 25649437010 ps
CPU time 177.7 seconds
Started Aug 28 07:09:07 PM UTC 24
Finished Aug 28 07:12:08 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644873005 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1644873005
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/8.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_zero_delays.416126133
Short name T349
Test name
Test status
Simulation time 65681000 ps
CPU time 7.77 seconds
Started Aug 28 07:09:05 PM UTC 24
Finished Aug 28 07:09:14 PM UTC 24
Peak memory 212312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416126133 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.416126133
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/8.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_same_source.721401783
Short name T351
Test name
Test status
Simulation time 321973784 ps
CPU time 7.32 seconds
Started Aug 28 07:09:10 PM UTC 24
Finished Aug 28 07:09:18 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721401783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.721401783
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/8.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke.3659947803
Short name T343
Test name
Test status
Simulation time 174030554 ps
CPU time 2.13 seconds
Started Aug 28 07:09:00 PM UTC 24
Finished Aug 28 07:09:03 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659947803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3659947803
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/8.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_large_delays.346688538
Short name T350
Test name
Test status
Simulation time 2268418999 ps
CPU time 11.26 seconds
Started Aug 28 07:09:02 PM UTC 24
Finished Aug 28 07:09:14 PM UTC 24
Peak memory 212396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346688538 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.346688538
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/8.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.3038690417
Short name T268
Test name
Test status
Simulation time 1441666907 ps
CPU time 16.38 seconds
Started Aug 28 07:09:03 PM UTC 24
Finished Aug 28 07:09:21 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038690417 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3038690417
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/8.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.2190887159
Short name T345
Test name
Test status
Simulation time 12118186 ps
CPU time 1.78 seconds
Started Aug 28 07:09:02 PM UTC 24
Finished Aug 28 07:09:05 PM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190887159 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.2190887159
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/8.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all.4291919397
Short name T253
Test name
Test status
Simulation time 1469135257 ps
CPU time 32.02 seconds
Started Aug 28 07:09:13 PM UTC 24
Finished Aug 28 07:09:47 PM UTC 24
Peak memory 214176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291919397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.4291919397
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/8.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_error.2624812406
Short name T270
Test name
Test status
Simulation time 13216173935 ps
CPU time 100.59 seconds
Started Aug 28 07:09:15 PM UTC 24
Finished Aug 28 07:10:58 PM UTC 24
Peak memory 214248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624812406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.2624812406
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/8.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.3152804515
Short name T216
Test name
Test status
Simulation time 1248982289 ps
CPU time 56.52 seconds
Started Aug 28 07:09:15 PM UTC 24
Finished Aug 28 07:10:13 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152804515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.3152804515
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/8.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.524080269
Short name T293
Test name
Test status
Simulation time 1939726086 ps
CPU time 111.27 seconds
Started Aug 28 07:09:17 PM UTC 24
Finished Aug 28 07:11:11 PM UTC 24
Peak memory 214188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524080269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.524080269
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/8.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_unmapped_addr.1807758399
Short name T81
Test name
Test status
Simulation time 2472858183 ps
CPU time 10.18 seconds
Started Aug 28 07:09:12 PM UTC 24
Finished Aug 28 07:09:23 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807758399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1807758399
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/8.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device.636027940
Short name T358
Test name
Test status
Simulation time 18262744 ps
CPU time 3.94 seconds
Started Aug 28 07:09:26 PM UTC 24
Finished Aug 28 07:09:31 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636027940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.636027940
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/9.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.1341915003
Short name T118
Test name
Test status
Simulation time 46944291102 ps
CPU time 490.36 seconds
Started Aug 28 07:09:27 PM UTC 24
Finished Aug 28 07:17:44 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341915003 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.1341915003
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/9.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1305857825
Short name T249
Test name
Test status
Simulation time 44623501 ps
CPU time 4.8 seconds
Started Aug 28 07:09:32 PM UTC 24
Finished Aug 28 07:09:38 PM UTC 24
Peak memory 212116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305857825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.1305857825
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/9.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_error_random.2181940708
Short name T360
Test name
Test status
Simulation time 980024852 ps
CPU time 15.13 seconds
Started Aug 28 07:09:31 PM UTC 24
Finished Aug 28 07:09:48 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181940708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2181940708
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/9.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random.716897882
Short name T357
Test name
Test status
Simulation time 37989952 ps
CPU time 6.19 seconds
Started Aug 28 07:09:23 PM UTC 24
Finished Aug 28 07:09:30 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716897882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.716897882
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/9.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_large_delays.898590317
Short name T363
Test name
Test status
Simulation time 9222320472 ps
CPU time 29.15 seconds
Started Aug 28 07:09:24 PM UTC 24
Finished Aug 28 07:09:54 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898590317 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.898590317
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/9.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_slow_rsp.4013031636
Short name T415
Test name
Test status
Simulation time 36455409966 ps
CPU time 151.96 seconds
Started Aug 28 07:09:25 PM UTC 24
Finished Aug 28 07:12:00 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013031636 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.4013031636
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/9.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_zero_delays.3361277685
Short name T359
Test name
Test status
Simulation time 42894177 ps
CPU time 7.02 seconds
Started Aug 28 07:09:24 PM UTC 24
Finished Aug 28 07:09:32 PM UTC 24
Peak memory 211828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361277685 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.3361277685
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/9.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_same_source.442519365
Short name T250
Test name
Test status
Simulation time 557897904 ps
CPU time 12.29 seconds
Started Aug 28 07:09:27 PM UTC 24
Finished Aug 28 07:09:41 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442519365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.442519365
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/9.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke.178580789
Short name T353
Test name
Test status
Simulation time 9051667 ps
CPU time 1.85 seconds
Started Aug 28 07:09:19 PM UTC 24
Finished Aug 28 07:09:22 PM UTC 24
Peak memory 211120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178580789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.178580789
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/9.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_large_delays.3692768662
Short name T251
Test name
Test status
Simulation time 3584208780 ps
CPU time 21.47 seconds
Started Aug 28 07:09:21 PM UTC 24
Finished Aug 28 07:09:44 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692768662 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3692768662
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/9.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.4123685441
Short name T35
Test name
Test status
Simulation time 1269342383 ps
CPU time 8.27 seconds
Started Aug 28 07:09:22 PM UTC 24
Finished Aug 28 07:09:32 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123685441 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.4123685441
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/9.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.1603486698
Short name T355
Test name
Test status
Simulation time 15325292 ps
CPU time 1.64 seconds
Started Aug 28 07:09:21 PM UTC 24
Finished Aug 28 07:09:24 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603486698 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.1603486698
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/9.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all.2719860350
Short name T364
Test name
Test status
Simulation time 6036945261 ps
CPU time 19.75 seconds
Started Aug 28 07:09:33 PM UTC 24
Finished Aug 28 07:09:54 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719860350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2719860350
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/9.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_error.1822305945
Short name T269
Test name
Test status
Simulation time 24974412208 ps
CPU time 72.2 seconds
Started Aug 28 07:09:36 PM UTC 24
Finished Aug 28 07:10:51 PM UTC 24
Peak memory 214440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822305945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.1822305945
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/9.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.277578866
Short name T93
Test name
Test status
Simulation time 317454620 ps
CPU time 53.09 seconds
Started Aug 28 07:09:34 PM UTC 24
Finished Aug 28 07:10:29 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277578866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.277578866
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/9.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.1433084132
Short name T204
Test name
Test status
Simulation time 2209143372 ps
CPU time 117.34 seconds
Started Aug 28 07:09:38 PM UTC 24
Finished Aug 28 07:11:38 PM UTC 24
Peak memory 216296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433084132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.1433084132
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/9.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_unmapped_addr.830073420
Short name T84
Test name
Test status
Simulation time 1125049395 ps
CPU time 10.52 seconds
Started Aug 28 07:09:32 PM UTC 24
Finished Aug 28 07:09:44 PM UTC 24
Peak memory 212084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830073420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.830073420
Directory /workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/9.xbar_unmapped_addr/latest
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