Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	439	1			T44	5		T327	4		T328	1
all_values[1]	458	1			T51	1		T53	1		T327	1
all_values[2]	398	1			T18	1		T41	1		T53	1
all_values[3]	443	1			T327	1		T77	1		T329	2
all_values[4]	451	1			T329	2		T318	2		T330	1
all_values[5]	447	1			T18	1		T189	1		T327	1
all_values[6]	402	1			T44	1		T51	1		T53	1
all_values[7]	454	1			T41	2		T327	2		T74	2
all_values[8]	420	1			T189	1		T41	2		T44	1
all_values[9]	439	1			T51	1		T53	2		T327	1
all_values[10]	435	1			T4	1		T41	1		T44	1
all_values[11]	413	1			T18	1		T41	1		T53	1
all_values[12]	433	1			T189	1		T41	1		T44	1
all_values[13]	414	1			T41	1		T44	1		T53	1
all_values[14]	436	1			T41	1		T44	2		T327	3
all_values[15]	404	1			T18	2		T189	2		T41	1
all_values[16]	438	1			T44	1		T51	1		T53	1
all_values[17]	445	1			T41	1		T53	1		T327	2
all_values[18]	416	1			T18	3		T189	1		T53	2
all_values[19]	381	1			T44	1		T51	1		T327	1
all_values[20]	468	1			T41	1		T51	1		T53	3
all_values[21]	456	1			T41	1		T327	1		T329	2
all_values[22]	419	1			T189	1		T44	1		T329	4
all_values[23]	427	1			T18	1		T189	1		T53	1
all_values[24]	432	1			T4	1		T189	2		T327	1
all_values[25]	425	1			T41	1		T51	1		T53	1
all_values[26]	426	1			T327	3		T74	1		T328	3