| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.30 | 100.00 | 95.80 | 100.00 | 100.00 | 100.00 | 100.00 |
| T780 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.1277772735 | Sep 01 06:18:08 AM UTC 24 | Sep 01 06:18:20 AM UTC 24 | 508315528 ps | ||
| T781 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random.2352145389 | Sep 01 06:18:02 AM UTC 24 | Sep 01 06:18:21 AM UTC 24 | 594583636 ps | ||
| T782 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1952698466 | Sep 01 06:18:19 AM UTC 24 | Sep 01 06:18:22 AM UTC 24 | 19586179 ps | ||
| T783 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.1203700956 | Sep 01 06:18:19 AM UTC 24 | Sep 01 06:18:22 AM UTC 24 | 81383298 ps | ||
| T784 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.2830455815 | Sep 01 06:18:08 AM UTC 24 | Sep 01 06:18:22 AM UTC 24 | 857680509 ps | ||
| T785 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.3981256578 | Sep 01 06:18:07 AM UTC 24 | Sep 01 06:18:23 AM UTC 24 | 1713896492 ps | ||
| T786 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.2862572567 | Sep 01 06:14:44 AM UTC 24 | Sep 01 06:18:25 AM UTC 24 | 68944036370 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.860075004 | Sep 01 06:12:05 AM UTC 24 | Sep 01 06:18:26 AM UTC 24 | 42161356563 ps | ||
| T787 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3964444616 | Sep 01 06:17:57 AM UTC 24 | Sep 01 06:18:26 AM UTC 24 | 384413803 ps | ||
| T788 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.3706425568 | Sep 01 06:16:52 AM UTC 24 | Sep 01 06:18:26 AM UTC 24 | 24467010737 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.103977517 | Sep 01 06:15:13 AM UTC 24 | Sep 01 06:18:28 AM UTC 24 | 21566209421 ps | ||
| T789 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.2532756486 | Sep 01 06:16:02 AM UTC 24 | Sep 01 06:18:30 AM UTC 24 | 69329018672 ps | ||
| T790 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.1170074544 | Sep 01 06:17:23 AM UTC 24 | Sep 01 06:18:30 AM UTC 24 | 475673842 ps | ||
| T791 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.418994856 | Sep 01 06:18:28 AM UTC 24 | Sep 01 06:18:32 AM UTC 24 | 80146692 ps | ||
| T792 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random.305510021 | Sep 01 06:18:23 AM UTC 24 | Sep 01 06:18:32 AM UTC 24 | 73539655 ps | ||
| T793 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.2755837893 | Sep 01 06:18:21 AM UTC 24 | Sep 01 06:18:33 AM UTC 24 | 1952200989 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.453081331 | Sep 01 06:18:29 AM UTC 24 | Sep 01 06:18:34 AM UTC 24 | 198871571 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.3077461776 | Sep 01 06:18:28 AM UTC 24 | Sep 01 06:18:35 AM UTC 24 | 46453689 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.1387920435 | Sep 01 06:14:19 AM UTC 24 | Sep 01 06:18:35 AM UTC 24 | 43166952349 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.1740398131 | Sep 01 06:18:23 AM UTC 24 | Sep 01 06:18:35 AM UTC 24 | 71187255 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.1929364313 | Sep 01 06:17:00 AM UTC 24 | Sep 01 06:18:36 AM UTC 24 | 37506522283 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.3504687080 | Sep 01 06:18:21 AM UTC 24 | Sep 01 06:18:36 AM UTC 24 | 1327107750 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.4086412056 | Sep 01 06:15:32 AM UTC 24 | Sep 01 06:18:36 AM UTC 24 | 46670976845 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3629514255 | Sep 01 06:15:28 AM UTC 24 | Sep 01 06:18:36 AM UTC 24 | 1391473627 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.3653788514 | Sep 01 06:16:42 AM UTC 24 | Sep 01 06:18:37 AM UTC 24 | 13536706140 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.1531748613 | Sep 01 06:18:34 AM UTC 24 | Sep 01 06:18:37 AM UTC 24 | 31215837 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2004982627 | Sep 01 06:18:13 AM UTC 24 | Sep 01 06:18:37 AM UTC 24 | 304987210 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.446648973 | Sep 01 06:14:00 AM UTC 24 | Sep 01 06:18:37 AM UTC 24 | 38176651631 ps | ||
| T257 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.2371421053 | Sep 01 06:16:52 AM UTC 24 | Sep 01 06:18:38 AM UTC 24 | 9293569868 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1046357240 | Sep 01 06:18:35 AM UTC 24 | Sep 01 06:18:38 AM UTC 24 | 15163695 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.388446420 | Sep 01 06:18:28 AM UTC 24 | Sep 01 06:18:38 AM UTC 24 | 513064287 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.2840983413 | Sep 01 06:15:47 AM UTC 24 | Sep 01 06:18:40 AM UTC 24 | 274754220834 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.2110884964 | Sep 01 06:17:55 AM UTC 24 | Sep 01 06:18:42 AM UTC 24 | 508817353 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.2497884708 | Sep 01 06:18:10 AM UTC 24 | Sep 01 06:18:42 AM UTC 24 | 6152445141 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random.1932652717 | Sep 01 06:18:38 AM UTC 24 | Sep 01 06:18:43 AM UTC 24 | 454452586 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.653223368 | Sep 01 06:18:24 AM UTC 24 | Sep 01 06:18:43 AM UTC 24 | 73018910 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.3434376682 | Sep 01 06:18:38 AM UTC 24 | Sep 01 06:18:44 AM UTC 24 | 206497220 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2037290690 | Sep 01 06:18:41 AM UTC 24 | Sep 01 06:18:44 AM UTC 24 | 17354777 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1804845559 | Sep 01 06:17:57 AM UTC 24 | Sep 01 06:18:47 AM UTC 24 | 578800657 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.3915770263 | Sep 01 06:18:32 AM UTC 24 | Sep 01 06:18:47 AM UTC 24 | 2948099641 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.4092999691 | Sep 01 06:18:46 AM UTC 24 | Sep 01 06:18:48 AM UTC 24 | 12589591 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.2091297112 | Sep 01 06:18:46 AM UTC 24 | Sep 01 06:18:48 AM UTC 24 | 10798922 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.1662168047 | Sep 01 06:17:38 AM UTC 24 | Sep 01 06:18:49 AM UTC 24 | 414189007 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.594673083 | Sep 01 06:18:41 AM UTC 24 | Sep 01 06:18:49 AM UTC 24 | 1746387659 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.2689811955 | Sep 01 06:17:07 AM UTC 24 | Sep 01 06:18:51 AM UTC 24 | 3967133969 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random.1151518843 | Sep 01 06:18:47 AM UTC 24 | Sep 01 06:18:52 AM UTC 24 | 121514301 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.1694490485 | Sep 01 06:16:27 AM UTC 24 | Sep 01 06:18:53 AM UTC 24 | 20883126064 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.3233233681 | Sep 01 06:17:38 AM UTC 24 | Sep 01 06:18:53 AM UTC 24 | 4763260301 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.2378079124 | Sep 01 06:18:38 AM UTC 24 | Sep 01 06:18:54 AM UTC 24 | 576137999 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.1242767144 | Sep 01 06:18:51 AM UTC 24 | Sep 01 06:18:54 AM UTC 24 | 16537178 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.849381740 | Sep 01 06:18:37 AM UTC 24 | Sep 01 06:18:56 AM UTC 24 | 2524090912 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.1901748905 | Sep 01 06:18:46 AM UTC 24 | Sep 01 06:18:56 AM UTC 24 | 27102446 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.1715286974 | Sep 01 06:18:41 AM UTC 24 | Sep 01 06:18:56 AM UTC 24 | 1679263323 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3123901280 | Sep 01 06:18:04 AM UTC 24 | Sep 01 06:18:56 AM UTC 24 | 8465976253 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.3364246940 | Sep 01 06:13:41 AM UTC 24 | Sep 01 06:18:56 AM UTC 24 | 130199667932 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.1615900647 | Sep 01 06:18:41 AM UTC 24 | Sep 01 06:18:57 AM UTC 24 | 823036505 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.2709861895 | Sep 01 06:17:37 AM UTC 24 | Sep 01 06:18:57 AM UTC 24 | 11418503782 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.498539638 | Sep 01 06:18:52 AM UTC 24 | Sep 01 06:18:57 AM UTC 24 | 31708913 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.499493325 | Sep 01 06:17:29 AM UTC 24 | Sep 01 06:18:58 AM UTC 24 | 53537444580 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.2199235226 | Sep 01 06:18:52 AM UTC 24 | Sep 01 06:18:59 AM UTC 24 | 52981168 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.721607808 | Sep 01 06:18:41 AM UTC 24 | Sep 01 06:19:00 AM UTC 24 | 191063382 ps | ||
| T832 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3093373462 | Sep 01 06:18:55 AM UTC 24 | Sep 01 06:19:01 AM UTC 24 | 143964481 ps | ||
| T833 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.3178704006 | Sep 01 06:18:59 AM UTC 24 | Sep 01 06:19:01 AM UTC 24 | 11195700 ps | ||
| T834 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1302986778 | Sep 01 06:18:46 AM UTC 24 | Sep 01 06:19:02 AM UTC 24 | 1508896724 ps | ||
| T835 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.2888501960 | Sep 01 06:18:59 AM UTC 24 | Sep 01 06:19:02 AM UTC 24 | 44108604 ps | ||
| T836 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.892458654 | Sep 01 06:11:32 AM UTC 24 | Sep 01 06:19:02 AM UTC 24 | 61130247177 ps | ||
| T837 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.4240900036 | Sep 01 06:18:59 AM UTC 24 | Sep 01 06:19:02 AM UTC 24 | 79951200 ps | ||
| T838 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.3768857785 | Sep 01 06:18:52 AM UTC 24 | Sep 01 06:19:03 AM UTC 24 | 113755581 ps | ||
| T839 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.3351532342 | Sep 01 06:18:55 AM UTC 24 | Sep 01 06:19:03 AM UTC 24 | 553664779 ps | ||
| T840 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.1664863087 | Sep 01 06:18:55 AM UTC 24 | Sep 01 06:19:05 AM UTC 24 | 284614961 ps | ||
| T841 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2611311526 | Sep 01 06:18:55 AM UTC 24 | Sep 01 06:20:03 AM UTC 24 | 6751826045 ps | ||
| T842 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.2156891012 | Sep 01 06:16:24 AM UTC 24 | Sep 01 06:19:05 AM UTC 24 | 2735492636 ps | ||
| T843 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1064371638 | Sep 01 06:14:45 AM UTC 24 | Sep 01 06:19:05 AM UTC 24 | 33013883789 ps | ||
| T844 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.4193704255 | Sep 01 06:19:03 AM UTC 24 | Sep 01 06:19:06 AM UTC 24 | 13165075 ps | ||
| T845 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.4149143227 | Sep 01 06:18:47 AM UTC 24 | Sep 01 06:19:07 AM UTC 24 | 2064604177 ps | ||
| T846 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.3255605694 | Sep 01 06:18:59 AM UTC 24 | Sep 01 06:19:07 AM UTC 24 | 2179064379 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.976582846 | Sep 01 06:17:12 AM UTC 24 | Sep 01 06:19:09 AM UTC 24 | 18174893675 ps | ||
| T847 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3071319089 | Sep 01 06:19:04 AM UTC 24 | Sep 01 06:19:11 AM UTC 24 | 42889389 ps | ||
| T848 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1854193083 | Sep 01 06:19:08 AM UTC 24 | Sep 01 06:19:11 AM UTC 24 | 27793565 ps | ||
| T849 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.854687716 | Sep 01 06:19:08 AM UTC 24 | Sep 01 06:19:11 AM UTC 24 | 84950903 ps | ||
| T850 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.642233178 | Sep 01 06:19:03 AM UTC 24 | Sep 01 06:19:11 AM UTC 24 | 613407882 ps | ||
| T851 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.2456475699 | Sep 01 06:18:59 AM UTC 24 | Sep 01 06:19:12 AM UTC 24 | 856600292 ps | ||
| T216 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.134966578 | Sep 01 06:18:11 AM UTC 24 | Sep 01 06:19:12 AM UTC 24 | 5000956675 ps | ||
| T852 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random.1727519756 | Sep 01 06:18:59 AM UTC 24 | Sep 01 06:19:14 AM UTC 24 | 3769229883 ps | ||
| T853 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.3641882844 | Sep 01 06:19:04 AM UTC 24 | Sep 01 06:19:14 AM UTC 24 | 372839565 ps | ||
| T854 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random.2147969840 | Sep 01 06:19:08 AM UTC 24 | Sep 01 06:19:15 AM UTC 24 | 226033348 ps | ||
| T855 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1048934304 | Sep 01 06:19:08 AM UTC 24 | Sep 01 06:19:18 AM UTC 24 | 954919458 ps | ||
| T856 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.3413183093 | Sep 01 06:19:11 AM UTC 24 | Sep 01 06:19:18 AM UTC 24 | 295600457 ps | ||
| T857 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1992826009 | Sep 01 06:14:33 AM UTC 24 | Sep 01 06:19:19 AM UTC 24 | 37242645755 ps | ||
| T858 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.2718721922 | Sep 01 06:19:03 AM UTC 24 | Sep 01 06:19:19 AM UTC 24 | 244818064 ps | ||
| T859 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.3577231087 | Sep 01 06:18:51 AM UTC 24 | Sep 01 06:19:20 AM UTC 24 | 5575163337 ps | ||
| T860 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.2434534397 | Sep 01 06:18:41 AM UTC 24 | Sep 01 06:19:21 AM UTC 24 | 2057042884 ps | ||
| T861 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.3340227505 | Sep 01 06:19:15 AM UTC 24 | Sep 01 06:19:22 AM UTC 24 | 218105718 ps | ||
| T862 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.2460026190 | Sep 01 06:19:15 AM UTC 24 | Sep 01 06:19:23 AM UTC 24 | 84624578 ps | ||
| T863 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.2143255362 | Sep 01 06:19:08 AM UTC 24 | Sep 01 06:19:24 AM UTC 24 | 7785242383 ps | ||
| T864 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.2522601626 | Sep 01 06:19:15 AM UTC 24 | Sep 01 06:19:26 AM UTC 24 | 97287591 ps | ||
| T865 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.2114173049 | Sep 01 06:17:12 AM UTC 24 | Sep 01 06:19:29 AM UTC 24 | 22176216836 ps | ||
| T866 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.1005108142 | Sep 01 06:19:12 AM UTC 24 | Sep 01 06:19:29 AM UTC 24 | 263826596 ps | ||
| T867 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.3767866579 | Sep 01 06:19:03 AM UTC 24 | Sep 01 06:19:30 AM UTC 24 | 11678315892 ps | ||
| T868 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.52941935 | Sep 01 06:19:16 AM UTC 24 | Sep 01 06:19:31 AM UTC 24 | 1116853950 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.50322069 | Sep 01 06:16:16 AM UTC 24 | Sep 01 06:19:31 AM UTC 24 | 32219361862 ps | ||
| T869 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1371741576 | Sep 01 06:19:15 AM UTC 24 | Sep 01 06:19:33 AM UTC 24 | 804733652 ps | ||
| T870 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.720966295 | Sep 01 06:19:04 AM UTC 24 | Sep 01 06:19:36 AM UTC 24 | 1798233615 ps | ||
| T871 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.810153019 | Sep 01 06:18:59 AM UTC 24 | Sep 01 06:19:43 AM UTC 24 | 57065100733 ps | ||
| T872 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.2033978450 | Sep 01 06:18:44 AM UTC 24 | Sep 01 06:19:44 AM UTC 24 | 3437472570 ps | ||
| T873 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1565325574 | Sep 01 06:18:34 AM UTC 24 | Sep 01 06:19:45 AM UTC 24 | 3460246228 ps | ||
| T874 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.626257372 | Sep 01 06:18:34 AM UTC 24 | Sep 01 06:19:49 AM UTC 24 | 3757368048 ps | ||
| T875 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.1203638489 | Sep 01 06:19:11 AM UTC 24 | Sep 01 06:19:51 AM UTC 24 | 8408806752 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1883487241 | Sep 01 06:17:00 AM UTC 24 | Sep 01 06:19:54 AM UTC 24 | 18842637988 ps | ||
| T274 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.1618943343 | Sep 01 06:12:39 AM UTC 24 | Sep 01 06:19:56 AM UTC 24 | 74309139923 ps | ||
| T876 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.4016262818 | Sep 01 06:17:45 AM UTC 24 | Sep 01 06:19:56 AM UTC 24 | 40580757046 ps | ||
| T877 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.2987416463 | Sep 01 06:18:55 AM UTC 24 | Sep 01 06:19:59 AM UTC 24 | 502367608 ps | ||
| T878 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.4091591876 | Sep 01 06:15:11 AM UTC 24 | Sep 01 06:19:59 AM UTC 24 | 42736731131 ps | ||
| T879 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.2794722005 | Sep 01 06:19:15 AM UTC 24 | Sep 01 06:20:03 AM UTC 24 | 3495839977 ps | ||
| T880 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.820307765 | Sep 01 06:16:36 AM UTC 24 | Sep 01 06:20:04 AM UTC 24 | 7834433684 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.2388353824 | Sep 01 06:18:51 AM UTC 24 | Sep 01 06:20:05 AM UTC 24 | 25056833535 ps | ||
| T881 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.3281734022 | Sep 01 06:19:16 AM UTC 24 | Sep 01 06:20:08 AM UTC 24 | 4526639596 ps | ||
| T310 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2022577441 | Sep 01 06:14:08 AM UTC 24 | Sep 01 06:20:09 AM UTC 24 | 66336744776 ps | ||
| T882 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1073206964 | Sep 01 06:19:08 AM UTC 24 | Sep 01 06:20:15 AM UTC 24 | 693132011 ps | ||
| T883 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2519708643 | Sep 01 06:18:15 AM UTC 24 | Sep 01 06:20:18 AM UTC 24 | 4713499025 ps | ||
| T255 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.3688737249 | Sep 01 06:18:04 AM UTC 24 | Sep 01 06:20:22 AM UTC 24 | 107335923551 ps | ||
| T884 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.3052084277 | Sep 01 06:19:18 AM UTC 24 | Sep 01 06:20:22 AM UTC 24 | 814300664 ps | ||
| T885 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.2880978138 | Sep 01 06:16:28 AM UTC 24 | Sep 01 06:20:23 AM UTC 24 | 27367323200 ps | ||
| T313 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.1075838948 | Sep 01 06:15:34 AM UTC 24 | Sep 01 06:20:25 AM UTC 24 | 64468519182 ps | ||
| T886 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1198005749 | Sep 01 06:19:08 AM UTC 24 | Sep 01 06:20:30 AM UTC 24 | 8531666974 ps | ||
| T887 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1007669146 | Sep 01 06:18:41 AM UTC 24 | Sep 01 06:20:33 AM UTC 24 | 14966164734 ps | ||
| T888 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.3168098167 | Sep 01 06:18:32 AM UTC 24 | Sep 01 06:20:35 AM UTC 24 | 1202548649 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.1039630279 | Sep 01 06:15:26 AM UTC 24 | Sep 01 06:20:41 AM UTC 24 | 127348946365 ps | ||
| T889 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.200328376 | Sep 01 06:17:43 AM UTC 24 | Sep 01 06:20:47 AM UTC 24 | 72391285963 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.2080202696 | Sep 01 06:18:05 AM UTC 24 | Sep 01 06:20:51 AM UTC 24 | 25997057064 ps | ||
| T890 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.606778802 | Sep 01 06:17:28 AM UTC 24 | Sep 01 06:20:53 AM UTC 24 | 35837522524 ps | ||
| T891 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.1388722157 | Sep 01 06:18:38 AM UTC 24 | Sep 01 06:21:04 AM UTC 24 | 103945667502 ps | ||
| T892 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.2598378846 | Sep 01 06:18:23 AM UTC 24 | Sep 01 06:21:12 AM UTC 24 | 26991383317 ps | ||
| T314 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.888615307 | Sep 01 06:18:28 AM UTC 24 | Sep 01 06:21:19 AM UTC 24 | 20071227409 ps | ||
| T893 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.4005184664 | Sep 01 06:16:16 AM UTC 24 | Sep 01 06:21:22 AM UTC 24 | 45019292430 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.1940271220 | Sep 01 06:15:01 AM UTC 24 | Sep 01 06:21:25 AM UTC 24 | 64537765958 ps | ||
| T894 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3952881747 | Sep 01 06:19:04 AM UTC 24 | Sep 01 06:21:27 AM UTC 24 | 8184877314 ps | ||
| T895 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3525077153 | Sep 01 06:19:15 AM UTC 24 | Sep 01 06:21:28 AM UTC 24 | 13285985560 ps | ||
| T896 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.786979158 | Sep 01 06:18:23 AM UTC 24 | Sep 01 06:21:32 AM UTC 24 | 24594724056 ps | ||
| T897 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.971671312 | Sep 01 06:19:12 AM UTC 24 | Sep 01 06:21:39 AM UTC 24 | 21185037221 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.1262535733 | Sep 01 06:18:52 AM UTC 24 | Sep 01 06:21:40 AM UTC 24 | 93274349406 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.1651118300 | Sep 01 06:18:55 AM UTC 24 | Sep 01 06:21:42 AM UTC 24 | 9210819117 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3486123527 | Sep 01 06:17:02 AM UTC 24 | Sep 01 06:21:51 AM UTC 24 | 81228440604 ps | ||
| T898 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.1324904736 | Sep 01 06:16:29 AM UTC 24 | Sep 01 06:21:55 AM UTC 24 | 82253217093 ps | ||
| T315 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2100007145 | Sep 01 06:17:31 AM UTC 24 | Sep 01 06:22:04 AM UTC 24 | 86496440548 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.4083369017 | Sep 01 06:18:38 AM UTC 24 | Sep 01 06:22:14 AM UTC 24 | 51553106768 ps | ||
| T247 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.867104128 | Sep 01 06:19:03 AM UTC 24 | Sep 01 06:22:17 AM UTC 24 | 35281273441 ps | ||
| T899 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.609216713 | Sep 01 06:15:13 AM UTC 24 | Sep 01 06:22:21 AM UTC 24 | 303511646998 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1920813735 | Sep 01 06:17:13 AM UTC 24 | Sep 01 06:22:49 AM UTC 24 | 67556841187 ps | ||
| T900 | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.2870294999 | Sep 01 06:17:45 AM UTC 24 | Sep 01 06:23:12 AM UTC 24 | 44212194316 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.303581953 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 70241055 ps |
| CPU time | 5.19 seconds |
| Started | Sep 01 06:07:16 AM UTC 24 |
| Finished | Sep 01 06:07:22 AM UTC 24 |
| Peak memory | 212140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303581953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.303581953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.2595529761 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 49250518700 ps |
| CPU time | 354.7 seconds |
| Started | Sep 01 06:07:59 AM UTC 24 |
| Finished | Sep 01 06:13:59 AM UTC 24 |
| Peak memory | 214248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595529761 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.2595529761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.782690775 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 113898105789 ps |
| CPU time | 367.74 seconds |
| Started | Sep 01 06:10:38 AM UTC 24 |
| Finished | Sep 01 06:16:50 AM UTC 24 |
| Peak memory | 220184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782690775 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.782690775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke.3012214467 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 79270027 ps |
| CPU time | 2.47 seconds |
| Started | Sep 01 06:07:20 AM UTC 24 |
| Finished | Sep 01 06:07:23 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012214467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3012214467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/1.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.285785805 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 36380880413 ps |
| CPU time | 222.3 seconds |
| Started | Sep 01 06:07:27 AM UTC 24 |
| Finished | Sep 01 06:11:13 AM UTC 24 |
| Peak memory | 214236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285785805 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.285785805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.860075004 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 42161356563 ps |
| CPU time | 375.57 seconds |
| Started | Sep 01 06:12:05 AM UTC 24 |
| Finished | Sep 01 06:18:26 AM UTC 24 |
| Peak memory | 214248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860075004 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.860075004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all.751434653 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 264880640 ps |
| CPU time | 16.48 seconds |
| Started | Sep 01 06:07:16 AM UTC 24 |
| Finished | Sep 01 06:07:34 AM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751434653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.751434653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/0.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.195987525 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 10167074789 ps |
| CPU time | 73.42 seconds |
| Started | Sep 01 06:07:50 AM UTC 24 |
| Finished | Sep 01 06:09:06 AM UTC 24 |
| Peak memory | 216292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195987525 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.195987525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.2292185966 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 11474001996 ps |
| CPU time | 195.54 seconds |
| Started | Sep 01 06:07:18 AM UTC 24 |
| Finished | Sep 01 06:10:37 AM UTC 24 |
| Peak memory | 216292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292185966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.2292185966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.3229923542 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 50356136051 ps |
| CPU time | 453.83 seconds |
| Started | Sep 01 06:08:54 AM UTC 24 |
| Finished | Sep 01 06:16:33 AM UTC 24 |
| Peak memory | 217944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229923542 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.3229923542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_large_delays.304919279 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 57647513577 ps |
| CPU time | 50.08 seconds |
| Started | Sep 01 06:07:23 AM UTC 24 |
| Finished | Sep 01 06:08:15 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304919279 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.304919279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/1.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_slow_rsp.2631666583 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 5231518111 ps |
| CPU time | 35.86 seconds |
| Started | Sep 01 06:07:09 AM UTC 24 |
| Finished | Sep 01 06:07:46 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631666583 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.2631666583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/0.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.3364246940 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 130199667932 ps |
| CPU time | 310.48 seconds |
| Started | Sep 01 06:13:41 AM UTC 24 |
| Finished | Sep 01 06:18:56 AM UTC 24 |
| Peak memory | 214436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364246940 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.3364246940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.494782465 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 26548501271 ps |
| CPU time | 209.14 seconds |
| Started | Sep 01 06:11:50 AM UTC 24 |
| Finished | Sep 01 06:15:22 AM UTC 24 |
| Peak memory | 214244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494782465 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.494782465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.931087433 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5574633811 ps |
| CPU time | 132.01 seconds |
| Started | Sep 01 06:07:47 AM UTC 24 |
| Finished | Sep 01 06:10:02 AM UTC 24 |
| Peak memory | 216292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931087433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.931087433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2100007145 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 86496440548 ps |
| CPU time | 269.16 seconds |
| Started | Sep 01 06:17:31 AM UTC 24 |
| Finished | Sep 01 06:22:04 AM UTC 24 |
| Peak memory | 214240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100007145 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.2100007145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random.2405833039 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 72419828 ps |
| CPU time | 5.26 seconds |
| Started | Sep 01 06:07:06 AM UTC 24 |
| Finished | Sep 01 06:07:13 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405833039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.2405833039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/0.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.31928426 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 7673180660 ps |
| CPU time | 115.66 seconds |
| Started | Sep 01 06:07:18 AM UTC 24 |
| Finished | Sep 01 06:09:17 AM UTC 24 |
| Peak memory | 216296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31928426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.31928426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.4247084451 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 462885714 ps |
| CPU time | 52.35 seconds |
| Started | Sep 01 06:15:57 AM UTC 24 |
| Finished | Sep 01 06:16:50 AM UTC 24 |
| Peak memory | 214188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247084451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.4247084451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random.239664273 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 616471797 ps |
| CPU time | 17.44 seconds |
| Started | Sep 01 06:08:15 AM UTC 24 |
| Finished | Sep 01 06:08:34 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239664273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.239664273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/4.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.4178156018 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1721438832 ps |
| CPU time | 301.56 seconds |
| Started | Sep 01 06:10:53 AM UTC 24 |
| Finished | Sep 01 06:15:59 AM UTC 24 |
| Peak memory | 216424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178156018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.4178156018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.3688743124 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4560473104 ps |
| CPU time | 150.1 seconds |
| Started | Sep 01 06:09:45 AM UTC 24 |
| Finished | Sep 01 06:12:18 AM UTC 24 |
| Peak memory | 216488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688743124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.3688743124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.2029083092 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 82038786 ps |
| CPU time | 17.24 seconds |
| Started | Sep 01 06:10:20 AM UTC 24 |
| Finished | Sep 01 06:10:38 AM UTC 24 |
| Peak memory | 214184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029083092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.2029083092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.4178925432 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 384784412 ps |
| CPU time | 31.58 seconds |
| Started | Sep 01 06:14:14 AM UTC 24 |
| Finished | Sep 01 06:14:47 AM UTC 24 |
| Peak memory | 214184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178925432 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.4178925432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.2469511737 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 3398512508 ps |
| CPU time | 29.97 seconds |
| Started | Sep 01 06:17:35 AM UTC 24 |
| Finished | Sep 01 06:18:07 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469511737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2469511737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/42.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all.564802107 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 1655739466 ps |
| CPU time | 33.72 seconds |
| Started | Sep 01 06:09:45 AM UTC 24 |
| Finished | Sep 01 06:10:20 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564802107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.564802107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/9.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random.4019973328 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1789492692 ps |
| CPU time | 17.37 seconds |
| Started | Sep 01 06:07:34 AM UTC 24 |
| Finished | Sep 01 06:07:53 AM UTC 24 |
| Peak memory | 212120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019973328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.4019973328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/2.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.446648973 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 38176651631 ps |
| CPU time | 273.09 seconds |
| Started | Sep 01 06:14:00 AM UTC 24 |
| Finished | Sep 01 06:18:37 AM UTC 24 |
| Peak memory | 214248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446648973 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.446648973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.4116195822 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 14137285822 ps |
| CPU time | 170.74 seconds |
| Started | Sep 01 06:11:22 AM UTC 24 |
| Finished | Sep 01 06:14:16 AM UTC 24 |
| Peak memory | 216292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116195822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.4116195822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_error.1606782709 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 2726524176 ps |
| CPU time | 22.57 seconds |
| Started | Sep 01 06:07:18 AM UTC 24 |
| Finished | Sep 01 06:07:42 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606782709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1606782709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/0.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.279212137 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 8886178956 ps |
| CPU time | 144.79 seconds |
| Started | Sep 01 06:10:30 AM UTC 24 |
| Finished | Sep 01 06:12:57 AM UTC 24 |
| Peak memory | 216484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279212137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.279212137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_error.393868062 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 2697224038 ps |
| CPU time | 48.12 seconds |
| Started | Sep 01 06:10:01 AM UTC 24 |
| Finished | Sep 01 06:10:51 AM UTC 24 |
| Peak memory | 214496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393868062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.393868062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/10.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all.4121566818 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4959958427 ps |
| CPU time | 73.42 seconds |
| Started | Sep 01 06:10:01 AM UTC 24 |
| Finished | Sep 01 06:11:16 AM UTC 24 |
| Peak memory | 214248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121566818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.4121566818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/10.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.2934367675 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 65302767856 ps |
| CPU time | 174.12 seconds |
| Started | Sep 01 06:13:17 AM UTC 24 |
| Finished | Sep 01 06:16:14 AM UTC 24 |
| Peak memory | 214240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934367675 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.2934367675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device.202750228 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 17770408 ps |
| CPU time | 3 seconds |
| Started | Sep 01 06:07:11 AM UTC 24 |
| Finished | Sep 01 06:07:15 AM UTC 24 |
| Peak memory | 212256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202750228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.202750228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/0.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.3983455018 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 13301953583 ps |
| CPU time | 91.58 seconds |
| Started | Sep 01 06:07:11 AM UTC 24 |
| Finished | Sep 01 06:08:44 AM UTC 24 |
| Peak memory | 212144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983455018 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.3983455018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_error_random.1585911913 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 963194875 ps |
| CPU time | 15.8 seconds |
| Started | Sep 01 06:07:14 AM UTC 24 |
| Finished | Sep 01 06:07:31 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585911913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1585911913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/0.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_large_delays.1736879675 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5947001408 ps |
| CPU time | 7.78 seconds |
| Started | Sep 01 06:07:09 AM UTC 24 |
| Finished | Sep 01 06:07:18 AM UTC 24 |
| Peak memory | 212184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736879675 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1736879675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/0.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_zero_delays.2034654680 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 10114816 ps |
| CPU time | 2.11 seconds |
| Started | Sep 01 06:07:06 AM UTC 24 |
| Finished | Sep 01 06:07:09 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034654680 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.2034654680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/0.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_same_source.3565658234 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 107424055 ps |
| CPU time | 6.17 seconds |
| Started | Sep 01 06:07:12 AM UTC 24 |
| Finished | Sep 01 06:07:19 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565658234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.3565658234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/0.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke.1704396955 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 42659848 ps |
| CPU time | 2.17 seconds |
| Started | Sep 01 06:07:02 AM UTC 24 |
| Finished | Sep 01 06:07:05 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704396955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.1704396955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/0.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_large_delays.2813484067 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 2172913056 ps |
| CPU time | 18.18 seconds |
| Started | Sep 01 06:07:05 AM UTC 24 |
| Finished | Sep 01 06:07:25 AM UTC 24 |
| Peak memory | 212452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813484067 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2813484067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/0.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.1089790579 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4100118415 ps |
| CPU time | 14.53 seconds |
| Started | Sep 01 06:07:05 AM UTC 24 |
| Finished | Sep 01 06:07:21 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089790579 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1089790579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.3632922847 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 12356335 ps |
| CPU time | 1.48 seconds |
| Started | Sep 01 06:07:02 AM UTC 24 |
| Finished | Sep 01 06:07:04 AM UTC 24 |
| Peak memory | 211664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632922847 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.3632922847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/0.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_unmapped_addr.1730678773 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 84286819 ps |
| CPU time | 8.1 seconds |
| Started | Sep 01 06:07:14 AM UTC 24 |
| Finished | Sep 01 06:07:23 AM UTC 24 |
| Peak memory | 212324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730678773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.1730678773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/0.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device.1443840885 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 765747396 ps |
| CPU time | 19.96 seconds |
| Started | Sep 01 06:07:25 AM UTC 24 |
| Finished | Sep 01 06:07:46 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443840885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.1443840885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/1.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.1806627972 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 1650429573 ps |
| CPU time | 14.62 seconds |
| Started | Sep 01 06:07:29 AM UTC 24 |
| Finished | Sep 01 06:07:45 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806627972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.1806627972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_error_random.1403432039 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 2471166309 ps |
| CPU time | 16.79 seconds |
| Started | Sep 01 06:07:27 AM UTC 24 |
| Finished | Sep 01 06:07:46 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403432039 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1403432039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/1.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random.1042733328 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 47199105 ps |
| CPU time | 1.61 seconds |
| Started | Sep 01 06:07:23 AM UTC 24 |
| Finished | Sep 01 06:07:26 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042733328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.1042733328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/1.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_slow_rsp.2906577730 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 13480028374 ps |
| CPU time | 111.07 seconds |
| Started | Sep 01 06:07:25 AM UTC 24 |
| Finished | Sep 01 06:09:18 AM UTC 24 |
| Peak memory | 212168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906577730 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2906577730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/1.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_zero_delays.2487795110 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 73905349 ps |
| CPU time | 6.9 seconds |
| Started | Sep 01 06:07:23 AM UTC 24 |
| Finished | Sep 01 06:07:31 AM UTC 24 |
| Peak memory | 212384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487795110 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.2487795110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/1.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_same_source.1557441361 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 20377721 ps |
| CPU time | 3.39 seconds |
| Started | Sep 01 06:07:27 AM UTC 24 |
| Finished | Sep 01 06:07:32 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557441361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.1557441361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/1.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_large_delays.3084230278 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3052923067 ps |
| CPU time | 11.48 seconds |
| Started | Sep 01 06:07:21 AM UTC 24 |
| Finished | Sep 01 06:07:34 AM UTC 24 |
| Peak memory | 212264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084230278 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3084230278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/1.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.1352612821 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2495865100 ps |
| CPU time | 11.31 seconds |
| Started | Sep 01 06:07:21 AM UTC 24 |
| Finished | Sep 01 06:07:34 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352612821 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1352612821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.3645951122 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 8482258 ps |
| CPU time | 1.69 seconds |
| Started | Sep 01 06:07:20 AM UTC 24 |
| Finished | Sep 01 06:07:22 AM UTC 24 |
| Peak memory | 211132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645951122 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.3645951122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/1.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all.2196803265 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 303372635 ps |
| CPU time | 41.39 seconds |
| Started | Sep 01 06:07:31 AM UTC 24 |
| Finished | Sep 01 06:08:14 AM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196803265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2196803265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/1.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_error.735623159 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 4589648638 ps |
| CPU time | 94.6 seconds |
| Started | Sep 01 06:07:33 AM UTC 24 |
| Finished | Sep 01 06:09:10 AM UTC 24 |
| Peak memory | 216292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735623159 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.735623159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/1.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.783114419 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 988791671 ps |
| CPU time | 113.38 seconds |
| Started | Sep 01 06:07:31 AM UTC 24 |
| Finished | Sep 01 06:09:27 AM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783114419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.783114419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.3251324966 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1767247576 ps |
| CPU time | 149.37 seconds |
| Started | Sep 01 06:07:33 AM UTC 24 |
| Finished | Sep 01 06:10:05 AM UTC 24 |
| Peak memory | 218388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251324966 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.3251324966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_unmapped_addr.4027385698 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 71401099 ps |
| CPU time | 6.52 seconds |
| Started | Sep 01 06:07:27 AM UTC 24 |
| Finished | Sep 01 06:07:35 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027385698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.4027385698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/1.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device.4145530252 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 375714833 ps |
| CPU time | 9.78 seconds |
| Started | Sep 01 06:09:52 AM UTC 24 |
| Finished | Sep 01 06:10:03 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145530252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.4145530252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/10.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1929434583 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 4052240161 ps |
| CPU time | 26.98 seconds |
| Started | Sep 01 06:09:55 AM UTC 24 |
| Finished | Sep 01 06:10:23 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929434583 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.1929434583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.3523571310 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 83414151 ps |
| CPU time | 3.26 seconds |
| Started | Sep 01 06:09:58 AM UTC 24 |
| Finished | Sep 01 06:10:03 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523571310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.3523571310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_error_random.2969373707 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 88076246 ps |
| CPU time | 6.11 seconds |
| Started | Sep 01 06:09:57 AM UTC 24 |
| Finished | Sep 01 06:10:05 AM UTC 24 |
| Peak memory | 212264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969373707 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2969373707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/10.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random.3949805219 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 64151957 ps |
| CPU time | 7.12 seconds |
| Started | Sep 01 06:09:49 AM UTC 24 |
| Finished | Sep 01 06:09:58 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949805219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.3949805219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/10.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_large_delays.2526164690 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 11291048988 ps |
| CPU time | 55.22 seconds |
| Started | Sep 01 06:09:51 AM UTC 24 |
| Finished | Sep 01 06:10:47 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526164690 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2526164690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/10.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_slow_rsp.4039147959 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 4884728668 ps |
| CPU time | 34.29 seconds |
| Started | Sep 01 06:09:51 AM UTC 24 |
| Finished | Sep 01 06:10:26 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039147959 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.4039147959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/10.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_zero_delays.3528018115 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 59765598 ps |
| CPU time | 5.67 seconds |
| Started | Sep 01 06:09:50 AM UTC 24 |
| Finished | Sep 01 06:09:56 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528018115 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3528018115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/10.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_same_source.1342036605 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 918852522 ps |
| CPU time | 15.37 seconds |
| Started | Sep 01 06:09:56 AM UTC 24 |
| Finished | Sep 01 06:10:13 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342036605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1342036605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/10.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke.3997507894 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 19292103 ps |
| CPU time | 1.75 seconds |
| Started | Sep 01 06:09:46 AM UTC 24 |
| Finished | Sep 01 06:09:49 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997507894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3997507894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/10.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_large_delays.1044171465 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 7066127600 ps |
| CPU time | 11.27 seconds |
| Started | Sep 01 06:09:47 AM UTC 24 |
| Finished | Sep 01 06:10:00 AM UTC 24 |
| Peak memory | 212184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044171465 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1044171465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/10.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3979093755 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 1272937766 ps |
| CPU time | 7.31 seconds |
| Started | Sep 01 06:09:49 AM UTC 24 |
| Finished | Sep 01 06:09:58 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979093755 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3979093755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.1876059059 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 9826043 ps |
| CPU time | 1.89 seconds |
| Started | Sep 01 06:09:47 AM UTC 24 |
| Finished | Sep 01 06:09:50 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876059059 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.1876059059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/10.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.1734338992 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 3184105925 ps |
| CPU time | 163.84 seconds |
| Started | Sep 01 06:10:01 AM UTC 24 |
| Finished | Sep 01 06:12:48 AM UTC 24 |
| Peak memory | 214244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734338992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.1734338992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.217979255 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 166188543 ps |
| CPU time | 14.72 seconds |
| Started | Sep 01 06:10:02 AM UTC 24 |
| Finished | Sep 01 06:10:19 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217979255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.217979255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_unmapped_addr.2645379747 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 116537467 ps |
| CPU time | 6.16 seconds |
| Started | Sep 01 06:09:58 AM UTC 24 |
| Finished | Sep 01 06:10:06 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645379747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.2645379747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/10.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device.187857630 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 73634669 ps |
| CPU time | 10.95 seconds |
| Started | Sep 01 06:10:09 AM UTC 24 |
| Finished | Sep 01 06:10:21 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187857630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.187857630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/11.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.996255063 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 125718839948 ps |
| CPU time | 292.44 seconds |
| Started | Sep 01 06:10:12 AM UTC 24 |
| Finished | Sep 01 06:15:09 AM UTC 24 |
| Peak memory | 214440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996255063 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.996255063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.636976121 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 687287113 ps |
| CPU time | 15.11 seconds |
| Started | Sep 01 06:10:20 AM UTC 24 |
| Finished | Sep 01 06:10:36 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636976121 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.636976121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_error_random.4203745944 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 1838660702 ps |
| CPU time | 7.71 seconds |
| Started | Sep 01 06:10:17 AM UTC 24 |
| Finished | Sep 01 06:10:26 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203745944 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.4203745944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/11.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random.1533594947 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 486450758 ps |
| CPU time | 12.53 seconds |
| Started | Sep 01 06:10:07 AM UTC 24 |
| Finished | Sep 01 06:10:21 AM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533594947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.1533594947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/11.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_large_delays.44564137 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 49097604994 ps |
| CPU time | 91.67 seconds |
| Started | Sep 01 06:10:08 AM UTC 24 |
| Finished | Sep 01 06:11:42 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44564137 -assert nopostproc +UVM_TESTNAME=xbar_base_ test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.44564137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/11.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_slow_rsp.1877476735 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 55242121549 ps |
| CPU time | 201.07 seconds |
| Started | Sep 01 06:10:09 AM UTC 24 |
| Finished | Sep 01 06:13:33 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877476735 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.1877476735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/11.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_zero_delays.1087656729 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 287440545 ps |
| CPU time | 7.56 seconds |
| Started | Sep 01 06:10:07 AM UTC 24 |
| Finished | Sep 01 06:10:15 AM UTC 24 |
| Peak memory | 211868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087656729 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.1087656729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/11.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_same_source.1671892786 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 2695282868 ps |
| CPU time | 17.85 seconds |
| Started | Sep 01 06:10:13 AM UTC 24 |
| Finished | Sep 01 06:10:33 AM UTC 24 |
| Peak memory | 212184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671892786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.1671892786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/11.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke.3999550622 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 55742049 ps |
| CPU time | 2.56 seconds |
| Started | Sep 01 06:10:04 AM UTC 24 |
| Finished | Sep 01 06:10:08 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999550622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.3999550622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/11.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_large_delays.3931015311 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 9996196499 ps |
| CPU time | 12.29 seconds |
| Started | Sep 01 06:10:04 AM UTC 24 |
| Finished | Sep 01 06:10:18 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931015311 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.3931015311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/11.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.3303766922 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 801768035 ps |
| CPU time | 11.97 seconds |
| Started | Sep 01 06:10:06 AM UTC 24 |
| Finished | Sep 01 06:10:19 AM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303766922 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3303766922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.677915768 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 10311269 ps |
| CPU time | 1.72 seconds |
| Started | Sep 01 06:10:04 AM UTC 24 |
| Finished | Sep 01 06:10:08 AM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677915768 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.677915768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/11.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all.3663948246 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 5588482986 ps |
| CPU time | 31.27 seconds |
| Started | Sep 01 06:10:20 AM UTC 24 |
| Finished | Sep 01 06:10:52 AM UTC 24 |
| Peak memory | 214436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663948246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.3663948246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/11.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_error.1104010789 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 392012952 ps |
| CPU time | 7.67 seconds |
| Started | Sep 01 06:10:20 AM UTC 24 |
| Finished | Sep 01 06:10:29 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104010789 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1104010789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/11.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.1080439403 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 9099784000 ps |
| CPU time | 72.49 seconds |
| Started | Sep 01 06:10:21 AM UTC 24 |
| Finished | Sep 01 06:11:35 AM UTC 24 |
| Peak memory | 214236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080439403 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.1080439403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_unmapped_addr.2463244173 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 71542050 ps |
| CPU time | 9.3 seconds |
| Started | Sep 01 06:10:18 AM UTC 24 |
| Finished | Sep 01 06:10:29 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463244173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2463244173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/11.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device.613001673 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 19369023 ps |
| CPU time | 4.88 seconds |
| Started | Sep 01 06:10:27 AM UTC 24 |
| Finished | Sep 01 06:10:33 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613001673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.613001673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/12.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.3150970035 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 63524037656 ps |
| CPU time | 225.95 seconds |
| Started | Sep 01 06:10:27 AM UTC 24 |
| Finished | Sep 01 06:14:17 AM UTC 24 |
| Peak memory | 214308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150970035 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.3150970035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.3942229813 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 580647553 ps |
| CPU time | 7.15 seconds |
| Started | Sep 01 06:10:29 AM UTC 24 |
| Finished | Sep 01 06:10:38 AM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942229813 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.3942229813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_error_random.1764408725 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 7920654473 ps |
| CPU time | 15.98 seconds |
| Started | Sep 01 06:10:28 AM UTC 24 |
| Finished | Sep 01 06:10:46 AM UTC 24 |
| Peak memory | 212452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764408725 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1764408725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/12.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random.2076348110 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 28186863 ps |
| CPU time | 3.69 seconds |
| Started | Sep 01 06:10:26 AM UTC 24 |
| Finished | Sep 01 06:10:30 AM UTC 24 |
| Peak memory | 212256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076348110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.2076348110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/12.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_large_delays.1965676423 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 29846531447 ps |
| CPU time | 73.1 seconds |
| Started | Sep 01 06:10:26 AM UTC 24 |
| Finished | Sep 01 06:11:41 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965676423 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1965676423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/12.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_slow_rsp.4198448226 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 31742541188 ps |
| CPU time | 212.37 seconds |
| Started | Sep 01 06:10:26 AM UTC 24 |
| Finished | Sep 01 06:14:01 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198448226 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.4198448226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/12.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_zero_delays.941471619 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 13804962 ps |
| CPU time | 2 seconds |
| Started | Sep 01 06:10:26 AM UTC 24 |
| Finished | Sep 01 06:10:29 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941471619 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.941471619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/12.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_same_source.3184895592 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 476843929 ps |
| CPU time | 7.59 seconds |
| Started | Sep 01 06:10:27 AM UTC 24 |
| Finished | Sep 01 06:10:36 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184895592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3184895592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/12.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke.3802282079 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 68751488 ps |
| CPU time | 2.48 seconds |
| Started | Sep 01 06:10:21 AM UTC 24 |
| Finished | Sep 01 06:10:24 AM UTC 24 |
| Peak memory | 212060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802282079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.3802282079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/12.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_large_delays.427219437 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 2007026597 ps |
| CPU time | 16.48 seconds |
| Started | Sep 01 06:10:22 AM UTC 24 |
| Finished | Sep 01 06:10:40 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427219437 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.427219437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/12.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.170857827 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 1084473515 ps |
| CPU time | 9.18 seconds |
| Started | Sep 01 06:10:24 AM UTC 24 |
| Finished | Sep 01 06:10:34 AM UTC 24 |
| Peak memory | 212324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170857827 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.170857827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.3093634238 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 9313002 ps |
| CPU time | 1.81 seconds |
| Started | Sep 01 06:10:22 AM UTC 24 |
| Finished | Sep 01 06:10:25 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093634238 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.3093634238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/12.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all.2956215877 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 397649428 ps |
| CPU time | 4.46 seconds |
| Started | Sep 01 06:10:29 AM UTC 24 |
| Finished | Sep 01 06:10:35 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956215877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2956215877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/12.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3796209323 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 2526869861 ps |
| CPU time | 24.03 seconds |
| Started | Sep 01 06:10:32 AM UTC 24 |
| Finished | Sep 01 06:10:57 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796209323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3796209323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/12.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.1046646072 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 11726227123 ps |
| CPU time | 134.75 seconds |
| Started | Sep 01 06:10:34 AM UTC 24 |
| Finished | Sep 01 06:12:51 AM UTC 24 |
| Peak memory | 218540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046646072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.1046646072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_unmapped_addr.374243158 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 81533949 ps |
| CPU time | 2.21 seconds |
| Started | Sep 01 06:10:29 AM UTC 24 |
| Finished | Sep 01 06:10:33 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374243158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.374243158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/12.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device.446354314 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 1122678593 ps |
| CPU time | 14.97 seconds |
| Started | Sep 01 06:10:36 AM UTC 24 |
| Finished | Sep 01 06:10:52 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446354314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.446354314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/13.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.773155522 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 370274846 ps |
| CPU time | 7.68 seconds |
| Started | Sep 01 06:10:39 AM UTC 24 |
| Finished | Sep 01 06:10:48 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773155522 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.773155522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_error_random.3750655263 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 87337422 ps |
| CPU time | 4.63 seconds |
| Started | Sep 01 06:10:38 AM UTC 24 |
| Finished | Sep 01 06:10:43 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750655263 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3750655263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/13.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random.2766552646 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 586156451 ps |
| CPU time | 12.44 seconds |
| Started | Sep 01 06:10:35 AM UTC 24 |
| Finished | Sep 01 06:10:49 AM UTC 24 |
| Peak memory | 212120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766552646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.2766552646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/13.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_large_delays.234654471 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 24073879474 ps |
| CPU time | 157.11 seconds |
| Started | Sep 01 06:10:36 AM UTC 24 |
| Finished | Sep 01 06:13:16 AM UTC 24 |
| Peak memory | 212188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234654471 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.234654471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/13.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_slow_rsp.96193685 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 1740405991 ps |
| CPU time | 16.48 seconds |
| Started | Sep 01 06:10:36 AM UTC 24 |
| Finished | Sep 01 06:10:54 AM UTC 24 |
| Peak memory | 212312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96193685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.96193685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/13.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_zero_delays.404025195 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 30670371 ps |
| CPU time | 3 seconds |
| Started | Sep 01 06:10:35 AM UTC 24 |
| Finished | Sep 01 06:10:39 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404025195 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.404025195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/13.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_same_source.2985853851 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 47898665 ps |
| CPU time | 8.06 seconds |
| Started | Sep 01 06:10:38 AM UTC 24 |
| Finished | Sep 01 06:10:47 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985853851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2985853851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/13.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke.3015492105 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 21189781 ps |
| CPU time | 1.65 seconds |
| Started | Sep 01 06:10:34 AM UTC 24 |
| Finished | Sep 01 06:10:36 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015492105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.3015492105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/13.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_large_delays.1153774311 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 2193625825 ps |
| CPU time | 11.68 seconds |
| Started | Sep 01 06:10:34 AM UTC 24 |
| Finished | Sep 01 06:10:47 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153774311 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.1153774311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/13.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.3323271708 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1179091052 ps |
| CPU time | 12.29 seconds |
| Started | Sep 01 06:10:34 AM UTC 24 |
| Finished | Sep 01 06:10:47 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323271708 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.3323271708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.2268634047 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 21874510 ps |
| CPU time | 1.76 seconds |
| Started | Sep 01 06:10:34 AM UTC 24 |
| Finished | Sep 01 06:10:37 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268634047 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.2268634047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/13.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all.2726731705 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 86260590 ps |
| CPU time | 7.93 seconds |
| Started | Sep 01 06:10:40 AM UTC 24 |
| Finished | Sep 01 06:10:49 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726731705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.2726731705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/13.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_error.1471236371 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 2011699559 ps |
| CPU time | 36.52 seconds |
| Started | Sep 01 06:10:42 AM UTC 24 |
| Finished | Sep 01 06:11:20 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471236371 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.1471236371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/13.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.3215196357 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 745524374 ps |
| CPU time | 110.25 seconds |
| Started | Sep 01 06:10:40 AM UTC 24 |
| Finished | Sep 01 06:12:33 AM UTC 24 |
| Peak memory | 216296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215196357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.3215196357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.2370050651 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 602534141 ps |
| CPU time | 77.37 seconds |
| Started | Sep 01 06:10:45 AM UTC 24 |
| Finished | Sep 01 06:12:04 AM UTC 24 |
| Peak memory | 214380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370050651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.2370050651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_unmapped_addr.2630611862 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 144803726 ps |
| CPU time | 6.91 seconds |
| Started | Sep 01 06:10:39 AM UTC 24 |
| Finished | Sep 01 06:10:47 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630611862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.2630611862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/13.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device.4010012892 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1426427828 ps |
| CPU time | 13.45 seconds |
| Started | Sep 01 06:10:49 AM UTC 24 |
| Finished | Sep 01 06:11:04 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010012892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.4010012892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/14.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.79587295 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 114609501571 ps |
| CPU time | 410.24 seconds |
| Started | Sep 01 06:10:49 AM UTC 24 |
| Finished | Sep 01 06:17:45 AM UTC 24 |
| Peak memory | 218072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79587295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.79587295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.1099143632 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 2755895547 ps |
| CPU time | 14.16 seconds |
| Started | Sep 01 06:10:53 AM UTC 24 |
| Finished | Sep 01 06:11:08 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099143632 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.1099143632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_error_random.3792472423 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 43300829 ps |
| CPU time | 4.67 seconds |
| Started | Sep 01 06:10:52 AM UTC 24 |
| Finished | Sep 01 06:10:57 AM UTC 24 |
| Peak memory | 212324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792472423 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.3792472423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/14.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random.2161675864 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 102229785 ps |
| CPU time | 3.61 seconds |
| Started | Sep 01 06:10:48 AM UTC 24 |
| Finished | Sep 01 06:10:52 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161675864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.2161675864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/14.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_large_delays.3432345183 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 10994511061 ps |
| CPU time | 62.54 seconds |
| Started | Sep 01 06:10:49 AM UTC 24 |
| Finished | Sep 01 06:11:53 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432345183 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3432345183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/14.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_slow_rsp.951175131 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 914941859 ps |
| CPU time | 12.05 seconds |
| Started | Sep 01 06:10:49 AM UTC 24 |
| Finished | Sep 01 06:11:02 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951175131 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.951175131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/14.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_zero_delays.366149999 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 182067710 ps |
| CPU time | 9.64 seconds |
| Started | Sep 01 06:10:48 AM UTC 24 |
| Finished | Sep 01 06:10:59 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366149999 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.366149999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/14.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_same_source.3620921767 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 6190181358 ps |
| CPU time | 17.03 seconds |
| Started | Sep 01 06:10:50 AM UTC 24 |
| Finished | Sep 01 06:11:09 AM UTC 24 |
| Peak memory | 212384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620921767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.3620921767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/14.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke.754261817 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 51165250 ps |
| CPU time | 2.22 seconds |
| Started | Sep 01 06:10:48 AM UTC 24 |
| Finished | Sep 01 06:10:51 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754261817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.754261817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/14.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_large_delays.1279106077 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 3317967340 ps |
| CPU time | 9.98 seconds |
| Started | Sep 01 06:10:48 AM UTC 24 |
| Finished | Sep 01 06:10:59 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279106077 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.1279106077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/14.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2091145390 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 999421372 ps |
| CPU time | 8.68 seconds |
| Started | Sep 01 06:10:48 AM UTC 24 |
| Finished | Sep 01 06:10:57 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091145390 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2091145390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.1332327029 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 8678466 ps |
| CPU time | 1.71 seconds |
| Started | Sep 01 06:10:48 AM UTC 24 |
| Finished | Sep 01 06:10:50 AM UTC 24 |
| Peak memory | 211132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332327029 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.1332327029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/14.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all.2552629387 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 5767936 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 06:10:53 AM UTC 24 |
| Finished | Sep 01 06:10:55 AM UTC 24 |
| Peak memory | 202424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552629387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2552629387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/14.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_error.2781016776 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 17871669155 ps |
| CPU time | 35.93 seconds |
| Started | Sep 01 06:10:53 AM UTC 24 |
| Finished | Sep 01 06:11:31 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781016776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.2781016776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/14.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.4039183909 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 691877822 ps |
| CPU time | 43.55 seconds |
| Started | Sep 01 06:10:54 AM UTC 24 |
| Finished | Sep 01 06:11:40 AM UTC 24 |
| Peak memory | 214188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039183909 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.4039183909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_unmapped_addr.172021314 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 21190672 ps |
| CPU time | 3.03 seconds |
| Started | Sep 01 06:10:52 AM UTC 24 |
| Finished | Sep 01 06:10:56 AM UTC 24 |
| Peak memory | 212324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172021314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.172021314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/14.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device.2937068643 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 252837610 ps |
| CPU time | 7.06 seconds |
| Started | Sep 01 06:11:00 AM UTC 24 |
| Finished | Sep 01 06:11:09 AM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937068643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.2937068643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/15.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.829732512 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 48613550105 ps |
| CPU time | 185.38 seconds |
| Started | Sep 01 06:11:00 AM UTC 24 |
| Finished | Sep 01 06:14:09 AM UTC 24 |
| Peak memory | 214244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829732512 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.829732512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.2820268723 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 344422712 ps |
| CPU time | 3.71 seconds |
| Started | Sep 01 06:11:09 AM UTC 24 |
| Finished | Sep 01 06:11:13 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820268723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2820268723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_error_random.1972214858 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 459819988 ps |
| CPU time | 11.26 seconds |
| Started | Sep 01 06:11:04 AM UTC 24 |
| Finished | Sep 01 06:11:16 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972214858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.1972214858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/15.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random.2236417372 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 797342632 ps |
| CPU time | 17.75 seconds |
| Started | Sep 01 06:10:58 AM UTC 24 |
| Finished | Sep 01 06:11:17 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236417372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2236417372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/15.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_large_delays.2478792413 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 28381360424 ps |
| CPU time | 130.74 seconds |
| Started | Sep 01 06:10:59 AM UTC 24 |
| Finished | Sep 01 06:13:12 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478792413 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2478792413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/15.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_slow_rsp.1522180310 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 13489352223 ps |
| CPU time | 93.35 seconds |
| Started | Sep 01 06:10:59 AM UTC 24 |
| Finished | Sep 01 06:12:34 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522180310 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1522180310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/15.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_zero_delays.3695020890 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 56192595 ps |
| CPU time | 3.1 seconds |
| Started | Sep 01 06:10:58 AM UTC 24 |
| Finished | Sep 01 06:11:02 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695020890 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.3695020890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/15.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_same_source.1083992407 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1106152665 ps |
| CPU time | 12.36 seconds |
| Started | Sep 01 06:11:03 AM UTC 24 |
| Finished | Sep 01 06:11:16 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083992407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1083992407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/15.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke.3423109967 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 10820077 ps |
| CPU time | 1.34 seconds |
| Started | Sep 01 06:10:57 AM UTC 24 |
| Finished | Sep 01 06:10:59 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423109967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3423109967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/15.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_large_delays.533227942 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 1642553805 ps |
| CPU time | 10.84 seconds |
| Started | Sep 01 06:10:57 AM UTC 24 |
| Finished | Sep 01 06:11:09 AM UTC 24 |
| Peak memory | 212324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533227942 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.533227942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/15.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.4279318345 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 8291704700 ps |
| CPU time | 20.43 seconds |
| Started | Sep 01 06:10:58 AM UTC 24 |
| Finished | Sep 01 06:11:20 AM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279318345 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.4279318345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.3641509306 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 8819318 ps |
| CPU time | 1.72 seconds |
| Started | Sep 01 06:10:57 AM UTC 24 |
| Finished | Sep 01 06:10:59 AM UTC 24 |
| Peak memory | 211132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641509306 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.3641509306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/15.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all.2384224549 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 228927787 ps |
| CPU time | 26.82 seconds |
| Started | Sep 01 06:11:10 AM UTC 24 |
| Finished | Sep 01 06:11:38 AM UTC 24 |
| Peak memory | 214248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384224549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.2384224549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/15.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_error.105531534 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 12667860054 ps |
| CPU time | 97.19 seconds |
| Started | Sep 01 06:11:10 AM UTC 24 |
| Finished | Sep 01 06:12:49 AM UTC 24 |
| Peak memory | 214240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105531534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.105531534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/15.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.1752409718 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 63613886 ps |
| CPU time | 6.63 seconds |
| Started | Sep 01 06:11:10 AM UTC 24 |
| Finished | Sep 01 06:11:18 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752409718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.1752409718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.580649632 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 9457590337 ps |
| CPU time | 205.53 seconds |
| Started | Sep 01 06:11:10 AM UTC 24 |
| Finished | Sep 01 06:14:39 AM UTC 24 |
| Peak memory | 218604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580649632 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.580649632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_unmapped_addr.3593660901 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1122300087 ps |
| CPU time | 12.49 seconds |
| Started | Sep 01 06:11:05 AM UTC 24 |
| Finished | Sep 01 06:11:18 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593660901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3593660901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/15.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device.796924907 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 593851654 ps |
| CPU time | 13.83 seconds |
| Started | Sep 01 06:11:18 AM UTC 24 |
| Finished | Sep 01 06:11:33 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796924907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.796924907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/16.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.1921245469 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 31938436196 ps |
| CPU time | 241.94 seconds |
| Started | Sep 01 06:11:18 AM UTC 24 |
| Finished | Sep 01 06:15:24 AM UTC 24 |
| Peak memory | 214240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921245469 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.1921245469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.3783212869 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 98583401 ps |
| CPU time | 7.96 seconds |
| Started | Sep 01 06:11:21 AM UTC 24 |
| Finished | Sep 01 06:11:30 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783212869 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.3783212869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_error_random.2790951590 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 707591449 ps |
| CPU time | 12.65 seconds |
| Started | Sep 01 06:11:21 AM UTC 24 |
| Finished | Sep 01 06:11:35 AM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790951590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.2790951590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/16.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random.1664020164 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 28608066 ps |
| CPU time | 1.79 seconds |
| Started | Sep 01 06:11:17 AM UTC 24 |
| Finished | Sep 01 06:11:20 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664020164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.1664020164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/16.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_large_delays.2801020616 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 153655914810 ps |
| CPU time | 123.38 seconds |
| Started | Sep 01 06:11:18 AM UTC 24 |
| Finished | Sep 01 06:13:24 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801020616 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2801020616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/16.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_slow_rsp.3764601465 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 26357186644 ps |
| CPU time | 111.59 seconds |
| Started | Sep 01 06:11:18 AM UTC 24 |
| Finished | Sep 01 06:13:12 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764601465 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.3764601465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/16.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_zero_delays.3933740059 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 14917548 ps |
| CPU time | 2.48 seconds |
| Started | Sep 01 06:11:18 AM UTC 24 |
| Finished | Sep 01 06:11:22 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933740059 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.3933740059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/16.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_same_source.2710912011 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 678588204 ps |
| CPU time | 5.16 seconds |
| Started | Sep 01 06:11:20 AM UTC 24 |
| Finished | Sep 01 06:11:26 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710912011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2710912011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/16.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke.3643005758 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 8789830 ps |
| CPU time | 1.83 seconds |
| Started | Sep 01 06:11:14 AM UTC 24 |
| Finished | Sep 01 06:11:17 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643005758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.3643005758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/16.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_large_delays.1358473418 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 3152357482 ps |
| CPU time | 20.55 seconds |
| Started | Sep 01 06:11:17 AM UTC 24 |
| Finished | Sep 01 06:11:38 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358473418 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1358473418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/16.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.2760913226 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 1879376722 ps |
| CPU time | 7.2 seconds |
| Started | Sep 01 06:11:17 AM UTC 24 |
| Finished | Sep 01 06:11:25 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760913226 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2760913226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.1869255247 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 12661064 ps |
| CPU time | 1.8 seconds |
| Started | Sep 01 06:11:14 AM UTC 24 |
| Finished | Sep 01 06:11:17 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869255247 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.1869255247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/16.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all.312166706 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 1295178249 ps |
| CPU time | 26.32 seconds |
| Started | Sep 01 06:11:21 AM UTC 24 |
| Finished | Sep 01 06:11:49 AM UTC 24 |
| Peak memory | 214308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312166706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.312166706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/16.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_error.2825690121 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 4412698296 ps |
| CPU time | 38.63 seconds |
| Started | Sep 01 06:11:23 AM UTC 24 |
| Finished | Sep 01 06:12:03 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825690121 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.2825690121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/16.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.487120912 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1005208058 ps |
| CPU time | 66.63 seconds |
| Started | Sep 01 06:11:24 AM UTC 24 |
| Finished | Sep 01 06:12:33 AM UTC 24 |
| Peak memory | 214188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487120912 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.487120912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_unmapped_addr.2189877323 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 261650278 ps |
| CPU time | 6.79 seconds |
| Started | Sep 01 06:11:21 AM UTC 24 |
| Finished | Sep 01 06:11:29 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189877323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.2189877323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/16.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device.1181970294 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 856329031 ps |
| CPU time | 28.71 seconds |
| Started | Sep 01 06:11:32 AM UTC 24 |
| Finished | Sep 01 06:12:02 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181970294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.1181970294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/17.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.892458654 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 61130247177 ps |
| CPU time | 444.49 seconds |
| Started | Sep 01 06:11:32 AM UTC 24 |
| Finished | Sep 01 06:19:02 AM UTC 24 |
| Peak memory | 219992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892458654 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.892458654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3934410336 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1278583542 ps |
| CPU time | 11.72 seconds |
| Started | Sep 01 06:11:37 AM UTC 24 |
| Finished | Sep 01 06:11:50 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934410336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.3934410336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_error_random.2474558149 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 670656860 ps |
| CPU time | 13.59 seconds |
| Started | Sep 01 06:11:37 AM UTC 24 |
| Finished | Sep 01 06:11:52 AM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474558149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2474558149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/17.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random.1000299388 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 43510718 ps |
| CPU time | 3.38 seconds |
| Started | Sep 01 06:11:30 AM UTC 24 |
| Finished | Sep 01 06:11:35 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000299388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.1000299388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/17.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_large_delays.712887107 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 14468292963 ps |
| CPU time | 66.51 seconds |
| Started | Sep 01 06:11:31 AM UTC 24 |
| Finished | Sep 01 06:12:39 AM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712887107 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.712887107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/17.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_slow_rsp.1910857969 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 20532122976 ps |
| CPU time | 167.85 seconds |
| Started | Sep 01 06:11:31 AM UTC 24 |
| Finished | Sep 01 06:14:21 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910857969 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.1910857969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/17.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_zero_delays.3031935915 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 393687210 ps |
| CPU time | 7.69 seconds |
| Started | Sep 01 06:11:30 AM UTC 24 |
| Finished | Sep 01 06:11:39 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031935915 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.3031935915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/17.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_same_source.3109865265 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1095061128 ps |
| CPU time | 8.68 seconds |
| Started | Sep 01 06:11:34 AM UTC 24 |
| Finished | Sep 01 06:11:44 AM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109865265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3109865265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/17.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke.2153412581 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 66989722 ps |
| CPU time | 2.43 seconds |
| Started | Sep 01 06:11:26 AM UTC 24 |
| Finished | Sep 01 06:11:29 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153412581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2153412581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/17.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_large_delays.3247054018 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 1233834332 ps |
| CPU time | 13.02 seconds |
| Started | Sep 01 06:11:27 AM UTC 24 |
| Finished | Sep 01 06:11:41 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247054018 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.3247054018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/17.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.3805206727 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 724983413 ps |
| CPU time | 7.51 seconds |
| Started | Sep 01 06:11:29 AM UTC 24 |
| Finished | Sep 01 06:11:38 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805206727 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.3805206727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.3302572315 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 11720817 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 06:11:27 AM UTC 24 |
| Finished | Sep 01 06:11:30 AM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302572315 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.3302572315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/17.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all.2983213935 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 154539750 ps |
| CPU time | 22.31 seconds |
| Started | Sep 01 06:11:37 AM UTC 24 |
| Finished | Sep 01 06:12:00 AM UTC 24 |
| Peak memory | 214376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983213935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.2983213935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/17.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_error.1767296192 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 543268129 ps |
| CPU time | 40.14 seconds |
| Started | Sep 01 06:11:39 AM UTC 24 |
| Finished | Sep 01 06:12:21 AM UTC 24 |
| Peak memory | 212324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767296192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.1767296192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/17.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.3751052397 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 10180399458 ps |
| CPU time | 141.88 seconds |
| Started | Sep 01 06:11:39 AM UTC 24 |
| Finished | Sep 01 06:14:04 AM UTC 24 |
| Peak memory | 216488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751052397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.3751052397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.3379799734 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 987307489 ps |
| CPU time | 148.63 seconds |
| Started | Sep 01 06:11:39 AM UTC 24 |
| Finished | Sep 01 06:14:11 AM UTC 24 |
| Peak memory | 218284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379799734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.3379799734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_unmapped_addr.1599946938 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 485130318 ps |
| CPU time | 15.86 seconds |
| Started | Sep 01 06:11:37 AM UTC 24 |
| Finished | Sep 01 06:11:54 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599946938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.1599946938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/17.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device.4063164249 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 25057864 ps |
| CPU time | 5.92 seconds |
| Started | Sep 01 06:11:48 AM UTC 24 |
| Finished | Sep 01 06:11:55 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063164249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.4063164249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/18.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.4117513423 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 131367382 ps |
| CPU time | 3.93 seconds |
| Started | Sep 01 06:11:53 AM UTC 24 |
| Finished | Sep 01 06:11:58 AM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117513423 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.4117513423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_error_random.4249782055 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 19670750 ps |
| CPU time | 2.05 seconds |
| Started | Sep 01 06:11:51 AM UTC 24 |
| Finished | Sep 01 06:11:54 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249782055 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.4249782055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/18.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random.96811866 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 48227651 ps |
| CPU time | 4.49 seconds |
| Started | Sep 01 06:11:43 AM UTC 24 |
| Finished | Sep 01 06:11:49 AM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96811866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.96811866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/18.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_large_delays.3330862546 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 24369081016 ps |
| CPU time | 136.18 seconds |
| Started | Sep 01 06:11:45 AM UTC 24 |
| Finished | Sep 01 06:14:04 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330862546 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.3330862546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/18.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_slow_rsp.2208661907 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 68976170800 ps |
| CPU time | 160.49 seconds |
| Started | Sep 01 06:11:45 AM UTC 24 |
| Finished | Sep 01 06:14:29 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208661907 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.2208661907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/18.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_zero_delays.3532546767 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 101529002 ps |
| CPU time | 6.37 seconds |
| Started | Sep 01 06:11:44 AM UTC 24 |
| Finished | Sep 01 06:11:51 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532546767 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.3532546767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/18.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_same_source.2732635592 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 4628055555 ps |
| CPU time | 11.94 seconds |
| Started | Sep 01 06:11:50 AM UTC 24 |
| Finished | Sep 01 06:12:03 AM UTC 24 |
| Peak memory | 212256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732635592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2732635592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/18.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke.1374100564 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 37972947 ps |
| CPU time | 2.12 seconds |
| Started | Sep 01 06:11:40 AM UTC 24 |
| Finished | Sep 01 06:11:44 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374100564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.1374100564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/18.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_large_delays.3795556768 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 1278973501 ps |
| CPU time | 11.69 seconds |
| Started | Sep 01 06:11:42 AM UTC 24 |
| Finished | Sep 01 06:11:55 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795556768 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.3795556768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/18.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.4188750906 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 3584106065 ps |
| CPU time | 19.91 seconds |
| Started | Sep 01 06:11:43 AM UTC 24 |
| Finished | Sep 01 06:12:04 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188750906 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.4188750906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.1988962348 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 9074691 ps |
| CPU time | 1.78 seconds |
| Started | Sep 01 06:11:40 AM UTC 24 |
| Finished | Sep 01 06:11:43 AM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988962348 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.1988962348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/18.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all.392929002 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 6359766121 ps |
| CPU time | 60.91 seconds |
| Started | Sep 01 06:11:54 AM UTC 24 |
| Finished | Sep 01 06:12:57 AM UTC 24 |
| Peak memory | 214436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392929002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.392929002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/18.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_error.2785124749 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1533491856 ps |
| CPU time | 31.95 seconds |
| Started | Sep 01 06:11:55 AM UTC 24 |
| Finished | Sep 01 06:12:29 AM UTC 24 |
| Peak memory | 212324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785124749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.2785124749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/18.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.2877297433 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 264425873 ps |
| CPU time | 42.59 seconds |
| Started | Sep 01 06:11:54 AM UTC 24 |
| Finished | Sep 01 06:12:38 AM UTC 24 |
| Peak memory | 216232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877297433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.2877297433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.2189916398 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 384294974 ps |
| CPU time | 81.75 seconds |
| Started | Sep 01 06:11:55 AM UTC 24 |
| Finished | Sep 01 06:13:19 AM UTC 24 |
| Peak memory | 214380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189916398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.2189916398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_unmapped_addr.4009904443 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 999448890 ps |
| CPU time | 15.78 seconds |
| Started | Sep 01 06:11:52 AM UTC 24 |
| Finished | Sep 01 06:12:09 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009904443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.4009904443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/18.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device.164210666 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 228851475 ps |
| CPU time | 4.59 seconds |
| Started | Sep 01 06:12:05 AM UTC 24 |
| Finished | Sep 01 06:12:11 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164210666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.164210666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/19.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.2092237860 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 211388685 ps |
| CPU time | 6.33 seconds |
| Started | Sep 01 06:12:11 AM UTC 24 |
| Finished | Sep 01 06:12:18 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092237860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.2092237860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_error_random.3578291595 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 66648313 ps |
| CPU time | 3.74 seconds |
| Started | Sep 01 06:12:08 AM UTC 24 |
| Finished | Sep 01 06:12:12 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578291595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.3578291595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/19.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random.2025567234 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 24498337 ps |
| CPU time | 3.94 seconds |
| Started | Sep 01 06:12:02 AM UTC 24 |
| Finished | Sep 01 06:12:07 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025567234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.2025567234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/19.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_large_delays.4180282678 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 34878476611 ps |
| CPU time | 163.8 seconds |
| Started | Sep 01 06:12:04 AM UTC 24 |
| Finished | Sep 01 06:14:50 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180282678 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.4180282678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/19.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_slow_rsp.1450315772 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 15717349035 ps |
| CPU time | 128.73 seconds |
| Started | Sep 01 06:12:05 AM UTC 24 |
| Finished | Sep 01 06:14:17 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450315772 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.1450315772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/19.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_zero_delays.2286973534 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 77462620 ps |
| CPU time | 8.68 seconds |
| Started | Sep 01 06:12:03 AM UTC 24 |
| Finished | Sep 01 06:12:13 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286973534 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.2286973534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/19.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_same_source.894645247 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1861807073 ps |
| CPU time | 18.27 seconds |
| Started | Sep 01 06:12:06 AM UTC 24 |
| Finished | Sep 01 06:12:25 AM UTC 24 |
| Peak memory | 212120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894645247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.894645247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/19.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke.1851288943 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 9467291 ps |
| CPU time | 1.55 seconds |
| Started | Sep 01 06:11:57 AM UTC 24 |
| Finished | Sep 01 06:11:59 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851288943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.1851288943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/19.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3379316808 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 2289958679 ps |
| CPU time | 8.91 seconds |
| Started | Sep 01 06:12:00 AM UTC 24 |
| Finished | Sep 01 06:12:10 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379316808 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3379316808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/19.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.1091208602 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 2872675830 ps |
| CPU time | 14.02 seconds |
| Started | Sep 01 06:12:01 AM UTC 24 |
| Finished | Sep 01 06:12:16 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091208602 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1091208602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.3618269092 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 16008483 ps |
| CPU time | 1.68 seconds |
| Started | Sep 01 06:11:59 AM UTC 24 |
| Finished | Sep 01 06:12:02 AM UTC 24 |
| Peak memory | 211132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618269092 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.3618269092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/19.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all.4258240744 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 416007103 ps |
| CPU time | 21.1 seconds |
| Started | Sep 01 06:12:13 AM UTC 24 |
| Finished | Sep 01 06:12:35 AM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258240744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.4258240744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/19.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_error.895531779 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1626625589 ps |
| CPU time | 15.24 seconds |
| Started | Sep 01 06:12:13 AM UTC 24 |
| Finished | Sep 01 06:12:29 AM UTC 24 |
| Peak memory | 212120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895531779 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.895531779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/19.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.902135263 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 799905414 ps |
| CPU time | 109.86 seconds |
| Started | Sep 01 06:12:13 AM UTC 24 |
| Finished | Sep 01 06:14:05 AM UTC 24 |
| Peak memory | 216420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902135263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.902135263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.3712172507 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 11391717317 ps |
| CPU time | 125.26 seconds |
| Started | Sep 01 06:12:14 AM UTC 24 |
| Finished | Sep 01 06:14:22 AM UTC 24 |
| Peak memory | 216296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712172507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.3712172507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_unmapped_addr.1209855257 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 48275378 ps |
| CPU time | 5.45 seconds |
| Started | Sep 01 06:12:10 AM UTC 24 |
| Finished | Sep 01 06:12:16 AM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209855257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.1209855257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/19.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device.2414648051 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 63266542 ps |
| CPU time | 12.77 seconds |
| Started | Sep 01 06:07:37 AM UTC 24 |
| Finished | Sep 01 06:07:51 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414648051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.2414648051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/2.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.1458148522 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 178412716019 ps |
| CPU time | 279.87 seconds |
| Started | Sep 01 06:07:37 AM UTC 24 |
| Finished | Sep 01 06:12:21 AM UTC 24 |
| Peak memory | 214440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458148522 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.1458148522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.2797424390 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 750337945 ps |
| CPU time | 5.35 seconds |
| Started | Sep 01 06:07:46 AM UTC 24 |
| Finished | Sep 01 06:07:52 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797424390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.2797424390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_error_random.2651649023 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 60500788 ps |
| CPU time | 8.08 seconds |
| Started | Sep 01 06:07:43 AM UTC 24 |
| Finished | Sep 01 06:07:52 AM UTC 24 |
| Peak memory | 212324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651649023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2651649023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/2.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_large_delays.2569536452 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 13346375529 ps |
| CPU time | 74.9 seconds |
| Started | Sep 01 06:07:37 AM UTC 24 |
| Finished | Sep 01 06:08:54 AM UTC 24 |
| Peak memory | 212188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569536452 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2569536452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/2.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_slow_rsp.403032356 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 9522493193 ps |
| CPU time | 77.25 seconds |
| Started | Sep 01 06:07:37 AM UTC 24 |
| Finished | Sep 01 06:08:56 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403032356 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.403032356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/2.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_zero_delays.2503239629 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 10556696 ps |
| CPU time | 1.81 seconds |
| Started | Sep 01 06:07:36 AM UTC 24 |
| Finished | Sep 01 06:07:39 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503239629 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.2503239629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/2.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_same_source.3484775145 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 101183277 ps |
| CPU time | 8.28 seconds |
| Started | Sep 01 06:07:40 AM UTC 24 |
| Finished | Sep 01 06:07:49 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484775145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3484775145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/2.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke.3373598125 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 372969917 ps |
| CPU time | 2.25 seconds |
| Started | Sep 01 06:07:33 AM UTC 24 |
| Finished | Sep 01 06:07:36 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373598125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3373598125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/2.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_large_delays.3666946722 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 2474659020 ps |
| CPU time | 14.67 seconds |
| Started | Sep 01 06:07:34 AM UTC 24 |
| Finished | Sep 01 06:07:50 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666946722 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3666946722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/2.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.4168624598 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 3350069009 ps |
| CPU time | 16.81 seconds |
| Started | Sep 01 06:07:34 AM UTC 24 |
| Finished | Sep 01 06:07:52 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168624598 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.4168624598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.252938208 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 8628812 ps |
| CPU time | 1.69 seconds |
| Started | Sep 01 06:07:33 AM UTC 24 |
| Finished | Sep 01 06:07:36 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252938208 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.252938208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/2.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all.2832848962 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 3134605386 ps |
| CPU time | 49.6 seconds |
| Started | Sep 01 06:07:47 AM UTC 24 |
| Finished | Sep 01 06:08:38 AM UTC 24 |
| Peak memory | 214248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832848962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.2832848962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/2.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_error.2399032172 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 820184238 ps |
| CPU time | 40.02 seconds |
| Started | Sep 01 06:07:47 AM UTC 24 |
| Finished | Sep 01 06:08:29 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399032172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.2399032172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/2.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_unmapped_addr.2443553958 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 2367275556 ps |
| CPU time | 15.97 seconds |
| Started | Sep 01 06:07:45 AM UTC 24 |
| Finished | Sep 01 06:08:02 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443553958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2443553958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/2.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device.3938607412 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 459823975 ps |
| CPU time | 5.97 seconds |
| Started | Sep 01 06:12:22 AM UTC 24 |
| Finished | Sep 01 06:12:29 AM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938607412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.3938607412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/20.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.1354467580 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 11007298658 ps |
| CPU time | 66.54 seconds |
| Started | Sep 01 06:12:25 AM UTC 24 |
| Finished | Sep 01 06:13:34 AM UTC 24 |
| Peak memory | 212516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354467580 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.1354467580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1847531486 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 179313731 ps |
| CPU time | 7.29 seconds |
| Started | Sep 01 06:12:30 AM UTC 24 |
| Finished | Sep 01 06:12:38 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847531486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.1847531486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_error_random.1784142870 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 45133086 ps |
| CPU time | 4.68 seconds |
| Started | Sep 01 06:12:28 AM UTC 24 |
| Finished | Sep 01 06:12:33 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784142870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.1784142870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/20.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random.2768436896 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 681736416 ps |
| CPU time | 14.23 seconds |
| Started | Sep 01 06:12:19 AM UTC 24 |
| Finished | Sep 01 06:12:34 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768436896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.2768436896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/20.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_large_delays.39780488 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 47636576029 ps |
| CPU time | 171.34 seconds |
| Started | Sep 01 06:12:21 AM UTC 24 |
| Finished | Sep 01 06:15:16 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39780488 -assert nopostproc +UVM_TESTNAME=xbar_base_ test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.39780488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/20.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_slow_rsp.2803729281 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 6581177069 ps |
| CPU time | 62.57 seconds |
| Started | Sep 01 06:12:22 AM UTC 24 |
| Finished | Sep 01 06:13:26 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803729281 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.2803729281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/20.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_zero_delays.377394649 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 119620089 ps |
| CPU time | 9.24 seconds |
| Started | Sep 01 06:12:19 AM UTC 24 |
| Finished | Sep 01 06:12:29 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377394649 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.377394649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/20.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_same_source.267663304 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 36132288 ps |
| CPU time | 3 seconds |
| Started | Sep 01 06:12:28 AM UTC 24 |
| Finished | Sep 01 06:12:32 AM UTC 24 |
| Peak memory | 212120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267663304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.267663304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/20.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke.619042701 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 8645924 ps |
| CPU time | 1.49 seconds |
| Started | Sep 01 06:12:14 AM UTC 24 |
| Finished | Sep 01 06:12:17 AM UTC 24 |
| Peak memory | 211132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619042701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.619042701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/20.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_large_delays.2776026293 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 2336653827 ps |
| CPU time | 8.49 seconds |
| Started | Sep 01 06:12:17 AM UTC 24 |
| Finished | Sep 01 06:12:27 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776026293 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2776026293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/20.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.3824218197 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 1443952687 ps |
| CPU time | 24.08 seconds |
| Started | Sep 01 06:12:17 AM UTC 24 |
| Finished | Sep 01 06:12:43 AM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824218197 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.3824218197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.1122167349 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 8456812 ps |
| CPU time | 1.76 seconds |
| Started | Sep 01 06:12:17 AM UTC 24 |
| Finished | Sep 01 06:12:20 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122167349 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.1122167349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/20.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all.3968863611 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 603115665 ps |
| CPU time | 55.53 seconds |
| Started | Sep 01 06:12:30 AM UTC 24 |
| Finished | Sep 01 06:13:27 AM UTC 24 |
| Peak memory | 214504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968863611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3968863611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/20.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_error.2154822689 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 729042534 ps |
| CPU time | 37.26 seconds |
| Started | Sep 01 06:12:30 AM UTC 24 |
| Finished | Sep 01 06:13:09 AM UTC 24 |
| Peak memory | 212324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154822689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.2154822689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/20.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.239748636 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 825782194 ps |
| CPU time | 133.6 seconds |
| Started | Sep 01 06:12:30 AM UTC 24 |
| Finished | Sep 01 06:14:46 AM UTC 24 |
| Peak memory | 216292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239748636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.239748636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.3944788757 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 8348304633 ps |
| CPU time | 75.2 seconds |
| Started | Sep 01 06:12:32 AM UTC 24 |
| Finished | Sep 01 06:13:49 AM UTC 24 |
| Peak memory | 218348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944788757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.3944788757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_unmapped_addr.1443937099 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 399182330 ps |
| CPU time | 6.25 seconds |
| Started | Sep 01 06:12:29 AM UTC 24 |
| Finished | Sep 01 06:12:36 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443937099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1443937099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/20.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device.2547530410 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 702793362 ps |
| CPU time | 8.57 seconds |
| Started | Sep 01 06:12:39 AM UTC 24 |
| Finished | Sep 01 06:12:48 AM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547530410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.2547530410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/21.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.1618943343 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 74309139923 ps |
| CPU time | 431.34 seconds |
| Started | Sep 01 06:12:39 AM UTC 24 |
| Finished | Sep 01 06:19:56 AM UTC 24 |
| Peak memory | 220120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618943343 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.1618943343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.3289291717 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 2287862328 ps |
| CPU time | 13.59 seconds |
| Started | Sep 01 06:12:43 AM UTC 24 |
| Finished | Sep 01 06:12:58 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289291717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.3289291717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_error_random.3144730671 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 731362022 ps |
| CPU time | 16.93 seconds |
| Started | Sep 01 06:12:40 AM UTC 24 |
| Finished | Sep 01 06:12:58 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144730671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3144730671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/21.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random.2959269209 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 2329398947 ps |
| CPU time | 15.28 seconds |
| Started | Sep 01 06:12:35 AM UTC 24 |
| Finished | Sep 01 06:12:51 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959269209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.2959269209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/21.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_large_delays.2472707043 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 39541017905 ps |
| CPU time | 222.11 seconds |
| Started | Sep 01 06:12:36 AM UTC 24 |
| Finished | Sep 01 06:16:21 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472707043 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2472707043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/21.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_slow_rsp.2923261983 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 9458423611 ps |
| CPU time | 75.56 seconds |
| Started | Sep 01 06:12:37 AM UTC 24 |
| Finished | Sep 01 06:13:55 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923261983 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.2923261983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/21.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_zero_delays.484506612 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 91401581 ps |
| CPU time | 9.51 seconds |
| Started | Sep 01 06:12:36 AM UTC 24 |
| Finished | Sep 01 06:12:47 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484506612 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.484506612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/21.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_same_source.2846363960 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 124271220 ps |
| CPU time | 4.31 seconds |
| Started | Sep 01 06:12:40 AM UTC 24 |
| Finished | Sep 01 06:12:45 AM UTC 24 |
| Peak memory | 212384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846363960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2846363960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/21.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke.390923431 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 71903218 ps |
| CPU time | 2.71 seconds |
| Started | Sep 01 06:12:34 AM UTC 24 |
| Finished | Sep 01 06:12:37 AM UTC 24 |
| Peak memory | 212120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390923431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.390923431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/21.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_large_delays.4197277543 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 2747645111 ps |
| CPU time | 15.32 seconds |
| Started | Sep 01 06:12:35 AM UTC 24 |
| Finished | Sep 01 06:12:51 AM UTC 24 |
| Peak memory | 212324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197277543 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.4197277543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/21.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.4071512226 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 1570699067 ps |
| CPU time | 17.83 seconds |
| Started | Sep 01 06:12:35 AM UTC 24 |
| Finished | Sep 01 06:12:54 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071512226 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.4071512226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.1537511144 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 9758514 ps |
| CPU time | 1.78 seconds |
| Started | Sep 01 06:12:35 AM UTC 24 |
| Finished | Sep 01 06:12:38 AM UTC 24 |
| Peak memory | 211132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537511144 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.1537511144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/21.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all.1884691149 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 2702626030 ps |
| CPU time | 45.1 seconds |
| Started | Sep 01 06:12:46 AM UTC 24 |
| Finished | Sep 01 06:13:33 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884691149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1884691149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/21.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_error.2458201470 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 8718545528 ps |
| CPU time | 75.19 seconds |
| Started | Sep 01 06:12:49 AM UTC 24 |
| Finished | Sep 01 06:14:06 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458201470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.2458201470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/21.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.843022411 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 415474959 ps |
| CPU time | 48.15 seconds |
| Started | Sep 01 06:12:48 AM UTC 24 |
| Finished | Sep 01 06:13:37 AM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843022411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.843022411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.3533589789 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 209775582 ps |
| CPU time | 29.53 seconds |
| Started | Sep 01 06:12:49 AM UTC 24 |
| Finished | Sep 01 06:13:20 AM UTC 24 |
| Peak memory | 214188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533589789 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.3533589789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_unmapped_addr.2041587949 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 906435775 ps |
| CPU time | 14.96 seconds |
| Started | Sep 01 06:12:40 AM UTC 24 |
| Finished | Sep 01 06:12:56 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041587949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.2041587949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/21.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device.620215150 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 159335622 ps |
| CPU time | 3.96 seconds |
| Started | Sep 01 06:12:57 AM UTC 24 |
| Finished | Sep 01 06:13:03 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620215150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.620215150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/22.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.679103259 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 13171311491 ps |
| CPU time | 121.63 seconds |
| Started | Sep 01 06:12:59 AM UTC 24 |
| Finished | Sep 01 06:15:03 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679103259 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.679103259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.3621549705 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 562140449 ps |
| CPU time | 6.05 seconds |
| Started | Sep 01 06:13:04 AM UTC 24 |
| Finished | Sep 01 06:13:11 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621549705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.3621549705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_error_random.1645217766 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 4154099582 ps |
| CPU time | 17.32 seconds |
| Started | Sep 01 06:12:59 AM UTC 24 |
| Finished | Sep 01 06:13:18 AM UTC 24 |
| Peak memory | 212188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645217766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1645217766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/22.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random.3533939710 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 595928252 ps |
| CPU time | 7.78 seconds |
| Started | Sep 01 06:12:54 AM UTC 24 |
| Finished | Sep 01 06:13:03 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533939710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.3533939710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/22.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_large_delays.4077956987 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 9192066661 ps |
| CPU time | 15.03 seconds |
| Started | Sep 01 06:12:57 AM UTC 24 |
| Finished | Sep 01 06:13:14 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077956987 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.4077956987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/22.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_slow_rsp.3083173397 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 112081512897 ps |
| CPU time | 184.4 seconds |
| Started | Sep 01 06:12:57 AM UTC 24 |
| Finished | Sep 01 06:16:05 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083173397 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.3083173397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/22.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_zero_delays.779657275 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 71048021 ps |
| CPU time | 10.05 seconds |
| Started | Sep 01 06:12:55 AM UTC 24 |
| Finished | Sep 01 06:13:06 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779657275 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.779657275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/22.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_same_source.914530260 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 34687676 ps |
| CPU time | 5.37 seconds |
| Started | Sep 01 06:12:59 AM UTC 24 |
| Finished | Sep 01 06:13:06 AM UTC 24 |
| Peak memory | 212312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914530260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.914530260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/22.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke.2142201900 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 14224389 ps |
| CPU time | 1.8 seconds |
| Started | Sep 01 06:12:50 AM UTC 24 |
| Finished | Sep 01 06:12:53 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142201900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2142201900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/22.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_large_delays.666891674 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 1736931449 ps |
| CPU time | 17.23 seconds |
| Started | Sep 01 06:12:53 AM UTC 24 |
| Finished | Sep 01 06:13:12 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666891674 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.666891674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/22.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.3227643077 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 9663104745 ps |
| CPU time | 16.53 seconds |
| Started | Sep 01 06:12:53 AM UTC 24 |
| Finished | Sep 01 06:13:11 AM UTC 24 |
| Peak memory | 212512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227643077 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3227643077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.3002570216 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 8796519 ps |
| CPU time | 1.75 seconds |
| Started | Sep 01 06:12:53 AM UTC 24 |
| Finished | Sep 01 06:12:56 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002570216 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.3002570216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/22.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all.2171739385 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 317637359 ps |
| CPU time | 45.15 seconds |
| Started | Sep 01 06:13:05 AM UTC 24 |
| Finished | Sep 01 06:13:52 AM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171739385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2171739385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/22.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_error.1750202217 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 905159263 ps |
| CPU time | 8.61 seconds |
| Started | Sep 01 06:13:08 AM UTC 24 |
| Finished | Sep 01 06:13:17 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750202217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.1750202217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/22.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.2654479125 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 818658667 ps |
| CPU time | 87.5 seconds |
| Started | Sep 01 06:13:06 AM UTC 24 |
| Finished | Sep 01 06:14:36 AM UTC 24 |
| Peak memory | 216488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654479125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.2654479125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.2017988729 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 59915784 ps |
| CPU time | 19.83 seconds |
| Started | Sep 01 06:13:10 AM UTC 24 |
| Finished | Sep 01 06:13:31 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017988729 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.2017988729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_unmapped_addr.3058910484 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 63001205 ps |
| CPU time | 6.67 seconds |
| Started | Sep 01 06:13:04 AM UTC 24 |
| Finished | Sep 01 06:13:12 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058910484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3058910484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/22.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device.4104317550 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 66081983 ps |
| CPU time | 12.29 seconds |
| Started | Sep 01 06:13:17 AM UTC 24 |
| Finished | Sep 01 06:13:30 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104317550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.4104317550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/23.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1029535425 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 109225199 ps |
| CPU time | 2.25 seconds |
| Started | Sep 01 06:13:19 AM UTC 24 |
| Finished | Sep 01 06:13:22 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029535425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.1029535425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_error_random.3438647994 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 141788868 ps |
| CPU time | 2.64 seconds |
| Started | Sep 01 06:13:18 AM UTC 24 |
| Finished | Sep 01 06:13:22 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438647994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3438647994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/23.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random.2298287912 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 427904234 ps |
| CPU time | 10.05 seconds |
| Started | Sep 01 06:13:13 AM UTC 24 |
| Finished | Sep 01 06:13:25 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298287912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.2298287912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/23.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_large_delays.904214704 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 6169056146 ps |
| CPU time | 39.11 seconds |
| Started | Sep 01 06:13:15 AM UTC 24 |
| Finished | Sep 01 06:13:55 AM UTC 24 |
| Peak memory | 212188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904214704 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.904214704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/23.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_slow_rsp.2799436263 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 68122747266 ps |
| CPU time | 120.12 seconds |
| Started | Sep 01 06:13:17 AM UTC 24 |
| Finished | Sep 01 06:15:19 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799436263 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.2799436263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/23.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_zero_delays.435892651 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 232662258 ps |
| CPU time | 6.89 seconds |
| Started | Sep 01 06:13:14 AM UTC 24 |
| Finished | Sep 01 06:13:22 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435892651 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.435892651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/23.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_same_source.3104162132 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 51660229 ps |
| CPU time | 4.81 seconds |
| Started | Sep 01 06:13:17 AM UTC 24 |
| Finished | Sep 01 06:13:23 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104162132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3104162132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/23.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke.3229680705 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 8467699 ps |
| CPU time | 1.72 seconds |
| Started | Sep 01 06:13:12 AM UTC 24 |
| Finished | Sep 01 06:13:15 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229680705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.3229680705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/23.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_large_delays.691681969 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 8986651876 ps |
| CPU time | 14.12 seconds |
| Started | Sep 01 06:13:12 AM UTC 24 |
| Finished | Sep 01 06:13:28 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691681969 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.691681969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/23.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.2364216688 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 1692028551 ps |
| CPU time | 7.77 seconds |
| Started | Sep 01 06:13:13 AM UTC 24 |
| Finished | Sep 01 06:13:22 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364216688 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.2364216688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.3913375023 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 14850296 ps |
| CPU time | 1.91 seconds |
| Started | Sep 01 06:13:12 AM UTC 24 |
| Finished | Sep 01 06:13:15 AM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913375023 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.3913375023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/23.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all.2377842802 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 305973868 ps |
| CPU time | 36.82 seconds |
| Started | Sep 01 06:13:21 AM UTC 24 |
| Finished | Sep 01 06:13:59 AM UTC 24 |
| Peak memory | 214440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377842802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2377842802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/23.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_error.2320797143 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 445255478 ps |
| CPU time | 37.84 seconds |
| Started | Sep 01 06:13:22 AM UTC 24 |
| Finished | Sep 01 06:14:02 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320797143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2320797143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/23.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.2275449778 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 1636382976 ps |
| CPU time | 40.07 seconds |
| Started | Sep 01 06:13:21 AM UTC 24 |
| Finished | Sep 01 06:14:03 AM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275449778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.2275449778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.1406625834 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 3101105542 ps |
| CPU time | 58.57 seconds |
| Started | Sep 01 06:13:23 AM UTC 24 |
| Finished | Sep 01 06:14:23 AM UTC 24 |
| Peak memory | 214444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406625834 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.1406625834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_unmapped_addr.7899576 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 41857405 ps |
| CPU time | 4.66 seconds |
| Started | Sep 01 06:13:18 AM UTC 24 |
| Finished | Sep 01 06:13:24 AM UTC 24 |
| Peak memory | 212324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7899576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_T EST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.7899576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/23.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device.3428402758 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 15028619 ps |
| CPU time | 3.26 seconds |
| Started | Sep 01 06:13:28 AM UTC 24 |
| Finished | Sep 01 06:13:32 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428402758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.3428402758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/24.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.491772227 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 49714910038 ps |
| CPU time | 270.39 seconds |
| Started | Sep 01 06:13:28 AM UTC 24 |
| Finished | Sep 01 06:18:02 AM UTC 24 |
| Peak memory | 214244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491772227 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.491772227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.3174398926 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 427287240 ps |
| CPU time | 8.81 seconds |
| Started | Sep 01 06:13:31 AM UTC 24 |
| Finished | Sep 01 06:13:41 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174398926 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.3174398926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_error_random.383852523 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 1276191886 ps |
| CPU time | 6.97 seconds |
| Started | Sep 01 06:13:29 AM UTC 24 |
| Finished | Sep 01 06:13:37 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383852523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.383852523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/24.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random.4124843864 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 211423992 ps |
| CPU time | 2.33 seconds |
| Started | Sep 01 06:13:25 AM UTC 24 |
| Finished | Sep 01 06:13:29 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124843864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.4124843864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/24.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_large_delays.1853319100 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 20142992543 ps |
| CPU time | 60.99 seconds |
| Started | Sep 01 06:13:25 AM UTC 24 |
| Finished | Sep 01 06:14:28 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853319100 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1853319100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/24.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_slow_rsp.53628046 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 11398966261 ps |
| CPU time | 94.53 seconds |
| Started | Sep 01 06:13:28 AM UTC 24 |
| Finished | Sep 01 06:15:04 AM UTC 24 |
| Peak memory | 212380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53628046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.53628046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/24.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_zero_delays.409743730 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 79466897 ps |
| CPU time | 9.63 seconds |
| Started | Sep 01 06:13:25 AM UTC 24 |
| Finished | Sep 01 06:13:36 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409743730 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.409743730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/24.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_same_source.789121775 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 2041923694 ps |
| CPU time | 17.68 seconds |
| Started | Sep 01 06:13:29 AM UTC 24 |
| Finished | Sep 01 06:13:48 AM UTC 24 |
| Peak memory | 212380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789121775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.789121775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/24.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke.1782277284 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 97941591 ps |
| CPU time | 2.47 seconds |
| Started | Sep 01 06:13:24 AM UTC 24 |
| Finished | Sep 01 06:13:28 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782277284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1782277284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/24.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_large_delays.3382165917 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 6978930196 ps |
| CPU time | 13.11 seconds |
| Started | Sep 01 06:13:24 AM UTC 24 |
| Finished | Sep 01 06:13:38 AM UTC 24 |
| Peak memory | 211660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382165917 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3382165917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/24.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.824098055 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 8851671835 ps |
| CPU time | 23.56 seconds |
| Started | Sep 01 06:13:25 AM UTC 24 |
| Finished | Sep 01 06:13:50 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824098055 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.824098055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1412063945 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 18170053 ps |
| CPU time | 1.67 seconds |
| Started | Sep 01 06:13:24 AM UTC 24 |
| Finished | Sep 01 06:13:27 AM UTC 24 |
| Peak memory | 210536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412063945 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1412063945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/24.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all.3546520035 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1908724843 ps |
| CPU time | 29.43 seconds |
| Started | Sep 01 06:13:33 AM UTC 24 |
| Finished | Sep 01 06:14:03 AM UTC 24 |
| Peak memory | 214440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546520035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.3546520035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/24.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_error.353986447 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 5796948136 ps |
| CPU time | 22.74 seconds |
| Started | Sep 01 06:13:34 AM UTC 24 |
| Finished | Sep 01 06:13:58 AM UTC 24 |
| Peak memory | 212384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353986447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.353986447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/24.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.313660737 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 311629313 ps |
| CPU time | 55.28 seconds |
| Started | Sep 01 06:13:33 AM UTC 24 |
| Finished | Sep 01 06:14:30 AM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313660737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.313660737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.3025821784 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 123431794 ps |
| CPU time | 10.57 seconds |
| Started | Sep 01 06:13:34 AM UTC 24 |
| Finished | Sep 01 06:13:46 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025821784 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.3025821784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_unmapped_addr.1832155526 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 62176195 ps |
| CPU time | 5.65 seconds |
| Started | Sep 01 06:13:30 AM UTC 24 |
| Finished | Sep 01 06:13:37 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832155526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1832155526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/24.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device.4003382085 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 159462712 ps |
| CPU time | 5.98 seconds |
| Started | Sep 01 06:13:40 AM UTC 24 |
| Finished | Sep 01 06:13:47 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003382085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.4003382085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/25.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.1167692858 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 1626952349 ps |
| CPU time | 16.35 seconds |
| Started | Sep 01 06:13:48 AM UTC 24 |
| Finished | Sep 01 06:14:05 AM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167692858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.1167692858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_error_random.172434467 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 341765432 ps |
| CPU time | 6.46 seconds |
| Started | Sep 01 06:13:45 AM UTC 24 |
| Finished | Sep 01 06:13:53 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172434467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.172434467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/25.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random.611552136 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 508747321 ps |
| CPU time | 17.87 seconds |
| Started | Sep 01 06:13:40 AM UTC 24 |
| Finished | Sep 01 06:13:59 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611552136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.611552136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/25.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_large_delays.4222772346 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 7151190193 ps |
| CPU time | 62.3 seconds |
| Started | Sep 01 06:13:40 AM UTC 24 |
| Finished | Sep 01 06:14:44 AM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222772346 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.4222772346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/25.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_slow_rsp.1518855737 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 12498469627 ps |
| CPU time | 107.74 seconds |
| Started | Sep 01 06:13:40 AM UTC 24 |
| Finished | Sep 01 06:15:30 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518855737 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1518855737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/25.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_zero_delays.3794669849 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 36805021 ps |
| CPU time | 3.72 seconds |
| Started | Sep 01 06:13:40 AM UTC 24 |
| Finished | Sep 01 06:13:44 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794669849 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.3794669849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/25.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_same_source.2145452355 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 60512250 ps |
| CPU time | 7.07 seconds |
| Started | Sep 01 06:13:42 AM UTC 24 |
| Finished | Sep 01 06:13:50 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145452355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2145452355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/25.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke.3129637644 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 57921447 ps |
| CPU time | 2.33 seconds |
| Started | Sep 01 06:13:35 AM UTC 24 |
| Finished | Sep 01 06:13:39 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129637644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.3129637644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/25.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_large_delays.3174793311 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 4173328485 ps |
| CPU time | 12.9 seconds |
| Started | Sep 01 06:13:40 AM UTC 24 |
| Finished | Sep 01 06:13:54 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174793311 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3174793311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/25.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.81131402 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 4232600860 ps |
| CPU time | 21.14 seconds |
| Started | Sep 01 06:13:40 AM UTC 24 |
| Finished | Sep 01 06:14:02 AM UTC 24 |
| Peak memory | 212188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81131402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.81131402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.1497225833 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 11958245 ps |
| CPU time | 1.69 seconds |
| Started | Sep 01 06:13:37 AM UTC 24 |
| Finished | Sep 01 06:13:40 AM UTC 24 |
| Peak memory | 211132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497225833 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.1497225833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/25.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all.670477276 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 9562832268 ps |
| CPU time | 114.47 seconds |
| Started | Sep 01 06:13:49 AM UTC 24 |
| Finished | Sep 01 06:15:46 AM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670477276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.670477276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/25.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_error.855610173 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 3725441523 ps |
| CPU time | 76.67 seconds |
| Started | Sep 01 06:13:51 AM UTC 24 |
| Finished | Sep 01 06:15:10 AM UTC 24 |
| Peak memory | 212188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855610173 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.855610173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/25.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.3005118654 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 360288186 ps |
| CPU time | 46.54 seconds |
| Started | Sep 01 06:13:50 AM UTC 24 |
| Finished | Sep 01 06:14:38 AM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005118654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.3005118654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.3929024642 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 3967254829 ps |
| CPU time | 60.94 seconds |
| Started | Sep 01 06:13:51 AM UTC 24 |
| Finished | Sep 01 06:14:54 AM UTC 24 |
| Peak memory | 214248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929024642 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.3929024642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_unmapped_addr.2858612600 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 85214673 ps |
| CPU time | 9.68 seconds |
| Started | Sep 01 06:13:47 AM UTC 24 |
| Finished | Sep 01 06:13:57 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858612600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.2858612600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/25.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device.1306100489 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 219657831 ps |
| CPU time | 11.48 seconds |
| Started | Sep 01 06:13:59 AM UTC 24 |
| Finished | Sep 01 06:14:11 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306100489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.1306100489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/26.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.1845245350 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 1999356049 ps |
| CPU time | 12.3 seconds |
| Started | Sep 01 06:14:02 AM UTC 24 |
| Finished | Sep 01 06:14:15 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845245350 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.1845245350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_error_random.2181724788 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 853467538 ps |
| CPU time | 19.68 seconds |
| Started | Sep 01 06:14:00 AM UTC 24 |
| Finished | Sep 01 06:14:21 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181724788 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2181724788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/26.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random.3281848503 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 119113565 ps |
| CPU time | 2.52 seconds |
| Started | Sep 01 06:13:56 AM UTC 24 |
| Finished | Sep 01 06:14:00 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281848503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.3281848503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/26.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_large_delays.1892187750 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 25632662612 ps |
| CPU time | 70.96 seconds |
| Started | Sep 01 06:13:59 AM UTC 24 |
| Finished | Sep 01 06:15:11 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892187750 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1892187750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/26.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_slow_rsp.1870411872 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 13113065873 ps |
| CPU time | 112.54 seconds |
| Started | Sep 01 06:13:59 AM UTC 24 |
| Finished | Sep 01 06:15:53 AM UTC 24 |
| Peak memory | 212456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870411872 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1870411872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/26.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_zero_delays.1163775451 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 28897189 ps |
| CPU time | 5.78 seconds |
| Started | Sep 01 06:13:57 AM UTC 24 |
| Finished | Sep 01 06:14:04 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163775451 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.1163775451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/26.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_same_source.936731445 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 41662802 ps |
| CPU time | 5.41 seconds |
| Started | Sep 01 06:14:00 AM UTC 24 |
| Finished | Sep 01 06:14:07 AM UTC 24 |
| Peak memory | 212312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936731445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.936731445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/26.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke.394646524 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 71094355 ps |
| CPU time | 2.65 seconds |
| Started | Sep 01 06:13:53 AM UTC 24 |
| Finished | Sep 01 06:13:56 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394646524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.394646524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/26.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_large_delays.2855381220 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 5829066302 ps |
| CPU time | 13.59 seconds |
| Started | Sep 01 06:13:55 AM UTC 24 |
| Finished | Sep 01 06:14:10 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855381220 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2855381220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/26.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.3254032013 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 1477639504 ps |
| CPU time | 8.34 seconds |
| Started | Sep 01 06:13:56 AM UTC 24 |
| Finished | Sep 01 06:14:06 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254032013 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.3254032013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.1677902241 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 35912713 ps |
| CPU time | 1.96 seconds |
| Started | Sep 01 06:13:54 AM UTC 24 |
| Finished | Sep 01 06:13:58 AM UTC 24 |
| Peak memory | 211132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677902241 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.1677902241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/26.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all.1355971980 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 646437505 ps |
| CPU time | 44.72 seconds |
| Started | Sep 01 06:14:03 AM UTC 24 |
| Finished | Sep 01 06:14:49 AM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355971980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.1355971980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/26.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1412258362 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 4873725840 ps |
| CPU time | 68.89 seconds |
| Started | Sep 01 06:14:04 AM UTC 24 |
| Finished | Sep 01 06:15:15 AM UTC 24 |
| Peak memory | 216484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412258362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1412258362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/26.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.2883120340 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 66584135 ps |
| CPU time | 4.19 seconds |
| Started | Sep 01 06:14:03 AM UTC 24 |
| Finished | Sep 01 06:14:08 AM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883120340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.2883120340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.1239033239 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 277337481 ps |
| CPU time | 37.92 seconds |
| Started | Sep 01 06:14:04 AM UTC 24 |
| Finished | Sep 01 06:14:44 AM UTC 24 |
| Peak memory | 214444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239033239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.1239033239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_unmapped_addr.1519162132 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 27444188 ps |
| CPU time | 3.15 seconds |
| Started | Sep 01 06:14:00 AM UTC 24 |
| Finished | Sep 01 06:14:05 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519162132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.1519162132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/26.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device.261919359 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 1580894754 ps |
| CPU time | 10.03 seconds |
| Started | Sep 01 06:14:08 AM UTC 24 |
| Finished | Sep 01 06:14:19 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261919359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.261919359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/27.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2022577441 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 66336744776 ps |
| CPU time | 356.3 seconds |
| Started | Sep 01 06:14:08 AM UTC 24 |
| Finished | Sep 01 06:20:09 AM UTC 24 |
| Peak memory | 216024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022577441 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.2022577441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.100015914 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 21548455 ps |
| CPU time | 2.6 seconds |
| Started | Sep 01 06:14:11 AM UTC 24 |
| Finished | Sep 01 06:14:15 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100015914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.100015914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_error_random.2398419153 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 194526018 ps |
| CPU time | 3.67 seconds |
| Started | Sep 01 06:14:10 AM UTC 24 |
| Finished | Sep 01 06:14:14 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398419153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2398419153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/27.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random.2202485358 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 44053999 ps |
| CPU time | 6.84 seconds |
| Started | Sep 01 06:14:06 AM UTC 24 |
| Finished | Sep 01 06:14:14 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202485358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.2202485358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/27.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_large_delays.926010697 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 31232951374 ps |
| CPU time | 70.99 seconds |
| Started | Sep 01 06:14:07 AM UTC 24 |
| Finished | Sep 01 06:15:19 AM UTC 24 |
| Peak memory | 212380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926010697 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.926010697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/27.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_slow_rsp.2607221002 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 37244734217 ps |
| CPU time | 69.09 seconds |
| Started | Sep 01 06:14:08 AM UTC 24 |
| Finished | Sep 01 06:15:19 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607221002 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.2607221002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/27.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_zero_delays.1442170534 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 68862277 ps |
| CPU time | 10.1 seconds |
| Started | Sep 01 06:14:06 AM UTC 24 |
| Finished | Sep 01 06:14:18 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442170534 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.1442170534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/27.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_same_source.3354810761 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 63126931 ps |
| CPU time | 2.61 seconds |
| Started | Sep 01 06:14:10 AM UTC 24 |
| Finished | Sep 01 06:14:13 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354810761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.3354810761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/27.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke.1093480141 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 59770257 ps |
| CPU time | 2.64 seconds |
| Started | Sep 01 06:14:06 AM UTC 24 |
| Finished | Sep 01 06:14:10 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093480141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.1093480141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/27.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_large_delays.2582948525 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 5401963711 ps |
| CPU time | 24.16 seconds |
| Started | Sep 01 06:14:06 AM UTC 24 |
| Finished | Sep 01 06:14:32 AM UTC 24 |
| Peak memory | 212188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582948525 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2582948525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/27.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.2477448078 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 1517304183 ps |
| CPU time | 12.68 seconds |
| Started | Sep 01 06:14:06 AM UTC 24 |
| Finished | Sep 01 06:14:20 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477448078 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.2477448078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.3911832429 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 12344317 ps |
| CPU time | 1.84 seconds |
| Started | Sep 01 06:14:06 AM UTC 24 |
| Finished | Sep 01 06:14:09 AM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911832429 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.3911832429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/27.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all.3154363715 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 4342551185 ps |
| CPU time | 86.77 seconds |
| Started | Sep 01 06:14:11 AM UTC 24 |
| Finished | Sep 01 06:15:40 AM UTC 24 |
| Peak memory | 214240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154363715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.3154363715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/27.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_error.2598062004 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 5427641304 ps |
| CPU time | 69.66 seconds |
| Started | Sep 01 06:14:13 AM UTC 24 |
| Finished | Sep 01 06:15:24 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598062004 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2598062004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/27.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.2513368105 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 4092642142 ps |
| CPU time | 77.36 seconds |
| Started | Sep 01 06:14:13 AM UTC 24 |
| Finished | Sep 01 06:15:32 AM UTC 24 |
| Peak memory | 214504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513368105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.2513368105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_unmapped_addr.2388016697 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 22548438 ps |
| CPU time | 2.21 seconds |
| Started | Sep 01 06:14:10 AM UTC 24 |
| Finished | Sep 01 06:14:13 AM UTC 24 |
| Peak memory | 212256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388016697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2388016697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/27.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device.280994696 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 574763130 ps |
| CPU time | 19.05 seconds |
| Started | Sep 01 06:14:18 AM UTC 24 |
| Finished | Sep 01 06:14:38 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280994696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.280994696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/28.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.1387920435 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 43166952349 ps |
| CPU time | 251.99 seconds |
| Started | Sep 01 06:14:19 AM UTC 24 |
| Finished | Sep 01 06:18:35 AM UTC 24 |
| Peak memory | 214240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387920435 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.1387920435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.2003638226 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 172471047 ps |
| CPU time | 3.88 seconds |
| Started | Sep 01 06:14:21 AM UTC 24 |
| Finished | Sep 01 06:14:26 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003638226 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.2003638226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_error_random.1274334141 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 1298754915 ps |
| CPU time | 11.92 seconds |
| Started | Sep 01 06:14:19 AM UTC 24 |
| Finished | Sep 01 06:14:32 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274334141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.1274334141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/28.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random.3992301037 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 1329768795 ps |
| CPU time | 16.13 seconds |
| Started | Sep 01 06:14:18 AM UTC 24 |
| Finished | Sep 01 06:14:35 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992301037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.3992301037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/28.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_large_delays.4195209866 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 28428700821 ps |
| CPU time | 149.67 seconds |
| Started | Sep 01 06:14:18 AM UTC 24 |
| Finished | Sep 01 06:16:50 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195209866 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.4195209866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/28.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_slow_rsp.3465493867 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 37102446540 ps |
| CPU time | 150.79 seconds |
| Started | Sep 01 06:14:18 AM UTC 24 |
| Finished | Sep 01 06:16:51 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465493867 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.3465493867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/28.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_zero_delays.2441056854 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 32378831 ps |
| CPU time | 5.25 seconds |
| Started | Sep 01 06:14:18 AM UTC 24 |
| Finished | Sep 01 06:14:24 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441056854 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.2441056854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/28.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_same_source.306712261 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 17807606 ps |
| CPU time | 2.59 seconds |
| Started | Sep 01 06:14:19 AM UTC 24 |
| Finished | Sep 01 06:14:23 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306712261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.306712261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/28.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke.3617669447 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 12796293 ps |
| CPU time | 1.7 seconds |
| Started | Sep 01 06:14:14 AM UTC 24 |
| Finished | Sep 01 06:14:17 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617669447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.3617669447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/28.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_large_delays.1926202007 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 3575558291 ps |
| CPU time | 13.49 seconds |
| Started | Sep 01 06:14:15 AM UTC 24 |
| Finished | Sep 01 06:14:30 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926202007 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.1926202007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/28.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.2910249225 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 2503551857 ps |
| CPU time | 21.02 seconds |
| Started | Sep 01 06:14:16 AM UTC 24 |
| Finished | Sep 01 06:14:38 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910249225 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.2910249225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.2273554102 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 10791102 ps |
| CPU time | 1.79 seconds |
| Started | Sep 01 06:14:15 AM UTC 24 |
| Finished | Sep 01 06:14:18 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273554102 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.2273554102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/28.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all.4043001342 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 4191308459 ps |
| CPU time | 38.25 seconds |
| Started | Sep 01 06:14:22 AM UTC 24 |
| Finished | Sep 01 06:15:02 AM UTC 24 |
| Peak memory | 214444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043001342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.4043001342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/28.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_error.2050574220 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 7546868466 ps |
| CPU time | 70.49 seconds |
| Started | Sep 01 06:14:24 AM UTC 24 |
| Finished | Sep 01 06:15:36 AM UTC 24 |
| Peak memory | 212260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050574220 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2050574220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/28.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.815109881 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 653165195 ps |
| CPU time | 104.79 seconds |
| Started | Sep 01 06:14:22 AM UTC 24 |
| Finished | Sep 01 06:16:09 AM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815109881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.815109881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.2256873825 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 5063731257 ps |
| CPU time | 102.41 seconds |
| Started | Sep 01 06:14:24 AM UTC 24 |
| Finished | Sep 01 06:16:08 AM UTC 24 |
| Peak memory | 214248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256873825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.2256873825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_unmapped_addr.926265629 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 867388290 ps |
| CPU time | 10.59 seconds |
| Started | Sep 01 06:14:21 AM UTC 24 |
| Finished | Sep 01 06:14:32 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926265629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.926265629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/28.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device.1163321642 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 1040455578 ps |
| CPU time | 8.93 seconds |
| Started | Sep 01 06:14:31 AM UTC 24 |
| Finished | Sep 01 06:14:42 AM UTC 24 |
| Peak memory | 212140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163321642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.1163321642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/29.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1992826009 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 37242645755 ps |
| CPU time | 282.18 seconds |
| Started | Sep 01 06:14:33 AM UTC 24 |
| Finished | Sep 01 06:19:19 AM UTC 24 |
| Peak memory | 214244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992826009 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.1992826009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.1557241768 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 14452625 ps |
| CPU time | 1.56 seconds |
| Started | Sep 01 06:14:36 AM UTC 24 |
| Finished | Sep 01 06:14:39 AM UTC 24 |
| Peak memory | 211184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557241768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.1557241768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_error_random.4115948887 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 1389415282 ps |
| CPU time | 10.33 seconds |
| Started | Sep 01 06:14:34 AM UTC 24 |
| Finished | Sep 01 06:14:45 AM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115948887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.4115948887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/29.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random.1008214302 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 392813289 ps |
| CPU time | 8.56 seconds |
| Started | Sep 01 06:14:29 AM UTC 24 |
| Finished | Sep 01 06:14:38 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008214302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.1008214302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/29.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_large_delays.3783993150 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 7496491550 ps |
| CPU time | 63.2 seconds |
| Started | Sep 01 06:14:30 AM UTC 24 |
| Finished | Sep 01 06:15:35 AM UTC 24 |
| Peak memory | 212028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783993150 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.3783993150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/29.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1598854640 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 11886255483 ps |
| CPU time | 66.51 seconds |
| Started | Sep 01 06:14:31 AM UTC 24 |
| Finished | Sep 01 06:15:40 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598854640 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1598854640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/29.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_zero_delays.34681757 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 55289542 ps |
| CPU time | 3.98 seconds |
| Started | Sep 01 06:14:30 AM UTC 24 |
| Finished | Sep 01 06:14:36 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34681757 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.34681757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/29.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_same_source.4126862840 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 297766190 ps |
| CPU time | 5.95 seconds |
| Started | Sep 01 06:14:34 AM UTC 24 |
| Finished | Sep 01 06:14:41 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126862840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.4126862840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/29.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke.3957055150 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 69234822 ps |
| CPU time | 2.5 seconds |
| Started | Sep 01 06:14:24 AM UTC 24 |
| Finished | Sep 01 06:14:27 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957055150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.3957055150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/29.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_large_delays.3769702291 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 2983232417 ps |
| CPU time | 18.54 seconds |
| Started | Sep 01 06:14:26 AM UTC 24 |
| Finished | Sep 01 06:14:46 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769702291 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3769702291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/29.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.1024769817 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 1963059099 ps |
| CPU time | 14.62 seconds |
| Started | Sep 01 06:14:29 AM UTC 24 |
| Finished | Sep 01 06:14:45 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024769817 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1024769817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.1207419253 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 8265422 ps |
| CPU time | 1.66 seconds |
| Started | Sep 01 06:14:25 AM UTC 24 |
| Finished | Sep 01 06:14:28 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207419253 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.1207419253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/29.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all.2675767873 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 140243615 ps |
| CPU time | 20.72 seconds |
| Started | Sep 01 06:14:38 AM UTC 24 |
| Finished | Sep 01 06:15:00 AM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675767873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.2675767873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/29.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_error.1441427750 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 24797838550 ps |
| CPU time | 44.11 seconds |
| Started | Sep 01 06:14:39 AM UTC 24 |
| Finished | Sep 01 06:15:25 AM UTC 24 |
| Peak memory | 214240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441427750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1441427750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/29.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.679559007 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 215251320 ps |
| CPU time | 28.04 seconds |
| Started | Sep 01 06:14:39 AM UTC 24 |
| Finished | Sep 01 06:15:09 AM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679559007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.679559007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.939414017 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 5533661724 ps |
| CPU time | 145.81 seconds |
| Started | Sep 01 06:14:39 AM UTC 24 |
| Finished | Sep 01 06:17:08 AM UTC 24 |
| Peak memory | 216296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939414017 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.939414017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_unmapped_addr.2331096624 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 301594685 ps |
| CPU time | 7.07 seconds |
| Started | Sep 01 06:14:36 AM UTC 24 |
| Finished | Sep 01 06:14:44 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331096624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.2331096624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/29.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device.172330261 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 73542857 ps |
| CPU time | 6.03 seconds |
| Started | Sep 01 06:07:58 AM UTC 24 |
| Finished | Sep 01 06:08:05 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172330261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.172330261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/3.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.3620998005 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 32168741 ps |
| CPU time | 3.61 seconds |
| Started | Sep 01 06:08:04 AM UTC 24 |
| Finished | Sep 01 06:08:09 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620998005 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.3620998005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_error_random.2035614411 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 56440557 ps |
| CPU time | 7.63 seconds |
| Started | Sep 01 06:08:03 AM UTC 24 |
| Finished | Sep 01 06:08:12 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035614411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2035614411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/3.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random.1365305077 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 157613138 ps |
| CPU time | 9.4 seconds |
| Started | Sep 01 06:07:54 AM UTC 24 |
| Finished | Sep 01 06:08:04 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365305077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.1365305077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/3.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_large_delays.1250456490 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 56294399158 ps |
| CPU time | 125.62 seconds |
| Started | Sep 01 06:07:55 AM UTC 24 |
| Finished | Sep 01 06:10:03 AM UTC 24 |
| Peak memory | 212184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250456490 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1250456490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/3.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_slow_rsp.4030876727 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 2771201762 ps |
| CPU time | 23.86 seconds |
| Started | Sep 01 06:07:56 AM UTC 24 |
| Finished | Sep 01 06:08:21 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030876727 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.4030876727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/3.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_zero_delays.1053968498 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 25436417 ps |
| CPU time | 3.5 seconds |
| Started | Sep 01 06:07:54 AM UTC 24 |
| Finished | Sep 01 06:07:58 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053968498 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.1053968498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/3.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_same_source.3389808072 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 979576370 ps |
| CPU time | 15.56 seconds |
| Started | Sep 01 06:07:59 AM UTC 24 |
| Finished | Sep 01 06:08:16 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389808072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.3389808072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/3.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke.2050889278 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 11365984 ps |
| CPU time | 1.74 seconds |
| Started | Sep 01 06:07:51 AM UTC 24 |
| Finished | Sep 01 06:07:54 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050889278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2050889278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/3.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_large_delays.1772237281 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 5168267225 ps |
| CPU time | 18.01 seconds |
| Started | Sep 01 06:07:53 AM UTC 24 |
| Finished | Sep 01 06:08:12 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772237281 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.1772237281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/3.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.3412753965 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 5691714470 ps |
| CPU time | 9.2 seconds |
| Started | Sep 01 06:07:54 AM UTC 24 |
| Finished | Sep 01 06:08:04 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412753965 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.3412753965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.2561535567 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 8275209 ps |
| CPU time | 1.63 seconds |
| Started | Sep 01 06:07:53 AM UTC 24 |
| Finished | Sep 01 06:07:55 AM UTC 24 |
| Peak memory | 211132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561535567 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.2561535567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/3.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all.3883327877 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 552503333 ps |
| CPU time | 47.1 seconds |
| Started | Sep 01 06:08:05 AM UTC 24 |
| Finished | Sep 01 06:08:54 AM UTC 24 |
| Peak memory | 214184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883327877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.3883327877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/3.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_error.1170209673 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 4817734195 ps |
| CPU time | 63.38 seconds |
| Started | Sep 01 06:08:05 AM UTC 24 |
| Finished | Sep 01 06:09:10 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170209673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.1170209673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/3.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.1026890179 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 11671780838 ps |
| CPU time | 158.22 seconds |
| Started | Sep 01 06:08:05 AM UTC 24 |
| Finished | Sep 01 06:10:46 AM UTC 24 |
| Peak memory | 218340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026890179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.1026890179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1931154435 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 79137762 ps |
| CPU time | 7.12 seconds |
| Started | Sep 01 06:08:10 AM UTC 24 |
| Finished | Sep 01 06:08:18 AM UTC 24 |
| Peak memory | 212396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931154435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.1931154435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_unmapped_addr.715390541 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 33978122 ps |
| CPU time | 5.53 seconds |
| Started | Sep 01 06:08:03 AM UTC 24 |
| Finished | Sep 01 06:08:10 AM UTC 24 |
| Peak memory | 212140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715390541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.715390541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/3.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device.2102511065 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 88190514 ps |
| CPU time | 18 seconds |
| Started | Sep 01 06:14:45 AM UTC 24 |
| Finished | Sep 01 06:15:04 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102511065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.2102511065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/30.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.208426763 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 31608858481 ps |
| CPU time | 102.05 seconds |
| Started | Sep 01 06:14:45 AM UTC 24 |
| Finished | Sep 01 06:16:29 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208426763 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.208426763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.1459427240 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 506837933 ps |
| CPU time | 12.6 seconds |
| Started | Sep 01 06:14:48 AM UTC 24 |
| Finished | Sep 01 06:15:02 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459427240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.1459427240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_error_random.1714545029 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 4298792280 ps |
| CPU time | 16.99 seconds |
| Started | Sep 01 06:14:47 AM UTC 24 |
| Finished | Sep 01 06:15:05 AM UTC 24 |
| Peak memory | 212188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714545029 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.1714545029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/30.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random.3530686787 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 206210309 ps |
| CPU time | 5.46 seconds |
| Started | Sep 01 06:14:43 AM UTC 24 |
| Finished | Sep 01 06:14:50 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530686787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.3530686787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/30.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.2862572567 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 68944036370 ps |
| CPU time | 218.31 seconds |
| Started | Sep 01 06:14:44 AM UTC 24 |
| Finished | Sep 01 06:18:25 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862572567 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2862572567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/30.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1064371638 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 33013883789 ps |
| CPU time | 256.31 seconds |
| Started | Sep 01 06:14:45 AM UTC 24 |
| Finished | Sep 01 06:19:05 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064371638 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1064371638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/30.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_zero_delays.704109318 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 57039023 ps |
| CPU time | 10.27 seconds |
| Started | Sep 01 06:14:44 AM UTC 24 |
| Finished | Sep 01 06:14:55 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704109318 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.704109318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/30.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_same_source.3106510911 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 1431080313 ps |
| CPU time | 8.51 seconds |
| Started | Sep 01 06:14:45 AM UTC 24 |
| Finished | Sep 01 06:14:55 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106510911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.3106510911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/30.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke.2213913007 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 9388691 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 06:14:39 AM UTC 24 |
| Finished | Sep 01 06:14:42 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213913007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2213913007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/30.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_large_delays.2881064068 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 8141350857 ps |
| CPU time | 14.11 seconds |
| Started | Sep 01 06:14:41 AM UTC 24 |
| Finished | Sep 01 06:14:56 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881064068 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.2881064068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/30.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2191664282 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 1084217366 ps |
| CPU time | 14.62 seconds |
| Started | Sep 01 06:14:42 AM UTC 24 |
| Finished | Sep 01 06:14:58 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191664282 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2191664282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.2999674402 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 15864076 ps |
| CPU time | 1.85 seconds |
| Started | Sep 01 06:14:40 AM UTC 24 |
| Finished | Sep 01 06:14:43 AM UTC 24 |
| Peak memory | 211132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999674402 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2999674402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/30.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all.3920741600 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 1254664333 ps |
| CPU time | 23.84 seconds |
| Started | Sep 01 06:14:48 AM UTC 24 |
| Finished | Sep 01 06:15:14 AM UTC 24 |
| Peak memory | 214248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920741600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.3920741600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/30.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_error.627676336 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 15654134 ps |
| CPU time | 1.88 seconds |
| Started | Sep 01 06:14:51 AM UTC 24 |
| Finished | Sep 01 06:14:54 AM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627676336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.627676336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/30.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2640053606 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 74916076 ps |
| CPU time | 16.49 seconds |
| Started | Sep 01 06:14:49 AM UTC 24 |
| Finished | Sep 01 06:15:07 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640053606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.2640053606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.2092902290 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 1831489498 ps |
| CPU time | 83.09 seconds |
| Started | Sep 01 06:14:51 AM UTC 24 |
| Finished | Sep 01 06:16:16 AM UTC 24 |
| Peak memory | 216236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092902290 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.2092902290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_unmapped_addr.755839185 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 1195045918 ps |
| CPU time | 7.43 seconds |
| Started | Sep 01 06:14:48 AM UTC 24 |
| Finished | Sep 01 06:14:57 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755839185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.755839185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/30.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device.1933587194 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 125322897 ps |
| CPU time | 13.91 seconds |
| Started | Sep 01 06:15:00 AM UTC 24 |
| Finished | Sep 01 06:15:15 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933587194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.1933587194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/31.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.1940271220 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 64537765958 ps |
| CPU time | 379.58 seconds |
| Started | Sep 01 06:15:01 AM UTC 24 |
| Finished | Sep 01 06:21:25 AM UTC 24 |
| Peak memory | 218136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940271220 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.1940271220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.679073878 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 560935335 ps |
| CPU time | 8.38 seconds |
| Started | Sep 01 06:15:06 AM UTC 24 |
| Finished | Sep 01 06:15:15 AM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679073878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.679073878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_error_random.3952154381 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 27128968 ps |
| CPU time | 3.68 seconds |
| Started | Sep 01 06:15:03 AM UTC 24 |
| Finished | Sep 01 06:15:08 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952154381 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3952154381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/31.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random.665305268 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 434473828 ps |
| CPU time | 7.94 seconds |
| Started | Sep 01 06:14:58 AM UTC 24 |
| Finished | Sep 01 06:15:07 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665305268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.665305268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/31.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_large_delays.2501228620 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 29857918558 ps |
| CPU time | 173.13 seconds |
| Started | Sep 01 06:14:59 AM UTC 24 |
| Finished | Sep 01 06:17:55 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501228620 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.2501228620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/31.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_slow_rsp.424476782 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 8723651826 ps |
| CPU time | 70.22 seconds |
| Started | Sep 01 06:15:00 AM UTC 24 |
| Finished | Sep 01 06:16:11 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424476782 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.424476782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/31.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_zero_delays.3006089097 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 34818042 ps |
| CPU time | 5.87 seconds |
| Started | Sep 01 06:14:58 AM UTC 24 |
| Finished | Sep 01 06:15:05 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006089097 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.3006089097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/31.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_same_source.1393157540 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 21242319 ps |
| CPU time | 2.12 seconds |
| Started | Sep 01 06:15:03 AM UTC 24 |
| Finished | Sep 01 06:15:06 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393157540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1393157540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/31.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke.3769152129 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 196210428 ps |
| CPU time | 2.43 seconds |
| Started | Sep 01 06:14:55 AM UTC 24 |
| Finished | Sep 01 06:14:59 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769152129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.3769152129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/31.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_large_delays.2907417558 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 11682379609 ps |
| CPU time | 17.19 seconds |
| Started | Sep 01 06:14:57 AM UTC 24 |
| Finished | Sep 01 06:15:15 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907417558 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.2907417558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/31.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.711945222 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 3167487107 ps |
| CPU time | 21.12 seconds |
| Started | Sep 01 06:14:57 AM UTC 24 |
| Finished | Sep 01 06:15:19 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711945222 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.711945222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.2331390793 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 13901528 ps |
| CPU time | 1.71 seconds |
| Started | Sep 01 06:14:55 AM UTC 24 |
| Finished | Sep 01 06:14:58 AM UTC 24 |
| Peak memory | 211132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331390793 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.2331390793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/31.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all.1518465694 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 520467738 ps |
| CPU time | 54.27 seconds |
| Started | Sep 01 06:15:06 AM UTC 24 |
| Finished | Sep 01 06:16:02 AM UTC 24 |
| Peak memory | 214248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518465694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.1518465694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/31.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_error.937301540 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 4842847160 ps |
| CPU time | 76.05 seconds |
| Started | Sep 01 06:15:06 AM UTC 24 |
| Finished | Sep 01 06:16:24 AM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937301540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.937301540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/31.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.3430389722 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 211758167 ps |
| CPU time | 26.68 seconds |
| Started | Sep 01 06:15:06 AM UTC 24 |
| Finished | Sep 01 06:15:34 AM UTC 24 |
| Peak memory | 216360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430389722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.3430389722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.706167628 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 2684215657 ps |
| CPU time | 84.49 seconds |
| Started | Sep 01 06:15:07 AM UTC 24 |
| Finished | Sep 01 06:16:34 AM UTC 24 |
| Peak memory | 214252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706167628 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.706167628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_unmapped_addr.396986695 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 43780562 ps |
| CPU time | 5.09 seconds |
| Started | Sep 01 06:15:04 AM UTC 24 |
| Finished | Sep 01 06:15:10 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396986695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.396986695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/31.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device.3780107754 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 500628045 ps |
| CPU time | 14.84 seconds |
| Started | Sep 01 06:15:13 AM UTC 24 |
| Finished | Sep 01 06:15:29 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780107754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.3780107754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/32.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.609216713 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 303511646998 ps |
| CPU time | 422.47 seconds |
| Started | Sep 01 06:15:13 AM UTC 24 |
| Finished | Sep 01 06:22:21 AM UTC 24 |
| Peak memory | 217948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609216713 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.609216713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2032646262 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 60470459 ps |
| CPU time | 8.14 seconds |
| Started | Sep 01 06:15:17 AM UTC 24 |
| Finished | Sep 01 06:15:26 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032646262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.2032646262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_error_random.2581772427 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 85415378 ps |
| CPU time | 7.32 seconds |
| Started | Sep 01 06:15:15 AM UTC 24 |
| Finished | Sep 01 06:15:24 AM UTC 24 |
| Peak memory | 211936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581772427 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2581772427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/32.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random.1883796615 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 2893520905 ps |
| CPU time | 14.17 seconds |
| Started | Sep 01 06:15:10 AM UTC 24 |
| Finished | Sep 01 06:15:25 AM UTC 24 |
| Peak memory | 212384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883796615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.1883796615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/32.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.4091591876 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 42736731131 ps |
| CPU time | 283.77 seconds |
| Started | Sep 01 06:15:11 AM UTC 24 |
| Finished | Sep 01 06:19:59 AM UTC 24 |
| Peak memory | 212456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091591876 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.4091591876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/32.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.103977517 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 21566209421 ps |
| CPU time | 192.17 seconds |
| Started | Sep 01 06:15:13 AM UTC 24 |
| Finished | Sep 01 06:18:28 AM UTC 24 |
| Peak memory | 212188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103977517 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.103977517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/32.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_zero_delays.2074040123 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 14593458 ps |
| CPU time | 2.18 seconds |
| Started | Sep 01 06:15:11 AM UTC 24 |
| Finished | Sep 01 06:15:14 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074040123 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.2074040123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/32.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_same_source.139516832 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 1845123778 ps |
| CPU time | 8.65 seconds |
| Started | Sep 01 06:15:14 AM UTC 24 |
| Finished | Sep 01 06:15:24 AM UTC 24 |
| Peak memory | 212120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139516832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.139516832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/32.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke.4166265585 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 15763638 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 06:15:08 AM UTC 24 |
| Finished | Sep 01 06:15:11 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166265585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.4166265585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/32.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_large_delays.3991854616 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 1875656636 ps |
| CPU time | 10.6 seconds |
| Started | Sep 01 06:15:09 AM UTC 24 |
| Finished | Sep 01 06:15:20 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991854616 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.3991854616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/32.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.4263011955 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 698737342 ps |
| CPU time | 6.17 seconds |
| Started | Sep 01 06:15:10 AM UTC 24 |
| Finished | Sep 01 06:15:17 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263011955 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.4263011955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.2991780106 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 18991654 ps |
| CPU time | 1.76 seconds |
| Started | Sep 01 06:15:08 AM UTC 24 |
| Finished | Sep 01 06:15:11 AM UTC 24 |
| Peak memory | 211132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991780106 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.2991780106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/32.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all.315383058 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 720462572 ps |
| CPU time | 58.56 seconds |
| Started | Sep 01 06:15:17 AM UTC 24 |
| Finished | Sep 01 06:16:17 AM UTC 24 |
| Peak memory | 214372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315383058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.315383058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/32.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1797455583 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 103035670 ps |
| CPU time | 9.99 seconds |
| Started | Sep 01 06:15:17 AM UTC 24 |
| Finished | Sep 01 06:15:28 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797455583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1797455583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/32.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.487124922 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 181348724 ps |
| CPU time | 39.15 seconds |
| Started | Sep 01 06:15:17 AM UTC 24 |
| Finished | Sep 01 06:15:58 AM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487124922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.487124922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.2911164204 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 6819214 ps |
| CPU time | 5.59 seconds |
| Started | Sep 01 06:15:17 AM UTC 24 |
| Finished | Sep 01 06:15:24 AM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911164204 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.2911164204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_unmapped_addr.294659708 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 3980739955 ps |
| CPU time | 11.58 seconds |
| Started | Sep 01 06:15:15 AM UTC 24 |
| Finished | Sep 01 06:15:28 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294659708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.294659708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/32.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device.3005809845 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 695104285 ps |
| CPU time | 13.5 seconds |
| Started | Sep 01 06:15:24 AM UTC 24 |
| Finished | Sep 01 06:15:39 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005809845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.3005809845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/33.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.1039630279 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 127348946365 ps |
| CPU time | 310.87 seconds |
| Started | Sep 01 06:15:26 AM UTC 24 |
| Finished | Sep 01 06:20:41 AM UTC 24 |
| Peak memory | 214240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039630279 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.1039630279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.89234654 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 558251287 ps |
| CPU time | 11.61 seconds |
| Started | Sep 01 06:15:26 AM UTC 24 |
| Finished | Sep 01 06:15:39 AM UTC 24 |
| Peak memory | 212140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89234654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.89234654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_error_random.3053617989 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 1617468959 ps |
| CPU time | 18.93 seconds |
| Started | Sep 01 06:15:26 AM UTC 24 |
| Finished | Sep 01 06:15:46 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053617989 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3053617989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/33.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random.3202600745 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 2475138612 ps |
| CPU time | 9.6 seconds |
| Started | Sep 01 06:15:20 AM UTC 24 |
| Finished | Sep 01 06:15:31 AM UTC 24 |
| Peak memory | 212256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202600745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.3202600745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/33.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_large_delays.3475175001 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 39710333650 ps |
| CPU time | 118.6 seconds |
| Started | Sep 01 06:15:23 AM UTC 24 |
| Finished | Sep 01 06:17:23 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475175001 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.3475175001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/33.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_slow_rsp.2948959940 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 20332137826 ps |
| CPU time | 155.77 seconds |
| Started | Sep 01 06:15:23 AM UTC 24 |
| Finished | Sep 01 06:18:01 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948959940 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.2948959940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/33.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_zero_delays.931586828 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 70812358 ps |
| CPU time | 4.66 seconds |
| Started | Sep 01 06:15:21 AM UTC 24 |
| Finished | Sep 01 06:15:27 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931586828 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.931586828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/33.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_same_source.1222194459 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 651112697 ps |
| CPU time | 7.93 seconds |
| Started | Sep 01 06:15:26 AM UTC 24 |
| Finished | Sep 01 06:15:35 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222194459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.1222194459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/33.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke.1689946359 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 396601863 ps |
| CPU time | 2.43 seconds |
| Started | Sep 01 06:15:19 AM UTC 24 |
| Finished | Sep 01 06:15:22 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689946359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1689946359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/33.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_large_delays.4149902499 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 2076606838 ps |
| CPU time | 8.53 seconds |
| Started | Sep 01 06:15:20 AM UTC 24 |
| Finished | Sep 01 06:15:30 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149902499 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.4149902499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/33.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.1484356374 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 782689479 ps |
| CPU time | 6.23 seconds |
| Started | Sep 01 06:15:20 AM UTC 24 |
| Finished | Sep 01 06:15:27 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484356374 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1484356374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.207863144 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 8707008 ps |
| CPU time | 1.6 seconds |
| Started | Sep 01 06:15:20 AM UTC 24 |
| Finished | Sep 01 06:15:23 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207863144 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.207863144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/33.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all.3988464596 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 6543602204 ps |
| CPU time | 86.49 seconds |
| Started | Sep 01 06:15:26 AM UTC 24 |
| Finished | Sep 01 06:16:55 AM UTC 24 |
| Peak memory | 214440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988464596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3988464596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/33.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_error.2334259393 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 14210668448 ps |
| CPU time | 33.97 seconds |
| Started | Sep 01 06:15:28 AM UTC 24 |
| Finished | Sep 01 06:16:03 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334259393 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.2334259393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/33.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3629514255 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 1391473627 ps |
| CPU time | 185.68 seconds |
| Started | Sep 01 06:15:28 AM UTC 24 |
| Finished | Sep 01 06:18:36 AM UTC 24 |
| Peak memory | 216228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629514255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.3629514255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.2341868985 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 2947550656 ps |
| CPU time | 86.12 seconds |
| Started | Sep 01 06:15:28 AM UTC 24 |
| Finished | Sep 01 06:16:56 AM UTC 24 |
| Peak memory | 214444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341868985 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.2341868985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_unmapped_addr.2987702631 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 85345817 ps |
| CPU time | 6.05 seconds |
| Started | Sep 01 06:15:26 AM UTC 24 |
| Finished | Sep 01 06:15:33 AM UTC 24 |
| Peak memory | 212316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987702631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.2987702631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/33.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device.633382565 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 118986188 ps |
| CPU time | 12.48 seconds |
| Started | Sep 01 06:15:33 AM UTC 24 |
| Finished | Sep 01 06:15:47 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633382565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.633382565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/34.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.1075838948 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 64468519182 ps |
| CPU time | 287.57 seconds |
| Started | Sep 01 06:15:34 AM UTC 24 |
| Finished | Sep 01 06:20:25 AM UTC 24 |
| Peak memory | 214240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075838948 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.1075838948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.626088097 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 1674427651 ps |
| CPU time | 11.56 seconds |
| Started | Sep 01 06:15:37 AM UTC 24 |
| Finished | Sep 01 06:15:49 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626088097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.626088097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_error_random.2078365342 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 473742076 ps |
| CPU time | 8.96 seconds |
| Started | Sep 01 06:15:35 AM UTC 24 |
| Finished | Sep 01 06:15:45 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078365342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.2078365342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/34.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random.256667415 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 1239237856 ps |
| CPU time | 13.54 seconds |
| Started | Sep 01 06:15:31 AM UTC 24 |
| Finished | Sep 01 06:15:45 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256667415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.256667415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/34.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.4086412056 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 46670976845 ps |
| CPU time | 181.52 seconds |
| Started | Sep 01 06:15:32 AM UTC 24 |
| Finished | Sep 01 06:18:36 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086412056 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.4086412056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/34.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_slow_rsp.4200716073 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 21678380311 ps |
| CPU time | 139.22 seconds |
| Started | Sep 01 06:15:33 AM UTC 24 |
| Finished | Sep 01 06:17:55 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200716073 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.4200716073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/34.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_zero_delays.4108932269 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 11730642 ps |
| CPU time | 1.96 seconds |
| Started | Sep 01 06:15:31 AM UTC 24 |
| Finished | Sep 01 06:15:34 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108932269 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.4108932269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/34.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_same_source.1494289824 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 1417192079 ps |
| CPU time | 14.69 seconds |
| Started | Sep 01 06:15:35 AM UTC 24 |
| Finished | Sep 01 06:15:51 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494289824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.1494289824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/34.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke.2639273922 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 291338589 ps |
| CPU time | 2.27 seconds |
| Started | Sep 01 06:15:29 AM UTC 24 |
| Finished | Sep 01 06:15:32 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639273922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.2639273922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/34.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_large_delays.921657165 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 2596025698 ps |
| CPU time | 12.56 seconds |
| Started | Sep 01 06:15:29 AM UTC 24 |
| Finished | Sep 01 06:15:43 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921657165 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.921657165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/34.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.3538028456 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 2464528302 ps |
| CPU time | 14.93 seconds |
| Started | Sep 01 06:15:31 AM UTC 24 |
| Finished | Sep 01 06:15:47 AM UTC 24 |
| Peak memory | 212520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538028456 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3538028456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.3590947793 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 14568970 ps |
| CPU time | 1.81 seconds |
| Started | Sep 01 06:15:29 AM UTC 24 |
| Finished | Sep 01 06:15:32 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590947793 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.3590947793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/34.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all.928041554 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 2549920572 ps |
| CPU time | 32.42 seconds |
| Started | Sep 01 06:15:37 AM UTC 24 |
| Finished | Sep 01 06:16:11 AM UTC 24 |
| Peak memory | 214240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928041554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.928041554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/34.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_error.3427881582 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 9608230080 ps |
| CPU time | 155.4 seconds |
| Started | Sep 01 06:15:39 AM UTC 24 |
| Finished | Sep 01 06:18:17 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427881582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3427881582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/34.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.2738444826 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 776261939 ps |
| CPU time | 58.23 seconds |
| Started | Sep 01 06:15:37 AM UTC 24 |
| Finished | Sep 01 06:16:37 AM UTC 24 |
| Peak memory | 216228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738444826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.2738444826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.1241437139 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 232875977 ps |
| CPU time | 26.63 seconds |
| Started | Sep 01 06:15:39 AM UTC 24 |
| Finished | Sep 01 06:16:07 AM UTC 24 |
| Peak memory | 214380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241437139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.1241437139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_unmapped_addr.3789127010 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 101502442 ps |
| CPU time | 8.96 seconds |
| Started | Sep 01 06:15:35 AM UTC 24 |
| Finished | Sep 01 06:15:45 AM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789127010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3789127010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/34.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device.827196830 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 17955108 ps |
| CPU time | 2.08 seconds |
| Started | Sep 01 06:15:48 AM UTC 24 |
| Finished | Sep 01 06:15:51 AM UTC 24 |
| Peak memory | 211972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827196830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.827196830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/35.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2174588928 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 21376585857 ps |
| CPU time | 52.13 seconds |
| Started | Sep 01 06:15:48 AM UTC 24 |
| Finished | Sep 01 06:16:41 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174588928 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.2174588928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.407268131 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 218313478 ps |
| CPU time | 2.88 seconds |
| Started | Sep 01 06:15:52 AM UTC 24 |
| Finished | Sep 01 06:15:56 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407268131 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.407268131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_error_random.766243649 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 884182773 ps |
| CPU time | 19.7 seconds |
| Started | Sep 01 06:15:49 AM UTC 24 |
| Finished | Sep 01 06:16:10 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766243649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.766243649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/35.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random.3720380744 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 91592823 ps |
| CPU time | 4.78 seconds |
| Started | Sep 01 06:15:46 AM UTC 24 |
| Finished | Sep 01 06:15:51 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720380744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.3720380744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/35.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.2840983413 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 274754220834 ps |
| CPU time | 170.47 seconds |
| Started | Sep 01 06:15:47 AM UTC 24 |
| Finished | Sep 01 06:18:40 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840983413 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.2840983413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/35.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.1671880924 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 20223212750 ps |
| CPU time | 74.33 seconds |
| Started | Sep 01 06:15:48 AM UTC 24 |
| Finished | Sep 01 06:17:04 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671880924 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.1671880924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/35.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_zero_delays.2973148093 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 63281266 ps |
| CPU time | 10.5 seconds |
| Started | Sep 01 06:15:47 AM UTC 24 |
| Finished | Sep 01 06:15:59 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973148093 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.2973148093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/35.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_same_source.676370807 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 540047698 ps |
| CPU time | 13.22 seconds |
| Started | Sep 01 06:15:49 AM UTC 24 |
| Finished | Sep 01 06:16:04 AM UTC 24 |
| Peak memory | 212120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676370807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.676370807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/35.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke.2598818820 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 247095658 ps |
| CPU time | 2.43 seconds |
| Started | Sep 01 06:15:41 AM UTC 24 |
| Finished | Sep 01 06:15:44 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598818820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.2598818820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/35.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_large_delays.3065549533 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 6683055664 ps |
| CPU time | 15.11 seconds |
| Started | Sep 01 06:15:44 AM UTC 24 |
| Finished | Sep 01 06:16:00 AM UTC 24 |
| Peak memory | 212516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065549533 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3065549533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/35.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.677389193 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 840951659 ps |
| CPU time | 10.31 seconds |
| Started | Sep 01 06:15:46 AM UTC 24 |
| Finished | Sep 01 06:15:57 AM UTC 24 |
| Peak memory | 212324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677389193 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.677389193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.1724034035 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 12274879 ps |
| CPU time | 1.97 seconds |
| Started | Sep 01 06:15:41 AM UTC 24 |
| Finished | Sep 01 06:15:44 AM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724034035 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.1724034035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/35.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all.2082129199 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 282432370 ps |
| CPU time | 14.65 seconds |
| Started | Sep 01 06:15:52 AM UTC 24 |
| Finished | Sep 01 06:16:08 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082129199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2082129199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/35.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_error.798972285 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 298119228 ps |
| CPU time | 14.08 seconds |
| Started | Sep 01 06:15:54 AM UTC 24 |
| Finished | Sep 01 06:16:10 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798972285 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.798972285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/35.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.2691351857 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 2718275459 ps |
| CPU time | 61.69 seconds |
| Started | Sep 01 06:15:52 AM UTC 24 |
| Finished | Sep 01 06:16:56 AM UTC 24 |
| Peak memory | 214440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691351857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.2691351857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_unmapped_addr.675966477 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 332097849 ps |
| CPU time | 7.97 seconds |
| Started | Sep 01 06:15:51 AM UTC 24 |
| Finished | Sep 01 06:16:00 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675966477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.675966477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/35.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device.676478927 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 25540349 ps |
| CPU time | 6.13 seconds |
| Started | Sep 01 06:16:04 AM UTC 24 |
| Finished | Sep 01 06:16:11 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676478927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.676478927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/36.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.2298994157 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 25999759858 ps |
| CPU time | 81.03 seconds |
| Started | Sep 01 06:16:04 AM UTC 24 |
| Finished | Sep 01 06:17:27 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298994157 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.2298994157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.1611891869 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 251053103 ps |
| CPU time | 5.16 seconds |
| Started | Sep 01 06:16:08 AM UTC 24 |
| Finished | Sep 01 06:16:15 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611891869 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.1611891869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_error_random.2150216339 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 788093390 ps |
| CPU time | 19.09 seconds |
| Started | Sep 01 06:16:06 AM UTC 24 |
| Finished | Sep 01 06:16:26 AM UTC 24 |
| Peak memory | 212324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150216339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2150216339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/36.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random.1550438268 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 822359289 ps |
| CPU time | 14.99 seconds |
| Started | Sep 01 06:16:01 AM UTC 24 |
| Finished | Sep 01 06:16:17 AM UTC 24 |
| Peak memory | 212316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550438268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.1550438268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/36.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.2532756486 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 69329018672 ps |
| CPU time | 145.6 seconds |
| Started | Sep 01 06:16:02 AM UTC 24 |
| Finished | Sep 01 06:18:30 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532756486 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2532756486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/36.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.319611635 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 14997754004 ps |
| CPU time | 128.13 seconds |
| Started | Sep 01 06:16:03 AM UTC 24 |
| Finished | Sep 01 06:18:15 AM UTC 24 |
| Peak memory | 212188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319611635 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.319611635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/36.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_zero_delays.2392561718 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 271509525 ps |
| CPU time | 11.47 seconds |
| Started | Sep 01 06:16:02 AM UTC 24 |
| Finished | Sep 01 06:16:15 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392561718 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.2392561718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/36.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_same_source.3714042680 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 10278124 ps |
| CPU time | 1.71 seconds |
| Started | Sep 01 06:16:05 AM UTC 24 |
| Finished | Sep 01 06:16:07 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714042680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3714042680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/36.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke.890044395 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 139526942 ps |
| CPU time | 2.52 seconds |
| Started | Sep 01 06:15:58 AM UTC 24 |
| Finished | Sep 01 06:16:01 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890044395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.890044395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/36.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_large_delays.2855761986 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 4593710267 ps |
| CPU time | 10.88 seconds |
| Started | Sep 01 06:16:01 AM UTC 24 |
| Finished | Sep 01 06:16:13 AM UTC 24 |
| Peak memory | 212164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855761986 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2855761986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/36.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.1754017882 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 12012555196 ps |
| CPU time | 17.82 seconds |
| Started | Sep 01 06:16:01 AM UTC 24 |
| Finished | Sep 01 06:16:20 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754017882 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.1754017882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.3065625677 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 11833397 ps |
| CPU time | 1.79 seconds |
| Started | Sep 01 06:15:59 AM UTC 24 |
| Finished | Sep 01 06:16:02 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065625677 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.3065625677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/36.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all.3158269121 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 261867822 ps |
| CPU time | 31.16 seconds |
| Started | Sep 01 06:16:09 AM UTC 24 |
| Finished | Sep 01 06:16:41 AM UTC 24 |
| Peak memory | 214184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158269121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3158269121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/36.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_error.3411745523 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 1189952490 ps |
| CPU time | 9.64 seconds |
| Started | Sep 01 06:16:10 AM UTC 24 |
| Finished | Sep 01 06:16:21 AM UTC 24 |
| Peak memory | 212324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411745523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.3411745523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/36.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.544448228 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 1356095254 ps |
| CPU time | 92.76 seconds |
| Started | Sep 01 06:16:10 AM UTC 24 |
| Finished | Sep 01 06:17:45 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544448228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.544448228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3843821808 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 13404980523 ps |
| CPU time | 112.29 seconds |
| Started | Sep 01 06:16:10 AM UTC 24 |
| Finished | Sep 01 06:18:05 AM UTC 24 |
| Peak memory | 216492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843821808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.3843821808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_unmapped_addr.27678291 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 921579710 ps |
| CPU time | 7.82 seconds |
| Started | Sep 01 06:16:08 AM UTC 24 |
| Finished | Sep 01 06:16:18 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27678291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.27678291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/36.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device.1310359274 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 55840500 ps |
| CPU time | 9.3 seconds |
| Started | Sep 01 06:16:16 AM UTC 24 |
| Finished | Sep 01 06:16:27 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310359274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.1310359274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/37.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.4005184664 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 45019292430 ps |
| CPU time | 301.82 seconds |
| Started | Sep 01 06:16:16 AM UTC 24 |
| Finished | Sep 01 06:21:22 AM UTC 24 |
| Peak memory | 214240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005184664 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.4005184664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.2057665494 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 45892225 ps |
| CPU time | 4.02 seconds |
| Started | Sep 01 06:16:19 AM UTC 24 |
| Finished | Sep 01 06:16:24 AM UTC 24 |
| Peak memory | 211776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057665494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.2057665494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_error_random.938897278 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 65668000 ps |
| CPU time | 4.35 seconds |
| Started | Sep 01 06:16:18 AM UTC 24 |
| Finished | Sep 01 06:16:23 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938897278 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.938897278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/37.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random.59813809 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 569345911 ps |
| CPU time | 11.36 seconds |
| Started | Sep 01 06:16:13 AM UTC 24 |
| Finished | Sep 01 06:16:26 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59813809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.59813809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/37.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.2580898944 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 17833163236 ps |
| CPU time | 46.01 seconds |
| Started | Sep 01 06:16:16 AM UTC 24 |
| Finished | Sep 01 06:17:04 AM UTC 24 |
| Peak memory | 212260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580898944 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2580898944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/37.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.50322069 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 32219361862 ps |
| CPU time | 192.31 seconds |
| Started | Sep 01 06:16:16 AM UTC 24 |
| Finished | Sep 01 06:19:31 AM UTC 24 |
| Peak memory | 212188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50322069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.50322069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/37.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_zero_delays.983516267 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 236691698 ps |
| CPU time | 8.93 seconds |
| Started | Sep 01 06:16:14 AM UTC 24 |
| Finished | Sep 01 06:16:24 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983516267 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.983516267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/37.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_same_source.3962716061 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 73883081 ps |
| CPU time | 4.5 seconds |
| Started | Sep 01 06:16:18 AM UTC 24 |
| Finished | Sep 01 06:16:23 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962716061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3962716061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/37.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke.44546471 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 154528789 ps |
| CPU time | 2.17 seconds |
| Started | Sep 01 06:16:12 AM UTC 24 |
| Finished | Sep 01 06:16:15 AM UTC 24 |
| Peak memory | 212384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44546471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.44546471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/37.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_large_delays.1728544220 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 2753575332 ps |
| CPU time | 21.34 seconds |
| Started | Sep 01 06:16:12 AM UTC 24 |
| Finished | Sep 01 06:16:34 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728544220 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1728544220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/37.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.3070662410 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 8356057720 ps |
| CPU time | 12.42 seconds |
| Started | Sep 01 06:16:13 AM UTC 24 |
| Finished | Sep 01 06:16:27 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070662410 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.3070662410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3667511342 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 9224350 ps |
| CPU time | 1.73 seconds |
| Started | Sep 01 06:16:12 AM UTC 24 |
| Finished | Sep 01 06:16:15 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667511342 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.3667511342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/37.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.1817023449 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 1528742983 ps |
| CPU time | 36.11 seconds |
| Started | Sep 01 06:16:20 AM UTC 24 |
| Finished | Sep 01 06:16:58 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817023449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.1817023449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/37.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_error.2310240796 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 577193646 ps |
| CPU time | 39.67 seconds |
| Started | Sep 01 06:16:23 AM UTC 24 |
| Finished | Sep 01 06:17:04 AM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310240796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2310240796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/37.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.368573962 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 700667434 ps |
| CPU time | 74.81 seconds |
| Started | Sep 01 06:16:23 AM UTC 24 |
| Finished | Sep 01 06:17:40 AM UTC 24 |
| Peak memory | 216292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368573962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.368573962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.2156891012 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 2735492636 ps |
| CPU time | 157.55 seconds |
| Started | Sep 01 06:16:24 AM UTC 24 |
| Finished | Sep 01 06:19:05 AM UTC 24 |
| Peak memory | 218536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156891012 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.2156891012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_unmapped_addr.132729984 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 13287213 ps |
| CPU time | 2.25 seconds |
| Started | Sep 01 06:16:19 AM UTC 24 |
| Finished | Sep 01 06:16:22 AM UTC 24 |
| Peak memory | 211808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132729984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.132729984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/37.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device.3065565843 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 46500137 ps |
| CPU time | 8.69 seconds |
| Started | Sep 01 06:16:29 AM UTC 24 |
| Finished | Sep 01 06:16:39 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065565843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.3065565843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/38.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.1324904736 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 82253217093 ps |
| CPU time | 322 seconds |
| Started | Sep 01 06:16:29 AM UTC 24 |
| Finished | Sep 01 06:21:55 AM UTC 24 |
| Peak memory | 214308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324904736 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.1324904736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.763597951 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 150440149 ps |
| CPU time | 2.98 seconds |
| Started | Sep 01 06:16:33 AM UTC 24 |
| Finished | Sep 01 06:16:37 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763597951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.763597951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_error_random.304617395 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 11886895 ps |
| CPU time | 2.12 seconds |
| Started | Sep 01 06:16:30 AM UTC 24 |
| Finished | Sep 01 06:16:33 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304617395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.304617395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/38.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random.3691369693 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 100489156 ps |
| CPU time | 2.95 seconds |
| Started | Sep 01 06:16:26 AM UTC 24 |
| Finished | Sep 01 06:16:31 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691369693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.3691369693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/38.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.1694490485 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 20883126064 ps |
| CPU time | 142.37 seconds |
| Started | Sep 01 06:16:27 AM UTC 24 |
| Finished | Sep 01 06:18:53 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694490485 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.1694490485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/38.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.2880978138 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 27367323200 ps |
| CPU time | 231.81 seconds |
| Started | Sep 01 06:16:28 AM UTC 24 |
| Finished | Sep 01 06:20:23 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880978138 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.2880978138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/38.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_zero_delays.3013715966 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 26513209 ps |
| CPU time | 2.56 seconds |
| Started | Sep 01 06:16:27 AM UTC 24 |
| Finished | Sep 01 06:16:31 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013715966 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.3013715966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/38.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_same_source.1590383203 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 597448691 ps |
| CPU time | 7.95 seconds |
| Started | Sep 01 06:16:30 AM UTC 24 |
| Finished | Sep 01 06:16:39 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590383203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1590383203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/38.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke.309202018 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 61674000 ps |
| CPU time | 2.04 seconds |
| Started | Sep 01 06:16:24 AM UTC 24 |
| Finished | Sep 01 06:16:28 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309202018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.309202018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/38.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_large_delays.506939083 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 3634296900 ps |
| CPU time | 14.49 seconds |
| Started | Sep 01 06:16:26 AM UTC 24 |
| Finished | Sep 01 06:16:42 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506939083 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.506939083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/38.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.3106025395 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 1196621271 ps |
| CPU time | 10.01 seconds |
| Started | Sep 01 06:16:26 AM UTC 24 |
| Finished | Sep 01 06:16:38 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106025395 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.3106025395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.1700423032 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 16587614 ps |
| CPU time | 1.73 seconds |
| Started | Sep 01 06:16:26 AM UTC 24 |
| Finished | Sep 01 06:16:29 AM UTC 24 |
| Peak memory | 211132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700423032 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.1700423032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/38.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.167300200 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 885148842 ps |
| CPU time | 56.72 seconds |
| Started | Sep 01 06:16:34 AM UTC 24 |
| Finished | Sep 01 06:17:33 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167300200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.167300200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/38.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.1521903500 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 2071802488 ps |
| CPU time | 26.61 seconds |
| Started | Sep 01 06:16:36 AM UTC 24 |
| Finished | Sep 01 06:17:04 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521903500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1521903500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/38.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.953514186 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 550147614 ps |
| CPU time | 47.92 seconds |
| Started | Sep 01 06:16:34 AM UTC 24 |
| Finished | Sep 01 06:17:24 AM UTC 24 |
| Peak memory | 216228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953514186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.953514186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.820307765 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 7834433684 ps |
| CPU time | 204.89 seconds |
| Started | Sep 01 06:16:36 AM UTC 24 |
| Finished | Sep 01 06:20:04 AM UTC 24 |
| Peak memory | 218348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820307765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.820307765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_unmapped_addr.806094936 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 495228044 ps |
| CPU time | 11.42 seconds |
| Started | Sep 01 06:16:32 AM UTC 24 |
| Finished | Sep 01 06:16:44 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806094936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.806094936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/38.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device.2045910127 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 673597797 ps |
| CPU time | 21.03 seconds |
| Started | Sep 01 06:16:43 AM UTC 24 |
| Finished | Sep 01 06:17:05 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045910127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.2045910127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/39.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.2779923251 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 60994621648 ps |
| CPU time | 73.58 seconds |
| Started | Sep 01 06:16:43 AM UTC 24 |
| Finished | Sep 01 06:17:58 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779923251 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.2779923251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.2839669070 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 77614020 ps |
| CPU time | 7.23 seconds |
| Started | Sep 01 06:16:52 AM UTC 24 |
| Finished | Sep 01 06:17:00 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839669070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.2839669070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_error_random.2664900300 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 123506406 ps |
| CPU time | 6.86 seconds |
| Started | Sep 01 06:16:48 AM UTC 24 |
| Finished | Sep 01 06:16:56 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664900300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.2664900300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/39.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random.2968623258 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 367281138 ps |
| CPU time | 7.41 seconds |
| Started | Sep 01 06:16:41 AM UTC 24 |
| Finished | Sep 01 06:16:49 AM UTC 24 |
| Peak memory | 212324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968623258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.2968623258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/39.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.148443703 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 2105698366 ps |
| CPU time | 20.6 seconds |
| Started | Sep 01 06:16:42 AM UTC 24 |
| Finished | Sep 01 06:17:04 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148443703 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.148443703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/39.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.3653788514 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 13536706140 ps |
| CPU time | 112.21 seconds |
| Started | Sep 01 06:16:42 AM UTC 24 |
| Finished | Sep 01 06:18:37 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653788514 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3653788514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/39.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_zero_delays.2721196554 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 115567592 ps |
| CPU time | 6.59 seconds |
| Started | Sep 01 06:16:42 AM UTC 24 |
| Finished | Sep 01 06:16:50 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721196554 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.2721196554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/39.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_same_source.514096542 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 13373097 ps |
| CPU time | 1.5 seconds |
| Started | Sep 01 06:16:45 AM UTC 24 |
| Finished | Sep 01 06:16:47 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514096542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.514096542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/39.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke.3849510386 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 52035728 ps |
| CPU time | 2.32 seconds |
| Started | Sep 01 06:16:38 AM UTC 24 |
| Finished | Sep 01 06:16:41 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849510386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3849510386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/39.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3699418219 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 3808258811 ps |
| CPU time | 16.79 seconds |
| Started | Sep 01 06:16:39 AM UTC 24 |
| Finished | Sep 01 06:16:57 AM UTC 24 |
| Peak memory | 212188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699418219 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3699418219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/39.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.279355949 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 2804534654 ps |
| CPU time | 12.84 seconds |
| Started | Sep 01 06:16:41 AM UTC 24 |
| Finished | Sep 01 06:16:55 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279355949 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.279355949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.1149562424 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 9521553 ps |
| CPU time | 1.74 seconds |
| Started | Sep 01 06:16:38 AM UTC 24 |
| Finished | Sep 01 06:16:40 AM UTC 24 |
| Peak memory | 211132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149562424 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.1149562424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/39.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.3706425568 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 24467010737 ps |
| CPU time | 92.48 seconds |
| Started | Sep 01 06:16:52 AM UTC 24 |
| Finished | Sep 01 06:18:26 AM UTC 24 |
| Peak memory | 214244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706425568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3706425568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/39.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.423330471 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 1528289283 ps |
| CPU time | 60.62 seconds |
| Started | Sep 01 06:16:52 AM UTC 24 |
| Finished | Sep 01 06:17:54 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423330471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.423330471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/39.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.2371421053 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 9293569868 ps |
| CPU time | 103.54 seconds |
| Started | Sep 01 06:16:52 AM UTC 24 |
| Finished | Sep 01 06:18:38 AM UTC 24 |
| Peak memory | 216424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371421053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.2371421053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.4020418629 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 1326945585 ps |
| CPU time | 13.06 seconds |
| Started | Sep 01 06:16:53 AM UTC 24 |
| Finished | Sep 01 06:17:08 AM UTC 24 |
| Peak memory | 212140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020418629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.4020418629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_unmapped_addr.1551963440 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 420179507 ps |
| CPU time | 9.5 seconds |
| Started | Sep 01 06:16:52 AM UTC 24 |
| Finished | Sep 01 06:17:02 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551963440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1551963440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/39.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device.2217013648 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 718094040 ps |
| CPU time | 21.5 seconds |
| Started | Sep 01 06:08:17 AM UTC 24 |
| Finished | Sep 01 06:08:39 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217013648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.2217013648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/4.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.1840893478 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 30903987309 ps |
| CPU time | 182.39 seconds |
| Started | Sep 01 06:08:17 AM UTC 24 |
| Finished | Sep 01 06:11:22 AM UTC 24 |
| Peak memory | 214248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840893478 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.1840893478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.1262919442 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 357744250 ps |
| CPU time | 6.81 seconds |
| Started | Sep 01 06:08:22 AM UTC 24 |
| Finished | Sep 01 06:08:30 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262919442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.1262919442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_error_random.1399976480 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 1713807997 ps |
| CPU time | 10.77 seconds |
| Started | Sep 01 06:08:21 AM UTC 24 |
| Finished | Sep 01 06:08:33 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399976480 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.1399976480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/4.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_large_delays.285720068 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 33459373483 ps |
| CPU time | 122.73 seconds |
| Started | Sep 01 06:08:15 AM UTC 24 |
| Finished | Sep 01 06:10:20 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285720068 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.285720068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/4.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_slow_rsp.359385879 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 8537051440 ps |
| CPU time | 65.23 seconds |
| Started | Sep 01 06:08:17 AM UTC 24 |
| Finished | Sep 01 06:09:23 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359385879 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.359385879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/4.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_zero_delays.2343546134 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 45079030 ps |
| CPU time | 3.52 seconds |
| Started | Sep 01 06:08:15 AM UTC 24 |
| Finished | Sep 01 06:08:20 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343546134 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.2343546134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/4.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_same_source.1702461581 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 629221343 ps |
| CPU time | 9.35 seconds |
| Started | Sep 01 06:08:19 AM UTC 24 |
| Finished | Sep 01 06:08:29 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702461581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1702461581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/4.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke.1376242569 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 8283829 ps |
| CPU time | 1.87 seconds |
| Started | Sep 01 06:08:11 AM UTC 24 |
| Finished | Sep 01 06:08:13 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376242569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1376242569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/4.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_large_delays.3741519622 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 2926376597 ps |
| CPU time | 18.84 seconds |
| Started | Sep 01 06:08:12 AM UTC 24 |
| Finished | Sep 01 06:08:32 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741519622 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.3741519622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/4.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.3916259846 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 2336746053 ps |
| CPU time | 7.39 seconds |
| Started | Sep 01 06:08:13 AM UTC 24 |
| Finished | Sep 01 06:08:22 AM UTC 24 |
| Peak memory | 212456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916259846 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.3916259846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.649765741 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 11536731 ps |
| CPU time | 2 seconds |
| Started | Sep 01 06:08:12 AM UTC 24 |
| Finished | Sep 01 06:08:15 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649765741 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.649765741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/4.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all.4026993460 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 4060069249 ps |
| CPU time | 70.95 seconds |
| Started | Sep 01 06:08:29 AM UTC 24 |
| Finished | Sep 01 06:09:42 AM UTC 24 |
| Peak memory | 214248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026993460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.4026993460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/4.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_error.2941685195 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 1068630571 ps |
| CPU time | 23.13 seconds |
| Started | Sep 01 06:08:32 AM UTC 24 |
| Finished | Sep 01 06:08:56 AM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941685195 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2941685195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/4.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.1357140300 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 13326232666 ps |
| CPU time | 174.44 seconds |
| Started | Sep 01 06:08:32 AM UTC 24 |
| Finished | Sep 01 06:11:29 AM UTC 24 |
| Peak memory | 216292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357140300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.1357140300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.2443994206 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1287781529 ps |
| CPU time | 47.17 seconds |
| Started | Sep 01 06:08:32 AM UTC 24 |
| Finished | Sep 01 06:09:21 AM UTC 24 |
| Peak memory | 214184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443994206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.2443994206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_unmapped_addr.1778382078 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 348107756 ps |
| CPU time | 9.75 seconds |
| Started | Sep 01 06:08:22 AM UTC 24 |
| Finished | Sep 01 06:08:33 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778382078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1778382078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/4.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device.4220595827 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 571060487 ps |
| CPU time | 6.16 seconds |
| Started | Sep 01 06:17:00 AM UTC 24 |
| Finished | Sep 01 06:17:08 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220595827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.4220595827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/40.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3486123527 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 81228440604 ps |
| CPU time | 284.72 seconds |
| Started | Sep 01 06:17:02 AM UTC 24 |
| Finished | Sep 01 06:21:51 AM UTC 24 |
| Peak memory | 214244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486123527 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.3486123527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.3765936790 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 84171521 ps |
| CPU time | 4.3 seconds |
| Started | Sep 01 06:17:05 AM UTC 24 |
| Finished | Sep 01 06:17:11 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765936790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.3765936790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_error_random.1167076781 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 1357305750 ps |
| CPU time | 12.44 seconds |
| Started | Sep 01 06:17:05 AM UTC 24 |
| Finished | Sep 01 06:17:19 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167076781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.1167076781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/40.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random.759961944 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 59485242 ps |
| CPU time | 7.56 seconds |
| Started | Sep 01 06:16:58 AM UTC 24 |
| Finished | Sep 01 06:17:07 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759961944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.759961944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/40.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.1929364313 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 37506522283 ps |
| CPU time | 93.55 seconds |
| Started | Sep 01 06:17:00 AM UTC 24 |
| Finished | Sep 01 06:18:36 AM UTC 24 |
| Peak memory | 211856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929364313 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.1929364313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/40.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1883487241 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 18842637988 ps |
| CPU time | 171.48 seconds |
| Started | Sep 01 06:17:00 AM UTC 24 |
| Finished | Sep 01 06:19:54 AM UTC 24 |
| Peak memory | 211956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883487241 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1883487241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/40.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_zero_delays.3892349509 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 30680955 ps |
| CPU time | 3.99 seconds |
| Started | Sep 01 06:16:58 AM UTC 24 |
| Finished | Sep 01 06:17:03 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892349509 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.3892349509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/40.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_same_source.3354631602 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 129525229 ps |
| CPU time | 9.19 seconds |
| Started | Sep 01 06:17:03 AM UTC 24 |
| Finished | Sep 01 06:17:13 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354631602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3354631602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/40.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke.2807632740 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 49074140 ps |
| CPU time | 2.24 seconds |
| Started | Sep 01 06:16:56 AM UTC 24 |
| Finished | Sep 01 06:16:59 AM UTC 24 |
| Peak memory | 212384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807632740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2807632740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/40.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_large_delays.99514163 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 4729521886 ps |
| CPU time | 8.07 seconds |
| Started | Sep 01 06:16:58 AM UTC 24 |
| Finished | Sep 01 06:17:07 AM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99514163 -assert nopostproc +UVM_TESTNAME=xbar_base_ test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.99514163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/40.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.2406342442 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 1240145205 ps |
| CPU time | 9.41 seconds |
| Started | Sep 01 06:16:58 AM UTC 24 |
| Finished | Sep 01 06:17:09 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406342442 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.2406342442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.1623099984 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 9080678 ps |
| CPU time | 1.68 seconds |
| Started | Sep 01 06:16:56 AM UTC 24 |
| Finished | Sep 01 06:16:59 AM UTC 24 |
| Peak memory | 211132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623099984 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.1623099984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/40.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.1989979121 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 222697160 ps |
| CPU time | 18.81 seconds |
| Started | Sep 01 06:17:05 AM UTC 24 |
| Finished | Sep 01 06:17:25 AM UTC 24 |
| Peak memory | 214188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989979121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1989979121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/40.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.1104546406 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 342285919 ps |
| CPU time | 11.03 seconds |
| Started | Sep 01 06:17:07 AM UTC 24 |
| Finished | Sep 01 06:17:19 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104546406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1104546406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/40.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.301336620 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 26421774 ps |
| CPU time | 13.08 seconds |
| Started | Sep 01 06:17:05 AM UTC 24 |
| Finished | Sep 01 06:17:20 AM UTC 24 |
| Peak memory | 212260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301336620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.301336620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.2689811955 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 3967133969 ps |
| CPU time | 101.52 seconds |
| Started | Sep 01 06:17:07 AM UTC 24 |
| Finished | Sep 01 06:18:51 AM UTC 24 |
| Peak memory | 218344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689811955 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.2689811955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_unmapped_addr.1276861215 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 24995864 ps |
| CPU time | 1.62 seconds |
| Started | Sep 01 06:17:05 AM UTC 24 |
| Finished | Sep 01 06:17:08 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276861215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1276861215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/40.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device.1271541984 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 346840631 ps |
| CPU time | 16.79 seconds |
| Started | Sep 01 06:17:13 AM UTC 24 |
| Finished | Sep 01 06:17:31 AM UTC 24 |
| Peak memory | 212332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271541984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.1271541984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/41.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1920813735 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 67556841187 ps |
| CPU time | 331.79 seconds |
| Started | Sep 01 06:17:13 AM UTC 24 |
| Finished | Sep 01 06:22:49 AM UTC 24 |
| Peak memory | 218048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920813735 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.1920813735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.4026377481 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 106159930 ps |
| CPU time | 2.84 seconds |
| Started | Sep 01 06:17:20 AM UTC 24 |
| Finished | Sep 01 06:17:24 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026377481 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.4026377481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_error_random.314911338 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 256701134 ps |
| CPU time | 2.77 seconds |
| Started | Sep 01 06:17:17 AM UTC 24 |
| Finished | Sep 01 06:17:21 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314911338 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.314911338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/41.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random.1440477851 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 870057689 ps |
| CPU time | 6.15 seconds |
| Started | Sep 01 06:17:09 AM UTC 24 |
| Finished | Sep 01 06:17:17 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440477851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.1440477851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/41.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.976582846 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 18174893675 ps |
| CPU time | 115.35 seconds |
| Started | Sep 01 06:17:12 AM UTC 24 |
| Finished | Sep 01 06:19:09 AM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976582846 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.976582846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/41.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.2114173049 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 22176216836 ps |
| CPU time | 134.93 seconds |
| Started | Sep 01 06:17:12 AM UTC 24 |
| Finished | Sep 01 06:19:29 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114173049 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.2114173049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/41.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_zero_delays.809242436 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 27731556 ps |
| CPU time | 3.24 seconds |
| Started | Sep 01 06:17:11 AM UTC 24 |
| Finished | Sep 01 06:17:16 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809242436 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.809242436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/41.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_same_source.2065416956 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 955247679 ps |
| CPU time | 13.74 seconds |
| Started | Sep 01 06:17:15 AM UTC 24 |
| Finished | Sep 01 06:17:29 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065416956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.2065416956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/41.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke.2384688116 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 10018573 ps |
| CPU time | 1.78 seconds |
| Started | Sep 01 06:17:09 AM UTC 24 |
| Finished | Sep 01 06:17:12 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384688116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.2384688116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/41.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_large_delays.556849601 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 1862122610 ps |
| CPU time | 12.26 seconds |
| Started | Sep 01 06:17:09 AM UTC 24 |
| Finished | Sep 01 06:17:23 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556849601 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.556849601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/41.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.3179094187 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 4483886777 ps |
| CPU time | 21.16 seconds |
| Started | Sep 01 06:17:09 AM UTC 24 |
| Finished | Sep 01 06:17:32 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179094187 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.3179094187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.3442117641 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 11026384 ps |
| CPU time | 1.6 seconds |
| Started | Sep 01 06:17:09 AM UTC 24 |
| Finished | Sep 01 06:17:12 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442117641 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.3442117641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/41.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.3198217276 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 852661458 ps |
| CPU time | 13.84 seconds |
| Started | Sep 01 06:17:20 AM UTC 24 |
| Finished | Sep 01 06:17:35 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198217276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.3198217276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/41.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.3089398940 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 31152119 ps |
| CPU time | 3.45 seconds |
| Started | Sep 01 06:17:22 AM UTC 24 |
| Finished | Sep 01 06:17:26 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089398940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3089398940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/41.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1549666782 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 171275027 ps |
| CPU time | 15.49 seconds |
| Started | Sep 01 06:17:22 AM UTC 24 |
| Finished | Sep 01 06:17:38 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549666782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.1549666782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.1170074544 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 475673842 ps |
| CPU time | 65.83 seconds |
| Started | Sep 01 06:17:23 AM UTC 24 |
| Finished | Sep 01 06:18:30 AM UTC 24 |
| Peak memory | 214380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170074544 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.1170074544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_unmapped_addr.1653671627 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 1033048584 ps |
| CPU time | 10.51 seconds |
| Started | Sep 01 06:17:18 AM UTC 24 |
| Finished | Sep 01 06:17:30 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653671627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1653671627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/41.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device.946671184 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 413060387 ps |
| CPU time | 11.78 seconds |
| Started | Sep 01 06:17:30 AM UTC 24 |
| Finished | Sep 01 06:17:42 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946671184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.946671184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/42.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.300948415 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 97530784 ps |
| CPU time | 6.42 seconds |
| Started | Sep 01 06:17:34 AM UTC 24 |
| Finished | Sep 01 06:17:42 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300948415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.300948415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_error_random.2596495601 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 218277986 ps |
| CPU time | 5.67 seconds |
| Started | Sep 01 06:17:33 AM UTC 24 |
| Finished | Sep 01 06:17:40 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596495601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.2596495601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/42.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random.2857242489 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 397594261 ps |
| CPU time | 9.75 seconds |
| Started | Sep 01 06:17:26 AM UTC 24 |
| Finished | Sep 01 06:17:37 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857242489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2857242489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/42.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.606778802 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 35837522524 ps |
| CPU time | 201.8 seconds |
| Started | Sep 01 06:17:28 AM UTC 24 |
| Finished | Sep 01 06:20:53 AM UTC 24 |
| Peak memory | 212188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606778802 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.606778802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/42.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.499493325 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 53537444580 ps |
| CPU time | 86.51 seconds |
| Started | Sep 01 06:17:29 AM UTC 24 |
| Finished | Sep 01 06:18:58 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499493325 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.499493325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/42.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_zero_delays.799520148 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 47664754 ps |
| CPU time | 6.35 seconds |
| Started | Sep 01 06:17:28 AM UTC 24 |
| Finished | Sep 01 06:17:35 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799520148 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.799520148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/42.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_same_source.847550731 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 208228395 ps |
| CPU time | 5.88 seconds |
| Started | Sep 01 06:17:31 AM UTC 24 |
| Finished | Sep 01 06:17:38 AM UTC 24 |
| Peak memory | 212120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847550731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.847550731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/42.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke.1075060784 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 10257345 ps |
| CPU time | 1.72 seconds |
| Started | Sep 01 06:17:25 AM UTC 24 |
| Finished | Sep 01 06:17:28 AM UTC 24 |
| Peak memory | 211136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075060784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.1075060784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/42.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_large_delays.2288043086 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 1284624770 ps |
| CPU time | 11.01 seconds |
| Started | Sep 01 06:17:25 AM UTC 24 |
| Finished | Sep 01 06:17:37 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288043086 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.2288043086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/42.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.3885696953 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 1703544986 ps |
| CPU time | 12.47 seconds |
| Started | Sep 01 06:17:25 AM UTC 24 |
| Finished | Sep 01 06:17:39 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885696953 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3885696953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.2946938721 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 11575107 ps |
| CPU time | 1.81 seconds |
| Started | Sep 01 06:17:25 AM UTC 24 |
| Finished | Sep 01 06:17:28 AM UTC 24 |
| Peak memory | 211132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946938721 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.2946938721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/42.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.1662168047 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 414189007 ps |
| CPU time | 68.63 seconds |
| Started | Sep 01 06:17:38 AM UTC 24 |
| Finished | Sep 01 06:18:49 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662168047 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.1662168047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/42.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.2709861895 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 11418503782 ps |
| CPU time | 78.69 seconds |
| Started | Sep 01 06:17:37 AM UTC 24 |
| Finished | Sep 01 06:18:57 AM UTC 24 |
| Peak memory | 216424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709861895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.2709861895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.3233233681 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 4763260301 ps |
| CPU time | 72.93 seconds |
| Started | Sep 01 06:17:38 AM UTC 24 |
| Finished | Sep 01 06:18:53 AM UTC 24 |
| Peak memory | 214248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233233681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.3233233681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_unmapped_addr.3930257239 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 289163048 ps |
| CPU time | 9.48 seconds |
| Started | Sep 01 06:17:33 AM UTC 24 |
| Finished | Sep 01 06:17:43 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930257239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3930257239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/42.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.1958207694 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 1551723866 ps |
| CPU time | 22.21 seconds |
| Started | Sep 01 06:17:45 AM UTC 24 |
| Finished | Sep 01 06:18:09 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958207694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.1958207694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/43.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.2870294999 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 44212194316 ps |
| CPU time | 322.3 seconds |
| Started | Sep 01 06:17:45 AM UTC 24 |
| Finished | Sep 01 06:23:12 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870294999 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.2870294999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.3552174732 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 726949684 ps |
| CPU time | 16.37 seconds |
| Started | Sep 01 06:17:51 AM UTC 24 |
| Finished | Sep 01 06:18:09 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552174732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.3552174732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.2298764362 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 70226731 ps |
| CPU time | 2.05 seconds |
| Started | Sep 01 06:17:47 AM UTC 24 |
| Finished | Sep 01 06:17:50 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298764362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.2298764362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/43.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random.1880143101 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 304322829 ps |
| CPU time | 7.77 seconds |
| Started | Sep 01 06:17:42 AM UTC 24 |
| Finished | Sep 01 06:17:51 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880143101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.1880143101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/43.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.200328376 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 72391285963 ps |
| CPU time | 180.93 seconds |
| Started | Sep 01 06:17:43 AM UTC 24 |
| Finished | Sep 01 06:20:47 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200328376 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.200328376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/43.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.4016262818 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 40580757046 ps |
| CPU time | 127.74 seconds |
| Started | Sep 01 06:17:45 AM UTC 24 |
| Finished | Sep 01 06:19:56 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016262818 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.4016262818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/43.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.1130264462 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 43107559 ps |
| CPU time | 3.91 seconds |
| Started | Sep 01 06:17:43 AM UTC 24 |
| Finished | Sep 01 06:17:49 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130264462 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.1130264462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/43.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.2694648136 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 84793582 ps |
| CPU time | 4.96 seconds |
| Started | Sep 01 06:17:47 AM UTC 24 |
| Finished | Sep 01 06:17:53 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694648136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.2694648136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/43.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke.1042332361 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 33788607 ps |
| CPU time | 1.77 seconds |
| Started | Sep 01 06:17:40 AM UTC 24 |
| Finished | Sep 01 06:17:44 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042332361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1042332361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/43.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.2899146296 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 2981343621 ps |
| CPU time | 18.02 seconds |
| Started | Sep 01 06:17:40 AM UTC 24 |
| Finished | Sep 01 06:18:00 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899146296 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2899146296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/43.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.812257046 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 8769420451 ps |
| CPU time | 14.35 seconds |
| Started | Sep 01 06:17:40 AM UTC 24 |
| Finished | Sep 01 06:17:56 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812257046 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.812257046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.3452624928 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 13829414 ps |
| CPU time | 1.74 seconds |
| Started | Sep 01 06:17:40 AM UTC 24 |
| Finished | Sep 01 06:17:43 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452624928 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.3452624928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/43.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.1436268164 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 88229226 ps |
| CPU time | 8.44 seconds |
| Started | Sep 01 06:17:52 AM UTC 24 |
| Finished | Sep 01 06:18:02 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436268164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.1436268164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/43.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1804845559 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 578800657 ps |
| CPU time | 48.21 seconds |
| Started | Sep 01 06:17:57 AM UTC 24 |
| Finished | Sep 01 06:18:47 AM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804845559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1804845559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/43.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.2110884964 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 508817353 ps |
| CPU time | 45.84 seconds |
| Started | Sep 01 06:17:55 AM UTC 24 |
| Finished | Sep 01 06:18:42 AM UTC 24 |
| Peak memory | 216232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110884964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.2110884964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3964444616 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 384413803 ps |
| CPU time | 27.56 seconds |
| Started | Sep 01 06:17:57 AM UTC 24 |
| Finished | Sep 01 06:18:26 AM UTC 24 |
| Peak memory | 214184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964444616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.3964444616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.3035274709 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 1572142963 ps |
| CPU time | 12.44 seconds |
| Started | Sep 01 06:17:50 AM UTC 24 |
| Finished | Sep 01 06:18:03 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035274709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.3035274709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/43.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.209930786 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 99183731 ps |
| CPU time | 14.07 seconds |
| Started | Sep 01 06:18:04 AM UTC 24 |
| Finished | Sep 01 06:18:19 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209930786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.209930786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/44.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.2080202696 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 25997057064 ps |
| CPU time | 163.54 seconds |
| Started | Sep 01 06:18:05 AM UTC 24 |
| Finished | Sep 01 06:20:51 AM UTC 24 |
| Peak memory | 214240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080202696 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.2080202696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.404597936 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 80879571 ps |
| CPU time | 6.28 seconds |
| Started | Sep 01 06:18:10 AM UTC 24 |
| Finished | Sep 01 06:18:17 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404597936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.404597936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.1277772735 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 508315528 ps |
| CPU time | 10.75 seconds |
| Started | Sep 01 06:18:08 AM UTC 24 |
| Finished | Sep 01 06:18:20 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277772735 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1277772735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/44.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random.2352145389 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 594583636 ps |
| CPU time | 18.01 seconds |
| Started | Sep 01 06:18:02 AM UTC 24 |
| Finished | Sep 01 06:18:21 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352145389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.2352145389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/44.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.3688737249 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 107335923551 ps |
| CPU time | 135.76 seconds |
| Started | Sep 01 06:18:04 AM UTC 24 |
| Finished | Sep 01 06:20:22 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688737249 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.3688737249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/44.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3123901280 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 8465976253 ps |
| CPU time | 50.52 seconds |
| Started | Sep 01 06:18:04 AM UTC 24 |
| Finished | Sep 01 06:18:56 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123901280 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3123901280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/44.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.1026015100 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 73529812 ps |
| CPU time | 4.79 seconds |
| Started | Sep 01 06:18:02 AM UTC 24 |
| Finished | Sep 01 06:18:08 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026015100 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.1026015100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/44.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.3981256578 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 1713896492 ps |
| CPU time | 15.44 seconds |
| Started | Sep 01 06:18:07 AM UTC 24 |
| Finished | Sep 01 06:18:23 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981256578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3981256578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/44.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.827589276 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 90281644 ps |
| CPU time | 2.1 seconds |
| Started | Sep 01 06:17:57 AM UTC 24 |
| Finished | Sep 01 06:18:00 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827589276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.827589276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/44.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1909405976 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 2263448935 ps |
| CPU time | 9.11 seconds |
| Started | Sep 01 06:17:59 AM UTC 24 |
| Finished | Sep 01 06:18:09 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909405976 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1909405976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/44.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.1268609989 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 632146735 ps |
| CPU time | 8.88 seconds |
| Started | Sep 01 06:18:01 AM UTC 24 |
| Finished | Sep 01 06:18:12 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268609989 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.1268609989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.512443636 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 14840098 ps |
| CPU time | 1.83 seconds |
| Started | Sep 01 06:17:57 AM UTC 24 |
| Finished | Sep 01 06:18:00 AM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512443636 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.512443636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/44.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.2497884708 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 6152445141 ps |
| CPU time | 31 seconds |
| Started | Sep 01 06:18:10 AM UTC 24 |
| Finished | Sep 01 06:18:42 AM UTC 24 |
| Peak memory | 214440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497884708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.2497884708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/44.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2004982627 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 304987210 ps |
| CPU time | 22.6 seconds |
| Started | Sep 01 06:18:13 AM UTC 24 |
| Finished | Sep 01 06:18:37 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004982627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2004982627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/44.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.134966578 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 5000956675 ps |
| CPU time | 59.33 seconds |
| Started | Sep 01 06:18:11 AM UTC 24 |
| Finished | Sep 01 06:19:12 AM UTC 24 |
| Peak memory | 216548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134966578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.134966578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2519708643 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 4713499025 ps |
| CPU time | 120.57 seconds |
| Started | Sep 01 06:18:15 AM UTC 24 |
| Finished | Sep 01 06:20:18 AM UTC 24 |
| Peak memory | 218348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519708643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.2519708643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.2830455815 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 857680509 ps |
| CPU time | 12.3 seconds |
| Started | Sep 01 06:18:08 AM UTC 24 |
| Finished | Sep 01 06:18:22 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830455815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2830455815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/44.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.653223368 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 73018910 ps |
| CPU time | 17.11 seconds |
| Started | Sep 01 06:18:24 AM UTC 24 |
| Finished | Sep 01 06:18:43 AM UTC 24 |
| Peak memory | 212120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653223368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.653223368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/45.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.888615307 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 20071227409 ps |
| CPU time | 168.84 seconds |
| Started | Sep 01 06:18:28 AM UTC 24 |
| Finished | Sep 01 06:21:19 AM UTC 24 |
| Peak memory | 214244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888615307 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.888615307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.453081331 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 198871571 ps |
| CPU time | 3.84 seconds |
| Started | Sep 01 06:18:29 AM UTC 24 |
| Finished | Sep 01 06:18:34 AM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453081331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.453081331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.3077461776 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 46453689 ps |
| CPU time | 5.85 seconds |
| Started | Sep 01 06:18:28 AM UTC 24 |
| Finished | Sep 01 06:18:35 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077461776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3077461776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/45.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random.305510021 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 73539655 ps |
| CPU time | 7.91 seconds |
| Started | Sep 01 06:18:23 AM UTC 24 |
| Finished | Sep 01 06:18:32 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305510021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.305510021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/45.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.2598378846 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 26991383317 ps |
| CPU time | 166.22 seconds |
| Started | Sep 01 06:18:23 AM UTC 24 |
| Finished | Sep 01 06:21:12 AM UTC 24 |
| Peak memory | 212456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598378846 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2598378846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/45.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.786979158 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 24594724056 ps |
| CPU time | 185.91 seconds |
| Started | Sep 01 06:18:23 AM UTC 24 |
| Finished | Sep 01 06:21:32 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786979158 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.786979158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/45.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.1740398131 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 71187255 ps |
| CPU time | 11.03 seconds |
| Started | Sep 01 06:18:23 AM UTC 24 |
| Finished | Sep 01 06:18:35 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740398131 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.1740398131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/45.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.388446420 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 513064287 ps |
| CPU time | 9.57 seconds |
| Started | Sep 01 06:18:28 AM UTC 24 |
| Finished | Sep 01 06:18:38 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388446420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.388446420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/45.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.1203700956 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 81383298 ps |
| CPU time | 1.89 seconds |
| Started | Sep 01 06:18:19 AM UTC 24 |
| Finished | Sep 01 06:18:22 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203700956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.1203700956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/45.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.2755837893 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 1952200989 ps |
| CPU time | 10.92 seconds |
| Started | Sep 01 06:18:21 AM UTC 24 |
| Finished | Sep 01 06:18:33 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755837893 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2755837893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/45.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.3504687080 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 1327107750 ps |
| CPU time | 13.87 seconds |
| Started | Sep 01 06:18:21 AM UTC 24 |
| Finished | Sep 01 06:18:36 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504687080 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.3504687080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1952698466 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 19586179 ps |
| CPU time | 1.72 seconds |
| Started | Sep 01 06:18:19 AM UTC 24 |
| Finished | Sep 01 06:18:22 AM UTC 24 |
| Peak memory | 211132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952698466 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.1952698466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/45.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.3915770263 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 2948099641 ps |
| CPU time | 14.03 seconds |
| Started | Sep 01 06:18:32 AM UTC 24 |
| Finished | Sep 01 06:18:47 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915770263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3915770263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/45.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.626257372 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 3757368048 ps |
| CPU time | 73.2 seconds |
| Started | Sep 01 06:18:34 AM UTC 24 |
| Finished | Sep 01 06:19:49 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626257372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.626257372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/45.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.3168098167 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 1202548649 ps |
| CPU time | 120.56 seconds |
| Started | Sep 01 06:18:32 AM UTC 24 |
| Finished | Sep 01 06:20:35 AM UTC 24 |
| Peak memory | 216232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168098167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.3168098167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1565325574 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 3460246228 ps |
| CPU time | 69.79 seconds |
| Started | Sep 01 06:18:34 AM UTC 24 |
| Finished | Sep 01 06:19:45 AM UTC 24 |
| Peak memory | 214248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565325574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.1565325574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.418994856 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 80146692 ps |
| CPU time | 2.74 seconds |
| Started | Sep 01 06:18:28 AM UTC 24 |
| Finished | Sep 01 06:18:32 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418994856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.418994856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/45.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.2378079124 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 576137999 ps |
| CPU time | 14.75 seconds |
| Started | Sep 01 06:18:38 AM UTC 24 |
| Finished | Sep 01 06:18:54 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378079124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2378079124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/46.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1007669146 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 14966164734 ps |
| CPU time | 109.74 seconds |
| Started | Sep 01 06:18:41 AM UTC 24 |
| Finished | Sep 01 06:20:33 AM UTC 24 |
| Peak memory | 214436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007669146 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.1007669146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2037290690 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 17354777 ps |
| CPU time | 1.86 seconds |
| Started | Sep 01 06:18:41 AM UTC 24 |
| Finished | Sep 01 06:18:44 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037290690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.2037290690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.1615900647 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 823036505 ps |
| CPU time | 14.84 seconds |
| Started | Sep 01 06:18:41 AM UTC 24 |
| Finished | Sep 01 06:18:57 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615900647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1615900647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/46.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random.1932652717 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 454452586 ps |
| CPU time | 4.04 seconds |
| Started | Sep 01 06:18:38 AM UTC 24 |
| Finished | Sep 01 06:18:43 AM UTC 24 |
| Peak memory | 212384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932652717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.1932652717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/46.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.1388722157 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 103945667502 ps |
| CPU time | 144.01 seconds |
| Started | Sep 01 06:18:38 AM UTC 24 |
| Finished | Sep 01 06:21:04 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388722157 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1388722157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/46.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.4083369017 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 51553106768 ps |
| CPU time | 213.45 seconds |
| Started | Sep 01 06:18:38 AM UTC 24 |
| Finished | Sep 01 06:22:14 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083369017 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.4083369017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/46.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.3434376682 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 206497220 ps |
| CPU time | 4.92 seconds |
| Started | Sep 01 06:18:38 AM UTC 24 |
| Finished | Sep 01 06:18:44 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434376682 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.3434376682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/46.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.594673083 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 1746387659 ps |
| CPU time | 6.66 seconds |
| Started | Sep 01 06:18:41 AM UTC 24 |
| Finished | Sep 01 06:18:49 AM UTC 24 |
| Peak memory | 212316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594673083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.594673083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/46.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.1531748613 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 31215837 ps |
| CPU time | 1.85 seconds |
| Started | Sep 01 06:18:34 AM UTC 24 |
| Finished | Sep 01 06:18:37 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531748613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.1531748613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/46.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.849381740 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 2524090912 ps |
| CPU time | 16.83 seconds |
| Started | Sep 01 06:18:37 AM UTC 24 |
| Finished | Sep 01 06:18:56 AM UTC 24 |
| Peak memory | 212188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849381740 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.849381740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/46.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.1865451080 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 1002167742 ps |
| CPU time | 8.77 seconds |
| Started | Sep 01 06:18:37 AM UTC 24 |
| Finished | Sep 01 06:18:47 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865451080 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1865451080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1046357240 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 15163695 ps |
| CPU time | 1.74 seconds |
| Started | Sep 01 06:18:35 AM UTC 24 |
| Finished | Sep 01 06:18:38 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046357240 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.1046357240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/46.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.2434534397 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 2057042884 ps |
| CPU time | 38.12 seconds |
| Started | Sep 01 06:18:41 AM UTC 24 |
| Finished | Sep 01 06:19:21 AM UTC 24 |
| Peak memory | 214376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434534397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2434534397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/46.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.2033978450 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 3437472570 ps |
| CPU time | 57.83 seconds |
| Started | Sep 01 06:18:44 AM UTC 24 |
| Finished | Sep 01 06:19:44 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033978450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2033978450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/46.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.721607808 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 191063382 ps |
| CPU time | 17.41 seconds |
| Started | Sep 01 06:18:41 AM UTC 24 |
| Finished | Sep 01 06:19:00 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721607808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.721607808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.1901748905 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 27102446 ps |
| CPU time | 8.95 seconds |
| Started | Sep 01 06:18:46 AM UTC 24 |
| Finished | Sep 01 06:18:56 AM UTC 24 |
| Peak memory | 212204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901748905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.1901748905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.1715286974 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 1679263323 ps |
| CPU time | 13.34 seconds |
| Started | Sep 01 06:18:41 AM UTC 24 |
| Finished | Sep 01 06:18:56 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715286974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1715286974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/46.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.3768857785 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 113755581 ps |
| CPU time | 10.55 seconds |
| Started | Sep 01 06:18:52 AM UTC 24 |
| Finished | Sep 01 06:19:03 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768857785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.3768857785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/47.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.1262535733 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 93274349406 ps |
| CPU time | 166.15 seconds |
| Started | Sep 01 06:18:52 AM UTC 24 |
| Finished | Sep 01 06:21:40 AM UTC 24 |
| Peak memory | 214240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262535733 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.1262535733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3093373462 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 143964481 ps |
| CPU time | 4.9 seconds |
| Started | Sep 01 06:18:55 AM UTC 24 |
| Finished | Sep 01 06:19:01 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093373462 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.3093373462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.498539638 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 31708913 ps |
| CPU time | 4.68 seconds |
| Started | Sep 01 06:18:52 AM UTC 24 |
| Finished | Sep 01 06:18:57 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498539638 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.498539638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/47.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random.1151518843 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 121514301 ps |
| CPU time | 4.11 seconds |
| Started | Sep 01 06:18:47 AM UTC 24 |
| Finished | Sep 01 06:18:52 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151518843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.1151518843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/47.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.3577231087 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 5575163337 ps |
| CPU time | 27.56 seconds |
| Started | Sep 01 06:18:51 AM UTC 24 |
| Finished | Sep 01 06:19:20 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577231087 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3577231087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/47.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.2388353824 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 25056833535 ps |
| CPU time | 72.11 seconds |
| Started | Sep 01 06:18:51 AM UTC 24 |
| Finished | Sep 01 06:20:05 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388353824 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.2388353824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/47.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.1242767144 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 16537178 ps |
| CPU time | 1.54 seconds |
| Started | Sep 01 06:18:51 AM UTC 24 |
| Finished | Sep 01 06:18:54 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242767144 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.1242767144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/47.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.2199235226 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 52981168 ps |
| CPU time | 5.82 seconds |
| Started | Sep 01 06:18:52 AM UTC 24 |
| Finished | Sep 01 06:18:59 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199235226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2199235226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/47.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.4092999691 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 12589591 ps |
| CPU time | 1.67 seconds |
| Started | Sep 01 06:18:46 AM UTC 24 |
| Finished | Sep 01 06:18:48 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092999691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.4092999691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/47.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1302986778 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 1508896724 ps |
| CPU time | 14.73 seconds |
| Started | Sep 01 06:18:46 AM UTC 24 |
| Finished | Sep 01 06:19:02 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302986778 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1302986778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/47.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.4149143227 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 2064604177 ps |
| CPU time | 18.74 seconds |
| Started | Sep 01 06:18:47 AM UTC 24 |
| Finished | Sep 01 06:19:07 AM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149143227 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.4149143227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.2091297112 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 10798922 ps |
| CPU time | 1.57 seconds |
| Started | Sep 01 06:18:46 AM UTC 24 |
| Finished | Sep 01 06:18:48 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091297112 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.2091297112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/47.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.1664863087 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 284614961 ps |
| CPU time | 8.94 seconds |
| Started | Sep 01 06:18:55 AM UTC 24 |
| Finished | Sep 01 06:19:05 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664863087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.1664863087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/47.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2611311526 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 6751826045 ps |
| CPU time | 66.39 seconds |
| Started | Sep 01 06:18:55 AM UTC 24 |
| Finished | Sep 01 06:20:03 AM UTC 24 |
| Peak memory | 214244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611311526 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.2611311526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/47.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.1651118300 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 9210819117 ps |
| CPU time | 163.69 seconds |
| Started | Sep 01 06:18:55 AM UTC 24 |
| Finished | Sep 01 06:21:42 AM UTC 24 |
| Peak memory | 216292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651118300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.1651118300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.2987416463 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 502367608 ps |
| CPU time | 62.27 seconds |
| Started | Sep 01 06:18:55 AM UTC 24 |
| Finished | Sep 01 06:19:59 AM UTC 24 |
| Peak memory | 214184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987416463 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.2987416463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.3351532342 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 553664779 ps |
| CPU time | 7.46 seconds |
| Started | Sep 01 06:18:55 AM UTC 24 |
| Finished | Sep 01 06:19:03 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351532342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.3351532342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/47.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.2718721922 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 244818064 ps |
| CPU time | 14.21 seconds |
| Started | Sep 01 06:19:03 AM UTC 24 |
| Finished | Sep 01 06:19:19 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718721922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.2718721922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/48.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.3767866579 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 11678315892 ps |
| CPU time | 25.58 seconds |
| Started | Sep 01 06:19:03 AM UTC 24 |
| Finished | Sep 01 06:19:30 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767866579 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.3767866579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3071319089 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 42889389 ps |
| CPU time | 5.86 seconds |
| Started | Sep 01 06:19:04 AM UTC 24 |
| Finished | Sep 01 06:19:11 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071319089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.3071319089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.642233178 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 613407882 ps |
| CPU time | 6.81 seconds |
| Started | Sep 01 06:19:03 AM UTC 24 |
| Finished | Sep 01 06:19:11 AM UTC 24 |
| Peak memory | 212260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642233178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.642233178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/48.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random.1727519756 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 3769229883 ps |
| CPU time | 13.65 seconds |
| Started | Sep 01 06:18:59 AM UTC 24 |
| Finished | Sep 01 06:19:14 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727519756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.1727519756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/48.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.810153019 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 57065100733 ps |
| CPU time | 42.78 seconds |
| Started | Sep 01 06:18:59 AM UTC 24 |
| Finished | Sep 01 06:19:43 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810153019 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.810153019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/48.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.867104128 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 35281273441 ps |
| CPU time | 190.22 seconds |
| Started | Sep 01 06:19:03 AM UTC 24 |
| Finished | Sep 01 06:22:17 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867104128 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.867104128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/48.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.4240900036 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 79951200 ps |
| CPU time | 2.59 seconds |
| Started | Sep 01 06:18:59 AM UTC 24 |
| Finished | Sep 01 06:19:02 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240900036 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.4240900036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/48.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.4193704255 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 13165075 ps |
| CPU time | 1.96 seconds |
| Started | Sep 01 06:19:03 AM UTC 24 |
| Finished | Sep 01 06:19:06 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193704255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.4193704255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/48.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.2888501960 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 44108604 ps |
| CPU time | 2.22 seconds |
| Started | Sep 01 06:18:59 AM UTC 24 |
| Finished | Sep 01 06:19:02 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888501960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.2888501960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/48.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.3255605694 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 2179064379 ps |
| CPU time | 7.71 seconds |
| Started | Sep 01 06:18:59 AM UTC 24 |
| Finished | Sep 01 06:19:07 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255605694 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.3255605694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/48.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.2456475699 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 856600292 ps |
| CPU time | 12.15 seconds |
| Started | Sep 01 06:18:59 AM UTC 24 |
| Finished | Sep 01 06:19:12 AM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456475699 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.2456475699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.3178704006 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 11195700 ps |
| CPU time | 1.73 seconds |
| Started | Sep 01 06:18:59 AM UTC 24 |
| Finished | Sep 01 06:19:01 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178704006 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.3178704006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/48.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.720966295 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 1798233615 ps |
| CPU time | 30.99 seconds |
| Started | Sep 01 06:19:04 AM UTC 24 |
| Finished | Sep 01 06:19:36 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720966295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.720966295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/48.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1198005749 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 8531666974 ps |
| CPU time | 80.23 seconds |
| Started | Sep 01 06:19:08 AM UTC 24 |
| Finished | Sep 01 06:20:30 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198005749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.1198005749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/48.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3952881747 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 8184877314 ps |
| CPU time | 140.5 seconds |
| Started | Sep 01 06:19:04 AM UTC 24 |
| Finished | Sep 01 06:21:27 AM UTC 24 |
| Peak memory | 216292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952881747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.3952881747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1073206964 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 693132011 ps |
| CPU time | 65.77 seconds |
| Started | Sep 01 06:19:08 AM UTC 24 |
| Finished | Sep 01 06:20:15 AM UTC 24 |
| Peak memory | 214380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073206964 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.1073206964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.3641882844 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 372839565 ps |
| CPU time | 9.45 seconds |
| Started | Sep 01 06:19:04 AM UTC 24 |
| Finished | Sep 01 06:19:14 AM UTC 24 |
| Peak memory | 212064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641882844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3641882844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/48.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.1005108142 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 263826596 ps |
| CPU time | 16.64 seconds |
| Started | Sep 01 06:19:12 AM UTC 24 |
| Finished | Sep 01 06:19:29 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005108142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.1005108142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/49.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3525077153 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 13285985560 ps |
| CPU time | 130.23 seconds |
| Started | Sep 01 06:19:15 AM UTC 24 |
| Finished | Sep 01 06:21:28 AM UTC 24 |
| Peak memory | 211836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525077153 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.3525077153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1371741576 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 804733652 ps |
| CPU time | 15.41 seconds |
| Started | Sep 01 06:19:15 AM UTC 24 |
| Finished | Sep 01 06:19:33 AM UTC 24 |
| Peak memory | 212060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371741576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.1371741576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.2522601626 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 97287591 ps |
| CPU time | 8.97 seconds |
| Started | Sep 01 06:19:15 AM UTC 24 |
| Finished | Sep 01 06:19:26 AM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522601626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.2522601626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/49.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random.2147969840 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 226033348 ps |
| CPU time | 5.94 seconds |
| Started | Sep 01 06:19:08 AM UTC 24 |
| Finished | Sep 01 06:19:15 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147969840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.2147969840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/49.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.1203638489 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 8408806752 ps |
| CPU time | 38.31 seconds |
| Started | Sep 01 06:19:11 AM UTC 24 |
| Finished | Sep 01 06:19:51 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203638489 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.1203638489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/49.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.971671312 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 21185037221 ps |
| CPU time | 144.78 seconds |
| Started | Sep 01 06:19:12 AM UTC 24 |
| Finished | Sep 01 06:21:39 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971671312 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.971671312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/49.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.3413183093 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 295600457 ps |
| CPU time | 5.75 seconds |
| Started | Sep 01 06:19:11 AM UTC 24 |
| Finished | Sep 01 06:19:18 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413183093 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.3413183093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/49.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.3340227505 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 218105718 ps |
| CPU time | 4.57 seconds |
| Started | Sep 01 06:19:15 AM UTC 24 |
| Finished | Sep 01 06:19:22 AM UTC 24 |
| Peak memory | 211896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340227505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.3340227505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/49.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.854687716 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 84950903 ps |
| CPU time | 2.29 seconds |
| Started | Sep 01 06:19:08 AM UTC 24 |
| Finished | Sep 01 06:19:11 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854687716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.854687716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/49.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.2143255362 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 7785242383 ps |
| CPU time | 14.9 seconds |
| Started | Sep 01 06:19:08 AM UTC 24 |
| Finished | Sep 01 06:19:24 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143255362 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.2143255362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/49.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1048934304 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 954919458 ps |
| CPU time | 8.74 seconds |
| Started | Sep 01 06:19:08 AM UTC 24 |
| Finished | Sep 01 06:19:18 AM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048934304 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.1048934304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1854193083 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 27793565 ps |
| CPU time | 1.85 seconds |
| Started | Sep 01 06:19:08 AM UTC 24 |
| Finished | Sep 01 06:19:11 AM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854193083 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.1854193083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/49.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.2794722005 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 3495839977 ps |
| CPU time | 46.15 seconds |
| Started | Sep 01 06:19:15 AM UTC 24 |
| Finished | Sep 01 06:20:03 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794722005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.2794722005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/49.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.52941935 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 1116853950 ps |
| CPU time | 13.54 seconds |
| Started | Sep 01 06:19:16 AM UTC 24 |
| Finished | Sep 01 06:19:31 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52941935 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.52941935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/49.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.3281734022 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 4526639596 ps |
| CPU time | 50.3 seconds |
| Started | Sep 01 06:19:16 AM UTC 24 |
| Finished | Sep 01 06:20:08 AM UTC 24 |
| Peak memory | 216552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281734022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.3281734022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.3052084277 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 814300664 ps |
| CPU time | 62.19 seconds |
| Started | Sep 01 06:19:18 AM UTC 24 |
| Finished | Sep 01 06:20:22 AM UTC 24 |
| Peak memory | 216232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052084277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.3052084277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.2460026190 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 84624578 ps |
| CPU time | 5.76 seconds |
| Started | Sep 01 06:19:15 AM UTC 24 |
| Finished | Sep 01 06:19:23 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460026190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2460026190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/49.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device.3922261761 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 281759939 ps |
| CPU time | 10.78 seconds |
| Started | Sep 01 06:08:37 AM UTC 24 |
| Finished | Sep 01 06:08:49 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922261761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.3922261761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/5.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.2844852469 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 43361742151 ps |
| CPU time | 393.56 seconds |
| Started | Sep 01 06:08:37 AM UTC 24 |
| Finished | Sep 01 06:15:15 AM UTC 24 |
| Peak memory | 218140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844852469 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.2844852469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.2548085584 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 16512249 ps |
| CPU time | 2.46 seconds |
| Started | Sep 01 06:08:40 AM UTC 24 |
| Finished | Sep 01 06:08:44 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548085584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.2548085584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_error_random.640985282 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 85176517 ps |
| CPU time | 7.42 seconds |
| Started | Sep 01 06:08:39 AM UTC 24 |
| Finished | Sep 01 06:08:47 AM UTC 24 |
| Peak memory | 212120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640985282 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.640985282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/5.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random.3618549103 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 269636144 ps |
| CPU time | 10.29 seconds |
| Started | Sep 01 06:08:35 AM UTC 24 |
| Finished | Sep 01 06:08:46 AM UTC 24 |
| Peak memory | 212120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618549103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.3618549103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/5.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_large_delays.3073087418 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 58438749430 ps |
| CPU time | 43.15 seconds |
| Started | Sep 01 06:08:35 AM UTC 24 |
| Finished | Sep 01 06:09:20 AM UTC 24 |
| Peak memory | 212188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073087418 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3073087418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/5.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_slow_rsp.3807304413 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 17783058059 ps |
| CPU time | 106.92 seconds |
| Started | Sep 01 06:08:35 AM UTC 24 |
| Finished | Sep 01 06:10:24 AM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807304413 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.3807304413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/5.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_zero_delays.3791837556 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 103817278 ps |
| CPU time | 8.05 seconds |
| Started | Sep 01 06:08:35 AM UTC 24 |
| Finished | Sep 01 06:08:44 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791837556 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.3791837556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/5.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_same_source.3368537732 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 5605237755 ps |
| CPU time | 14.28 seconds |
| Started | Sep 01 06:08:37 AM UTC 24 |
| Finished | Sep 01 06:08:52 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368537732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.3368537732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/5.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke.3961296994 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 40810832 ps |
| CPU time | 2.24 seconds |
| Started | Sep 01 06:08:32 AM UTC 24 |
| Finished | Sep 01 06:08:35 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961296994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.3961296994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/5.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_large_delays.3649396839 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 2572279616 ps |
| CPU time | 13.82 seconds |
| Started | Sep 01 06:08:33 AM UTC 24 |
| Finished | Sep 01 06:08:48 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649396839 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.3649396839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/5.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.709159288 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 1672571777 ps |
| CPU time | 14.07 seconds |
| Started | Sep 01 06:08:33 AM UTC 24 |
| Finished | Sep 01 06:08:49 AM UTC 24 |
| Peak memory | 212380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709159288 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.709159288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.3712867017 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 9210518 ps |
| CPU time | 1.51 seconds |
| Started | Sep 01 06:08:33 AM UTC 24 |
| Finished | Sep 01 06:08:36 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712867017 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.3712867017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/5.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all.4047748229 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 8853985050 ps |
| CPU time | 117.55 seconds |
| Started | Sep 01 06:08:42 AM UTC 24 |
| Finished | Sep 01 06:10:42 AM UTC 24 |
| Peak memory | 214244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047748229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.4047748229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/5.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_error.2766904696 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 5095662261 ps |
| CPU time | 91.03 seconds |
| Started | Sep 01 06:08:45 AM UTC 24 |
| Finished | Sep 01 06:10:18 AM UTC 24 |
| Peak memory | 214436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766904696 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2766904696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/5.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.3963909865 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 1043903354 ps |
| CPU time | 97.41 seconds |
| Started | Sep 01 06:08:45 AM UTC 24 |
| Finished | Sep 01 06:10:25 AM UTC 24 |
| Peak memory | 216232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963909865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.3963909865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.4177505437 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 179995532 ps |
| CPU time | 24.52 seconds |
| Started | Sep 01 06:08:45 AM UTC 24 |
| Finished | Sep 01 06:09:11 AM UTC 24 |
| Peak memory | 214380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177505437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.4177505437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_unmapped_addr.797797765 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 801378463 ps |
| CPU time | 15.55 seconds |
| Started | Sep 01 06:08:40 AM UTC 24 |
| Finished | Sep 01 06:08:57 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797797765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.797797765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/5.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device.2126899336 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 80429615 ps |
| CPU time | 13.77 seconds |
| Started | Sep 01 06:08:54 AM UTC 24 |
| Finished | Sep 01 06:09:09 AM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126899336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2126899336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/6.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.3595170729 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 793611264 ps |
| CPU time | 14.15 seconds |
| Started | Sep 01 06:08:57 AM UTC 24 |
| Finished | Sep 01 06:09:12 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595170729 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.3595170729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_error_random.3246112397 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 84181874 ps |
| CPU time | 10.89 seconds |
| Started | Sep 01 06:08:55 AM UTC 24 |
| Finished | Sep 01 06:09:07 AM UTC 24 |
| Peak memory | 212260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246112397 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.3246112397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/6.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random.1169865277 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 235470017 ps |
| CPU time | 2.35 seconds |
| Started | Sep 01 06:08:49 AM UTC 24 |
| Finished | Sep 01 06:08:52 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169865277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.1169865277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/6.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_large_delays.3886375934 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 53752290643 ps |
| CPU time | 173.29 seconds |
| Started | Sep 01 06:08:51 AM UTC 24 |
| Finished | Sep 01 06:11:47 AM UTC 24 |
| Peak memory | 212384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886375934 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.3886375934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/6.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_slow_rsp.620174671 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 8306336968 ps |
| CPU time | 45.12 seconds |
| Started | Sep 01 06:08:52 AM UTC 24 |
| Finished | Sep 01 06:09:39 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620174671 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.620174671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/6.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_zero_delays.1532942421 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 43188423 ps |
| CPU time | 4.02 seconds |
| Started | Sep 01 06:08:50 AM UTC 24 |
| Finished | Sep 01 06:08:55 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532942421 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.1532942421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/6.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_same_source.4185758504 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 27754718 ps |
| CPU time | 3.04 seconds |
| Started | Sep 01 06:08:55 AM UTC 24 |
| Finished | Sep 01 06:08:59 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185758504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.4185758504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/6.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke.2874445723 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 139829682 ps |
| CPU time | 2.51 seconds |
| Started | Sep 01 06:08:47 AM UTC 24 |
| Finished | Sep 01 06:08:51 AM UTC 24 |
| Peak memory | 212324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874445723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2874445723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/6.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_large_delays.3364407722 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 3038634349 ps |
| CPU time | 15.1 seconds |
| Started | Sep 01 06:08:49 AM UTC 24 |
| Finished | Sep 01 06:09:05 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364407722 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3364407722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/6.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.2723077533 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 9116085654 ps |
| CPU time | 20.44 seconds |
| Started | Sep 01 06:08:49 AM UTC 24 |
| Finished | Sep 01 06:09:11 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723077533 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.2723077533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.713621268 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 13704847 ps |
| CPU time | 1.67 seconds |
| Started | Sep 01 06:08:49 AM UTC 24 |
| Finished | Sep 01 06:08:52 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713621268 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.713621268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/6.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all.2916138274 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 163331473 ps |
| CPU time | 12.67 seconds |
| Started | Sep 01 06:08:57 AM UTC 24 |
| Finished | Sep 01 06:09:11 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916138274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2916138274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/6.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_error.1894843026 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 161102895 ps |
| CPU time | 19 seconds |
| Started | Sep 01 06:08:59 AM UTC 24 |
| Finished | Sep 01 06:09:19 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894843026 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.1894843026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/6.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.1284386778 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 276480083 ps |
| CPU time | 44.01 seconds |
| Started | Sep 01 06:08:59 AM UTC 24 |
| Finished | Sep 01 06:09:44 AM UTC 24 |
| Peak memory | 214184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284386778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.1284386778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1516511678 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 12878611246 ps |
| CPU time | 137.05 seconds |
| Started | Sep 01 06:09:00 AM UTC 24 |
| Finished | Sep 01 06:11:19 AM UTC 24 |
| Peak memory | 216296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516511678 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.1516511678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_unmapped_addr.3684723282 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 205586904 ps |
| CPU time | 2.48 seconds |
| Started | Sep 01 06:08:56 AM UTC 24 |
| Finished | Sep 01 06:08:59 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684723282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3684723282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/6.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device.1431965687 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 1219234410 ps |
| CPU time | 29.34 seconds |
| Started | Sep 01 06:09:10 AM UTC 24 |
| Finished | Sep 01 06:09:41 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431965687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.1431965687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/7.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.3323809576 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 20809907783 ps |
| CPU time | 198.24 seconds |
| Started | Sep 01 06:09:12 AM UTC 24 |
| Finished | Sep 01 06:12:33 AM UTC 24 |
| Peak memory | 214244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323809576 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.3323809576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.3463178867 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 431894759 ps |
| CPU time | 8.18 seconds |
| Started | Sep 01 06:09:13 AM UTC 24 |
| Finished | Sep 01 06:09:23 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463178867 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.3463178867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_error_random.4066794325 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 571870854 ps |
| CPU time | 11.3 seconds |
| Started | Sep 01 06:09:12 AM UTC 24 |
| Finished | Sep 01 06:09:25 AM UTC 24 |
| Peak memory | 212384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066794325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.4066794325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/7.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random.1103424992 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 157529696 ps |
| CPU time | 3.74 seconds |
| Started | Sep 01 06:09:07 AM UTC 24 |
| Finished | Sep 01 06:09:12 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103424992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.1103424992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/7.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_large_delays.2974879227 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 123139821128 ps |
| CPU time | 135.02 seconds |
| Started | Sep 01 06:09:08 AM UTC 24 |
| Finished | Sep 01 06:11:26 AM UTC 24 |
| Peak memory | 212384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974879227 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2974879227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/7.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_slow_rsp.658547269 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 34758813902 ps |
| CPU time | 135.81 seconds |
| Started | Sep 01 06:09:09 AM UTC 24 |
| Finished | Sep 01 06:11:27 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658547269 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.658547269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/7.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_zero_delays.633900398 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 51614250 ps |
| CPU time | 9.28 seconds |
| Started | Sep 01 06:09:07 AM UTC 24 |
| Finished | Sep 01 06:09:17 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633900398 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.633900398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/7.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_same_source.1832758310 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 17274853 ps |
| CPU time | 2.77 seconds |
| Started | Sep 01 06:09:12 AM UTC 24 |
| Finished | Sep 01 06:09:16 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832758310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.1832758310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/7.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke.2781814943 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 9809196 ps |
| CPU time | 1.39 seconds |
| Started | Sep 01 06:09:00 AM UTC 24 |
| Finished | Sep 01 06:09:02 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781814943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.2781814943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/7.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_large_delays.1585974523 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 9499640943 ps |
| CPU time | 10.77 seconds |
| Started | Sep 01 06:09:06 AM UTC 24 |
| Finished | Sep 01 06:09:17 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585974523 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.1585974523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/7.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3721726997 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 4454696956 ps |
| CPU time | 13 seconds |
| Started | Sep 01 06:09:07 AM UTC 24 |
| Finished | Sep 01 06:09:21 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721726997 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3721726997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.917941508 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 12097425 ps |
| CPU time | 1.92 seconds |
| Started | Sep 01 06:09:03 AM UTC 24 |
| Finished | Sep 01 06:09:06 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917941508 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.917941508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/7.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all.1084725189 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 177635027 ps |
| CPU time | 24.89 seconds |
| Started | Sep 01 06:09:13 AM UTC 24 |
| Finished | Sep 01 06:09:39 AM UTC 24 |
| Peak memory | 212324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084725189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1084725189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/7.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_error.117538038 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 31618049348 ps |
| CPU time | 67.14 seconds |
| Started | Sep 01 06:09:19 AM UTC 24 |
| Finished | Sep 01 06:10:27 AM UTC 24 |
| Peak memory | 214436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117538038 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.117538038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/7.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.2384614056 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 10759956924 ps |
| CPU time | 171.99 seconds |
| Started | Sep 01 06:09:16 AM UTC 24 |
| Finished | Sep 01 06:12:12 AM UTC 24 |
| Peak memory | 216488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384614056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.2384614056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.4112295718 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 243512501 ps |
| CPU time | 19.85 seconds |
| Started | Sep 01 06:09:19 AM UTC 24 |
| Finished | Sep 01 06:09:40 AM UTC 24 |
| Peak memory | 214252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112295718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.4112295718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_unmapped_addr.3462247736 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 363893735 ps |
| CPU time | 8.08 seconds |
| Started | Sep 01 06:09:12 AM UTC 24 |
| Finished | Sep 01 06:09:21 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462247736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3462247736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/7.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device.2742657083 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 54818046 ps |
| CPU time | 13.84 seconds |
| Started | Sep 01 06:09:23 AM UTC 24 |
| Finished | Sep 01 06:09:38 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742657083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.2742657083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/8.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.3457680569 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 32750813649 ps |
| CPU time | 218.34 seconds |
| Started | Sep 01 06:09:23 AM UTC 24 |
| Finished | Sep 01 06:13:04 AM UTC 24 |
| Peak memory | 214440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457680569 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.3457680569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.3545531102 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 618720524 ps |
| CPU time | 11.97 seconds |
| Started | Sep 01 06:09:25 AM UTC 24 |
| Finished | Sep 01 06:09:38 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545531102 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.3545531102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_error_random.758630567 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 1534145045 ps |
| CPU time | 6.29 seconds |
| Started | Sep 01 06:09:24 AM UTC 24 |
| Finished | Sep 01 06:09:31 AM UTC 24 |
| Peak memory | 212188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758630567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.758630567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/8.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random.3412250801 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 1460367651 ps |
| CPU time | 19.83 seconds |
| Started | Sep 01 06:09:20 AM UTC 24 |
| Finished | Sep 01 06:09:41 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412250801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.3412250801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/8.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_large_delays.4209224902 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 21381381026 ps |
| CPU time | 63.01 seconds |
| Started | Sep 01 06:09:22 AM UTC 24 |
| Finished | Sep 01 06:10:26 AM UTC 24 |
| Peak memory | 212448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209224902 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.4209224902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/8.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_slow_rsp.2061315549 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 32689661930 ps |
| CPU time | 48.45 seconds |
| Started | Sep 01 06:09:22 AM UTC 24 |
| Finished | Sep 01 06:10:12 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061315549 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.2061315549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/8.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_zero_delays.2890819322 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 197497215 ps |
| CPU time | 7.18 seconds |
| Started | Sep 01 06:09:22 AM UTC 24 |
| Finished | Sep 01 06:09:30 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890819322 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.2890819322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/8.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_same_source.3737893445 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 51299377 ps |
| CPU time | 2.24 seconds |
| Started | Sep 01 06:09:23 AM UTC 24 |
| Finished | Sep 01 06:09:26 AM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737893445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.3737893445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/8.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke.84184075 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 88239862 ps |
| CPU time | 2.45 seconds |
| Started | Sep 01 06:09:19 AM UTC 24 |
| Finished | Sep 01 06:09:22 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84184075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.84184075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/8.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_large_delays.2558828414 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 4272042494 ps |
| CPU time | 8.87 seconds |
| Started | Sep 01 06:09:20 AM UTC 24 |
| Finished | Sep 01 06:09:30 AM UTC 24 |
| Peak memory | 212456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558828414 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.2558828414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/8.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.3903437969 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 3813308968 ps |
| CPU time | 11.97 seconds |
| Started | Sep 01 06:09:20 AM UTC 24 |
| Finished | Sep 01 06:09:33 AM UTC 24 |
| Peak memory | 212456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903437969 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3903437969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.2279143477 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 9183513 ps |
| CPU time | 1.72 seconds |
| Started | Sep 01 06:09:20 AM UTC 24 |
| Finished | Sep 01 06:09:23 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279143477 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.2279143477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/8.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all.1881550596 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 265188826 ps |
| CPU time | 26.39 seconds |
| Started | Sep 01 06:09:27 AM UTC 24 |
| Finished | Sep 01 06:09:54 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881550596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1881550596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/8.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_error.3468347719 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 558133657 ps |
| CPU time | 9.22 seconds |
| Started | Sep 01 06:09:28 AM UTC 24 |
| Finished | Sep 01 06:09:38 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468347719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.3468347719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/8.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.27556049 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 478619885 ps |
| CPU time | 105.21 seconds |
| Started | Sep 01 06:09:28 AM UTC 24 |
| Finished | Sep 01 06:11:16 AM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27556049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.27556049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.3942818660 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 606822304 ps |
| CPU time | 34.04 seconds |
| Started | Sep 01 06:09:31 AM UTC 24 |
| Finished | Sep 01 06:10:07 AM UTC 24 |
| Peak memory | 214252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942818660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.3942818660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_unmapped_addr.4153104709 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 350813855 ps |
| CPU time | 6.94 seconds |
| Started | Sep 01 06:09:24 AM UTC 24 |
| Finished | Sep 01 06:09:32 AM UTC 24 |
| Peak memory | 212324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153104709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.4153104709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/8.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device.76783737 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 636250971 ps |
| CPU time | 15.02 seconds |
| Started | Sep 01 06:09:39 AM UTC 24 |
| Finished | Sep 01 06:09:55 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76783737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.76783737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/9.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.2136804806 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 5338801789 ps |
| CPU time | 46.62 seconds |
| Started | Sep 01 06:09:40 AM UTC 24 |
| Finished | Sep 01 06:10:28 AM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136804806 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.2136804806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.2454617620 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 221398256 ps |
| CPU time | 2.54 seconds |
| Started | Sep 01 06:09:43 AM UTC 24 |
| Finished | Sep 01 06:09:46 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454617620 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.2454617620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_error_random.3686815397 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 148647185 ps |
| CPU time | 6.58 seconds |
| Started | Sep 01 06:09:40 AM UTC 24 |
| Finished | Sep 01 06:09:48 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686815397 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.3686815397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/9.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random.552991977 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 346054214 ps |
| CPU time | 9.09 seconds |
| Started | Sep 01 06:09:35 AM UTC 24 |
| Finished | Sep 01 06:09:45 AM UTC 24 |
| Peak memory | 212324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552991977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.552991977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/9.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_large_delays.3142131124 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 61201607096 ps |
| CPU time | 214.39 seconds |
| Started | Sep 01 06:09:39 AM UTC 24 |
| Finished | Sep 01 06:13:17 AM UTC 24 |
| Peak memory | 212184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142131124 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.3142131124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/9.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_slow_rsp.3884035003 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 52465981518 ps |
| CPU time | 221.07 seconds |
| Started | Sep 01 06:09:39 AM UTC 24 |
| Finished | Sep 01 06:13:23 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884035003 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.3884035003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/9.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_zero_delays.2150924727 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 54808767 ps |
| CPU time | 5.73 seconds |
| Started | Sep 01 06:09:36 AM UTC 24 |
| Finished | Sep 01 06:09:43 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150924727 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.2150924727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/9.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_same_source.3482897495 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 78050143 ps |
| CPU time | 7.3 seconds |
| Started | Sep 01 06:09:40 AM UTC 24 |
| Finished | Sep 01 06:09:49 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482897495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3482897495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/9.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke.3174417600 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 12751962 ps |
| CPU time | 1.68 seconds |
| Started | Sep 01 06:09:31 AM UTC 24 |
| Finished | Sep 01 06:09:34 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174417600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3174417600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/9.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_large_delays.473002047 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 3175442950 ps |
| CPU time | 14.46 seconds |
| Started | Sep 01 06:09:33 AM UTC 24 |
| Finished | Sep 01 06:09:49 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473002047 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.473002047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/9.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.2078216800 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 989717369 ps |
| CPU time | 14.83 seconds |
| Started | Sep 01 06:09:35 AM UTC 24 |
| Finished | Sep 01 06:09:51 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078216800 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2078216800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.2179485906 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 7893534 ps |
| CPU time | 1.62 seconds |
| Started | Sep 01 06:09:32 AM UTC 24 |
| Finished | Sep 01 06:09:35 AM UTC 24 |
| Peak memory | 211132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179485906 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.2179485906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/9.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_error.1871045157 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 1558597939 ps |
| CPU time | 48.08 seconds |
| Started | Sep 01 06:09:45 AM UTC 24 |
| Finished | Sep 01 06:10:34 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871045157 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.1871045157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/9.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.2247413159 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 815718985 ps |
| CPU time | 135.99 seconds |
| Started | Sep 01 06:09:45 AM UTC 24 |
| Finished | Sep 01 06:12:03 AM UTC 24 |
| Peak memory | 214316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247413159 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.2247413159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_unmapped_addr.4146331685 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 27850099 ps |
| CPU time | 3.55 seconds |
| Started | Sep 01 06:09:42 AM UTC 24 |
| Finished | Sep 01 06:09:46 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146331685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.4146331685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/9.xbar_unmapped_addr/latest |
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