Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	424	1			T340	3		T341	2		T241	1
all_values[1]	428	1			T17	1		T39	1		T81	1
all_values[2]	411	1			T256	1		T230	2		T342	1
all_values[3]	441	1			T17	1		T14	1		T81	2
all_values[4]	416	1			T256	1		T342	1		T341	1
all_values[5]	408	1			T14	1		T256	2		T230	1
all_values[6]	431	1			T44	1		T274	1		T230	1
all_values[7]	442	1			T62	1		T340	1		T341	1
all_values[8]	431	1			T197	1		T213	1		T341	1
all_values[9]	391	1			T39	1		T197	1		T274	1
all_values[10]	414	1			T274	2		T256	2		T230	1
all_values[11]	423	1			T14	1		T81	2		T256	1
all_values[12]	399	1			T17	2		T230	1		T241	1
all_values[13]	425	1			T39	1		T274	1		T341	1
all_values[14]	413	1			T17	2		T340	2		T242	2
all_values[15]	429	1			T340	1		T341	1		T242	3
all_values[16]	441	1			T256	1		T230	2		T341	1
all_values[17]	374	1			T17	1		T62	1		T244	1
all_values[18]	437	1			T44	2		T81	2		T67	1
all_values[19]	457	1			T17	2		T14	1		T40	1
all_values[20]	401	1			T44	1		T230	1		T213	1
all_values[21]	455	1			T292	1		T242	4		T244	1
all_values[22]	437	1			T17	2		T197	2		T274	1
all_values[23]	451	1			T213	1		T62	3		T340	2
all_values[24]	453	1			T44	1		T81	1		T274	1
all_values[25]	435	1			T17	1		T39	1		T44	1
all_values[26]	410	1			T274	3		T213	1		T342	1