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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.24 100.00 95.42 100.00 100.00 100.00 100.00


Total test records in report: 900
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T771 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random.951167005 Sep 03 11:36:09 PM UTC 24 Sep 03 11:36:15 PM UTC 24 300125206 ps
T772 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.2508187901 Sep 03 11:36:12 PM UTC 24 Sep 03 11:36:16 PM UTC 24 93959587 ps
T773 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.441833326 Sep 03 11:36:14 PM UTC 24 Sep 03 11:36:17 PM UTC 24 14107446 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.3028527418 Sep 03 11:34:05 PM UTC 24 Sep 03 11:36:17 PM UTC 24 25168394023 ps
T774 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.1048519917 Sep 03 11:36:09 PM UTC 24 Sep 03 11:36:17 PM UTC 24 42636544 ps
T775 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.3793672962 Sep 03 11:36:09 PM UTC 24 Sep 03 11:36:18 PM UTC 24 1485916610 ps
T776 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.723607652 Sep 03 11:36:12 PM UTC 24 Sep 03 11:36:19 PM UTC 24 88115434 ps
T777 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.2916035590 Sep 03 11:36:16 PM UTC 24 Sep 03 11:36:19 PM UTC 24 9760672 ps
T778 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.2325586139 Sep 03 11:35:14 PM UTC 24 Sep 03 11:36:20 PM UTC 24 3843375679 ps
T779 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1607939397 Sep 03 11:36:06 PM UTC 24 Sep 03 11:36:21 PM UTC 24 2553748301 ps
T780 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.3704409302 Sep 03 11:36:06 PM UTC 24 Sep 03 11:36:22 PM UTC 24 1252718336 ps
T781 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.868602589 Sep 03 11:36:02 PM UTC 24 Sep 03 11:36:24 PM UTC 24 1022036749 ps
T782 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.3439795597 Sep 03 11:36:16 PM UTC 24 Sep 03 11:36:25 PM UTC 24 692805338 ps
T783 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.665837452 Sep 03 11:36:20 PM UTC 24 Sep 03 11:36:25 PM UTC 24 25813966 ps
T784 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.3364493379 Sep 03 11:36:12 PM UTC 24 Sep 03 11:36:25 PM UTC 24 62661098 ps
T785 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.2691482672 Sep 03 11:36:12 PM UTC 24 Sep 03 11:36:25 PM UTC 24 1430991840 ps
T786 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.579285672 Sep 03 11:36:16 PM UTC 24 Sep 03 11:36:26 PM UTC 24 2311494411 ps
T787 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.4197863879 Sep 03 11:36:22 PM UTC 24 Sep 03 11:36:27 PM UTC 24 34233209 ps
T788 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.2109255210 Sep 03 11:36:18 PM UTC 24 Sep 03 11:36:27 PM UTC 24 319786473 ps
T789 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.2667190879 Sep 03 11:35:54 PM UTC 24 Sep 03 11:36:28 PM UTC 24 1940208754 ps
T790 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random.2897245183 Sep 03 11:36:18 PM UTC 24 Sep 03 11:36:28 PM UTC 24 78412727 ps
T791 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.2380773366 Sep 03 11:35:58 PM UTC 24 Sep 03 11:36:29 PM UTC 24 7178483995 ps
T792 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.3965993150 Sep 03 11:36:28 PM UTC 24 Sep 03 11:36:30 PM UTC 24 8984399 ps
T793 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.2076010018 Sep 03 11:36:28 PM UTC 24 Sep 03 11:36:31 PM UTC 24 41397231 ps
T794 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.4170039894 Sep 03 11:35:54 PM UTC 24 Sep 03 11:36:32 PM UTC 24 3414879420 ps
T795 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random.1732273445 Sep 03 11:36:29 PM UTC 24 Sep 03 11:36:43 PM UTC 24 1471689653 ps
T796 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_slow_rsp.89924498 Sep 03 11:34:17 PM UTC 24 Sep 03 11:36:33 PM UTC 24 31361499120 ps
T797 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.1030835579 Sep 03 11:36:22 PM UTC 24 Sep 03 11:36:34 PM UTC 24 1256902712 ps
T798 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.2627876722 Sep 03 11:35:16 PM UTC 24 Sep 03 11:36:34 PM UTC 24 739559495 ps
T799 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2501109196 Sep 03 11:33:58 PM UTC 24 Sep 03 11:36:35 PM UTC 24 829161427 ps
T800 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.2750068783 Sep 03 11:36:27 PM UTC 24 Sep 03 11:36:35 PM UTC 24 273815549 ps
T801 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.213959613 Sep 03 11:36:30 PM UTC 24 Sep 03 11:36:36 PM UTC 24 77122855 ps
T802 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.712288878 Sep 03 11:36:19 PM UTC 24 Sep 03 11:36:36 PM UTC 24 3291984426 ps
T803 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1446884052 Sep 03 11:36:28 PM UTC 24 Sep 03 11:36:37 PM UTC 24 3857864372 ps
T804 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.318470549 Sep 03 11:36:34 PM UTC 24 Sep 03 11:36:39 PM UTC 24 71601950 ps
T805 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.3077138191 Sep 03 11:36:28 PM UTC 24 Sep 03 11:36:39 PM UTC 24 2810593402 ps
T806 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.1876455311 Sep 03 11:36:38 PM UTC 24 Sep 03 11:36:42 PM UTC 24 76372893 ps
T807 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1538821802 Sep 03 11:36:41 PM UTC 24 Sep 03 11:36:44 PM UTC 24 8984796 ps
T808 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.729955029 Sep 03 11:36:36 PM UTC 24 Sep 03 11:36:44 PM UTC 24 250875787 ps
T809 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.2006232129 Sep 03 11:36:20 PM UTC 24 Sep 03 11:36:45 PM UTC 24 1292705637 ps
T810 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.2870689129 Sep 03 11:36:23 PM UTC 24 Sep 03 11:36:47 PM UTC 24 695401690 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.1959005339 Sep 03 11:34:25 PM UTC 24 Sep 03 11:36:47 PM UTC 24 19027152525 ps
T811 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.505523857 Sep 03 11:36:12 PM UTC 24 Sep 03 11:36:47 PM UTC 24 228136838 ps
T812 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.329887909 Sep 03 11:35:54 PM UTC 24 Sep 03 11:36:49 PM UTC 24 15409866329 ps
T813 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.3408011609 Sep 03 11:36:45 PM UTC 24 Sep 03 11:36:49 PM UTC 24 15856078 ps
T814 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.2701597641 Sep 03 11:36:31 PM UTC 24 Sep 03 11:36:50 PM UTC 24 7149618305 ps
T815 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.990413944 Sep 03 11:36:36 PM UTC 24 Sep 03 11:36:50 PM UTC 24 2001571378 ps
T816 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.3904242745 Sep 03 11:35:33 PM UTC 24 Sep 03 11:36:52 PM UTC 24 15896076219 ps
T817 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.4278963604 Sep 03 11:36:41 PM UTC 24 Sep 03 11:36:52 PM UTC 24 2420683489 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.1155574481 Sep 03 11:30:32 PM UTC 24 Sep 03 11:36:53 PM UTC 24 150737960156 ps
T818 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.1309277521 Sep 03 11:36:33 PM UTC 24 Sep 03 11:36:55 PM UTC 24 2681048361 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3234945469 Sep 03 11:34:47 PM UTC 24 Sep 03 11:37:34 PM UTC 24 61992409025 ps
T819 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.3882576267 Sep 03 11:36:50 PM UTC 24 Sep 03 11:36:55 PM UTC 24 38386718 ps
T820 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.1099866397 Sep 03 11:36:50 PM UTC 24 Sep 03 11:36:56 PM UTC 24 94841163 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.4287881455 Sep 03 11:36:48 PM UTC 24 Sep 03 11:36:56 PM UTC 24 985541446 ps
T821 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random.3842659746 Sep 03 11:36:45 PM UTC 24 Sep 03 11:36:57 PM UTC 24 401724546 ps
T822 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3212913665 Sep 03 11:36:42 PM UTC 24 Sep 03 11:36:58 PM UTC 24 6430670857 ps
T823 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2376144738 Sep 03 11:36:52 PM UTC 24 Sep 03 11:36:58 PM UTC 24 257116014 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.4120951580 Sep 03 11:34:27 PM UTC 24 Sep 03 11:36:58 PM UTC 24 110478484226 ps
T824 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.1268457021 Sep 03 11:36:55 PM UTC 24 Sep 03 11:36:58 PM UTC 24 46581886 ps
T825 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.553828653 Sep 03 11:36:12 PM UTC 24 Sep 03 11:37:00 PM UTC 24 3075742352 ps
T826 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2715637057 Sep 03 11:36:58 PM UTC 24 Sep 03 11:37:00 PM UTC 24 39001648 ps
T827 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.2954530914 Sep 03 11:36:54 PM UTC 24 Sep 03 11:37:01 PM UTC 24 236786133 ps
T828 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.1049457890 Sep 03 11:36:54 PM UTC 24 Sep 03 11:37:02 PM UTC 24 1842560028 ps
T829 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.597516719 Sep 03 11:37:00 PM UTC 24 Sep 03 11:37:03 PM UTC 24 9502534 ps
T830 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.576357898 Sep 03 11:36:49 PM UTC 24 Sep 03 11:37:04 PM UTC 24 1495248682 ps
T831 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.2647777091 Sep 03 11:34:46 PM UTC 24 Sep 03 11:37:05 PM UTC 24 47038161628 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.435688486 Sep 03 11:35:58 PM UTC 24 Sep 03 11:37:07 PM UTC 24 57231650356 ps
T832 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.1777566214 Sep 03 11:37:06 PM UTC 24 Sep 03 11:37:08 PM UTC 24 6008613 ps
T833 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.4125269546 Sep 03 11:36:52 PM UTC 24 Sep 03 11:37:08 PM UTC 24 4687270368 ps
T834 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1487796503 Sep 03 11:36:38 PM UTC 24 Sep 03 11:37:08 PM UTC 24 314073416 ps
T835 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random.3457176525 Sep 03 11:37:00 PM UTC 24 Sep 03 11:37:09 PM UTC 24 60741484 ps
T836 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.442682836 Sep 03 11:36:58 PM UTC 24 Sep 03 11:37:09 PM UTC 24 1452341079 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.3011680237 Sep 03 11:37:01 PM UTC 24 Sep 03 11:37:10 PM UTC 24 669066128 ps
T837 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.3580438336 Sep 03 11:37:03 PM UTC 24 Sep 03 11:37:11 PM UTC 24 676906983 ps
T838 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.1511676583 Sep 03 11:34:15 PM UTC 24 Sep 03 11:37:13 PM UTC 24 145096382166 ps
T839 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.4041649328 Sep 03 11:37:07 PM UTC 24 Sep 03 11:37:14 PM UTC 24 71199957 ps
T840 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.1852863863 Sep 03 11:37:12 PM UTC 24 Sep 03 11:37:14 PM UTC 24 11147608 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.1252565199 Sep 03 11:32:08 PM UTC 24 Sep 03 11:37:14 PM UTC 24 53022156852 ps
T841 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.2523675114 Sep 03 11:37:04 PM UTC 24 Sep 03 11:37:14 PM UTC 24 762926261 ps
T842 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.2077023701 Sep 03 11:37:12 PM UTC 24 Sep 03 11:37:14 PM UTC 24 10363272 ps
T843 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.2989438734 Sep 03 11:36:38 PM UTC 24 Sep 03 11:37:16 PM UTC 24 323446754 ps
T844 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.3805284109 Sep 03 11:37:12 PM UTC 24 Sep 03 11:37:17 PM UTC 24 113227621 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.450164852 Sep 03 11:35:04 PM UTC 24 Sep 03 11:37:17 PM UTC 24 1059666057 ps
T845 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.769136884 Sep 03 11:37:03 PM UTC 24 Sep 03 11:37:18 PM UTC 24 1102476574 ps
T846 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1767817832 Sep 03 11:36:05 PM UTC 24 Sep 03 11:37:18 PM UTC 24 16674585787 ps
T847 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.294367050 Sep 03 11:36:28 PM UTC 24 Sep 03 11:37:18 PM UTC 24 722705045 ps
T848 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.237671678 Sep 03 11:37:04 PM UTC 24 Sep 03 11:37:19 PM UTC 24 795681732 ps
T849 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.2273976783 Sep 03 11:36:58 PM UTC 24 Sep 03 11:37:19 PM UTC 24 10875314503 ps
T850 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2307018534 Sep 03 11:36:54 PM UTC 24 Sep 03 11:37:19 PM UTC 24 195423373 ps
T851 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3088531603 Sep 03 11:36:31 PM UTC 24 Sep 03 11:37:21 PM UTC 24 6538015158 ps
T852 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.132476197 Sep 03 11:37:16 PM UTC 24 Sep 03 11:37:21 PM UTC 24 49973179 ps
T853 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.4196785917 Sep 03 11:34:54 PM UTC 24 Sep 03 11:37:21 PM UTC 24 3662853933 ps
T854 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.2942954986 Sep 03 11:36:05 PM UTC 24 Sep 03 11:37:21 PM UTC 24 5338925448 ps
T855 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1111929542 Sep 03 11:37:12 PM UTC 24 Sep 03 11:37:22 PM UTC 24 3085386281 ps
T856 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.3633818815 Sep 03 11:36:38 PM UTC 24 Sep 03 11:37:22 PM UTC 24 293365094 ps
T857 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1465181077 Sep 03 11:37:18 PM UTC 24 Sep 03 11:37:23 PM UTC 24 58792446 ps
T858 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.3535436372 Sep 03 11:37:18 PM UTC 24 Sep 03 11:37:24 PM UTC 24 197309811 ps
T859 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.353191362 Sep 03 11:37:12 PM UTC 24 Sep 03 11:37:25 PM UTC 24 5235250524 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.4205046200 Sep 03 11:32:59 PM UTC 24 Sep 03 11:37:26 PM UTC 24 78069609506 ps
T860 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.4101269180 Sep 03 11:37:16 PM UTC 24 Sep 03 11:37:26 PM UTC 24 587443726 ps
T861 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random.3001886884 Sep 03 11:37:12 PM UTC 24 Sep 03 11:37:26 PM UTC 24 3659527436 ps
T862 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.1657134681 Sep 03 11:35:20 PM UTC 24 Sep 03 11:37:27 PM UTC 24 66972255965 ps
T863 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.374086998 Sep 03 11:37:16 PM UTC 24 Sep 03 11:37:28 PM UTC 24 1153895356 ps
T864 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.2417160650 Sep 03 11:34:58 PM UTC 24 Sep 03 11:37:28 PM UTC 24 21562266071 ps
T865 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.2308821373 Sep 03 11:35:10 PM UTC 24 Sep 03 11:37:29 PM UTC 24 25156514722 ps
T866 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1042551398 Sep 03 11:37:09 PM UTC 24 Sep 03 11:37:29 PM UTC 24 3815391189 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.1221534271 Sep 03 11:31:53 PM UTC 24 Sep 03 11:37:30 PM UTC 24 189420612279 ps
T867 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.3613292782 Sep 03 11:36:20 PM UTC 24 Sep 03 11:37:31 PM UTC 24 57138193217 ps
T868 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1070700922 Sep 03 11:37:21 PM UTC 24 Sep 03 11:37:31 PM UTC 24 56892949 ps
T869 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.1944121447 Sep 03 11:35:54 PM UTC 24 Sep 03 11:37:31 PM UTC 24 975036091 ps
T870 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.1411820023 Sep 03 11:37:22 PM UTC 24 Sep 03 11:37:33 PM UTC 24 47638842 ps
T871 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1042767577 Sep 03 11:35:33 PM UTC 24 Sep 03 11:37:36 PM UTC 24 23185284813 ps
T872 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.765930851 Sep 03 11:37:22 PM UTC 24 Sep 03 11:37:37 PM UTC 24 147073790 ps
T873 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.2261832152 Sep 03 11:37:21 PM UTC 24 Sep 03 11:37:38 PM UTC 24 1110301580 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.1074633665 Sep 03 11:31:16 PM UTC 24 Sep 03 11:37:43 PM UTC 24 97157596661 ps
T874 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.3297924111 Sep 03 11:36:30 PM UTC 24 Sep 03 11:37:43 PM UTC 24 45322092846 ps
T875 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.2331687619 Sep 03 11:37:00 PM UTC 24 Sep 03 11:37:44 PM UTC 24 19281566042 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.3464251795 Sep 03 11:35:20 PM UTC 24 Sep 03 11:37:48 PM UTC 24 67328490234 ps
T876 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.3276236417 Sep 03 11:35:46 PM UTC 24 Sep 03 11:37:49 PM UTC 24 21997803874 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.1974532056 Sep 03 11:34:18 PM UTC 24 Sep 03 11:37:50 PM UTC 24 52135540069 ps
T877 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.463832507 Sep 03 11:36:36 PM UTC 24 Sep 03 11:37:57 PM UTC 24 20002283622 ps
T878 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.3605864990 Sep 03 11:36:19 PM UTC 24 Sep 03 11:37:57 PM UTC 24 20835554449 ps
T879 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.4201368986 Sep 03 11:35:10 PM UTC 24 Sep 03 11:38:04 PM UTC 24 36721897921 ps
T880 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1842562183 Sep 03 11:36:33 PM UTC 24 Sep 03 11:38:09 PM UTC 24 14072665397 ps
T881 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.280020764 Sep 03 11:35:58 PM UTC 24 Sep 03 11:38:11 PM UTC 24 34533283818 ps
T882 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.2328443642 Sep 03 11:34:35 PM UTC 24 Sep 03 11:38:18 PM UTC 24 62498716786 ps
T883 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.819061029 Sep 03 11:35:47 PM UTC 24 Sep 03 11:38:20 PM UTC 24 60684136041 ps
T884 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.4020620479 Sep 03 11:36:09 PM UTC 24 Sep 03 11:38:20 PM UTC 24 21890589228 ps
T885 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1180804489 Sep 03 11:36:27 PM UTC 24 Sep 03 11:38:22 PM UTC 24 3257268329 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.4108759161 Sep 03 11:32:32 PM UTC 24 Sep 03 11:38:27 PM UTC 24 57110677890 ps
T886 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.3883697180 Sep 03 11:35:45 PM UTC 24 Sep 03 11:38:34 PM UTC 24 87114795328 ps
T887 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2292063306 Sep 03 11:36:12 PM UTC 24 Sep 03 11:38:36 PM UTC 24 7935500763 ps
T888 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.4158097427 Sep 03 11:36:47 PM UTC 24 Sep 03 11:38:41 PM UTC 24 56944567297 ps
T889 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3679420023 Sep 03 11:37:00 PM UTC 24 Sep 03 11:38:46 PM UTC 24 35979008597 ps
T890 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.1495575665 Sep 03 11:37:16 PM UTC 24 Sep 03 11:38:47 PM UTC 24 14124643646 ps
T891 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.254859262 Sep 03 11:35:01 PM UTC 24 Sep 03 11:38:58 PM UTC 24 36396136986 ps
T892 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.2052426036 Sep 03 11:36:19 PM UTC 24 Sep 03 11:39:07 PM UTC 24 41066811460 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.3871566382 Sep 03 11:36:45 PM UTC 24 Sep 03 11:39:11 PM UTC 24 44571195053 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.257078525 Sep 03 11:31:40 PM UTC 24 Sep 03 11:39:13 PM UTC 24 62601159192 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1552850032 Sep 03 11:35:33 PM UTC 24 Sep 03 11:39:25 PM UTC 24 30537656325 ps
T893 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.335690087 Sep 03 11:37:09 PM UTC 24 Sep 03 11:39:30 PM UTC 24 2035344410 ps
T894 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.1021382807 Sep 03 11:37:14 PM UTC 24 Sep 03 11:39:41 PM UTC 24 42617287696 ps
T895 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.2217194769 Sep 03 11:33:55 PM UTC 24 Sep 03 11:39:48 PM UTC 24 40227987851 ps
T896 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.440586807 Sep 03 11:37:16 PM UTC 24 Sep 03 11:39:57 PM UTC 24 28282753281 ps
T897 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.2973377816 Sep 03 11:35:22 PM UTC 24 Sep 03 11:40:05 PM UTC 24 233529422360 ps
T898 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.2504352758 Sep 03 11:36:49 PM UTC 24 Sep 03 11:40:05 PM UTC 24 32390939012 ps
T899 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.448535755 Sep 03 11:37:02 PM UTC 24 Sep 03 11:40:18 PM UTC 24 26726442613 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.1595238570 Sep 03 11:34:35 PM UTC 24 Sep 03 11:41:06 PM UTC 24 295491581762 ps
T900 /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3358812648 Sep 03 11:36:09 PM UTC 24 Sep 03 11:41:18 PM UTC 24 148771146306 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random.2582076455
Short name T4
Test name
Test status
Simulation time 720280698 ps
CPU time 4.82 seconds
Started Sep 03 11:27:56 PM UTC 24
Finished Sep 03 11:28:02 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582076455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.2582076455
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/0.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.812581580
Short name T296
Test name
Test status
Simulation time 163447591143 ps
CPU time 332.27 seconds
Started Sep 03 11:28:18 PM UTC 24
Finished Sep 03 11:33:55 PM UTC 24
Peak memory 217940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812581580 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.812581580
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/2.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.1155574481
Short name T313
Test name
Test status
Simulation time 150737960156 ps
CPU time 376.4 seconds
Started Sep 03 11:30:32 PM UTC 24
Finished Sep 03 11:36:53 PM UTC 24
Peak memory 217844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155574481 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.1155574481
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/16.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.482350614
Short name T103
Test name
Test status
Simulation time 46715854831 ps
CPU time 219.38 seconds
Started Sep 03 11:30:53 PM UTC 24
Finished Sep 03 11:34:35 PM UTC 24
Peak memory 214440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482350614 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.482350614
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/18.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.163078543
Short name T14
Test name
Test status
Simulation time 36407820 ps
CPU time 5.91 seconds
Started Sep 03 11:28:05 PM UTC 24
Finished Sep 03 11:28:12 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163078543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.163078543
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/0.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.861554135
Short name T286
Test name
Test status
Simulation time 11939290800 ps
CPU time 91.73 seconds
Started Sep 03 11:28:55 PM UTC 24
Finished Sep 03 11:30:28 PM UTC 24
Peak memory 214368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861554135 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.861554135
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/7.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.2205810644
Short name T225
Test name
Test status
Simulation time 15244812088 ps
CPU time 118.21 seconds
Started Sep 03 11:30:41 PM UTC 24
Finished Sep 03 11:32:42 PM UTC 24
Peak memory 214436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205810644 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.2205810644
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/17.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.1749637401
Short name T242
Test name
Test status
Simulation time 1176761129 ps
CPU time 51.8 seconds
Started Sep 03 11:28:19 PM UTC 24
Finished Sep 03 11:29:13 PM UTC 24
Peak memory 214188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749637401 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.1749637401
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/2.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.966961213
Short name T263
Test name
Test status
Simulation time 26550390050 ps
CPU time 160.63 seconds
Started Sep 03 11:29:03 PM UTC 24
Finished Sep 03 11:31:46 PM UTC 24
Peak memory 214432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966961213 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.966961213
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/8.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random.3921995387
Short name T38
Test name
Test status
Simulation time 810926750 ps
CPU time 7.27 seconds
Started Sep 03 11:28:16 PM UTC 24
Finished Sep 03 11:28:24 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921995387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.3921995387
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/2.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_large_delays.4022234021
Short name T21
Test name
Test status
Simulation time 22535208741 ps
CPU time 17.05 seconds
Started Sep 03 11:27:54 PM UTC 24
Finished Sep 03 11:28:12 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022234021 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.4022234021
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/0.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.1221534271
Short name T283
Test name
Test status
Simulation time 189420612279 ps
CPU time 332.27 seconds
Started Sep 03 11:31:53 PM UTC 24
Finished Sep 03 11:37:30 PM UTC 24
Peak memory 214240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221534271 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.1221534271
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/23.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device.1053190072
Short name T75
Test name
Test status
Simulation time 1082465341 ps
CPU time 22.23 seconds
Started Sep 03 11:29:34 PM UTC 24
Finished Sep 03 11:29:57 PM UTC 24
Peak memory 212264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053190072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.1053190072
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/11.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.3694142258
Short name T305
Test name
Test status
Simulation time 36408663909 ps
CPU time 163.21 seconds
Started Sep 03 11:27:59 PM UTC 24
Finished Sep 03 11:30:45 PM UTC 24
Peak memory 214248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694142258 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.3694142258
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/0.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.4030817575
Short name T15
Test name
Test status
Simulation time 1243284784 ps
CPU time 11.37 seconds
Started Sep 03 11:28:02 PM UTC 24
Finished Sep 03 11:28:15 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030817575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.4030817575
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/0.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.1252565199
Short name T105
Test name
Test status
Simulation time 53022156852 ps
CPU time 302.29 seconds
Started Sep 03 11:32:08 PM UTC 24
Finished Sep 03 11:37:14 PM UTC 24
Peak memory 216288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252565199 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.1252565199
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/24.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.450164852
Short name T11
Test name
Test status
Simulation time 1059666057 ps
CPU time 131.04 seconds
Started Sep 03 11:35:04 PM UTC 24
Finished Sep 03 11:37:17 PM UTC 24
Peak memory 216236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450164852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.450164852
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/38.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all.2627914215
Short name T295
Test name
Test status
Simulation time 2730830596 ps
CPU time 28.98 seconds
Started Sep 03 11:30:15 PM UTC 24
Finished Sep 03 11:30:46 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627914215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2627914215
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/14.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random.1241706554
Short name T22
Test name
Test status
Simulation time 202056870 ps
CPU time 7.47 seconds
Started Sep 03 11:28:08 PM UTC 24
Finished Sep 03 11:28:16 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241706554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.1241706554
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/1.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.2922954341
Short name T99
Test name
Test status
Simulation time 12247237565 ps
CPU time 149.11 seconds
Started Sep 03 11:30:16 PM UTC 24
Finished Sep 03 11:32:47 PM UTC 24
Peak memory 216292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922954341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.2922954341
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/14.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.2943624691
Short name T10
Test name
Test status
Simulation time 5545495919 ps
CPU time 149.92 seconds
Started Sep 03 11:32:35 PM UTC 24
Finished Sep 03 11:35:08 PM UTC 24
Peak memory 216488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943624691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.2943624691
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/26.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_same_source.1322650373
Short name T61
Test name
Test status
Simulation time 1932791757 ps
CPU time 8.55 seconds
Started Sep 03 11:28:40 PM UTC 24
Finished Sep 03 11:28:49 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322650373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.1322650373
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/5.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_error.2090435621
Short name T254
Test name
Test status
Simulation time 10389155385 ps
CPU time 81.33 seconds
Started Sep 03 11:28:19 PM UTC 24
Finished Sep 03 11:29:43 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090435621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.2090435621
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/2.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.4120951580
Short name T289
Test name
Test status
Simulation time 110478484226 ps
CPU time 148.66 seconds
Started Sep 03 11:34:27 PM UTC 24
Finished Sep 03 11:36:58 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120951580 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.4120951580
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/35.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_unmapped_addr.2884385834
Short name T77
Test name
Test status
Simulation time 1586738453 ps
CPU time 15.13 seconds
Started Sep 03 11:30:00 PM UTC 24
Finished Sep 03 11:30:17 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884385834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.2884385834
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/13.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.3991591904
Short name T331
Test name
Test status
Simulation time 2663074474 ps
CPU time 96.2 seconds
Started Sep 03 11:28:15 PM UTC 24
Finished Sep 03 11:29:54 PM UTC 24
Peak memory 216492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991591904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.3991591904
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/1.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random.3709092557
Short name T48
Test name
Test status
Simulation time 855047374 ps
CPU time 10.71 seconds
Started Sep 03 11:28:22 PM UTC 24
Finished Sep 03 11:28:35 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709092557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.3709092557
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/3.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.1147084413
Short name T631
Test name
Test status
Simulation time 1893354016 ps
CPU time 106.55 seconds
Started Sep 03 11:32:48 PM UTC 24
Finished Sep 03 11:34:37 PM UTC 24
Peak memory 216360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147084413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.1147084413
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/27.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.741849944
Short name T653
Test name
Test status
Simulation time 559702288 ps
CPU time 62.65 seconds
Started Sep 03 11:33:49 PM UTC 24
Finished Sep 03 11:34:53 PM UTC 24
Peak memory 216232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741849944 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.741849944
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/31.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.3295841549
Short name T536
Test name
Test status
Simulation time 11099491261 ps
CPU time 137.14 seconds
Started Sep 03 11:31:10 PM UTC 24
Finished Sep 03 11:33:30 PM UTC 24
Peak memory 216492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295841549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.3295841549
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/19.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_same_source.799223040
Short name T16
Test name
Test status
Simulation time 25678390 ps
CPU time 2.42 seconds
Started Sep 03 11:27:59 PM UTC 24
Finished Sep 03 11:28:03 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799223040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.799223040
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/0.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.2755402123
Short name T302
Test name
Test status
Simulation time 2211699055 ps
CPU time 69.03 seconds
Started Sep 03 11:28:34 PM UTC 24
Finished Sep 03 11:29:45 PM UTC 24
Peak memory 216492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755402123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.2755402123
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/4.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.3757302963
Short name T148
Test name
Test status
Simulation time 41884613927 ps
CPU time 149.2 seconds
Started Sep 03 11:28:37 PM UTC 24
Finished Sep 03 11:31:09 PM UTC 24
Peak memory 214248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757302963 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.3757302963
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/5.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random.914385243
Short name T84
Test name
Test status
Simulation time 454639426 ps
CPU time 4.05 seconds
Started Sep 03 11:30:20 PM UTC 24
Finished Sep 03 11:30:25 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914385243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.914385243
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/15.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.456989475
Short name T116
Test name
Test status
Simulation time 25665770012 ps
CPU time 140.94 seconds
Started Sep 03 11:30:22 PM UTC 24
Finished Sep 03 11:32:45 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456989475 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.456989475
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/15.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all.2757057139
Short name T97
Test name
Test status
Simulation time 5298074283 ps
CPU time 75.98 seconds
Started Sep 03 11:31:10 PM UTC 24
Finished Sep 03 11:32:28 PM UTC 24
Peak memory 214440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757057139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2757057139
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/19.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device.343501704
Short name T17
Test name
Test status
Simulation time 46221090 ps
CPU time 6.87 seconds
Started Sep 03 11:27:59 PM UTC 24
Finished Sep 03 11:28:07 PM UTC 24
Peak memory 212452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343501704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.343501704
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/0.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_error_random.1675224219
Short name T6
Test name
Test status
Simulation time 29016421 ps
CPU time 2.84 seconds
Started Sep 03 11:28:01 PM UTC 24
Finished Sep 03 11:28:06 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675224219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1675224219
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/0.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_large_delays.357528664
Short name T423
Test name
Test status
Simulation time 58267238451 ps
CPU time 169.12 seconds
Started Sep 03 11:27:59 PM UTC 24
Finished Sep 03 11:30:51 PM UTC 24
Peak memory 215900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357528664 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.357528664
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/0.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_slow_rsp.1869963739
Short name T113
Test name
Test status
Simulation time 108841744208 ps
CPU time 239.5 seconds
Started Sep 03 11:27:59 PM UTC 24
Finished Sep 03 11:32:02 PM UTC 24
Peak memory 216092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869963739 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1869963739
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/0.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_zero_delays.1230128455
Short name T3
Test name
Test status
Simulation time 16663992 ps
CPU time 2.34 seconds
Started Sep 03 11:27:56 PM UTC 24
Finished Sep 03 11:28:00 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230128455 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.1230128455
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/0.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke.1012376221
Short name T1
Test name
Test status
Simulation time 12614467 ps
CPU time 1.27 seconds
Started Sep 03 11:27:52 PM UTC 24
Finished Sep 03 11:27:54 PM UTC 24
Peak memory 211676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012376221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.1012376221
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/0.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.240490775
Short name T13
Test name
Test status
Simulation time 3357747194 ps
CPU time 10.89 seconds
Started Sep 03 11:27:56 PM UTC 24
Finished Sep 03 11:28:08 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240490775 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.240490775
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/0.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.1411153752
Short name T2
Test name
Test status
Simulation time 9487138 ps
CPU time 1.54 seconds
Started Sep 03 11:27:54 PM UTC 24
Finished Sep 03 11:27:57 PM UTC 24
Peak memory 211128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411153752 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.1411153752
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/0.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all.1372552438
Short name T213
Test name
Test status
Simulation time 4070686888 ps
CPU time 47.56 seconds
Started Sep 03 11:28:02 PM UTC 24
Finished Sep 03 11:28:51 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372552438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1372552438
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/0.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_error.2681032824
Short name T274
Test name
Test status
Simulation time 565003160 ps
CPU time 33.09 seconds
Started Sep 03 11:28:05 PM UTC 24
Finished Sep 03 11:28:40 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681032824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.2681032824
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/0.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1240587849
Short name T9
Test name
Test status
Simulation time 988241872 ps
CPU time 134.77 seconds
Started Sep 03 11:28:04 PM UTC 24
Finished Sep 03 11:30:22 PM UTC 24
Peak memory 214440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240587849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.1240587849
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/0.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_unmapped_addr.330960814
Short name T5
Test name
Test status
Simulation time 29180920 ps
CPU time 1.48 seconds
Started Sep 03 11:28:02 PM UTC 24
Finished Sep 03 11:28:05 PM UTC 24
Peak memory 211248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330960814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.330960814
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/0.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device.2551501348
Short name T39
Test name
Test status
Simulation time 16959717 ps
CPU time 2.95 seconds
Started Sep 03 11:28:10 PM UTC 24
Finished Sep 03 11:28:14 PM UTC 24
Peak memory 212112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551501348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.2551501348
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/1.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.226709975
Short name T294
Test name
Test status
Simulation time 92081763460 ps
CPU time 93.84 seconds
Started Sep 03 11:28:10 PM UTC 24
Finished Sep 03 11:29:46 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226709975 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.226709975
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/1.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.3475797711
Short name T52
Test name
Test status
Simulation time 235969682 ps
CPU time 3.15 seconds
Started Sep 03 11:28:13 PM UTC 24
Finished Sep 03 11:28:17 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475797711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.3475797711
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/1.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_error_random.3483585110
Short name T78
Test name
Test status
Simulation time 2341333579 ps
CPU time 15.22 seconds
Started Sep 03 11:28:10 PM UTC 24
Finished Sep 03 11:28:27 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483585110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.3483585110
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/1.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_large_delays.4275879562
Short name T186
Test name
Test status
Simulation time 112621048590 ps
CPU time 205.13 seconds
Started Sep 03 11:28:08 PM UTC 24
Finished Sep 03 11:31:36 PM UTC 24
Peak memory 213772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275879562 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.4275879562
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/1.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_slow_rsp.1639486632
Short name T291
Test name
Test status
Simulation time 9060933793 ps
CPU time 36.23 seconds
Started Sep 03 11:28:10 PM UTC 24
Finished Sep 03 11:28:48 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639486632 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.1639486632
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/1.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_zero_delays.1709803961
Short name T20
Test name
Test status
Simulation time 14038749 ps
CPU time 1.75 seconds
Started Sep 03 11:28:08 PM UTC 24
Finished Sep 03 11:28:10 PM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709803961 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.1709803961
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/1.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_same_source.1972951333
Short name T24
Test name
Test status
Simulation time 893531963 ps
CPU time 5.56 seconds
Started Sep 03 11:28:10 PM UTC 24
Finished Sep 03 11:28:17 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972951333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.1972951333
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/1.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke.2189431995
Short name T19
Test name
Test status
Simulation time 10689118 ps
CPU time 1.48 seconds
Started Sep 03 11:28:05 PM UTC 24
Finished Sep 03 11:28:08 PM UTC 24
Peak memory 211244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189431995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.2189431995
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/1.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_large_delays.623497424
Short name T23
Test name
Test status
Simulation time 1803111387 ps
CPU time 9.64 seconds
Started Sep 03 11:28:05 PM UTC 24
Finished Sep 03 11:28:16 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623497424 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.623497424
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/1.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.3991418565
Short name T53
Test name
Test status
Simulation time 2008296639 ps
CPU time 10.14 seconds
Started Sep 03 11:28:08 PM UTC 24
Finished Sep 03 11:28:19 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991418565 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3991418565
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/1.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.107735212
Short name T18
Test name
Test status
Simulation time 8422859 ps
CPU time 1.25 seconds
Started Sep 03 11:28:05 PM UTC 24
Finished Sep 03 11:28:08 PM UTC 24
Peak memory 211232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107735212 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.107735212
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/1.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all.2558170470
Short name T284
Test name
Test status
Simulation time 9642721196 ps
CPU time 64.22 seconds
Started Sep 03 11:28:13 PM UTC 24
Finished Sep 03 11:29:19 PM UTC 24
Peak memory 214436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558170470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2558170470
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/1.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_error.3276177892
Short name T40
Test name
Test status
Simulation time 28800296 ps
CPU time 1.45 seconds
Started Sep 03 11:28:13 PM UTC 24
Finished Sep 03 11:28:15 PM UTC 24
Peak memory 211124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276177892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.3276177892
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/1.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.1249357574
Short name T447
Test name
Test status
Simulation time 2818972333 ps
CPU time 179.47 seconds
Started Sep 03 11:28:13 PM UTC 24
Finished Sep 03 11:31:15 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249357574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.1249357574
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/1.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_unmapped_addr.3991419441
Short name T26
Test name
Test status
Simulation time 281446368 ps
CPU time 6.98 seconds
Started Sep 03 11:28:13 PM UTC 24
Finished Sep 03 11:28:21 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991419441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3991419441
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/1.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device.1249890179
Short name T249
Test name
Test status
Simulation time 488151751 ps
CPU time 13.79 seconds
Started Sep 03 11:29:21 PM UTC 24
Finished Sep 03 11:29:37 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249890179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.1249890179
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/10.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1837365204
Short name T299
Test name
Test status
Simulation time 35679567972 ps
CPU time 292.06 seconds
Started Sep 03 11:29:21 PM UTC 24
Finished Sep 03 11:34:17 PM UTC 24
Peak memory 218136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837365204 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.1837365204
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/10.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.2194917717
Short name T170
Test name
Test status
Simulation time 43984416 ps
CPU time 2.19 seconds
Started Sep 03 11:29:23 PM UTC 24
Finished Sep 03 11:29:27 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194917717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2194917717
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/10.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_error_random.1470802622
Short name T371
Test name
Test status
Simulation time 53161232 ps
CPU time 5.51 seconds
Started Sep 03 11:29:22 PM UTC 24
Finished Sep 03 11:29:28 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470802622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.1470802622
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/10.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random.843912485
Short name T369
Test name
Test status
Simulation time 840259652 ps
CPU time 5.48 seconds
Started Sep 03 11:29:20 PM UTC 24
Finished Sep 03 11:29:27 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843912485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.843912485
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/10.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_large_delays.2300161617
Short name T146
Test name
Test status
Simulation time 94589056211 ps
CPU time 105.61 seconds
Started Sep 03 11:29:21 PM UTC 24
Finished Sep 03 11:31:09 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300161617 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2300161617
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/10.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_slow_rsp.3628306564
Short name T259
Test name
Test status
Simulation time 58035800122 ps
CPU time 139.67 seconds
Started Sep 03 11:29:21 PM UTC 24
Finished Sep 03 11:31:44 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628306564 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3628306564
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/10.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_zero_delays.2057589044
Short name T169
Test name
Test status
Simulation time 66863102 ps
CPU time 3.67 seconds
Started Sep 03 11:29:21 PM UTC 24
Finished Sep 03 11:29:26 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057589044 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.2057589044
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/10.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_same_source.2188437715
Short name T372
Test name
Test status
Simulation time 54245252 ps
CPU time 6.66 seconds
Started Sep 03 11:29:22 PM UTC 24
Finished Sep 03 11:29:29 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188437715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2188437715
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/10.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke.2844565300
Short name T368
Test name
Test status
Simulation time 56813289 ps
CPU time 2.41 seconds
Started Sep 03 11:29:16 PM UTC 24
Finished Sep 03 11:29:19 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844565300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2844565300
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/10.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3255042656
Short name T373
Test name
Test status
Simulation time 3233138597 ps
CPU time 10.94 seconds
Started Sep 03 11:29:18 PM UTC 24
Finished Sep 03 11:29:30 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255042656 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3255042656
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/10.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.2380531591
Short name T72
Test name
Test status
Simulation time 1763165809 ps
CPU time 20.27 seconds
Started Sep 03 11:29:20 PM UTC 24
Finished Sep 03 11:29:41 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380531591 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.2380531591
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/10.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.2369966196
Short name T165
Test name
Test status
Simulation time 8927045 ps
CPU time 1.63 seconds
Started Sep 03 11:29:18 PM UTC 24
Finished Sep 03 11:29:20 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369966196 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.2369966196
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/10.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all.2109137131
Short name T248
Test name
Test status
Simulation time 190022227 ps
CPU time 11.32 seconds
Started Sep 03 11:29:23 PM UTC 24
Finished Sep 03 11:29:36 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109137131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.2109137131
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/10.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_error.1913999151
Short name T315
Test name
Test status
Simulation time 1547706610 ps
CPU time 28.09 seconds
Started Sep 03 11:29:27 PM UTC 24
Finished Sep 03 11:29:57 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913999151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.1913999151
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/10.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.13500908
Short name T324
Test name
Test status
Simulation time 29224055 ps
CPU time 20.18 seconds
Started Sep 03 11:29:25 PM UTC 24
Finished Sep 03 11:29:46 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13500908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.13500908
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/10.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.2488356486
Short name T333
Test name
Test status
Simulation time 1900500718 ps
CPU time 81.56 seconds
Started Sep 03 11:29:27 PM UTC 24
Finished Sep 03 11:30:51 PM UTC 24
Peak memory 216428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488356486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.2488356486
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/10.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_unmapped_addr.3479537754
Short name T370
Test name
Test status
Simulation time 21996311 ps
CPU time 3.24 seconds
Started Sep 03 11:29:23 PM UTC 24
Finished Sep 03 11:29:28 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479537754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.3479537754
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/10.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.1017547885
Short name T235
Test name
Test status
Simulation time 83694960979 ps
CPU time 173.14 seconds
Started Sep 03 11:29:35 PM UTC 24
Finished Sep 03 11:32:31 PM UTC 24
Peak memory 214240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017547885 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.1017547885
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/11.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.2033777009
Short name T376
Test name
Test status
Simulation time 96068705 ps
CPU time 6.84 seconds
Started Sep 03 11:29:37 PM UTC 24
Finished Sep 03 11:29:45 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033777009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.2033777009
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/11.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_error_random.3645019283
Short name T377
Test name
Test status
Simulation time 195651381 ps
CPU time 6.93 seconds
Started Sep 03 11:29:37 PM UTC 24
Finished Sep 03 11:29:45 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645019283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3645019283
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/11.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random.4143506303
Short name T73
Test name
Test status
Simulation time 1175050928 ps
CPU time 9.9 seconds
Started Sep 03 11:29:31 PM UTC 24
Finished Sep 03 11:29:42 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143506303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.4143506303
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/11.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_large_delays.2900770901
Short name T204
Test name
Test status
Simulation time 50245038593 ps
CPU time 170.16 seconds
Started Sep 03 11:29:31 PM UTC 24
Finished Sep 03 11:32:24 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900770901 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.2900770901
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/11.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_slow_rsp.3932354059
Short name T144
Test name
Test status
Simulation time 18796626422 ps
CPU time 92.52 seconds
Started Sep 03 11:29:32 PM UTC 24
Finished Sep 03 11:31:06 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932354059 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3932354059
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/11.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_zero_delays.2034152586
Short name T251
Test name
Test status
Simulation time 34352911 ps
CPU time 4.76 seconds
Started Sep 03 11:29:31 PM UTC 24
Finished Sep 03 11:29:37 PM UTC 24
Peak memory 212448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034152586 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.2034152586
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/11.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_same_source.614784146
Short name T74
Test name
Test status
Simulation time 1062359786 ps
CPU time 17.84 seconds
Started Sep 03 11:29:36 PM UTC 24
Finished Sep 03 11:29:55 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614784146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.614784146
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/11.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke.2842035544
Short name T374
Test name
Test status
Simulation time 12051760 ps
CPU time 1.6 seconds
Started Sep 03 11:29:27 PM UTC 24
Finished Sep 03 11:29:30 PM UTC 24
Peak memory 211244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842035544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.2842035544
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/11.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_large_delays.689777271
Short name T380
Test name
Test status
Simulation time 7242517437 ps
CPU time 16.74 seconds
Started Sep 03 11:29:29 PM UTC 24
Finished Sep 03 11:29:47 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689777271 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.689777271
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/11.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.1199825865
Short name T253
Test name
Test status
Simulation time 827541055 ps
CPU time 9.12 seconds
Started Sep 03 11:29:29 PM UTC 24
Finished Sep 03 11:29:40 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199825865 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.1199825865
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/11.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.1089655056
Short name T375
Test name
Test status
Simulation time 13569737 ps
CPU time 1.53 seconds
Started Sep 03 11:29:28 PM UTC 24
Finished Sep 03 11:29:31 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089655056 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.1089655056
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/11.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all.265139946
Short name T381
Test name
Test status
Simulation time 100322465 ps
CPU time 8.1 seconds
Started Sep 03 11:29:38 PM UTC 24
Finished Sep 03 11:29:48 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265139946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.265139946
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/11.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_error.2079116569
Short name T389
Test name
Test status
Simulation time 285677394 ps
CPU time 12.48 seconds
Started Sep 03 11:29:43 PM UTC 24
Finished Sep 03 11:29:57 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079116569 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2079116569
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/11.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.3576925288
Short name T325
Test name
Test status
Simulation time 354409733 ps
CPU time 25.23 seconds
Started Sep 03 11:29:41 PM UTC 24
Finished Sep 03 11:30:07 PM UTC 24
Peak memory 216232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576925288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.3576925288
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/11.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.2390947876
Short name T332
Test name
Test status
Simulation time 450587027 ps
CPU time 37.92 seconds
Started Sep 03 11:29:43 PM UTC 24
Finished Sep 03 11:30:22 PM UTC 24
Peak memory 214380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390947876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.2390947876
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/11.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_unmapped_addr.2730361271
Short name T378
Test name
Test status
Simulation time 376529024 ps
CPU time 7.51 seconds
Started Sep 03 11:29:37 PM UTC 24
Finished Sep 03 11:29:46 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730361271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2730361271
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/11.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device.1201360033
Short name T87
Test name
Test status
Simulation time 62445125 ps
CPU time 9.35 seconds
Started Sep 03 11:29:48 PM UTC 24
Finished Sep 03 11:29:58 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201360033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.1201360033
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/12.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.1997792996
Short name T298
Test name
Test status
Simulation time 24020672767 ps
CPU time 215.72 seconds
Started Sep 03 11:29:48 PM UTC 24
Finished Sep 03 11:33:27 PM UTC 24
Peak memory 214240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997792996 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.1997792996
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/12.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.2727091491
Short name T90
Test name
Test status
Simulation time 748034780 ps
CPU time 11.07 seconds
Started Sep 03 11:29:50 PM UTC 24
Finished Sep 03 11:30:02 PM UTC 24
Peak memory 212064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727091491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.2727091491
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/12.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_error_random.668012540
Short name T388
Test name
Test status
Simulation time 57170741 ps
CPU time 5.23 seconds
Started Sep 03 11:29:49 PM UTC 24
Finished Sep 03 11:29:55 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668012540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.668012540
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/12.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random.3911462417
Short name T382
Test name
Test status
Simulation time 52874210 ps
CPU time 5.99 seconds
Started Sep 03 11:29:46 PM UTC 24
Finished Sep 03 11:29:54 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911462417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.3911462417
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/12.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_large_delays.1880345536
Short name T442
Test name
Test status
Simulation time 86985851226 ps
CPU time 83.66 seconds
Started Sep 03 11:29:47 PM UTC 24
Finished Sep 03 11:31:13 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880345536 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1880345536
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/12.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_slow_rsp.3455411911
Short name T403
Test name
Test status
Simulation time 11169041650 ps
CPU time 27.79 seconds
Started Sep 03 11:29:47 PM UTC 24
Finished Sep 03 11:30:17 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455411911 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3455411911
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/12.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_zero_delays.1004590822
Short name T383
Test name
Test status
Simulation time 10316808 ps
CPU time 1.5 seconds
Started Sep 03 11:29:47 PM UTC 24
Finished Sep 03 11:29:50 PM UTC 24
Peak memory 211244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004590822 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.1004590822
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/12.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_same_source.2858166410
Short name T76
Test name
Test status
Simulation time 925253581 ps
CPU time 11.98 seconds
Started Sep 03 11:29:49 PM UTC 24
Finished Sep 03 11:30:02 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858166410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.2858166410
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/12.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke.1306739181
Short name T379
Test name
Test status
Simulation time 43841849 ps
CPU time 1.73 seconds
Started Sep 03 11:29:44 PM UTC 24
Finished Sep 03 11:29:47 PM UTC 24
Peak memory 211140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306739181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.1306739181
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/12.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_large_delays.2594652731
Short name T29
Test name
Test status
Simulation time 7839168673 ps
CPU time 17.63 seconds
Started Sep 03 11:29:46 PM UTC 24
Finished Sep 03 11:30:05 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594652731 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2594652731
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/12.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.2230877117
Short name T386
Test name
Test status
Simulation time 1531987246 ps
CPU time 5.65 seconds
Started Sep 03 11:29:46 PM UTC 24
Finished Sep 03 11:29:53 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230877117 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.2230877117
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/12.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.2399039219
Short name T250
Test name
Test status
Simulation time 12244425 ps
CPU time 1.56 seconds
Started Sep 03 11:29:46 PM UTC 24
Finished Sep 03 11:29:49 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399039219 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.2399039219
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/12.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all.1870286810
Short name T130
Test name
Test status
Simulation time 1877163844 ps
CPU time 39.6 seconds
Started Sep 03 11:29:51 PM UTC 24
Finished Sep 03 11:30:32 PM UTC 24
Peak memory 214176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870286810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1870286810
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/12.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3346344462
Short name T426
Test name
Test status
Simulation time 3554929314 ps
CPU time 57.5 seconds
Started Sep 03 11:29:52 PM UTC 24
Finished Sep 03 11:30:51 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346344462 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3346344462
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/12.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.2290799931
Short name T339
Test name
Test status
Simulation time 475049906 ps
CPU time 58.91 seconds
Started Sep 03 11:29:51 PM UTC 24
Finished Sep 03 11:30:52 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290799931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.2290799931
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/12.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3058036127
Short name T393
Test name
Test status
Simulation time 117185262 ps
CPU time 11.97 seconds
Started Sep 03 11:29:54 PM UTC 24
Finished Sep 03 11:30:07 PM UTC 24
Peak memory 212396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058036127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.3058036127
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/12.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_unmapped_addr.2871389709
Short name T387
Test name
Test status
Simulation time 23091042 ps
CPU time 3.57 seconds
Started Sep 03 11:29:50 PM UTC 24
Finished Sep 03 11:29:55 PM UTC 24
Peak memory 212052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871389709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2871389709
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/12.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device.453981320
Short name T392
Test name
Test status
Simulation time 37100494 ps
CPU time 7.25 seconds
Started Sep 03 11:29:58 PM UTC 24
Finished Sep 03 11:30:06 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453981320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.453981320
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/13.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.4073146193
Short name T301
Test name
Test status
Simulation time 154071695759 ps
CPU time 239.58 seconds
Started Sep 03 11:29:58 PM UTC 24
Finished Sep 03 11:34:01 PM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073146193 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.4073146193
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/13.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.733170781
Short name T395
Test name
Test status
Simulation time 51039090 ps
CPU time 4.53 seconds
Started Sep 03 11:30:03 PM UTC 24
Finished Sep 03 11:30:08 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733170781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.733170781
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/13.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_error_random.3702043256
Short name T92
Test name
Test status
Simulation time 39430945 ps
CPU time 3.47 seconds
Started Sep 03 11:29:59 PM UTC 24
Finished Sep 03 11:30:04 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702043256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3702043256
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/13.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random.1293012934
Short name T394
Test name
Test status
Simulation time 511245949 ps
CPU time 9.8 seconds
Started Sep 03 11:29:57 PM UTC 24
Finished Sep 03 11:30:08 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293012934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.1293012934
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/13.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_large_delays.4016230527
Short name T205
Test name
Test status
Simulation time 106935435005 ps
CPU time 144.21 seconds
Started Sep 03 11:29:57 PM UTC 24
Finished Sep 03 11:32:24 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016230527 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.4016230527
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/13.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_slow_rsp.4099854153
Short name T409
Test name
Test status
Simulation time 8766259354 ps
CPU time 29.81 seconds
Started Sep 03 11:29:58 PM UTC 24
Finished Sep 03 11:30:29 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099854153 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.4099854153
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/13.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_zero_delays.1203910371
Short name T89
Test name
Test status
Simulation time 8361005 ps
CPU time 1.6 seconds
Started Sep 03 11:29:57 PM UTC 24
Finished Sep 03 11:29:59 PM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203910371 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.1203910371
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/13.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_same_source.1465486949
Short name T93
Test name
Test status
Simulation time 45281222 ps
CPU time 3.69 seconds
Started Sep 03 11:29:59 PM UTC 24
Finished Sep 03 11:30:04 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465486949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1465486949
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/13.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke.6787204
Short name T391
Test name
Test status
Simulation time 317162829 ps
CPU time 2.03 seconds
Started Sep 03 11:29:54 PM UTC 24
Finished Sep 03 11:29:57 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6787204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_T
EST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/
coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.6787204
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/13.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_large_delays.3180444462
Short name T111
Test name
Test status
Simulation time 2109606933 ps
CPU time 8.6 seconds
Started Sep 03 11:29:56 PM UTC 24
Finished Sep 03 11:30:05 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180444462 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.3180444462
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/13.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.529279876
Short name T397
Test name
Test status
Simulation time 1578934488 ps
CPU time 12.37 seconds
Started Sep 03 11:29:56 PM UTC 24
Finished Sep 03 11:30:09 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529279876 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.529279876
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/13.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.648717161
Short name T88
Test name
Test status
Simulation time 8633361 ps
CPU time 1.66 seconds
Started Sep 03 11:29:56 PM UTC 24
Finished Sep 03 11:29:58 PM UTC 24
Peak memory 211128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648717161 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.648717161
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/13.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all.2399619222
Short name T429
Test name
Test status
Simulation time 466645771 ps
CPU time 49.65 seconds
Started Sep 03 11:30:03 PM UTC 24
Finished Sep 03 11:30:54 PM UTC 24
Peak memory 214376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399619222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.2399619222
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/13.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_error.3099281779
Short name T202
Test name
Test status
Simulation time 36364770107 ps
CPU time 136.06 seconds
Started Sep 03 11:30:05 PM UTC 24
Finished Sep 03 11:32:23 PM UTC 24
Peak memory 216292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099281779 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3099281779
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/13.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.1881581544
Short name T137
Test name
Test status
Simulation time 807152393 ps
CPU time 88.1 seconds
Started Sep 03 11:30:04 PM UTC 24
Finished Sep 03 11:31:34 PM UTC 24
Peak memory 216228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881581544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.1881581544
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/13.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.3403846641
Short name T207
Test name
Test status
Simulation time 183113246 ps
CPU time 27.19 seconds
Started Sep 03 11:30:05 PM UTC 24
Finished Sep 03 11:30:33 PM UTC 24
Peak memory 214380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403846641 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.3403846641
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/13.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device.3559380519
Short name T269
Test name
Test status
Simulation time 54642183 ps
CPU time 9.11 seconds
Started Sep 03 11:30:09 PM UTC 24
Finished Sep 03 11:30:19 PM UTC 24
Peak memory 212140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559380519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.3559380519
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/14.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.449547014
Short name T150
Test name
Test status
Simulation time 9755379881 ps
CPU time 57.99 seconds
Started Sep 03 11:30:10 PM UTC 24
Finished Sep 03 11:31:10 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449547014 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.449547014
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/14.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.1974754788
Short name T407
Test name
Test status
Simulation time 638079166 ps
CPU time 10.18 seconds
Started Sep 03 11:30:15 PM UTC 24
Finished Sep 03 11:30:27 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974754788 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.1974754788
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/14.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_error_random.3876577190
Short name T402
Test name
Test status
Simulation time 33959950 ps
CPU time 4.26 seconds
Started Sep 03 11:30:10 PM UTC 24
Finished Sep 03 11:30:15 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876577190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.3876577190
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/14.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random.1065944149
Short name T273
Test name
Test status
Simulation time 842233752 ps
CPU time 11.87 seconds
Started Sep 03 11:30:08 PM UTC 24
Finished Sep 03 11:30:20 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065944149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.1065944149
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/14.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_large_delays.1713258606
Short name T101
Test name
Test status
Simulation time 36517283779 ps
CPU time 209.75 seconds
Started Sep 03 11:30:09 PM UTC 24
Finished Sep 03 11:33:42 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713258606 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.1713258606
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/14.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_slow_rsp.2458808172
Short name T31
Test name
Test status
Simulation time 31941291591 ps
CPU time 80.69 seconds
Started Sep 03 11:30:09 PM UTC 24
Finished Sep 03 11:31:31 PM UTC 24
Peak memory 212456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458808172 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.2458808172
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/14.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_zero_delays.1557065315
Short name T399
Test name
Test status
Simulation time 35120663 ps
CPU time 4.88 seconds
Started Sep 03 11:30:09 PM UTC 24
Finished Sep 03 11:30:15 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557065315 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.1557065315
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/14.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_same_source.636876508
Short name T268
Test name
Test status
Simulation time 281331391 ps
CPU time 7.79 seconds
Started Sep 03 11:30:10 PM UTC 24
Finished Sep 03 11:30:19 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636876508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.636876508
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/14.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke.667581115
Short name T398
Test name
Test status
Simulation time 54532266 ps
CPU time 2.21 seconds
Started Sep 03 11:30:06 PM UTC 24
Finished Sep 03 11:30:09 PM UTC 24
Peak memory 212316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667581115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.667581115
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/14.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_large_delays.2481774120
Short name T400
Test name
Test status
Simulation time 2175388889 ps
CPU time 6.26 seconds
Started Sep 03 11:30:07 PM UTC 24
Finished Sep 03 11:30:15 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481774120 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2481774120
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/14.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.785905823
Short name T404
Test name
Test status
Simulation time 1060065433 ps
CPU time 12.17 seconds
Started Sep 03 11:30:07 PM UTC 24
Finished Sep 03 11:30:21 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785905823 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.785905823
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/14.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.2168847500
Short name T396
Test name
Test status
Simulation time 8875334 ps
CPU time 1.64 seconds
Started Sep 03 11:30:06 PM UTC 24
Finished Sep 03 11:30:09 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168847500 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.2168847500
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/14.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_error.2042603190
Short name T208
Test name
Test status
Simulation time 197918519 ps
CPU time 15.91 seconds
Started Sep 03 11:30:17 PM UTC 24
Finished Sep 03 11:30:34 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042603190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.2042603190
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/14.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.3237860090
Short name T123
Test name
Test status
Simulation time 6137190942 ps
CPU time 110.17 seconds
Started Sep 03 11:30:17 PM UTC 24
Finished Sep 03 11:32:09 PM UTC 24
Peak memory 216300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237860090 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.3237860090
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/14.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_unmapped_addr.1095215925
Short name T83
Test name
Test status
Simulation time 188666461 ps
CPU time 4.31 seconds
Started Sep 03 11:30:12 PM UTC 24
Finished Sep 03 11:30:18 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095215925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1095215925
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/14.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device.396736351
Short name T408
Test name
Test status
Simulation time 25765773 ps
CPU time 5.76 seconds
Started Sep 03 11:30:22 PM UTC 24
Finished Sep 03 11:30:28 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396736351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.396736351
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/15.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.2795555036
Short name T414
Test name
Test status
Simulation time 363565870 ps
CPU time 7.04 seconds
Started Sep 03 11:30:23 PM UTC 24
Finished Sep 03 11:30:31 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795555036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2795555036
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/15.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_error_random.2459996375
Short name T410
Test name
Test status
Simulation time 821023729 ps
CPU time 6.57 seconds
Started Sep 03 11:30:22 PM UTC 24
Finished Sep 03 11:30:29 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459996375 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2459996375
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/15.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_large_delays.815445766
Short name T415
Test name
Test status
Simulation time 11290278986 ps
CPU time 21.44 seconds
Started Sep 03 11:30:20 PM UTC 24
Finished Sep 03 11:30:43 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815445766 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.815445766
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/15.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_slow_rsp.3240717525
Short name T147
Test name
Test status
Simulation time 6190467022 ps
CPU time 45.89 seconds
Started Sep 03 11:30:22 PM UTC 24
Finished Sep 03 11:31:09 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240717525 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3240717525
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/15.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_zero_delays.193431769
Short name T406
Test name
Test status
Simulation time 29286318 ps
CPU time 4.58 seconds
Started Sep 03 11:30:20 PM UTC 24
Finished Sep 03 11:30:26 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193431769 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.193431769
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/15.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_same_source.2030544792
Short name T405
Test name
Test status
Simulation time 25838354 ps
CPU time 2.65 seconds
Started Sep 03 11:30:22 PM UTC 24
Finished Sep 03 11:30:25 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030544792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2030544792
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/15.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke.4258039892
Short name T271
Test name
Test status
Simulation time 7883601 ps
CPU time 1.48 seconds
Started Sep 03 11:30:18 PM UTC 24
Finished Sep 03 11:30:20 PM UTC 24
Peak memory 211140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258039892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.4258039892
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/15.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_large_delays.3705199581
Short name T209
Test name
Test status
Simulation time 4043854761 ps
CPU time 14.05 seconds
Started Sep 03 11:30:19 PM UTC 24
Finished Sep 03 11:30:34 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705199581 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3705199581
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/15.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.1024484387
Short name T411
Test name
Test status
Simulation time 948032395 ps
CPU time 9.48 seconds
Started Sep 03 11:30:19 PM UTC 24
Finished Sep 03 11:30:30 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024484387 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.1024484387
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/15.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.2270009453
Short name T270
Test name
Test status
Simulation time 9232253 ps
CPU time 1.11 seconds
Started Sep 03 11:30:18 PM UTC 24
Finished Sep 03 11:30:20 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270009453 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.2270009453
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/15.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all.1769849318
Short name T95
Test name
Test status
Simulation time 4387986825 ps
CPU time 38.63 seconds
Started Sep 03 11:30:24 PM UTC 24
Finished Sep 03 11:31:04 PM UTC 24
Peak memory 214568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769849318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1769849318
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/15.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_error.2543681955
Short name T443
Test name
Test status
Simulation time 2412196044 ps
CPU time 44.93 seconds
Started Sep 03 11:30:27 PM UTC 24
Finished Sep 03 11:31:13 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543681955 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2543681955
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/15.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.2634370795
Short name T12
Test name
Test status
Simulation time 10023183318 ps
CPU time 185.91 seconds
Started Sep 03 11:30:27 PM UTC 24
Finished Sep 03 11:33:35 PM UTC 24
Peak memory 218340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634370795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.2634370795
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/15.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.4170675955
Short name T138
Test name
Test status
Simulation time 5588354841 ps
CPU time 66.56 seconds
Started Sep 03 11:30:27 PM UTC 24
Finished Sep 03 11:31:35 PM UTC 24
Peak memory 216296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170675955 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.4170675955
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/15.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_unmapped_addr.3606021687
Short name T151
Test name
Test status
Simulation time 785778090 ps
CPU time 12.56 seconds
Started Sep 03 11:30:23 PM UTC 24
Finished Sep 03 11:30:37 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606021687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3606021687
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/15.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device.3267773198
Short name T192
Test name
Test status
Simulation time 1082666459 ps
CPU time 8.6 seconds
Started Sep 03 11:30:31 PM UTC 24
Finished Sep 03 11:30:40 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267773198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.3267773198
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/16.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.1161716391
Short name T210
Test name
Test status
Simulation time 26826058 ps
CPU time 2.4 seconds
Started Sep 03 11:30:33 PM UTC 24
Finished Sep 03 11:30:36 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161716391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.1161716391
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/16.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_error_random.1645255879
Short name T187
Test name
Test status
Simulation time 292243915 ps
CPU time 4.51 seconds
Started Sep 03 11:30:32 PM UTC 24
Finished Sep 03 11:30:37 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645255879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1645255879
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/16.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random.3545361168
Short name T239
Test name
Test status
Simulation time 392477779 ps
CPU time 1.98 seconds
Started Sep 03 11:30:29 PM UTC 24
Finished Sep 03 11:30:32 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545361168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.3545361168
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/16.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_large_delays.2177103877
Short name T194
Test name
Test status
Simulation time 1882932659 ps
CPU time 10.73 seconds
Started Sep 03 11:30:30 PM UTC 24
Finished Sep 03 11:30:42 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177103877 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2177103877
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/16.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_slow_rsp.641387862
Short name T521
Test name
Test status
Simulation time 86885891665 ps
CPU time 159.15 seconds
Started Sep 03 11:30:30 PM UTC 24
Finished Sep 03 11:33:12 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641387862 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.641387862
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/16.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_zero_delays.2580124032
Short name T188
Test name
Test status
Simulation time 62327652 ps
CPU time 6.03 seconds
Started Sep 03 11:30:30 PM UTC 24
Finished Sep 03 11:30:38 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580124032 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.2580124032
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/16.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_same_source.3581502755
Short name T390
Test name
Test status
Simulation time 28558583 ps
CPU time 2.49 seconds
Started Sep 03 11:30:32 PM UTC 24
Finished Sep 03 11:30:35 PM UTC 24
Peak memory 212116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581502755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.3581502755
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/16.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke.4044249041
Short name T413
Test name
Test status
Simulation time 58996398 ps
CPU time 1.95 seconds
Started Sep 03 11:30:28 PM UTC 24
Finished Sep 03 11:30:31 PM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044249041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.4044249041
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/16.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_large_delays.2424006248
Short name T416
Test name
Test status
Simulation time 2843646874 ps
CPU time 13.06 seconds
Started Sep 03 11:30:29 PM UTC 24
Finished Sep 03 11:30:43 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424006248 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2424006248
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/16.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.2173654032
Short name T189
Test name
Test status
Simulation time 831839819 ps
CPU time 7.67 seconds
Started Sep 03 11:30:29 PM UTC 24
Finished Sep 03 11:30:38 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173654032 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2173654032
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/16.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.3822389112
Short name T412
Test name
Test status
Simulation time 12593638 ps
CPU time 1.61 seconds
Started Sep 03 11:30:28 PM UTC 24
Finished Sep 03 11:30:31 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822389112 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.3822389112
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/16.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all.2382428792
Short name T96
Test name
Test status
Simulation time 21451500203 ps
CPU time 90.72 seconds
Started Sep 03 11:30:33 PM UTC 24
Finished Sep 03 11:32:06 PM UTC 24
Peak memory 214252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382428792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.2382428792
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/16.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_error.1758933122
Short name T145
Test name
Test status
Simulation time 898407272 ps
CPU time 32.39 seconds
Started Sep 03 11:30:34 PM UTC 24
Finished Sep 03 11:31:08 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758933122 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1758933122
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/16.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.1584695704
Short name T337
Test name
Test status
Simulation time 851705350 ps
CPU time 163.02 seconds
Started Sep 03 11:30:34 PM UTC 24
Finished Sep 03 11:33:20 PM UTC 24
Peak memory 218724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584695704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.1584695704
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/16.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.342003774
Short name T448
Test name
Test status
Simulation time 565722188 ps
CPU time 40.36 seconds
Started Sep 03 11:30:34 PM UTC 24
Finished Sep 03 11:31:16 PM UTC 24
Peak memory 214380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342003774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.342003774
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/16.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_unmapped_addr.2197769413
Short name T195
Test name
Test status
Simulation time 284129691 ps
CPU time 8.67 seconds
Started Sep 03 11:30:33 PM UTC 24
Finished Sep 03 11:30:43 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197769413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.2197769413
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/16.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device.2759628569
Short name T417
Test name
Test status
Simulation time 22872767 ps
CPU time 4.55 seconds
Started Sep 03 11:30:40 PM UTC 24
Finished Sep 03 11:30:46 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759628569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2759628569
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/17.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3065404258
Short name T427
Test name
Test status
Simulation time 780153480 ps
CPU time 6.63 seconds
Started Sep 03 11:30:44 PM UTC 24
Finished Sep 03 11:30:52 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065404258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.3065404258
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/17.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_error_random.2667495969
Short name T419
Test name
Test status
Simulation time 73756131 ps
CPU time 2.5 seconds
Started Sep 03 11:30:43 PM UTC 24
Finished Sep 03 11:30:47 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667495969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2667495969
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/17.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random.3675643147
Short name T418
Test name
Test status
Simulation time 207530071 ps
CPU time 6.31 seconds
Started Sep 03 11:30:39 PM UTC 24
Finished Sep 03 11:30:46 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675643147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.3675643147
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/17.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_large_delays.3912868732
Short name T524
Test name
Test status
Simulation time 77158539283 ps
CPU time 154.52 seconds
Started Sep 03 11:30:39 PM UTC 24
Finished Sep 03 11:33:16 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912868732 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3912868732
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/17.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_slow_rsp.2787008401
Short name T468
Test name
Test status
Simulation time 27411344525 ps
CPU time 56.84 seconds
Started Sep 03 11:30:40 PM UTC 24
Finished Sep 03 11:31:38 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787008401 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2787008401
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/17.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_zero_delays.1211925038
Short name T193
Test name
Test status
Simulation time 12889350 ps
CPU time 2.1 seconds
Started Sep 03 11:30:39 PM UTC 24
Finished Sep 03 11:30:42 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211925038 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.1211925038
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/17.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_same_source.854996397
Short name T431
Test name
Test status
Simulation time 1984893013 ps
CPU time 11.99 seconds
Started Sep 03 11:30:43 PM UTC 24
Finished Sep 03 11:30:56 PM UTC 24
Peak memory 212184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854996397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.854996397
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/17.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke.1062926059
Short name T190
Test name
Test status
Simulation time 59603589 ps
CPU time 1.98 seconds
Started Sep 03 11:30:35 PM UTC 24
Finished Sep 03 11:30:39 PM UTC 24
Peak memory 211228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062926059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.1062926059
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/17.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_large_delays.3715198343
Short name T420
Test name
Test status
Simulation time 1576309342 ps
CPU time 9.21 seconds
Started Sep 03 11:30:38 PM UTC 24
Finished Sep 03 11:30:48 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715198343 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.3715198343
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/17.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.937576333
Short name T425
Test name
Test status
Simulation time 1036776905 ps
CPU time 12.51 seconds
Started Sep 03 11:30:38 PM UTC 24
Finished Sep 03 11:30:51 PM UTC 24
Peak memory 212260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937576333 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.937576333
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/17.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.2214965275
Short name T191
Test name
Test status
Simulation time 17278354 ps
CPU time 1.69 seconds
Started Sep 03 11:30:36 PM UTC 24
Finished Sep 03 11:30:39 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214965275 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.2214965275
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/17.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all.3885261100
Short name T126
Test name
Test status
Simulation time 6036168235 ps
CPU time 84.98 seconds
Started Sep 03 11:30:44 PM UTC 24
Finished Sep 03 11:32:11 PM UTC 24
Peak memory 214440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885261100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3885261100
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/17.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_error.843688823
Short name T430
Test name
Test status
Simulation time 200673036 ps
CPU time 7.4 seconds
Started Sep 03 11:30:47 PM UTC 24
Finished Sep 03 11:30:55 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843688823 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.843688823
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/17.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.2887701508
Short name T338
Test name
Test status
Simulation time 373783103 ps
CPU time 38.1 seconds
Started Sep 03 11:30:46 PM UTC 24
Finished Sep 03 11:31:25 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887701508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.2887701508
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/17.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.441680605
Short name T327
Test name
Test status
Simulation time 68513478 ps
CPU time 9.28 seconds
Started Sep 03 11:30:47 PM UTC 24
Finished Sep 03 11:30:57 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441680605 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.441680605
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/17.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_unmapped_addr.1568479686
Short name T424
Test name
Test status
Simulation time 571760619 ps
CPU time 6.87 seconds
Started Sep 03 11:30:43 PM UTC 24
Finished Sep 03 11:30:51 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568479686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.1568479686
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/17.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device.1402487391
Short name T432
Test name
Test status
Simulation time 15511138 ps
CPU time 2.89 seconds
Started Sep 03 11:30:53 PM UTC 24
Finished Sep 03 11:30:57 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402487391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.1402487391
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/18.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3146283772
Short name T436
Test name
Test status
Simulation time 46842467 ps
CPU time 5.5 seconds
Started Sep 03 11:30:55 PM UTC 24
Finished Sep 03 11:31:02 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146283772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3146283772
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/18.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_error_random.3398925687
Short name T433
Test name
Test status
Simulation time 62675342 ps
CPU time 6.42 seconds
Started Sep 03 11:30:53 PM UTC 24
Finished Sep 03 11:31:00 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398925687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3398925687
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/18.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random.2987625439
Short name T143
Test name
Test status
Simulation time 7426380761 ps
CPU time 12.78 seconds
Started Sep 03 11:30:51 PM UTC 24
Finished Sep 03 11:31:05 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987625439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.2987625439
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/18.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_large_delays.940014970
Short name T37
Test name
Test status
Simulation time 146796860284 ps
CPU time 189.26 seconds
Started Sep 03 11:30:51 PM UTC 24
Finished Sep 03 11:34:03 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940014970 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.940014970
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/18.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_slow_rsp.495534808
Short name T124
Test name
Test status
Simulation time 11737390494 ps
CPU time 74.76 seconds
Started Sep 03 11:30:53 PM UTC 24
Finished Sep 03 11:32:09 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495534808 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.495534808
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/18.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_zero_delays.349267107
Short name T438
Test name
Test status
Simulation time 106066185 ps
CPU time 10.27 seconds
Started Sep 03 11:30:51 PM UTC 24
Finished Sep 03 11:31:03 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349267107 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.349267107
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/18.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_same_source.3695905339
Short name T152
Test name
Test status
Simulation time 204253153 ps
CPU time 3.36 seconds
Started Sep 03 11:30:53 PM UTC 24
Finished Sep 03 11:30:57 PM UTC 24
Peak memory 212448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695905339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3695905339
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/18.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke.3223910839
Short name T421
Test name
Test status
Simulation time 101860232 ps
CPU time 2.31 seconds
Started Sep 03 11:30:47 PM UTC 24
Finished Sep 03 11:30:50 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223910839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.3223910839
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/18.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_large_delays.3838125916
Short name T142
Test name
Test status
Simulation time 10483939922 ps
CPU time 14.58 seconds
Started Sep 03 11:30:49 PM UTC 24
Finished Sep 03 11:31:05 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838125916 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.3838125916
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/18.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.713155738
Short name T30
Test name
Test status
Simulation time 1137748386 ps
CPU time 8.57 seconds
Started Sep 03 11:30:51 PM UTC 24
Finished Sep 03 11:31:01 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713155738 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.713155738
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/18.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.1572740279
Short name T422
Test name
Test status
Simulation time 9475763 ps
CPU time 1.65 seconds
Started Sep 03 11:30:48 PM UTC 24
Finished Sep 03 11:30:51 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572740279 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.1572740279
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/18.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all.1490012152
Short name T306
Test name
Test status
Simulation time 5319744940 ps
CPU time 49.01 seconds
Started Sep 03 11:30:56 PM UTC 24
Finished Sep 03 11:31:47 PM UTC 24
Peak memory 214248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490012152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.1490012152
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/18.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_error.52860114
Short name T280
Test name
Test status
Simulation time 7211703063 ps
CPU time 103.66 seconds
Started Sep 03 11:30:57 PM UTC 24
Finished Sep 03 11:32:43 PM UTC 24
Peak memory 214248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52860114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.52860114
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/18.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.1687099862
Short name T234
Test name
Test status
Simulation time 8161913779 ps
CPU time 91.13 seconds
Started Sep 03 11:30:57 PM UTC 24
Finished Sep 03 11:32:30 PM UTC 24
Peak memory 214504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687099862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.1687099862
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/18.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.2221024863
Short name T566
Test name
Test status
Simulation time 9916081622 ps
CPU time 173.11 seconds
Started Sep 03 11:30:59 PM UTC 24
Finished Sep 03 11:33:55 PM UTC 24
Peak memory 216492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221024863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.2221024863
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/18.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_unmapped_addr.811901412
Short name T434
Test name
Test status
Simulation time 37387428 ps
CPU time 5.87 seconds
Started Sep 03 11:30:54 PM UTC 24
Finished Sep 03 11:31:01 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811901412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.811901412
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/18.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device.2196386306
Short name T279
Test name
Test status
Simulation time 878991785 ps
CPU time 14.53 seconds
Started Sep 03 11:31:03 PM UTC 24
Finished Sep 03 11:31:19 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196386306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.2196386306
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/19.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.2019081709
Short name T161
Test name
Test status
Simulation time 68909581993 ps
CPU time 285.69 seconds
Started Sep 03 11:31:05 PM UTC 24
Finished Sep 03 11:35:55 PM UTC 24
Peak memory 216008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019081709 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.2019081709
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/19.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.3448804046
Short name T450
Test name
Test status
Simulation time 237067533 ps
CPU time 6.9 seconds
Started Sep 03 11:31:09 PM UTC 24
Finished Sep 03 11:31:17 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448804046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.3448804046
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/19.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_error_random.1433227893
Short name T454
Test name
Test status
Simulation time 2952802350 ps
CPU time 13.48 seconds
Started Sep 03 11:31:06 PM UTC 24
Finished Sep 03 11:31:21 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433227893 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1433227893
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/19.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random.377232120
Short name T149
Test name
Test status
Simulation time 1529000506 ps
CPU time 6.45 seconds
Started Sep 03 11:31:02 PM UTC 24
Finished Sep 03 11:31:10 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377232120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.377232120
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/19.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_large_delays.1916531166
Short name T525
Test name
Test status
Simulation time 23208083732 ps
CPU time 131.67 seconds
Started Sep 03 11:31:02 PM UTC 24
Finished Sep 03 11:33:16 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916531166 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1916531166
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/19.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_slow_rsp.2745027656
Short name T506
Test name
Test status
Simulation time 22160472738 ps
CPU time 117.51 seconds
Started Sep 03 11:31:03 PM UTC 24
Finished Sep 03 11:33:03 PM UTC 24
Peak memory 212260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745027656 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2745027656
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/19.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_zero_delays.3754219805
Short name T441
Test name
Test status
Simulation time 61671812 ps
CPU time 9.59 seconds
Started Sep 03 11:31:02 PM UTC 24
Finished Sep 03 11:31:13 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754219805 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.3754219805
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/19.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_same_source.2878920466
Short name T444
Test name
Test status
Simulation time 78899169 ps
CPU time 7.54 seconds
Started Sep 03 11:31:05 PM UTC 24
Finished Sep 03 11:31:14 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878920466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.2878920466
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/19.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke.509165091
Short name T437
Test name
Test status
Simulation time 97254403 ps
CPU time 2.66 seconds
Started Sep 03 11:30:59 PM UTC 24
Finished Sep 03 11:31:02 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509165091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.509165091
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/19.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_large_delays.2746972693
Short name T452
Test name
Test status
Simulation time 11764256829 ps
CPU time 17.07 seconds
Started Sep 03 11:31:01 PM UTC 24
Finished Sep 03 11:31:19 PM UTC 24
Peak memory 212512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746972693 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2746972693
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/19.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.3265322646
Short name T440
Test name
Test status
Simulation time 1073968109 ps
CPU time 8.4 seconds
Started Sep 03 11:31:02 PM UTC 24
Finished Sep 03 11:31:11 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265322646 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3265322646
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/19.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.1202024376
Short name T435
Test name
Test status
Simulation time 9051805 ps
CPU time 1.8 seconds
Started Sep 03 11:30:59 PM UTC 24
Finished Sep 03 11:31:01 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202024376 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.1202024376
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/19.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_error.3476359546
Short name T308
Test name
Test status
Simulation time 9056806076 ps
CPU time 42.43 seconds
Started Sep 03 11:31:10 PM UTC 24
Finished Sep 03 11:31:54 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476359546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3476359546
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/19.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.2459821373
Short name T328
Test name
Test status
Simulation time 461485693 ps
CPU time 41.59 seconds
Started Sep 03 11:31:10 PM UTC 24
Finished Sep 03 11:31:53 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459821373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.2459821373
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/19.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_unmapped_addr.743795589
Short name T439
Test name
Test status
Simulation time 271923695 ps
CPU time 2.54 seconds
Started Sep 03 11:31:08 PM UTC 24
Finished Sep 03 11:31:11 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743795589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.743795589
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/19.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device.2023517448
Short name T44
Test name
Test status
Simulation time 355951330 ps
CPU time 6.46 seconds
Started Sep 03 11:28:18 PM UTC 24
Finished Sep 03 11:28:26 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023517448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.2023517448
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/2.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.1428407149
Short name T140
Test name
Test status
Simulation time 71853377 ps
CPU time 3.71 seconds
Started Sep 03 11:28:18 PM UTC 24
Finished Sep 03 11:28:23 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428407149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.1428407149
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/2.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_error_random.1817230877
Short name T63
Test name
Test status
Simulation time 30321262 ps
CPU time 1.45 seconds
Started Sep 03 11:28:18 PM UTC 24
Finished Sep 03 11:28:21 PM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817230877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1817230877
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/2.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_large_delays.159910268
Short name T171
Test name
Test status
Simulation time 55354322829 ps
CPU time 201.02 seconds
Started Sep 03 11:28:16 PM UTC 24
Finished Sep 03 11:31:40 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159910268 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.159910268
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/2.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_slow_rsp.1512768054
Short name T300
Test name
Test status
Simulation time 5868923944 ps
CPU time 42.29 seconds
Started Sep 03 11:28:16 PM UTC 24
Finished Sep 03 11:29:00 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512768054 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.1512768054
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/2.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_zero_delays.2620457151
Short name T36
Test name
Test status
Simulation time 68838976 ps
CPU time 5.71 seconds
Started Sep 03 11:28:16 PM UTC 24
Finished Sep 03 11:28:23 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620457151 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.2620457151
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/2.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_same_source.3316769526
Short name T27
Test name
Test status
Simulation time 171039771 ps
CPU time 2.91 seconds
Started Sep 03 11:28:18 PM UTC 24
Finished Sep 03 11:28:22 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316769526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3316769526
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/2.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke.3407208890
Short name T25
Test name
Test status
Simulation time 62828472 ps
CPU time 1.94 seconds
Started Sep 03 11:28:15 PM UTC 24
Finished Sep 03 11:28:19 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407208890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3407208890
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/2.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_large_delays.3826152521
Short name T80
Test name
Test status
Simulation time 2312319442 ps
CPU time 11.06 seconds
Started Sep 03 11:28:16 PM UTC 24
Finished Sep 03 11:28:28 PM UTC 24
Peak memory 212256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826152521 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3826152521
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/2.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.2452940297
Short name T141
Test name
Test status
Simulation time 941012294 ps
CPU time 6.41 seconds
Started Sep 03 11:28:16 PM UTC 24
Finished Sep 03 11:28:23 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452940297 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2452940297
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/2.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.2449869424
Short name T41
Test name
Test status
Simulation time 11451948 ps
CPU time 1.18 seconds
Started Sep 03 11:28:15 PM UTC 24
Finished Sep 03 11:28:18 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449869424 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.2449869424
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/2.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all.4095365463
Short name T342
Test name
Test status
Simulation time 464702888 ps
CPU time 40.16 seconds
Started Sep 03 11:28:19 PM UTC 24
Finished Sep 03 11:29:01 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095365463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.4095365463
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/2.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.2805954525
Short name T330
Test name
Test status
Simulation time 1266596394 ps
CPU time 124.96 seconds
Started Sep 03 11:28:19 PM UTC 24
Finished Sep 03 11:30:27 PM UTC 24
Peak memory 218280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805954525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.2805954525
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/2.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_unmapped_addr.1619874520
Short name T55
Test name
Test status
Simulation time 664255014 ps
CPU time 10.07 seconds
Started Sep 03 11:28:18 PM UTC 24
Finished Sep 03 11:28:29 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619874520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.1619874520
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/2.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device.1820675789
Short name T133
Test name
Test status
Simulation time 744794618 ps
CPU time 14.93 seconds
Started Sep 03 11:31:15 PM UTC 24
Finished Sep 03 11:31:31 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820675789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.1820675789
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/20.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.1074633665
Short name T290
Test name
Test status
Simulation time 97157596661 ps
CPU time 381.88 seconds
Started Sep 03 11:31:16 PM UTC 24
Finished Sep 03 11:37:43 PM UTC 24
Peak memory 217940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074633665 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.1074633665
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/20.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.2773660465
Short name T460
Test name
Test status
Simulation time 516751641 ps
CPU time 5.85 seconds
Started Sep 03 11:31:19 PM UTC 24
Finished Sep 03 11:31:25 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773660465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.2773660465
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/20.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_error_random.2456275300
Short name T463
Test name
Test status
Simulation time 816274430 ps
CPU time 9.56 seconds
Started Sep 03 11:31:17 PM UTC 24
Finished Sep 03 11:31:28 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456275300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.2456275300
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/20.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random.3726981854
Short name T449
Test name
Test status
Simulation time 58797786 ps
CPU time 2.42 seconds
Started Sep 03 11:31:14 PM UTC 24
Finished Sep 03 11:31:17 PM UTC 24
Peak memory 212084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726981854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.3726981854
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/20.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_large_delays.1350875825
Short name T550
Test name
Test status
Simulation time 177824590245 ps
CPU time 145.22 seconds
Started Sep 03 11:31:15 PM UTC 24
Finished Sep 03 11:33:43 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350875825 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1350875825
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/20.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_slow_rsp.400956688
Short name T118
Test name
Test status
Simulation time 18295954178 ps
CPU time 111.15 seconds
Started Sep 03 11:31:15 PM UTC 24
Finished Sep 03 11:33:08 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400956688 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.400956688
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/20.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_zero_delays.2749580937
Short name T456
Test name
Test status
Simulation time 83801015 ps
CPU time 6.89 seconds
Started Sep 03 11:31:14 PM UTC 24
Finished Sep 03 11:31:22 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749580937 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2749580937
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/20.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_same_source.4272781593
Short name T457
Test name
Test status
Simulation time 126620072 ps
CPU time 4.85 seconds
Started Sep 03 11:31:16 PM UTC 24
Finished Sep 03 11:31:22 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272781593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.4272781593
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/20.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke.239555638
Short name T445
Test name
Test status
Simulation time 10917875 ps
CPU time 1.77 seconds
Started Sep 03 11:31:11 PM UTC 24
Finished Sep 03 11:31:14 PM UTC 24
Peak memory 211128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239555638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.239555638
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/20.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_large_delays.1298993845
Short name T132
Test name
Test status
Simulation time 6146894939 ps
CPU time 17.6 seconds
Started Sep 03 11:31:12 PM UTC 24
Finished Sep 03 11:31:31 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298993845 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1298993845
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/20.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.1187162377
Short name T455
Test name
Test status
Simulation time 1399497374 ps
CPU time 6.93 seconds
Started Sep 03 11:31:13 PM UTC 24
Finished Sep 03 11:31:22 PM UTC 24
Peak memory 212364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187162377 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.1187162377
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/20.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.2222376399
Short name T446
Test name
Test status
Simulation time 10912739 ps
CPU time 1.46 seconds
Started Sep 03 11:31:12 PM UTC 24
Finished Sep 03 11:31:15 PM UTC 24
Peak memory 211232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222376399 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.2222376399
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/20.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all.744185276
Short name T206
Test name
Test status
Simulation time 463807430 ps
CPU time 62.41 seconds
Started Sep 03 11:31:20 PM UTC 24
Finished Sep 03 11:32:24 PM UTC 24
Peak memory 216220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744185276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.744185276
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/20.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_error.3301461248
Short name T462
Test name
Test status
Simulation time 258569155 ps
CPU time 4.89 seconds
Started Sep 03 11:31:21 PM UTC 24
Finished Sep 03 11:31:27 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301461248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.3301461248
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/20.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.3559589779
Short name T136
Test name
Test status
Simulation time 96551711 ps
CPU time 12.52 seconds
Started Sep 03 11:31:20 PM UTC 24
Finished Sep 03 11:31:33 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559589779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.3559589779
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/20.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.2233029090
Short name T461
Test name
Test status
Simulation time 10241155 ps
CPU time 2.14 seconds
Started Sep 03 11:31:22 PM UTC 24
Finished Sep 03 11:31:26 PM UTC 24
Peak memory 212140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233029090 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.2233029090
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/20.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_unmapped_addr.3686213922
Short name T453
Test name
Test status
Simulation time 362358872 ps
CPU time 2.06 seconds
Started Sep 03 11:31:17 PM UTC 24
Finished Sep 03 11:31:21 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686213922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3686213922
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/20.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device.1166812390
Short name T264
Test name
Test status
Simulation time 4131655285 ps
CPU time 17.76 seconds
Started Sep 03 11:31:27 PM UTC 24
Finished Sep 03 11:31:46 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166812390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.1166812390
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/21.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.562615727
Short name T288
Test name
Test status
Simulation time 263595343306 ps
CPU time 271.33 seconds
Started Sep 03 11:31:27 PM UTC 24
Finished Sep 03 11:36:02 PM UTC 24
Peak memory 214248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562615727 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.562615727
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/21.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.3755333623
Short name T261
Test name
Test status
Simulation time 524623353 ps
CPU time 13.27 seconds
Started Sep 03 11:31:31 PM UTC 24
Finished Sep 03 11:31:46 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755333623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.3755333623
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/21.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_error_random.2263920043
Short name T135
Test name
Test status
Simulation time 21686231 ps
CPU time 2.36 seconds
Started Sep 03 11:31:29 PM UTC 24
Finished Sep 03 11:31:33 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263920043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2263920043
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/21.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random.461842323
Short name T464
Test name
Test status
Simulation time 28584961 ps
CPU time 4.5 seconds
Started Sep 03 11:31:23 PM UTC 24
Finished Sep 03 11:31:29 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461842323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.461842323
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/21.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_large_delays.3834097225
Short name T507
Test name
Test status
Simulation time 39413238800 ps
CPU time 95.14 seconds
Started Sep 03 11:31:26 PM UTC 24
Finished Sep 03 11:33:03 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834097225 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3834097225
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/21.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_slow_rsp.1301609983
Short name T492
Test name
Test status
Simulation time 15662964962 ps
CPU time 65.11 seconds
Started Sep 03 11:31:27 PM UTC 24
Finished Sep 03 11:32:34 PM UTC 24
Peak memory 212456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301609983 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1301609983
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/21.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_zero_delays.906077473
Short name T134
Test name
Test status
Simulation time 53688478 ps
CPU time 5.61 seconds
Started Sep 03 11:31:26 PM UTC 24
Finished Sep 03 11:31:33 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906077473 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.906077473
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/21.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_same_source.3422800973
Short name T139
Test name
Test status
Simulation time 50626982 ps
CPU time 5.55 seconds
Started Sep 03 11:31:28 PM UTC 24
Finished Sep 03 11:31:35 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422800973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3422800973
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/21.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke.171033796
Short name T459
Test name
Test status
Simulation time 11840842 ps
CPU time 1.75 seconds
Started Sep 03 11:31:22 PM UTC 24
Finished Sep 03 11:31:25 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171033796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.171033796
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/21.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_large_delays.656564339
Short name T465
Test name
Test status
Simulation time 5630359732 ps
CPU time 10.29 seconds
Started Sep 03 11:31:23 PM UTC 24
Finished Sep 03 11:31:35 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656564339 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.656564339
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/21.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.880349355
Short name T265
Test name
Test status
Simulation time 2766341939 ps
CPU time 21.21 seconds
Started Sep 03 11:31:23 PM UTC 24
Finished Sep 03 11:31:46 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880349355 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.880349355
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/21.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.3050711910
Short name T458
Test name
Test status
Simulation time 9159910 ps
CPU time 1.43 seconds
Started Sep 03 11:31:22 PM UTC 24
Finished Sep 03 11:31:25 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050711910 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.3050711910
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/21.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all.922643071
Short name T196
Test name
Test status
Simulation time 1668114369 ps
CPU time 43.56 seconds
Started Sep 03 11:31:32 PM UTC 24
Finished Sep 03 11:32:17 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922643071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.922643071
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/21.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_error.2246627538
Short name T475
Test name
Test status
Simulation time 1402355926 ps
CPU time 19.36 seconds
Started Sep 03 11:31:32 PM UTC 24
Finished Sep 03 11:31:53 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246627538 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.2246627538
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/21.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.3203843368
Short name T591
Test name
Test status
Simulation time 4079335210 ps
CPU time 158.11 seconds
Started Sep 03 11:31:32 PM UTC 24
Finished Sep 03 11:34:13 PM UTC 24
Peak memory 218340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203843368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.3203843368
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/21.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.1980783163
Short name T182
Test name
Test status
Simulation time 339931978 ps
CPU time 30.68 seconds
Started Sep 03 11:31:34 PM UTC 24
Finished Sep 03 11:32:06 PM UTC 24
Peak memory 214316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980783163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.1980783163
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/21.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_unmapped_addr.44311541
Short name T257
Test name
Test status
Simulation time 133882697 ps
CPU time 9 seconds
Started Sep 03 11:31:30 PM UTC 24
Finished Sep 03 11:31:40 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44311541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.44311541
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/21.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device.566636873
Short name T260
Test name
Test status
Simulation time 229917008 ps
CPU time 4.57 seconds
Started Sep 03 11:31:39 PM UTC 24
Finished Sep 03 11:31:44 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566636873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.566636873
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/22.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.257078525
Short name T314
Test name
Test status
Simulation time 62601159192 ps
CPU time 448.1 seconds
Started Sep 03 11:31:40 PM UTC 24
Finished Sep 03 11:39:13 PM UTC 24
Peak memory 217944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257078525 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.257078525
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/22.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.1793299905
Short name T470
Test name
Test status
Simulation time 467609617 ps
CPU time 2.99 seconds
Started Sep 03 11:31:44 PM UTC 24
Finished Sep 03 11:31:48 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793299905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.1793299905
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/22.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_error_random.2475921042
Short name T478
Test name
Test status
Simulation time 774218893 ps
CPU time 13.98 seconds
Started Sep 03 11:31:41 PM UTC 24
Finished Sep 03 11:31:56 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475921042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2475921042
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/22.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random.2541036189
Short name T258
Test name
Test status
Simulation time 241634741 ps
CPU time 4.39 seconds
Started Sep 03 11:31:36 PM UTC 24
Finished Sep 03 11:31:42 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541036189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.2541036189
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/22.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_large_delays.2185164273
Short name T605
Test name
Test status
Simulation time 58260816746 ps
CPU time 163.11 seconds
Started Sep 03 11:31:36 PM UTC 24
Finished Sep 03 11:34:22 PM UTC 24
Peak memory 212172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185164273 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2185164273
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/22.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_slow_rsp.292675001
Short name T621
Test name
Test status
Simulation time 70345832347 ps
CPU time 171.86 seconds
Started Sep 03 11:31:37 PM UTC 24
Finished Sep 03 11:34:31 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292675001 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.292675001
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/22.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_zero_delays.4226867944
Short name T262
Test name
Test status
Simulation time 277813836 ps
CPU time 8.23 seconds
Started Sep 03 11:31:36 PM UTC 24
Finished Sep 03 11:31:46 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226867944 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.4226867944
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/22.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_same_source.3769137806
Short name T469
Test name
Test status
Simulation time 227801426 ps
CPU time 4.7 seconds
Started Sep 03 11:31:41 PM UTC 24
Finished Sep 03 11:31:46 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769137806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.3769137806
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/22.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke.2978646100
Short name T466
Test name
Test status
Simulation time 38781201 ps
CPU time 1.36 seconds
Started Sep 03 11:31:34 PM UTC 24
Finished Sep 03 11:31:36 PM UTC 24
Peak memory 211244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978646100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2978646100
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/22.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1040545247
Short name T474
Test name
Test status
Simulation time 9190012643 ps
CPU time 16.23 seconds
Started Sep 03 11:31:35 PM UTC 24
Finished Sep 03 11:31:52 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040545247 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1040545247
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/22.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.180998032
Short name T473
Test name
Test status
Simulation time 1255821569 ps
CPU time 14.02 seconds
Started Sep 03 11:31:36 PM UTC 24
Finished Sep 03 11:31:52 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180998032 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.180998032
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/22.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.3434985652
Short name T467
Test name
Test status
Simulation time 10141902 ps
CPU time 1.69 seconds
Started Sep 03 11:31:35 PM UTC 24
Finished Sep 03 11:31:38 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434985652 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.3434985652
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/22.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all.1543595463
Short name T227
Test name
Test status
Simulation time 6949610970 ps
CPU time 55.71 seconds
Started Sep 03 11:31:45 PM UTC 24
Finished Sep 03 11:32:42 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543595463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.1543595463
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/22.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_error.3200576615
Short name T237
Test name
Test status
Simulation time 2678645331 ps
CPU time 43.72 seconds
Started Sep 03 11:31:46 PM UTC 24
Finished Sep 03 11:32:32 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200576615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3200576615
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/22.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.2053592863
Short name T563
Test name
Test status
Simulation time 1148675600 ps
CPU time 124.09 seconds
Started Sep 03 11:31:46 PM UTC 24
Finished Sep 03 11:33:53 PM UTC 24
Peak memory 216228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053592863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.2053592863
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/22.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.428616957
Short name T486
Test name
Test status
Simulation time 7614402937 ps
CPU time 36.93 seconds
Started Sep 03 11:31:48 PM UTC 24
Finished Sep 03 11:32:26 PM UTC 24
Peak memory 214316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428616957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.428616957
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/22.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_unmapped_addr.603397696
Short name T184
Test name
Test status
Simulation time 2134831451 ps
CPU time 12.95 seconds
Started Sep 03 11:31:43 PM UTC 24
Finished Sep 03 11:31:57 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603397696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.603397696
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/22.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device.1689212261
Short name T119
Test name
Test status
Simulation time 1579943571 ps
CPU time 11.37 seconds
Started Sep 03 11:31:53 PM UTC 24
Finished Sep 03 11:32:06 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689212261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.1689212261
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/23.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1484039022
Short name T125
Test name
Test status
Simulation time 4818701651 ps
CPU time 13 seconds
Started Sep 03 11:31:57 PM UTC 24
Finished Sep 03 11:32:11 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484039022 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.1484039022
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/23.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_error_random.3089929376
Short name T178
Test name
Test status
Simulation time 71548587 ps
CPU time 8.82 seconds
Started Sep 03 11:31:55 PM UTC 24
Finished Sep 03 11:32:05 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089929376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3089929376
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/23.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random.2915301365
Short name T477
Test name
Test status
Simulation time 49332394 ps
CPU time 5.92 seconds
Started Sep 03 11:31:49 PM UTC 24
Finished Sep 03 11:31:56 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915301365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.2915301365
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/23.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_large_delays.4140142158
Short name T519
Test name
Test status
Simulation time 25233062026 ps
CPU time 78.83 seconds
Started Sep 03 11:31:51 PM UTC 24
Finished Sep 03 11:33:12 PM UTC 24
Peak memory 212456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140142158 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.4140142158
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/23.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_slow_rsp.1156575808
Short name T549
Test name
Test status
Simulation time 19610497492 ps
CPU time 106.44 seconds
Started Sep 03 11:31:52 PM UTC 24
Finished Sep 03 11:33:41 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156575808 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.1156575808
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/23.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_zero_delays.3622360770
Short name T479
Test name
Test status
Simulation time 70848511 ps
CPU time 5.09 seconds
Started Sep 03 11:31:51 PM UTC 24
Finished Sep 03 11:31:57 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622360770 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.3622360770
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/23.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_same_source.667758654
Short name T480
Test name
Test status
Simulation time 108985467 ps
CPU time 4.49 seconds
Started Sep 03 11:31:55 PM UTC 24
Finished Sep 03 11:32:00 PM UTC 24
Peak memory 212180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667758654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.667758654
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/23.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke.4107338300
Short name T471
Test name
Test status
Simulation time 21023843 ps
CPU time 1.55 seconds
Started Sep 03 11:31:48 PM UTC 24
Finished Sep 03 11:31:50 PM UTC 24
Peak memory 211244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107338300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.4107338300
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/23.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_large_delays.2667005201
Short name T177
Test name
Test status
Simulation time 2098898805 ps
CPU time 13.28 seconds
Started Sep 03 11:31:48 PM UTC 24
Finished Sep 03 11:32:02 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667005201 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2667005201
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/23.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.4035577909
Short name T32
Test name
Test status
Simulation time 728291040 ps
CPU time 8.97 seconds
Started Sep 03 11:31:48 PM UTC 24
Finished Sep 03 11:31:58 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035577909 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.4035577909
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/23.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.3235748785
Short name T472
Test name
Test status
Simulation time 10620094 ps
CPU time 1.73 seconds
Started Sep 03 11:31:48 PM UTC 24
Finished Sep 03 11:31:51 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235748785 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.3235748785
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/23.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all.827512075
Short name T159
Test name
Test status
Simulation time 9991072608 ps
CPU time 50.04 seconds
Started Sep 03 11:31:57 PM UTC 24
Finished Sep 03 11:32:49 PM UTC 24
Peak memory 214240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827512075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.827512075
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/23.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_error.995141598
Short name T201
Test name
Test status
Simulation time 6097120165 ps
CPU time 23.98 seconds
Started Sep 03 11:31:58 PM UTC 24
Finished Sep 03 11:32:23 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995141598 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.995141598
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/23.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.3673721665
Short name T540
Test name
Test status
Simulation time 8038802106 ps
CPU time 92.93 seconds
Started Sep 03 11:31:58 PM UTC 24
Finished Sep 03 11:33:33 PM UTC 24
Peak memory 216292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673721665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.3673721665
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/23.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.3878421994
Short name T120
Test name
Test status
Simulation time 19160449 ps
CPU time 5.68 seconds
Started Sep 03 11:31:59 PM UTC 24
Finished Sep 03 11:32:06 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878421994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.3878421994
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/23.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_unmapped_addr.2596890321
Short name T122
Test name
Test status
Simulation time 1880365944 ps
CPU time 12.47 seconds
Started Sep 03 11:31:55 PM UTC 24
Finished Sep 03 11:32:08 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596890321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2596890321
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/23.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device.1346291866
Short name T318
Test name
Test status
Simulation time 1068273217 ps
CPU time 15.56 seconds
Started Sep 03 11:32:08 PM UTC 24
Finished Sep 03 11:32:25 PM UTC 24
Peak memory 212140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346291866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.1346291866
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/24.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.2605202338
Short name T482
Test name
Test status
Simulation time 17773274 ps
CPU time 2.35 seconds
Started Sep 03 11:32:11 PM UTC 24
Finished Sep 03 11:32:14 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605202338 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.2605202338
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/24.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_error_random.247930745
Short name T484
Test name
Test status
Simulation time 122841615 ps
CPU time 7.24 seconds
Started Sep 03 11:32:08 PM UTC 24
Finished Sep 03 11:32:16 PM UTC 24
Peak memory 212260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247930745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.247930745
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/24.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random.921039026
Short name T33
Test name
Test status
Simulation time 1592583864 ps
CPU time 20.52 seconds
Started Sep 03 11:32:07 PM UTC 24
Finished Sep 03 11:32:28 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921039026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.921039026
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/24.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_large_delays.3776178991
Short name T567
Test name
Test status
Simulation time 21051468619 ps
CPU time 107.04 seconds
Started Sep 03 11:32:07 PM UTC 24
Finished Sep 03 11:33:56 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776178991 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3776178991
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/24.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_slow_rsp.2859342674
Short name T590
Test name
Test status
Simulation time 24562206437 ps
CPU time 123.89 seconds
Started Sep 03 11:32:07 PM UTC 24
Finished Sep 03 11:34:13 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859342674 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2859342674
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/24.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_zero_delays.1391788222
Short name T481
Test name
Test status
Simulation time 72906902 ps
CPU time 6.22 seconds
Started Sep 03 11:32:07 PM UTC 24
Finished Sep 03 11:32:14 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391788222 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.1391788222
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/24.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_same_source.3477433438
Short name T483
Test name
Test status
Simulation time 44219813 ps
CPU time 6.27 seconds
Started Sep 03 11:32:08 PM UTC 24
Finished Sep 03 11:32:15 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477433438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3477433438
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/24.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke.2197043324
Short name T179
Test name
Test status
Simulation time 130083670 ps
CPU time 2.38 seconds
Started Sep 03 11:32:01 PM UTC 24
Finished Sep 03 11:32:05 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197043324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2197043324
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/24.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_large_delays.4018600966
Short name T485
Test name
Test status
Simulation time 3539449350 ps
CPU time 11.74 seconds
Started Sep 03 11:32:04 PM UTC 24
Finished Sep 03 11:32:16 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018600966 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.4018600966
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/24.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.767705883
Short name T200
Test name
Test status
Simulation time 1254611513 ps
CPU time 11.74 seconds
Started Sep 03 11:32:06 PM UTC 24
Finished Sep 03 11:32:19 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767705883 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.767705883
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/24.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.2720249958
Short name T121
Test name
Test status
Simulation time 9332237 ps
CPU time 1.56 seconds
Started Sep 03 11:32:04 PM UTC 24
Finished Sep 03 11:32:06 PM UTC 24
Peak memory 211124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720249958 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.2720249958
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/24.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all.3766598729
Short name T224
Test name
Test status
Simulation time 1789630329 ps
CPU time 28.72 seconds
Started Sep 03 11:32:11 PM UTC 24
Finished Sep 03 11:32:41 PM UTC 24
Peak memory 214376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766598729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.3766598729
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/24.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_error.537143796
Short name T487
Test name
Test status
Simulation time 149242850 ps
CPU time 13.9 seconds
Started Sep 03 11:32:12 PM UTC 24
Finished Sep 03 11:32:27 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537143796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.537143796
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/24.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.1799782598
Short name T574
Test name
Test status
Simulation time 2801921561 ps
CPU time 105.6 seconds
Started Sep 03 11:32:12 PM UTC 24
Finished Sep 03 11:34:00 PM UTC 24
Peak memory 218536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799782598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.1799782598
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/24.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.1058212958
Short name T503
Test name
Test status
Simulation time 313343569 ps
CPU time 45.3 seconds
Started Sep 03 11:32:14 PM UTC 24
Finished Sep 03 11:33:01 PM UTC 24
Peak memory 214188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058212958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.1058212958
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/24.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_unmapped_addr.4278517886
Short name T127
Test name
Test status
Simulation time 28614181 ps
CPU time 3.12 seconds
Started Sep 03 11:32:09 PM UTC 24
Finished Sep 03 11:32:13 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278517886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.4278517886
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/24.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device.836492330
Short name T98
Test name
Test status
Simulation time 1030533506 ps
CPU time 16.69 seconds
Started Sep 03 11:32:20 PM UTC 24
Finished Sep 03 11:32:38 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836492330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.836492330
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/25.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.1338011614
Short name T281
Test name
Test status
Simulation time 58607325005 ps
CPU time 227.6 seconds
Started Sep 03 11:32:24 PM UTC 24
Finished Sep 03 11:36:15 PM UTC 24
Peak memory 214500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338011614 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.1338011614
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/25.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.735672615
Short name T232
Test name
Test status
Simulation time 38169034 ps
CPU time 3.51 seconds
Started Sep 03 11:32:25 PM UTC 24
Finished Sep 03 11:32:29 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735672615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.735672615
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/25.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_error_random.2353599928
Short name T233
Test name
Test status
Simulation time 35070471 ps
CPU time 4.68 seconds
Started Sep 03 11:32:25 PM UTC 24
Finished Sep 03 11:32:30 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353599928 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2353599928
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/25.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random.2747388132
Short name T203
Test name
Test status
Simulation time 27366217 ps
CPU time 4.82 seconds
Started Sep 03 11:32:18 PM UTC 24
Finished Sep 03 11:32:23 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747388132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.2747388132
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/25.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_large_delays.417706674
Short name T622
Test name
Test status
Simulation time 54676115523 ps
CPU time 130.71 seconds
Started Sep 03 11:32:19 PM UTC 24
Finished Sep 03 11:34:32 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417706674 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.417706674
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/25.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_slow_rsp.1544782287
Short name T238
Test name
Test status
Simulation time 3889182748 ps
CPU time 11.81 seconds
Started Sep 03 11:32:19 PM UTC 24
Finished Sep 03 11:32:32 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544782287 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1544782287
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/25.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_zero_delays.4267198808
Short name T488
Test name
Test status
Simulation time 74805265 ps
CPU time 7.51 seconds
Started Sep 03 11:32:19 PM UTC 24
Finished Sep 03 11:32:27 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267198808 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.4267198808
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/25.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_same_source.642709257
Short name T491
Test name
Test status
Simulation time 1011941484 ps
CPU time 7.79 seconds
Started Sep 03 11:32:25 PM UTC 24
Finished Sep 03 11:32:33 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642709257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.642709257
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/25.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke.2372177479
Short name T199
Test name
Test status
Simulation time 17130323 ps
CPU time 1.63 seconds
Started Sep 03 11:32:15 PM UTC 24
Finished Sep 03 11:32:18 PM UTC 24
Peak memory 211228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372177479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.2372177479
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/25.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_large_delays.960970628
Short name T489
Test name
Test status
Simulation time 8069828867 ps
CPU time 10.32 seconds
Started Sep 03 11:32:16 PM UTC 24
Finished Sep 03 11:32:28 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960970628 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.960970628
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/25.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.3061040779
Short name T493
Test name
Test status
Simulation time 2166692704 ps
CPU time 15.59 seconds
Started Sep 03 11:32:18 PM UTC 24
Finished Sep 03 11:32:34 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061040779 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3061040779
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/25.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.342840943
Short name T198
Test name
Test status
Simulation time 8594860 ps
CPU time 1.63 seconds
Started Sep 03 11:32:15 PM UTC 24
Finished Sep 03 11:32:18 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342840943 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.342840943
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/25.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all.93893715
Short name T499
Test name
Test status
Simulation time 1617972248 ps
CPU time 30.19 seconds
Started Sep 03 11:32:25 PM UTC 24
Finished Sep 03 11:32:56 PM UTC 24
Peak memory 212264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93893715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-si
m-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.93893715
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/25.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_error.1823049456
Short name T223
Test name
Test status
Simulation time 115743325 ps
CPU time 11.58 seconds
Started Sep 03 11:32:27 PM UTC 24
Finished Sep 03 11:32:40 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823049456 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1823049456
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/25.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.2707740245
Short name T221
Test name
Test status
Simulation time 14482658 ps
CPU time 11.64 seconds
Started Sep 03 11:32:26 PM UTC 24
Finished Sep 03 11:32:39 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707740245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.2707740245
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/25.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.3737630745
Short name T535
Test name
Test status
Simulation time 9758888788 ps
CPU time 59.46 seconds
Started Sep 03 11:32:28 PM UTC 24
Finished Sep 03 11:33:29 PM UTC 24
Peak memory 214572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737630745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.3737630745
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/25.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_unmapped_addr.3706925451
Short name T231
Test name
Test status
Simulation time 887875471 ps
CPU time 3.57 seconds
Started Sep 03 11:32:25 PM UTC 24
Finished Sep 03 11:32:29 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706925451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3706925451
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/25.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device.3396617628
Short name T153
Test name
Test status
Simulation time 326209268 ps
CPU time 10.73 seconds
Started Sep 03 11:32:32 PM UTC 24
Finished Sep 03 11:32:44 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396617628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.3396617628
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/26.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.4108759161
Short name T108
Test name
Test status
Simulation time 57110677890 ps
CPU time 350.69 seconds
Started Sep 03 11:32:32 PM UTC 24
Finished Sep 03 11:38:27 PM UTC 24
Peak memory 216000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108759161 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.4108759161
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/26.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.516062593
Short name T157
Test name
Test status
Simulation time 1635635330 ps
CPU time 12.76 seconds
Started Sep 03 11:32:34 PM UTC 24
Finished Sep 03 11:32:48 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516062593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.516062593
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/26.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_error_random.2750117972
Short name T494
Test name
Test status
Simulation time 560822303 ps
CPU time 10.39 seconds
Started Sep 03 11:32:33 PM UTC 24
Finished Sep 03 11:32:44 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750117972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2750117972
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/26.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random.3906125836
Short name T160
Test name
Test status
Simulation time 2403021574 ps
CPU time 16.8 seconds
Started Sep 03 11:32:31 PM UTC 24
Finished Sep 03 11:32:49 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906125836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.3906125836
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/26.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_large_delays.600047009
Short name T515
Test name
Test status
Simulation time 10244220115 ps
CPU time 37.14 seconds
Started Sep 03 11:32:31 PM UTC 24
Finished Sep 03 11:33:09 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600047009 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.600047009
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/26.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_slow_rsp.967656155
Short name T610
Test name
Test status
Simulation time 41372317388 ps
CPU time 112.16 seconds
Started Sep 03 11:32:31 PM UTC 24
Finished Sep 03 11:34:25 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967656155 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.967656155
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/26.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_zero_delays.3598203718
Short name T222
Test name
Test status
Simulation time 63877552 ps
CPU time 7.1 seconds
Started Sep 03 11:32:31 PM UTC 24
Finished Sep 03 11:32:39 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598203718 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.3598203718
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/26.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_same_source.1355939737
Short name T158
Test name
Test status
Simulation time 940030576 ps
CPU time 14.21 seconds
Started Sep 03 11:32:33 PM UTC 24
Finished Sep 03 11:32:48 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355939737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.1355939737
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/26.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke.862094752
Short name T236
Test name
Test status
Simulation time 99416561 ps
CPU time 2.19 seconds
Started Sep 03 11:32:28 PM UTC 24
Finished Sep 03 11:32:31 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862094752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.862094752
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/26.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_large_delays.753553042
Short name T155
Test name
Test status
Simulation time 3983845175 ps
CPU time 15.51 seconds
Started Sep 03 11:32:29 PM UTC 24
Finished Sep 03 11:32:46 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753553042 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.753553042
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/26.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.1411906901
Short name T175
Test name
Test status
Simulation time 3065829461 ps
CPU time 18.27 seconds
Started Sep 03 11:32:30 PM UTC 24
Finished Sep 03 11:32:49 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411906901 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1411906901
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/26.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.3834537855
Short name T490
Test name
Test status
Simulation time 11170313 ps
CPU time 1.54 seconds
Started Sep 03 11:32:29 PM UTC 24
Finished Sep 03 11:32:32 PM UTC 24
Peak memory 211232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834537855 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.3834537855
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/26.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all.3343122958
Short name T522
Test name
Test status
Simulation time 356532540 ps
CPU time 37.84 seconds
Started Sep 03 11:32:35 PM UTC 24
Finished Sep 03 11:33:14 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343122958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3343122958
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/26.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_error.2713005243
Short name T569
Test name
Test status
Simulation time 3672694007 ps
CPU time 75.24 seconds
Started Sep 03 11:32:39 PM UTC 24
Finished Sep 03 11:33:56 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713005243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.2713005243
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/26.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.2924125484
Short name T558
Test name
Test status
Simulation time 3790393265 ps
CPU time 69.28 seconds
Started Sep 03 11:32:39 PM UTC 24
Finished Sep 03 11:33:50 PM UTC 24
Peak memory 216556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924125484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.2924125484
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/26.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_unmapped_addr.639046939
Short name T226
Test name
Test status
Simulation time 234403348 ps
CPU time 8.09 seconds
Started Sep 03 11:32:33 PM UTC 24
Finished Sep 03 11:32:42 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639046939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.639046939
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/26.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device.1521159338
Short name T512
Test name
Test status
Simulation time 3441957296 ps
CPU time 21.11 seconds
Started Sep 03 11:32:44 PM UTC 24
Finished Sep 03 11:33:07 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521159338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.1521159338
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/27.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.1140362406
Short name T240
Test name
Test status
Simulation time 50197462716 ps
CPU time 75.96 seconds
Started Sep 03 11:32:46 PM UTC 24
Finished Sep 03 11:34:04 PM UTC 24
Peak memory 212144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140362406 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.1140362406
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/27.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.2528553920
Short name T504
Test name
Test status
Simulation time 2307507747 ps
CPU time 12.33 seconds
Started Sep 03 11:32:47 PM UTC 24
Finished Sep 03 11:33:01 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528553920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.2528553920
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/27.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_error_random.1643297399
Short name T501
Test name
Test status
Simulation time 820310389 ps
CPU time 10.1 seconds
Started Sep 03 11:32:46 PM UTC 24
Finished Sep 03 11:32:57 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643297399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.1643297399
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/27.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random.2697668871
Short name T498
Test name
Test status
Simulation time 614799586 ps
CPU time 11.32 seconds
Started Sep 03 11:32:43 PM UTC 24
Finished Sep 03 11:32:56 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697668871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.2697668871
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/27.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_large_delays.215143437
Short name T734
Test name
Test status
Simulation time 164487919928 ps
CPU time 183.51 seconds
Started Sep 03 11:32:44 PM UTC 24
Finished Sep 03 11:35:51 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215143437 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.215143437
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/27.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_slow_rsp.1514909224
Short name T128
Test name
Test status
Simulation time 22676399813 ps
CPU time 146.99 seconds
Started Sep 03 11:32:44 PM UTC 24
Finished Sep 03 11:35:14 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514909224 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.1514909224
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/27.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_zero_delays.4219260198
Short name T156
Test name
Test status
Simulation time 35437248 ps
CPU time 2.03 seconds
Started Sep 03 11:32:43 PM UTC 24
Finished Sep 03 11:32:46 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219260198 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.4219260198
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/27.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_same_source.4033139223
Short name T509
Test name
Test status
Simulation time 4119819408 ps
CPU time 16.58 seconds
Started Sep 03 11:32:46 PM UTC 24
Finished Sep 03 11:33:04 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033139223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.4033139223
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/27.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke.597066964
Short name T228
Test name
Test status
Simulation time 8265166 ps
CPU time 1.39 seconds
Started Sep 03 11:32:41 PM UTC 24
Finished Sep 03 11:32:43 PM UTC 24
Peak memory 211224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597066964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.597066964
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/27.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_large_delays.444327441
Short name T34
Test name
Test status
Simulation time 1569108749 ps
CPU time 10.42 seconds
Started Sep 03 11:32:42 PM UTC 24
Finished Sep 03 11:32:53 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444327441 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.444327441
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/27.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.893015993
Short name T500
Test name
Test status
Simulation time 14831568519 ps
CPU time 12.93 seconds
Started Sep 03 11:32:43 PM UTC 24
Finished Sep 03 11:32:57 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893015993 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.893015993
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/27.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.3448817582
Short name T229
Test name
Test status
Simulation time 8597531 ps
CPU time 1.39 seconds
Started Sep 03 11:32:41 PM UTC 24
Finished Sep 03 11:32:43 PM UTC 24
Peak memory 211112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448817582 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.3448817582
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/27.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all.730235360
Short name T518
Test name
Test status
Simulation time 1209215793 ps
CPU time 21.99 seconds
Started Sep 03 11:32:48 PM UTC 24
Finished Sep 03 11:33:12 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730235360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.730235360
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/27.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_error.1408668348
Short name T568
Test name
Test status
Simulation time 5036341400 ps
CPU time 66.26 seconds
Started Sep 03 11:32:48 PM UTC 24
Finished Sep 03 11:33:56 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408668348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.1408668348
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/27.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.3759419088
Short name T532
Test name
Test status
Simulation time 374410952 ps
CPU time 31.55 seconds
Started Sep 03 11:32:50 PM UTC 24
Finished Sep 03 11:33:23 PM UTC 24
Peak memory 214188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759419088 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.3759419088
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/27.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_unmapped_addr.668162409
Short name T497
Test name
Test status
Simulation time 206221422 ps
CPU time 5.32 seconds
Started Sep 03 11:32:47 PM UTC 24
Finished Sep 03 11:32:54 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668162409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.668162409
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/27.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device.2647096951
Short name T511
Test name
Test status
Simulation time 33065697 ps
CPU time 7.04 seconds
Started Sep 03 11:32:58 PM UTC 24
Finished Sep 03 11:33:06 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647096951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.2647096951
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/28.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.4205046200
Short name T106
Test name
Test status
Simulation time 78069609506 ps
CPU time 263.91 seconds
Started Sep 03 11:32:59 PM UTC 24
Finished Sep 03 11:37:26 PM UTC 24
Peak memory 214436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205046200 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.4205046200
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/28.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.1262233059
Short name T517
Test name
Test status
Simulation time 1140511069 ps
CPU time 6.87 seconds
Started Sep 03 11:33:03 PM UTC 24
Finished Sep 03 11:33:11 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262233059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.1262233059
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/28.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_error_random.516881106
Short name T520
Test name
Test status
Simulation time 478345714 ps
CPU time 8.62 seconds
Started Sep 03 11:33:02 PM UTC 24
Finished Sep 03 11:33:12 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516881106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.516881106
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/28.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random.2936371509
Short name T502
Test name
Test status
Simulation time 32336009 ps
CPU time 3.18 seconds
Started Sep 03 11:32:54 PM UTC 24
Finished Sep 03 11:32:59 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936371509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.2936371509
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/28.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_large_delays.811577281
Short name T114
Test name
Test status
Simulation time 59620576012 ps
CPU time 99.08 seconds
Started Sep 03 11:32:56 PM UTC 24
Finished Sep 03 11:34:38 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811577281 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.811577281
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/28.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_slow_rsp.606067032
Short name T618
Test name
Test status
Simulation time 47948934446 ps
CPU time 90.86 seconds
Started Sep 03 11:32:57 PM UTC 24
Finished Sep 03 11:34:30 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606067032 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.606067032
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/28.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_zero_delays.2607650865
Short name T508
Test name
Test status
Simulation time 103100531 ps
CPU time 7.19 seconds
Started Sep 03 11:32:55 PM UTC 24
Finished Sep 03 11:33:03 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607650865 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.2607650865
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/28.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_same_source.2294120584
Short name T513
Test name
Test status
Simulation time 108250527 ps
CPU time 6.66 seconds
Started Sep 03 11:33:00 PM UTC 24
Finished Sep 03 11:33:08 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294120584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.2294120584
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/28.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke.1060874262
Short name T495
Test name
Test status
Simulation time 10802290 ps
CPU time 1.27 seconds
Started Sep 03 11:32:50 PM UTC 24
Finished Sep 03 11:32:52 PM UTC 24
Peak memory 211140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060874262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.1060874262
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/28.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_large_delays.3840252710
Short name T510
Test name
Test status
Simulation time 1358957936 ps
CPU time 10.49 seconds
Started Sep 03 11:32:53 PM UTC 24
Finished Sep 03 11:33:05 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840252710 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.3840252710
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/28.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.1018775194
Short name T505
Test name
Test status
Simulation time 796738104 ps
CPU time 8 seconds
Started Sep 03 11:32:53 PM UTC 24
Finished Sep 03 11:33:03 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018775194 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.1018775194
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/28.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.3932603357
Short name T496
Test name
Test status
Simulation time 23522065 ps
CPU time 1.51 seconds
Started Sep 03 11:32:50 PM UTC 24
Finished Sep 03 11:32:52 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932603357 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.3932603357
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/28.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all.999008852
Short name T582
Test name
Test status
Simulation time 15102034152 ps
CPU time 60.31 seconds
Started Sep 03 11:33:04 PM UTC 24
Finished Sep 03 11:34:06 PM UTC 24
Peak memory 214372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999008852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.999008852
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/28.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_error.2118992384
Short name T541
Test name
Test status
Simulation time 468019887 ps
CPU time 28.16 seconds
Started Sep 03 11:33:05 PM UTC 24
Finished Sep 03 11:33:34 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118992384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2118992384
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/28.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.3057934118
Short name T102
Test name
Test status
Simulation time 616201963 ps
CPU time 73.71 seconds
Started Sep 03 11:33:04 PM UTC 24
Finished Sep 03 11:34:20 PM UTC 24
Peak memory 214508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057934118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.3057934118
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/28.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.827223414
Short name T615
Test name
Test status
Simulation time 4705768815 ps
CPU time 81.35 seconds
Started Sep 03 11:33:05 PM UTC 24
Finished Sep 03 11:34:29 PM UTC 24
Peak memory 216296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827223414 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.827223414
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/28.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_unmapped_addr.1922509073
Short name T514
Test name
Test status
Simulation time 95618184 ps
CPU time 5.41 seconds
Started Sep 03 11:33:02 PM UTC 24
Finished Sep 03 11:33:09 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922509073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.1922509073
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/28.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device.39281164
Short name T154
Test name
Test status
Simulation time 370964299 ps
CPU time 6 seconds
Started Sep 03 11:33:11 PM UTC 24
Finished Sep 03 11:33:18 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39281164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.39281164
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/29.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.3638132040
Short name T317
Test name
Test status
Simulation time 25340925847 ps
CPU time 55.48 seconds
Started Sep 03 11:33:12 PM UTC 24
Finished Sep 03 11:34:09 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638132040 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.3638132040
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/29.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.1374911676
Short name T534
Test name
Test status
Simulation time 523661102 ps
CPU time 13.54 seconds
Started Sep 03 11:33:13 PM UTC 24
Finished Sep 03 11:33:28 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374911676 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.1374911676
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/29.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_error_random.3230511183
Short name T539
Test name
Test status
Simulation time 1723663211 ps
CPU time 17.85 seconds
Started Sep 03 11:33:13 PM UTC 24
Finished Sep 03 11:33:32 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230511183 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3230511183
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/29.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random.624892588
Short name T527
Test name
Test status
Simulation time 341760693 ps
CPU time 6.05 seconds
Started Sep 03 11:33:09 PM UTC 24
Finished Sep 03 11:33:17 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624892588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.624892588
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/29.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_large_delays.3566694603
Short name T716
Test name
Test status
Simulation time 36257009994 ps
CPU time 143.37 seconds
Started Sep 03 11:33:09 PM UTC 24
Finished Sep 03 11:35:35 PM UTC 24
Peak memory 212264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566694603 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.3566694603
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/29.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_slow_rsp.822105460
Short name T255
Test name
Test status
Simulation time 35631690504 ps
CPU time 64.58 seconds
Started Sep 03 11:33:11 PM UTC 24
Finished Sep 03 11:34:17 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822105460 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.822105460
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/29.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_zero_delays.558030822
Short name T529
Test name
Test status
Simulation time 260249099 ps
CPU time 8.46 seconds
Started Sep 03 11:33:09 PM UTC 24
Finished Sep 03 11:33:19 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558030822 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.558030822
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/29.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_same_source.1151034280
Short name T526
Test name
Test status
Simulation time 13287927 ps
CPU time 2.26 seconds
Started Sep 03 11:33:13 PM UTC 24
Finished Sep 03 11:33:16 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151034280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1151034280
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/29.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke.2752275239
Short name T35
Test name
Test status
Simulation time 17642994 ps
CPU time 1.54 seconds
Started Sep 03 11:33:06 PM UTC 24
Finished Sep 03 11:33:08 PM UTC 24
Peak memory 211140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752275239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2752275239
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/29.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_large_delays.525201254
Short name T531
Test name
Test status
Simulation time 1896141682 ps
CPU time 12.62 seconds
Started Sep 03 11:33:08 PM UTC 24
Finished Sep 03 11:33:22 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525201254 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.525201254
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/29.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.368469221
Short name T523
Test name
Test status
Simulation time 1203821911 ps
CPU time 6.01 seconds
Started Sep 03 11:33:08 PM UTC 24
Finished Sep 03 11:33:16 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368469221 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.368469221
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/29.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.194444261
Short name T516
Test name
Test status
Simulation time 37283192 ps
CPU time 1.74 seconds
Started Sep 03 11:33:07 PM UTC 24
Finished Sep 03 11:33:10 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194444261 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.194444261
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/29.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all.1839113148
Short name T627
Test name
Test status
Simulation time 8280669309 ps
CPU time 77.15 seconds
Started Sep 03 11:33:15 PM UTC 24
Finished Sep 03 11:34:34 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839113148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.1839113148
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/29.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_error.734214008
Short name T601
Test name
Test status
Simulation time 5652593158 ps
CPU time 58.96 seconds
Started Sep 03 11:33:17 PM UTC 24
Finished Sep 03 11:34:17 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734214008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.734214008
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/29.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.2201571366
Short name T547
Test name
Test status
Simulation time 143639970 ps
CPU time 21.76 seconds
Started Sep 03 11:33:16 PM UTC 24
Finished Sep 03 11:33:40 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201571366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.2201571366
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/29.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.3969997143
Short name T551
Test name
Test status
Simulation time 205991410 ps
CPU time 23.74 seconds
Started Sep 03 11:33:18 PM UTC 24
Finished Sep 03 11:33:43 PM UTC 24
Peak memory 214188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969997143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.3969997143
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/29.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_unmapped_addr.1179458434
Short name T533
Test name
Test status
Simulation time 2335184444 ps
CPU time 13.25 seconds
Started Sep 03 11:33:13 PM UTC 24
Finished Sep 03 11:33:28 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179458434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.1179458434
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/29.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device.1138314892
Short name T81
Test name
Test status
Simulation time 30388714 ps
CPU time 5.1 seconds
Started Sep 03 11:28:23 PM UTC 24
Finished Sep 03 11:28:29 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138314892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.1138314892
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/3.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.2240375672
Short name T67
Test name
Test status
Simulation time 36320722952 ps
CPU time 48.23 seconds
Started Sep 03 11:28:23 PM UTC 24
Finished Sep 03 11:29:13 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240375672 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.2240375672
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/3.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.3887580087
Short name T277
Test name
Test status
Simulation time 2142555281 ps
CPU time 8.52 seconds
Started Sep 03 11:28:23 PM UTC 24
Finished Sep 03 11:28:33 PM UTC 24
Peak memory 212452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887580087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.3887580087
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/3.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_error_random.324046493
Short name T79
Test name
Test status
Simulation time 41280727 ps
CPU time 3.57 seconds
Started Sep 03 11:28:23 PM UTC 24
Finished Sep 03 11:28:28 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324046493 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.324046493
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/3.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_large_delays.658828797
Short name T451
Test name
Test status
Simulation time 33625620006 ps
CPU time 173.46 seconds
Started Sep 03 11:28:23 PM UTC 24
Finished Sep 03 11:31:19 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658828797 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.658828797
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/3.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_slow_rsp.1125181145
Short name T267
Test name
Test status
Simulation time 34829965970 ps
CPU time 113.44 seconds
Started Sep 03 11:28:23 PM UTC 24
Finished Sep 03 11:30:18 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125181145 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.1125181145
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/3.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_zero_delays.3306722034
Short name T46
Test name
Test status
Simulation time 27551408 ps
CPU time 3.5 seconds
Started Sep 03 11:28:23 PM UTC 24
Finished Sep 03 11:28:27 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306722034 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.3306722034
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/3.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_same_source.2325406109
Short name T82
Test name
Test status
Simulation time 2474693002 ps
CPU time 7.95 seconds
Started Sep 03 11:28:23 PM UTC 24
Finished Sep 03 11:28:32 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325406109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2325406109
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/3.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke.3811295740
Short name T43
Test name
Test status
Simulation time 10827764 ps
CPU time 1.28 seconds
Started Sep 03 11:28:19 PM UTC 24
Finished Sep 03 11:28:22 PM UTC 24
Peak memory 211140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811295740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3811295740
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/3.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_large_delays.1029982440
Short name T345
Test name
Test status
Simulation time 11433314511 ps
CPU time 12.01 seconds
Started Sep 03 11:28:21 PM UTC 24
Finished Sep 03 11:28:34 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029982440 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.1029982440
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/3.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1683812429
Short name T276
Test name
Test status
Simulation time 2150391602 ps
CPU time 10.66 seconds
Started Sep 03 11:28:21 PM UTC 24
Finished Sep 03 11:28:33 PM UTC 24
Peak memory 212264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683812429 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1683812429
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/3.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.3923924086
Short name T42
Test name
Test status
Simulation time 11030375 ps
CPU time 1.23 seconds
Started Sep 03 11:28:20 PM UTC 24
Finished Sep 03 11:28:22 PM UTC 24
Peak memory 211128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923924086 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.3923924086
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/3.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all.433148217
Short name T230
Test name
Test status
Simulation time 185287203 ps
CPU time 22.23 seconds
Started Sep 03 11:28:24 PM UTC 24
Finished Sep 03 11:28:48 PM UTC 24
Peak memory 214372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433148217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.433148217
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/3.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_error.4241434493
Short name T252
Test name
Test status
Simulation time 7217339044 ps
CPU time 71.62 seconds
Started Sep 03 11:28:24 PM UTC 24
Finished Sep 03 11:29:38 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241434493 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.4241434493
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/3.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.3038691117
Short name T180
Test name
Test status
Simulation time 1290944905 ps
CPU time 217.23 seconds
Started Sep 03 11:28:24 PM UTC 24
Finished Sep 03 11:32:05 PM UTC 24
Peak memory 218280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038691117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.3038691117
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/3.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.3500466134
Short name T8
Test name
Test status
Simulation time 682678584 ps
CPU time 112.01 seconds
Started Sep 03 11:28:24 PM UTC 24
Finished Sep 03 11:30:19 PM UTC 24
Peak memory 216232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500466134 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.3500466134
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/3.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_unmapped_addr.1438141008
Short name T56
Test name
Test status
Simulation time 542080309 ps
CPU time 8.07 seconds
Started Sep 03 11:28:23 PM UTC 24
Finished Sep 03 11:28:32 PM UTC 24
Peak memory 211944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438141008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.1438141008
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/3.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device.1290377011
Short name T100
Test name
Test status
Simulation time 2770560105 ps
CPU time 7.55 seconds
Started Sep 03 11:33:24 PM UTC 24
Finished Sep 03 11:33:32 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290377011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.1290377011
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/30.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.2379018707
Short name T312
Test name
Test status
Simulation time 50053555929 ps
CPU time 164.17 seconds
Started Sep 03 11:33:28 PM UTC 24
Finished Sep 03 11:36:15 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379018707 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.2379018707
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/30.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.2060025803
Short name T543
Test name
Test status
Simulation time 42123996 ps
CPU time 4.44 seconds
Started Sep 03 11:33:31 PM UTC 24
Finished Sep 03 11:33:36 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060025803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.2060025803
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/30.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_error_random.1969198398
Short name T553
Test name
Test status
Simulation time 1247135812 ps
CPU time 13.67 seconds
Started Sep 03 11:33:29 PM UTC 24
Finished Sep 03 11:33:44 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969198398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.1969198398
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/30.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random.446672123
Short name T548
Test name
Test status
Simulation time 744466095 ps
CPU time 16.91 seconds
Started Sep 03 11:33:21 PM UTC 24
Finished Sep 03 11:33:40 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446672123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.446672123
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/30.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.2425564415
Short name T589
Test name
Test status
Simulation time 9705959821 ps
CPU time 48.33 seconds
Started Sep 03 11:33:22 PM UTC 24
Finished Sep 03 11:34:11 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425564415 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2425564415
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/30.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_slow_rsp.3312149597
Short name T584
Test name
Test status
Simulation time 47874810318 ps
CPU time 49.35 seconds
Started Sep 03 11:33:23 PM UTC 24
Finished Sep 03 11:34:14 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312149597 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3312149597
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/30.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_zero_delays.2741688716
Short name T538
Test name
Test status
Simulation time 118558080 ps
CPU time 9.35 seconds
Started Sep 03 11:33:22 PM UTC 24
Finished Sep 03 11:33:32 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741688716 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.2741688716
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/30.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_same_source.1818627905
Short name T552
Test name
Test status
Simulation time 1769485891 ps
CPU time 14.62 seconds
Started Sep 03 11:33:28 PM UTC 24
Finished Sep 03 11:33:44 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818627905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.1818627905
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/30.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke.2130407948
Short name T528
Test name
Test status
Simulation time 14888104 ps
CPU time 1.5 seconds
Started Sep 03 11:33:18 PM UTC 24
Finished Sep 03 11:33:20 PM UTC 24
Peak memory 211244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130407948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2130407948
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/30.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_large_delays.1467568994
Short name T542
Test name
Test status
Simulation time 6931166153 ps
CPU time 15.7 seconds
Started Sep 03 11:33:19 PM UTC 24
Finished Sep 03 11:33:36 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467568994 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1467568994
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/30.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2278779074
Short name T537
Test name
Test status
Simulation time 925160008 ps
CPU time 10.16 seconds
Started Sep 03 11:33:20 PM UTC 24
Finished Sep 03 11:33:31 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278779074 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2278779074
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/30.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.2074838980
Short name T530
Test name
Test status
Simulation time 11400893 ps
CPU time 1.57 seconds
Started Sep 03 11:33:18 PM UTC 24
Finished Sep 03 11:33:20 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074838980 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2074838980
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/30.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all.1895647856
Short name T571
Test name
Test status
Simulation time 340794298 ps
CPU time 24.2 seconds
Started Sep 03 11:33:32 PM UTC 24
Finished Sep 03 11:33:57 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895647856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1895647856
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/30.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_error.677549885
Short name T310
Test name
Test status
Simulation time 4783679548 ps
CPU time 54.56 seconds
Started Sep 03 11:33:33 PM UTC 24
Finished Sep 03 11:34:29 PM UTC 24
Peak memory 214432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677549885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.677549885
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/30.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.476910651
Short name T730
Test name
Test status
Simulation time 2034093332 ps
CPU time 132.61 seconds
Started Sep 03 11:33:33 PM UTC 24
Finished Sep 03 11:35:48 PM UTC 24
Peak memory 216224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476910651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.476910651
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/30.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.2861778643
Short name T697
Test name
Test status
Simulation time 921529733 ps
CPU time 106.24 seconds
Started Sep 03 11:33:33 PM UTC 24
Finished Sep 03 11:35:21 PM UTC 24
Peak memory 218600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861778643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.2861778643
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/30.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_unmapped_addr.3480346620
Short name T546
Test name
Test status
Simulation time 66374492 ps
CPU time 7.12 seconds
Started Sep 03 11:33:31 PM UTC 24
Finished Sep 03 11:33:39 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480346620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.3480346620
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/30.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device.2961450685
Short name T573
Test name
Test status
Simulation time 4482698009 ps
CPU time 16.79 seconds
Started Sep 03 11:33:40 PM UTC 24
Finished Sep 03 11:33:58 PM UTC 24
Peak memory 212456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961450685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.2961450685
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/31.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2052819135
Short name T287
Test name
Test status
Simulation time 39773302594 ps
CPU time 74.18 seconds
Started Sep 03 11:33:41 PM UTC 24
Finished Sep 03 11:34:56 PM UTC 24
Peak memory 214372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052819135 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.2052819135
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/31.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.1749870447
Short name T560
Test name
Test status
Simulation time 67955805 ps
CPU time 6.87 seconds
Started Sep 03 11:33:44 PM UTC 24
Finished Sep 03 11:33:52 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749870447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.1749870447
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/31.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_error_random.3216317948
Short name T564
Test name
Test status
Simulation time 418663933 ps
CPU time 9.05 seconds
Started Sep 03 11:33:43 PM UTC 24
Finished Sep 03 11:33:53 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216317948 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3216317948
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/31.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random.1287449300
Short name T562
Test name
Test status
Simulation time 1117185435 ps
CPU time 14.22 seconds
Started Sep 03 11:33:37 PM UTC 24
Finished Sep 03 11:33:52 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287449300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.1287449300
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/31.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_large_delays.553394258
Short name T592
Test name
Test status
Simulation time 8622502854 ps
CPU time 32.73 seconds
Started Sep 03 11:33:39 PM UTC 24
Finished Sep 03 11:34:13 PM UTC 24
Peak memory 212184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553394258 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.553394258
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/31.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_slow_rsp.4129324580
Short name T640
Test name
Test status
Simulation time 57213257388 ps
CPU time 61.94 seconds
Started Sep 03 11:33:40 PM UTC 24
Finished Sep 03 11:34:44 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129324580 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.4129324580
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/31.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_zero_delays.214612347
Short name T556
Test name
Test status
Simulation time 167171495 ps
CPU time 8.15 seconds
Started Sep 03 11:33:38 PM UTC 24
Finished Sep 03 11:33:47 PM UTC 24
Peak memory 212460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214612347 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.214612347
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/31.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_same_source.1107449093
Short name T554
Test name
Test status
Simulation time 540681752 ps
CPU time 3.77 seconds
Started Sep 03 11:33:42 PM UTC 24
Finished Sep 03 11:33:46 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107449093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1107449093
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/31.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke.2890958155
Short name T544
Test name
Test status
Simulation time 8864113 ps
CPU time 1.6 seconds
Started Sep 03 11:33:34 PM UTC 24
Finished Sep 03 11:33:37 PM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890958155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2890958155
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/31.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_large_delays.3843989324
Short name T565
Test name
Test status
Simulation time 13803710773 ps
CPU time 15.5 seconds
Started Sep 03 11:33:37 PM UTC 24
Finished Sep 03 11:33:53 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843989324 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.3843989324
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/31.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.2799633270
Short name T555
Test name
Test status
Simulation time 966562331 ps
CPU time 9.16 seconds
Started Sep 03 11:33:37 PM UTC 24
Finished Sep 03 11:33:47 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799633270 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2799633270
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/31.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.3916502088
Short name T545
Test name
Test status
Simulation time 9002705 ps
CPU time 1.6 seconds
Started Sep 03 11:33:36 PM UTC 24
Finished Sep 03 11:33:38 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916502088 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.3916502088
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/31.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all.97765992
Short name T586
Test name
Test status
Simulation time 1435082701 ps
CPU time 24.1 seconds
Started Sep 03 11:33:45 PM UTC 24
Finished Sep 03 11:34:10 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97765992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-si
m-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.97765992
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/31.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_error.1347871428
Short name T646
Test name
Test status
Simulation time 26452732967 ps
CPU time 57.29 seconds
Started Sep 03 11:33:47 PM UTC 24
Finished Sep 03 11:34:46 PM UTC 24
Peak memory 214436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347871428 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.1347871428
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/31.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.2577560376
Short name T598
Test name
Test status
Simulation time 116166749 ps
CPU time 29.15 seconds
Started Sep 03 11:33:45 PM UTC 24
Finished Sep 03 11:34:16 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577560376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.2577560376
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/31.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_unmapped_addr.1153841444
Short name T557
Test name
Test status
Simulation time 35184203 ps
CPU time 4.25 seconds
Started Sep 03 11:33:44 PM UTC 24
Finished Sep 03 11:33:49 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153841444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1153841444
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/31.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device.3367291453
Short name T311
Test name
Test status
Simulation time 3036602275 ps
CPU time 12.61 seconds
Started Sep 03 11:33:54 PM UTC 24
Finished Sep 03 11:34:07 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367291453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.3367291453
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/32.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.2217194769
Short name T895
Test name
Test status
Simulation time 40227987851 ps
CPU time 348.67 seconds
Started Sep 03 11:33:55 PM UTC 24
Finished Sep 03 11:39:48 PM UTC 24
Peak memory 217940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217194769 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.2217194769
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/32.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3514875661
Short name T580
Test name
Test status
Simulation time 63522549 ps
CPU time 6.44 seconds
Started Sep 03 11:33:58 PM UTC 24
Finished Sep 03 11:34:05 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514875661 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.3514875661
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/32.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_error_random.459094423
Short name T578
Test name
Test status
Simulation time 358374749 ps
CPU time 6.22 seconds
Started Sep 03 11:33:56 PM UTC 24
Finished Sep 03 11:34:03 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459094423 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.459094423
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/32.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random.964716201
Short name T572
Test name
Test status
Simulation time 29170564 ps
CPU time 3.55 seconds
Started Sep 03 11:33:54 PM UTC 24
Finished Sep 03 11:33:58 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964716201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.964716201
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/32.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.241895794
Short name T633
Test name
Test status
Simulation time 7464250852 ps
CPU time 43.22 seconds
Started Sep 03 11:33:54 PM UTC 24
Finished Sep 03 11:34:38 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241895794 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.241895794
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/32.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.2911550435
Short name T700
Test name
Test status
Simulation time 56408499482 ps
CPU time 88.79 seconds
Started Sep 03 11:33:54 PM UTC 24
Finished Sep 03 11:35:24 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911550435 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2911550435
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/32.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_zero_delays.4015791503
Short name T570
Test name
Test status
Simulation time 73315322 ps
CPU time 2.26 seconds
Started Sep 03 11:33:54 PM UTC 24
Finished Sep 03 11:33:57 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015791503 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.4015791503
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/32.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_same_source.2443530002
Short name T581
Test name
Test status
Simulation time 660104041 ps
CPU time 9.22 seconds
Started Sep 03 11:33:56 PM UTC 24
Finished Sep 03 11:34:06 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443530002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.2443530002
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/32.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke.1248510019
Short name T559
Test name
Test status
Simulation time 36577294 ps
CPU time 1.92 seconds
Started Sep 03 11:33:49 PM UTC 24
Finished Sep 03 11:33:51 PM UTC 24
Peak memory 211244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248510019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.1248510019
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/32.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_large_delays.3008639668
Short name T577
Test name
Test status
Simulation time 3919264099 ps
CPU time 10.65 seconds
Started Sep 03 11:33:51 PM UTC 24
Finished Sep 03 11:34:03 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008639668 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.3008639668
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/32.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.2154848384
Short name T575
Test name
Test status
Simulation time 909894238 ps
CPU time 7.71 seconds
Started Sep 03 11:33:52 PM UTC 24
Finished Sep 03 11:34:01 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154848384 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2154848384
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/32.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.3838998565
Short name T561
Test name
Test status
Simulation time 8427676 ps
CPU time 1.51 seconds
Started Sep 03 11:33:50 PM UTC 24
Finished Sep 03 11:33:52 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838998565 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.3838998565
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/32.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all.1756823620
Short name T129
Test name
Test status
Simulation time 4039963325 ps
CPU time 85.35 seconds
Started Sep 03 11:33:58 PM UTC 24
Finished Sep 03 11:35:25 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756823620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1756823620
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/32.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_error.2200342709
Short name T599
Test name
Test status
Simulation time 2502387966 ps
CPU time 15.51 seconds
Started Sep 03 11:34:00 PM UTC 24
Finished Sep 03 11:34:16 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200342709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.2200342709
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/32.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2501109196
Short name T799
Test name
Test status
Simulation time 829161427 ps
CPU time 154.43 seconds
Started Sep 03 11:33:58 PM UTC 24
Finished Sep 03 11:36:35 PM UTC 24
Peak memory 216228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501109196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.2501109196
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/32.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.1572421555
Short name T673
Test name
Test status
Simulation time 5041988575 ps
CPU time 63.77 seconds
Started Sep 03 11:34:00 PM UTC 24
Finished Sep 03 11:35:05 PM UTC 24
Peak memory 214248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572421555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.1572421555
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/32.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_unmapped_addr.3081764123
Short name T583
Test name
Test status
Simulation time 495023840 ps
CPU time 9.76 seconds
Started Sep 03 11:33:56 PM UTC 24
Finished Sep 03 11:34:07 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081764123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.3081764123
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/32.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device.3193068030
Short name T602
Test name
Test status
Simulation time 833781137 ps
CPU time 11.05 seconds
Started Sep 03 11:34:05 PM UTC 24
Finished Sep 03 11:34:17 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193068030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.3193068030
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/33.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.3028527418
Short name T282
Test name
Test status
Simulation time 25168394023 ps
CPU time 129.34 seconds
Started Sep 03 11:34:05 PM UTC 24
Finished Sep 03 11:36:17 PM UTC 24
Peak memory 214240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028527418 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.3028527418
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/33.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.2067759141
Short name T587
Test name
Test status
Simulation time 10816014 ps
CPU time 1.7 seconds
Started Sep 03 11:34:08 PM UTC 24
Finished Sep 03 11:34:11 PM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067759141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.2067759141
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/33.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_error_random.1235344381
Short name T603
Test name
Test status
Simulation time 1304241340 ps
CPU time 10.56 seconds
Started Sep 03 11:34:08 PM UTC 24
Finished Sep 03 11:34:20 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235344381 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.1235344381
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/33.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random.3569221538
Short name T588
Test name
Test status
Simulation time 281523691 ps
CPU time 5.15 seconds
Started Sep 03 11:34:05 PM UTC 24
Finished Sep 03 11:34:11 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569221538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.3569221538
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/33.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_large_delays.548140540
Short name T652
Test name
Test status
Simulation time 10633134753 ps
CPU time 46.13 seconds
Started Sep 03 11:34:05 PM UTC 24
Finished Sep 03 11:34:52 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548140540 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.548140540
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/33.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_slow_rsp.503625322
Short name T686
Test name
Test status
Simulation time 21411099899 ps
CPU time 68 seconds
Started Sep 03 11:34:05 PM UTC 24
Finished Sep 03 11:35:15 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503625322 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.503625322
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/33.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_zero_delays.1463884488
Short name T593
Test name
Test status
Simulation time 57832367 ps
CPU time 8.03 seconds
Started Sep 03 11:34:05 PM UTC 24
Finished Sep 03 11:34:14 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463884488 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.1463884488
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/33.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_same_source.4017861873
Short name T585
Test name
Test status
Simulation time 29108373 ps
CPU time 2.26 seconds
Started Sep 03 11:34:06 PM UTC 24
Finished Sep 03 11:34:10 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017861873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.4017861873
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/33.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke.2991846470
Short name T576
Test name
Test status
Simulation time 8782035 ps
CPU time 1.3 seconds
Started Sep 03 11:34:00 PM UTC 24
Finished Sep 03 11:34:02 PM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991846470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2991846470
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/33.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_large_delays.1834479734
Short name T600
Test name
Test status
Simulation time 3021930709 ps
CPU time 13.34 seconds
Started Sep 03 11:34:03 PM UTC 24
Finished Sep 03 11:34:17 PM UTC 24
Peak memory 212452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834479734 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.1834479734
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/33.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.3134543981
Short name T594
Test name
Test status
Simulation time 5033018164 ps
CPU time 10.38 seconds
Started Sep 03 11:34:03 PM UTC 24
Finished Sep 03 11:34:14 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134543981 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.3134543981
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/33.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.3947707483
Short name T579
Test name
Test status
Simulation time 32176168 ps
CPU time 1.36 seconds
Started Sep 03 11:34:01 PM UTC 24
Finished Sep 03 11:34:04 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947707483 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.3947707483
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/33.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all.2656384371
Short name T664
Test name
Test status
Simulation time 6245787108 ps
CPU time 48.26 seconds
Started Sep 03 11:34:10 PM UTC 24
Finished Sep 03 11:34:59 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656384371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.2656384371
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/33.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_error.3414368957
Short name T639
Test name
Test status
Simulation time 587609280 ps
CPU time 31.43 seconds
Started Sep 03 11:34:11 PM UTC 24
Finished Sep 03 11:34:44 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414368957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3414368957
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/33.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.4184787742
Short name T703
Test name
Test status
Simulation time 530712824 ps
CPU time 73.7 seconds
Started Sep 03 11:34:10 PM UTC 24
Finished Sep 03 11:35:25 PM UTC 24
Peak memory 216196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184787742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.4184787742
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/33.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.3806847024
Short name T741
Test name
Test status
Simulation time 3078444977 ps
CPU time 101.79 seconds
Started Sep 03 11:34:11 PM UTC 24
Finished Sep 03 11:35:55 PM UTC 24
Peak memory 218344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806847024 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.3806847024
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/33.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_unmapped_addr.3764005925
Short name T597
Test name
Test status
Simulation time 62546829 ps
CPU time 6.32 seconds
Started Sep 03 11:34:08 PM UTC 24
Finished Sep 03 11:34:15 PM UTC 24
Peak memory 212060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764005925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3764005925
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/33.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device.2244508026
Short name T616
Test name
Test status
Simulation time 50447157 ps
CPU time 10.4 seconds
Started Sep 03 11:34:17 PM UTC 24
Finished Sep 03 11:34:29 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244508026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.2244508026
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/34.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.1974532056
Short name T107
Test name
Test status
Simulation time 52135540069 ps
CPU time 209.39 seconds
Started Sep 03 11:34:18 PM UTC 24
Finished Sep 03 11:37:50 PM UTC 24
Peak memory 214240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974532056 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.1974532056
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/34.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.359322910
Short name T613
Test name
Test status
Simulation time 120339731 ps
CPU time 5.18 seconds
Started Sep 03 11:34:20 PM UTC 24
Finished Sep 03 11:34:26 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359322910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.359322910
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/34.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_error_random.3726110369
Short name T609
Test name
Test status
Simulation time 870163754 ps
CPU time 6.35 seconds
Started Sep 03 11:34:18 PM UTC 24
Finished Sep 03 11:34:25 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726110369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.3726110369
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/34.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random.2350826358
Short name T607
Test name
Test status
Simulation time 1386753385 ps
CPU time 7.35 seconds
Started Sep 03 11:34:15 PM UTC 24
Finished Sep 03 11:34:23 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350826358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.2350826358
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/34.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.1511676583
Short name T838
Test name
Test status
Simulation time 145096382166 ps
CPU time 175.3 seconds
Started Sep 03 11:34:15 PM UTC 24
Finished Sep 03 11:37:13 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511676583 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1511676583
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/34.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_slow_rsp.89924498
Short name T796
Test name
Test status
Simulation time 31361499120 ps
CPU time 133.37 seconds
Started Sep 03 11:34:17 PM UTC 24
Finished Sep 03 11:36:33 PM UTC 24
Peak memory 212184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89924498 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.89924498
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/34.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_zero_delays.899614713
Short name T608
Test name
Test status
Simulation time 151260990 ps
CPU time 7.65 seconds
Started Sep 03 11:34:15 PM UTC 24
Finished Sep 03 11:34:23 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899614713 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.899614713
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/34.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_same_source.2614745907
Short name T604
Test name
Test status
Simulation time 25697772 ps
CPU time 1.93 seconds
Started Sep 03 11:34:18 PM UTC 24
Finished Sep 03 11:34:20 PM UTC 24
Peak memory 211232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614745907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.2614745907
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/34.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke.175830964
Short name T595
Test name
Test status
Simulation time 60122590 ps
CPU time 1.51 seconds
Started Sep 03 11:34:12 PM UTC 24
Finished Sep 03 11:34:15 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175830964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.175830964
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/34.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_large_delays.519480689
Short name T612
Test name
Test status
Simulation time 5230887285 ps
CPU time 12.29 seconds
Started Sep 03 11:34:13 PM UTC 24
Finished Sep 03 11:34:26 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519480689 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.519480689
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/34.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.463239389
Short name T619
Test name
Test status
Simulation time 1987254324 ps
CPU time 14.73 seconds
Started Sep 03 11:34:15 PM UTC 24
Finished Sep 03 11:34:30 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463239389 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.463239389
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/34.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.1452765444
Short name T596
Test name
Test status
Simulation time 12976010 ps
CPU time 1.84 seconds
Started Sep 03 11:34:13 PM UTC 24
Finished Sep 03 11:34:15 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452765444 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.1452765444
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/34.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all.1377437041
Short name T670
Test name
Test status
Simulation time 547484882 ps
CPU time 41.43 seconds
Started Sep 03 11:34:20 PM UTC 24
Finished Sep 03 11:35:03 PM UTC 24
Peak memory 216224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377437041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1377437041
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/34.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_error.3953327401
Short name T743
Test name
Test status
Simulation time 24163792373 ps
CPU time 93.41 seconds
Started Sep 03 11:34:20 PM UTC 24
Finished Sep 03 11:35:56 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953327401 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3953327401
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/34.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.2426647156
Short name T104
Test name
Test status
Simulation time 3825431267 ps
CPU time 77.73 seconds
Started Sep 03 11:34:20 PM UTC 24
Finished Sep 03 11:35:40 PM UTC 24
Peak memory 214440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426647156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.2426647156
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/34.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.1465803925
Short name T667
Test name
Test status
Simulation time 832376779 ps
CPU time 39.49 seconds
Started Sep 03 11:34:20 PM UTC 24
Finished Sep 03 11:35:01 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465803925 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.1465803925
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/34.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_unmapped_addr.2553690988
Short name T614
Test name
Test status
Simulation time 90629793 ps
CPU time 8.93 seconds
Started Sep 03 11:34:18 PM UTC 24
Finished Sep 03 11:34:28 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553690988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.2553690988
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/34.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device.1776598372
Short name T648
Test name
Test status
Simulation time 1471597038 ps
CPU time 19.17 seconds
Started Sep 03 11:34:27 PM UTC 24
Finished Sep 03 11:34:47 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776598372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.1776598372
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/35.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.4228254059
Short name T632
Test name
Test status
Simulation time 171508161 ps
CPU time 6.68 seconds
Started Sep 03 11:34:29 PM UTC 24
Finished Sep 03 11:34:37 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228254059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.4228254059
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/35.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_error_random.3047481983
Short name T637
Test name
Test status
Simulation time 1024863029 ps
CPU time 10.74 seconds
Started Sep 03 11:34:29 PM UTC 24
Finished Sep 03 11:34:41 PM UTC 24
Peak memory 212452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047481983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3047481983
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/35.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random.1304916029
Short name T617
Test name
Test status
Simulation time 150896270 ps
CPU time 4.05 seconds
Started Sep 03 11:34:24 PM UTC 24
Finished Sep 03 11:34:30 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304916029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.1304916029
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/35.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.1751933590
Short name T665
Test name
Test status
Simulation time 6461682301 ps
CPU time 33.76 seconds
Started Sep 03 11:34:24 PM UTC 24
Finished Sep 03 11:35:00 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751933590 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.1751933590
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/35.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.1959005339
Short name T115
Test name
Test status
Simulation time 19027152525 ps
CPU time 139.75 seconds
Started Sep 03 11:34:25 PM UTC 24
Finished Sep 03 11:36:47 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959005339 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.1959005339
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/35.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_zero_delays.2378530749
Short name T623
Test name
Test status
Simulation time 85863583 ps
CPU time 6.67 seconds
Started Sep 03 11:34:24 PM UTC 24
Finished Sep 03 11:34:32 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378530749 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.2378530749
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/35.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_same_source.3424609804
Short name T625
Test name
Test status
Simulation time 45570469 ps
CPU time 4.86 seconds
Started Sep 03 11:34:27 PM UTC 24
Finished Sep 03 11:34:33 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424609804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3424609804
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/35.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke.956278985
Short name T606
Test name
Test status
Simulation time 9202993 ps
CPU time 1.43 seconds
Started Sep 03 11:34:20 PM UTC 24
Finished Sep 03 11:34:23 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956278985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.956278985
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/35.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_large_delays.2183271654
Short name T620
Test name
Test status
Simulation time 6832787961 ps
CPU time 6.84 seconds
Started Sep 03 11:34:22 PM UTC 24
Finished Sep 03 11:34:30 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183271654 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.2183271654
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/35.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.93367054
Short name T624
Test name
Test status
Simulation time 624345112 ps
CPU time 8.77 seconds
Started Sep 03 11:34:22 PM UTC 24
Finished Sep 03 11:34:32 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93367054 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.93367054
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/35.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.670641851
Short name T611
Test name
Test status
Simulation time 8815960 ps
CPU time 1.66 seconds
Started Sep 03 11:34:22 PM UTC 24
Finished Sep 03 11:34:25 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670641851 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.670641851
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/35.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all.2457848551
Short name T626
Test name
Test status
Simulation time 203761673 ps
CPU time 3.12 seconds
Started Sep 03 11:34:29 PM UTC 24
Finished Sep 03 11:34:34 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457848551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2457848551
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/35.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_error.2167837854
Short name T630
Test name
Test status
Simulation time 21558380 ps
CPU time 2.4 seconds
Started Sep 03 11:34:32 PM UTC 24
Finished Sep 03 11:34:36 PM UTC 24
Peak memory 212104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167837854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.2167837854
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/35.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.3047203345
Short name T751
Test name
Test status
Simulation time 921554568 ps
CPU time 87.61 seconds
Started Sep 03 11:34:32 PM UTC 24
Finished Sep 03 11:36:02 PM UTC 24
Peak memory 218484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047203345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.3047203345
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/35.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.3403751394
Short name T752
Test name
Test status
Simulation time 5341456925 ps
CPU time 87.91 seconds
Started Sep 03 11:34:32 PM UTC 24
Finished Sep 03 11:36:02 PM UTC 24
Peak memory 218540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403751394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.3403751394
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/35.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_unmapped_addr.763394658
Short name T635
Test name
Test status
Simulation time 640848179 ps
CPU time 9.79 seconds
Started Sep 03 11:34:29 PM UTC 24
Finished Sep 03 11:34:40 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763394658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.763394658
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/35.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device.392801521
Short name T657
Test name
Test status
Simulation time 1112693360 ps
CPU time 18.09 seconds
Started Sep 03 11:34:35 PM UTC 24
Finished Sep 03 11:34:55 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392801521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.392801521
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/36.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.1595238570
Short name T110
Test name
Test status
Simulation time 295491581762 ps
CPU time 385.45 seconds
Started Sep 03 11:34:35 PM UTC 24
Finished Sep 03 11:41:06 PM UTC 24
Peak memory 217944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595238570 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.1595238570
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/36.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.399148026
Short name T644
Test name
Test status
Simulation time 74550988 ps
CPU time 6.26 seconds
Started Sep 03 11:34:37 PM UTC 24
Finished Sep 03 11:34:45 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399148026 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.399148026
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/36.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_error_random.1050292480
Short name T645
Test name
Test status
Simulation time 56051710 ps
CPU time 6.87 seconds
Started Sep 03 11:34:37 PM UTC 24
Finished Sep 03 11:34:45 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050292480 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1050292480
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/36.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random.4276674464
Short name T642
Test name
Test status
Simulation time 313258046 ps
CPU time 8.3 seconds
Started Sep 03 11:34:35 PM UTC 24
Finished Sep 03 11:34:45 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276674464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.4276674464
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/36.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.2328443642
Short name T882
Test name
Test status
Simulation time 62498716786 ps
CPU time 219.27 seconds
Started Sep 03 11:34:35 PM UTC 24
Finished Sep 03 11:38:18 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328443642 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2328443642
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/36.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.2539825108
Short name T654
Test name
Test status
Simulation time 12740630340 ps
CPU time 16.6 seconds
Started Sep 03 11:34:35 PM UTC 24
Finished Sep 03 11:34:54 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539825108 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.2539825108
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/36.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_zero_delays.1000322057
Short name T634
Test name
Test status
Simulation time 42190134 ps
CPU time 3.55 seconds
Started Sep 03 11:34:35 PM UTC 24
Finished Sep 03 11:34:40 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000322057 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.1000322057
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/36.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_same_source.910428051
Short name T636
Test name
Test status
Simulation time 89009737 ps
CPU time 2.74 seconds
Started Sep 03 11:34:37 PM UTC 24
Finished Sep 03 11:34:41 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910428051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.910428051
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/36.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke.294993130
Short name T629
Test name
Test status
Simulation time 9289204 ps
CPU time 1.79 seconds
Started Sep 03 11:34:32 PM UTC 24
Finished Sep 03 11:34:35 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294993130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.294993130
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/36.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_large_delays.1892733946
Short name T649
Test name
Test status
Simulation time 2257411048 ps
CPU time 15.47 seconds
Started Sep 03 11:34:35 PM UTC 24
Finished Sep 03 11:34:52 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892733946 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.1892733946
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/36.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.3227622060
Short name T638
Test name
Test status
Simulation time 1197445474 ps
CPU time 7.09 seconds
Started Sep 03 11:34:35 PM UTC 24
Finished Sep 03 11:34:43 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227622060 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3227622060
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/36.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.2738347864
Short name T628
Test name
Test status
Simulation time 9932681 ps
CPU time 1.72 seconds
Started Sep 03 11:34:32 PM UTC 24
Finished Sep 03 11:34:35 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738347864 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.2738347864
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/36.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all.2033759639
Short name T647
Test name
Test status
Simulation time 464262841 ps
CPU time 6.91 seconds
Started Sep 03 11:34:39 PM UTC 24
Finished Sep 03 11:34:47 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033759639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.2033759639
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/36.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_error.3601985569
Short name T717
Test name
Test status
Simulation time 624230534 ps
CPU time 55.27 seconds
Started Sep 03 11:34:39 PM UTC 24
Finished Sep 03 11:35:36 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601985569 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.3601985569
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/36.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1950326425
Short name T680
Test name
Test status
Simulation time 220947180 ps
CPU time 29.75 seconds
Started Sep 03 11:34:39 PM UTC 24
Finished Sep 03 11:35:10 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950326425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.1950326425
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/36.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3095965949
Short name T658
Test name
Test status
Simulation time 185895982 ps
CPU time 14.67 seconds
Started Sep 03 11:34:39 PM UTC 24
Finished Sep 03 11:34:55 PM UTC 24
Peak memory 212332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095965949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.3095965949
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/36.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_unmapped_addr.2362149467
Short name T651
Test name
Test status
Simulation time 1698696112 ps
CPU time 13.77 seconds
Started Sep 03 11:34:37 PM UTC 24
Finished Sep 03 11:34:52 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362149467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2362149467
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/36.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device.1446492311
Short name T666
Test name
Test status
Simulation time 500908285 ps
CPU time 12.75 seconds
Started Sep 03 11:34:46 PM UTC 24
Finished Sep 03 11:35:01 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446492311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.1446492311
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/37.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3234945469
Short name T307
Test name
Test status
Simulation time 61992409025 ps
CPU time 165.11 seconds
Started Sep 03 11:34:47 PM UTC 24
Finished Sep 03 11:37:34 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234945469 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.3234945469
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/37.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.2425697233
Short name T655
Test name
Test status
Simulation time 44225373 ps
CPU time 3.78 seconds
Started Sep 03 11:34:49 PM UTC 24
Finished Sep 03 11:34:54 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425697233 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.2425697233
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/37.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_error_random.3303712616
Short name T669
Test name
Test status
Simulation time 1409183828 ps
CPU time 13.05 seconds
Started Sep 03 11:34:49 PM UTC 24
Finished Sep 03 11:35:03 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303712616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.3303712616
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/37.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random.1958873874
Short name T663
Test name
Test status
Simulation time 4617499549 ps
CPU time 11.44 seconds
Started Sep 03 11:34:46 PM UTC 24
Finished Sep 03 11:34:59 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958873874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.1958873874
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/37.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.2647777091
Short name T831
Test name
Test status
Simulation time 47038161628 ps
CPU time 136.55 seconds
Started Sep 03 11:34:46 PM UTC 24
Finished Sep 03 11:37:05 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647777091 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2647777091
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/37.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.1171392855
Short name T733
Test name
Test status
Simulation time 10666393726 ps
CPU time 62.38 seconds
Started Sep 03 11:34:46 PM UTC 24
Finished Sep 03 11:35:51 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171392855 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1171392855
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/37.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_zero_delays.2101744088
Short name T660
Test name
Test status
Simulation time 263696685 ps
CPU time 10.21 seconds
Started Sep 03 11:34:46 PM UTC 24
Finished Sep 03 11:34:58 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101744088 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.2101744088
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/37.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_same_source.2944309409
Short name T656
Test name
Test status
Simulation time 441786579 ps
CPU time 7.24 seconds
Started Sep 03 11:34:47 PM UTC 24
Finished Sep 03 11:34:55 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944309409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2944309409
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/37.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke.1739774607
Short name T641
Test name
Test status
Simulation time 8376599 ps
CPU time 1.6 seconds
Started Sep 03 11:34:42 PM UTC 24
Finished Sep 03 11:34:45 PM UTC 24
Peak memory 211140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739774607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.1739774607
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/37.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_large_delays.2499025891
Short name T661
Test name
Test status
Simulation time 8023642444 ps
CPU time 15.06 seconds
Started Sep 03 11:34:42 PM UTC 24
Finished Sep 03 11:34:58 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499025891 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.2499025891
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/37.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.1795672093
Short name T650
Test name
Test status
Simulation time 1403104015 ps
CPU time 7.25 seconds
Started Sep 03 11:34:43 PM UTC 24
Finished Sep 03 11:34:52 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795672093 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1795672093
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/37.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.440011486
Short name T643
Test name
Test status
Simulation time 9456167 ps
CPU time 1.69 seconds
Started Sep 03 11:34:42 PM UTC 24
Finished Sep 03 11:34:45 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440011486 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.440011486
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/37.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.3883305710
Short name T685
Test name
Test status
Simulation time 715815649 ps
CPU time 24.01 seconds
Started Sep 03 11:34:49 PM UTC 24
Finished Sep 03 11:35:14 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883305710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3883305710
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/37.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_error.2731939031
Short name T721
Test name
Test status
Simulation time 5749337453 ps
CPU time 44.02 seconds
Started Sep 03 11:34:54 PM UTC 24
Finished Sep 03 11:35:40 PM UTC 24
Peak memory 212260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731939031 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2731939031
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/37.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.4195807383
Short name T720
Test name
Test status
Simulation time 236494026 ps
CPU time 44 seconds
Started Sep 03 11:34:54 PM UTC 24
Finished Sep 03 11:35:40 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195807383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.4195807383
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/37.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.4196785917
Short name T853
Test name
Test status
Simulation time 3662853933 ps
CPU time 144.74 seconds
Started Sep 03 11:34:54 PM UTC 24
Finished Sep 03 11:37:21 PM UTC 24
Peak memory 216296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196785917 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.4196785917
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/37.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_unmapped_addr.1585705302
Short name T668
Test name
Test status
Simulation time 995926937 ps
CPU time 12.29 seconds
Started Sep 03 11:34:49 PM UTC 24
Finished Sep 03 11:35:02 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585705302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1585705302
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/37.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device.3199825038
Short name T682
Test name
Test status
Simulation time 1916792189 ps
CPU time 11.91 seconds
Started Sep 03 11:34:58 PM UTC 24
Finished Sep 03 11:35:11 PM UTC 24
Peak memory 212264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199825038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.3199825038
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/38.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.254859262
Short name T891
Test name
Test status
Simulation time 36396136986 ps
CPU time 233.55 seconds
Started Sep 03 11:35:01 PM UTC 24
Finished Sep 03 11:38:58 PM UTC 24
Peak memory 214240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254859262 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.254859262
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/38.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.471112022
Short name T678
Test name
Test status
Simulation time 214332229 ps
CPU time 4.4 seconds
Started Sep 03 11:35:03 PM UTC 24
Finished Sep 03 11:35:09 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471112022 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.471112022
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/38.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_error_random.4183207070
Short name T684
Test name
Test status
Simulation time 636740868 ps
CPU time 11.41 seconds
Started Sep 03 11:35:01 PM UTC 24
Finished Sep 03 11:35:13 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183207070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.4183207070
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/38.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random.2195146988
Short name T674
Test name
Test status
Simulation time 1297567630 ps
CPU time 8.9 seconds
Started Sep 03 11:34:57 PM UTC 24
Finished Sep 03 11:35:07 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195146988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.2195146988
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/38.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.1665663221
Short name T766
Test name
Test status
Simulation time 15275804468 ps
CPU time 70.85 seconds
Started Sep 03 11:34:57 PM UTC 24
Finished Sep 03 11:36:09 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665663221 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.1665663221
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/38.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.2417160650
Short name T864
Test name
Test status
Simulation time 21562266071 ps
CPU time 147.15 seconds
Started Sep 03 11:34:58 PM UTC 24
Finished Sep 03 11:37:28 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417160650 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.2417160650
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/38.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_zero_delays.3880043079
Short name T671
Test name
Test status
Simulation time 450203996 ps
CPU time 6.45 seconds
Started Sep 03 11:34:57 PM UTC 24
Finished Sep 03 11:35:04 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880043079 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.3880043079
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/38.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_same_source.869516898
Short name T672
Test name
Test status
Simulation time 35887710 ps
CPU time 2.97 seconds
Started Sep 03 11:35:01 PM UTC 24
Finished Sep 03 11:35:05 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869516898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.869516898
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/38.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke.714001423
Short name T659
Test name
Test status
Simulation time 57968099 ps
CPU time 2.21 seconds
Started Sep 03 11:34:54 PM UTC 24
Finished Sep 03 11:34:57 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714001423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.714001423
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/38.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_large_delays.2355056812
Short name T679
Test name
Test status
Simulation time 1218305902 ps
CPU time 11.48 seconds
Started Sep 03 11:34:56 PM UTC 24
Finished Sep 03 11:35:09 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355056812 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2355056812
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/38.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.2697175392
Short name T675
Test name
Test status
Simulation time 2045797177 ps
CPU time 8.9 seconds
Started Sep 03 11:34:57 PM UTC 24
Finished Sep 03 11:35:07 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697175392 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2697175392
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/38.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.730747110
Short name T662
Test name
Test status
Simulation time 10104149 ps
CPU time 1.38 seconds
Started Sep 03 11:34:56 PM UTC 24
Finished Sep 03 11:34:59 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730747110 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.730747110
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/38.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.3503725816
Short name T696
Test name
Test status
Simulation time 138345099 ps
CPU time 16.45 seconds
Started Sep 03 11:35:03 PM UTC 24
Finished Sep 03 11:35:21 PM UTC 24
Peak memory 214376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503725816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.3503725816
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/38.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.2639639062
Short name T736
Test name
Test status
Simulation time 12541969899 ps
CPU time 46.69 seconds
Started Sep 03 11:35:04 PM UTC 24
Finished Sep 03 11:35:52 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639639062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2639639062
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/38.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2976629058
Short name T713
Test name
Test status
Simulation time 2477838518 ps
CPU time 28.65 seconds
Started Sep 03 11:35:03 PM UTC 24
Finished Sep 03 11:35:33 PM UTC 24
Peak memory 216360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976629058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.2976629058
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/38.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_unmapped_addr.1476493895
Short name T681
Test name
Test status
Simulation time 596665862 ps
CPU time 8.91 seconds
Started Sep 03 11:35:01 PM UTC 24
Finished Sep 03 11:35:11 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476493895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1476493895
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/38.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device.603158702
Short name T704
Test name
Test status
Simulation time 140469144 ps
CPU time 14.77 seconds
Started Sep 03 11:35:10 PM UTC 24
Finished Sep 03 11:35:26 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603158702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.603158702
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/39.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.2308821373
Short name T865
Test name
Test status
Simulation time 25156514722 ps
CPU time 136.94 seconds
Started Sep 03 11:35:10 PM UTC 24
Finished Sep 03 11:37:29 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308821373 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.2308821373
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/39.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.1847276819
Short name T692
Test name
Test status
Simulation time 1544341543 ps
CPU time 5.38 seconds
Started Sep 03 11:35:12 PM UTC 24
Finished Sep 03 11:35:18 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847276819 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.1847276819
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/39.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_error_random.3176966953
Short name T693
Test name
Test status
Simulation time 51647502 ps
CPU time 5.73 seconds
Started Sep 03 11:35:12 PM UTC 24
Finished Sep 03 11:35:19 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176966953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.3176966953
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/39.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random.1590093933
Short name T683
Test name
Test status
Simulation time 37865253 ps
CPU time 4.86 seconds
Started Sep 03 11:35:07 PM UTC 24
Finished Sep 03 11:35:13 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590093933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.1590093933
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/39.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.4201368986
Short name T879
Test name
Test status
Simulation time 36721897921 ps
CPU time 171.29 seconds
Started Sep 03 11:35:10 PM UTC 24
Finished Sep 03 11:38:04 PM UTC 24
Peak memory 212456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201368986 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.4201368986
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/39.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.960379218
Short name T702
Test name
Test status
Simulation time 1909504288 ps
CPU time 13.96 seconds
Started Sep 03 11:35:10 PM UTC 24
Finished Sep 03 11:35:25 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960379218 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.960379218
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/39.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_zero_delays.3251361869
Short name T687
Test name
Test status
Simulation time 254501775 ps
CPU time 5.53 seconds
Started Sep 03 11:35:10 PM UTC 24
Finished Sep 03 11:35:16 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251361869 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.3251361869
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/39.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_same_source.3617009912
Short name T694
Test name
Test status
Simulation time 55346237 ps
CPU time 6.72 seconds
Started Sep 03 11:35:12 PM UTC 24
Finished Sep 03 11:35:20 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617009912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3617009912
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/39.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke.2793000296
Short name T677
Test name
Test status
Simulation time 47051422 ps
CPU time 1.39 seconds
Started Sep 03 11:35:05 PM UTC 24
Finished Sep 03 11:35:07 PM UTC 24
Peak memory 211184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793000296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2793000296
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/39.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_large_delays.2809854439
Short name T688
Test name
Test status
Simulation time 1534967309 ps
CPU time 10.3 seconds
Started Sep 03 11:35:05 PM UTC 24
Finished Sep 03 11:35:16 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809854439 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2809854439
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/39.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.375336402
Short name T690
Test name
Test status
Simulation time 5452921800 ps
CPU time 9.54 seconds
Started Sep 03 11:35:07 PM UTC 24
Finished Sep 03 11:35:18 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375336402 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.375336402
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/39.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2005112977
Short name T676
Test name
Test status
Simulation time 15679398 ps
CPU time 1.27 seconds
Started Sep 03 11:35:05 PM UTC 24
Finished Sep 03 11:35:07 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005112977 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.2005112977
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/39.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.2325586139
Short name T778
Test name
Test status
Simulation time 3843375679 ps
CPU time 65.08 seconds
Started Sep 03 11:35:14 PM UTC 24
Finished Sep 03 11:36:20 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325586139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.2325586139
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/39.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.4293584154
Short name T710
Test name
Test status
Simulation time 148645541 ps
CPU time 14.87 seconds
Started Sep 03 11:35:15 PM UTC 24
Finished Sep 03 11:35:31 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293584154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.4293584154
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/39.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.1673328043
Short name T762
Test name
Test status
Simulation time 2839038686 ps
CPU time 52.33 seconds
Started Sep 03 11:35:14 PM UTC 24
Finished Sep 03 11:36:08 PM UTC 24
Peak memory 214248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673328043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.1673328043
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/39.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.2627876722
Short name T798
Test name
Test status
Simulation time 739559495 ps
CPU time 77.25 seconds
Started Sep 03 11:35:16 PM UTC 24
Finished Sep 03 11:36:34 PM UTC 24
Peak memory 216232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627876722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.2627876722
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/39.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_unmapped_addr.1949309282
Short name T689
Test name
Test status
Simulation time 137676321 ps
CPU time 4.17 seconds
Started Sep 03 11:35:12 PM UTC 24
Finished Sep 03 11:35:17 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949309282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1949309282
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/39.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device.4138225357
Short name T197
Test name
Test status
Simulation time 23512600 ps
CPU time 5.08 seconds
Started Sep 03 11:28:28 PM UTC 24
Finished Sep 03 11:28:34 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138225357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.4138225357
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/4.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.4223200540
Short name T293
Test name
Test status
Simulation time 18108255432 ps
CPU time 75.57 seconds
Started Sep 03 11:28:28 PM UTC 24
Finished Sep 03 11:29:45 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223200540 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.4223200540
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/4.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.2486459757
Short name T320
Test name
Test status
Simulation time 1033240962 ps
CPU time 9.63 seconds
Started Sep 03 11:28:32 PM UTC 24
Finished Sep 03 11:28:43 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486459757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.2486459757
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/4.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_error_random.3141252165
Short name T346
Test name
Test status
Simulation time 859635460 ps
CPU time 7.86 seconds
Started Sep 03 11:28:30 PM UTC 24
Finished Sep 03 11:28:39 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141252165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3141252165
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/4.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random.3297818443
Short name T57
Test name
Test status
Simulation time 1041798240 ps
CPU time 10.67 seconds
Started Sep 03 11:28:27 PM UTC 24
Finished Sep 03 11:28:39 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297818443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.3297818443
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/4.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_large_delays.2409518528
Short name T71
Test name
Test status
Simulation time 11846667804 ps
CPU time 65.34 seconds
Started Sep 03 11:28:28 PM UTC 24
Finished Sep 03 11:29:35 PM UTC 24
Peak memory 212512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409518528 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.2409518528
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/4.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_slow_rsp.859664526
Short name T303
Test name
Test status
Simulation time 11245034589 ps
CPU time 75.92 seconds
Started Sep 03 11:28:28 PM UTC 24
Finished Sep 03 11:29:46 PM UTC 24
Peak memory 212188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859664526 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.859664526
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/4.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_zero_delays.2224989614
Short name T47
Test name
Test status
Simulation time 142886737 ps
CPU time 3.26 seconds
Started Sep 03 11:28:28 PM UTC 24
Finished Sep 03 11:28:32 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224989614 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.2224989614
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/4.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_same_source.3611393197
Short name T59
Test name
Test status
Simulation time 2272022000 ps
CPU time 12.81 seconds
Started Sep 03 11:28:29 PM UTC 24
Finished Sep 03 11:28:43 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611393197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3611393197
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/4.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke.3326383878
Short name T54
Test name
Test status
Simulation time 63713585 ps
CPU time 1.92 seconds
Started Sep 03 11:28:24 PM UTC 24
Finished Sep 03 11:28:27 PM UTC 24
Peak memory 211140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326383878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.3326383878
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/4.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_large_delays.1642161031
Short name T344
Test name
Test status
Simulation time 1111099805 ps
CPU time 6.82 seconds
Started Sep 03 11:28:25 PM UTC 24
Finished Sep 03 11:28:33 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642161031 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1642161031
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/4.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.2601586141
Short name T304
Test name
Test status
Simulation time 3594531162 ps
CPU time 10.81 seconds
Started Sep 03 11:28:27 PM UTC 24
Finished Sep 03 11:28:39 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601586141 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2601586141
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/4.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.2460012943
Short name T45
Test name
Test status
Simulation time 18488772 ps
CPU time 1.47 seconds
Started Sep 03 11:28:24 PM UTC 24
Finished Sep 03 11:28:27 PM UTC 24
Peak memory 211176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460012943 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.2460012943
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/4.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all.3295620814
Short name T340
Test name
Test status
Simulation time 282123959 ps
CPU time 30.62 seconds
Started Sep 03 11:28:32 PM UTC 24
Finished Sep 03 11:29:04 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295620814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.3295620814
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/4.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_error.621894864
Short name T275
Test name
Test status
Simulation time 705629216 ps
CPU time 11.01 seconds
Started Sep 03 11:28:34 PM UTC 24
Finished Sep 03 11:28:46 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621894864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.621894864
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/4.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.3772951468
Short name T86
Test name
Test status
Simulation time 5224867764 ps
CPU time 115.68 seconds
Started Sep 03 11:28:34 PM UTC 24
Finished Sep 03 11:30:32 PM UTC 24
Peak memory 216296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772951468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.3772951468
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/4.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_unmapped_addr.526489248
Short name T58
Test name
Test status
Simulation time 3728526324 ps
CPU time 10.23 seconds
Started Sep 03 11:28:30 PM UTC 24
Finished Sep 03 11:28:42 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526489248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.526489248
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/4.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device.1832331258
Short name T722
Test name
Test status
Simulation time 1096262073 ps
CPU time 19.95 seconds
Started Sep 03 11:35:20 PM UTC 24
Finished Sep 03 11:35:41 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832331258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.1832331258
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/40.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.2973377816
Short name T897
Test name
Test status
Simulation time 233529422360 ps
CPU time 279.14 seconds
Started Sep 03 11:35:22 PM UTC 24
Finished Sep 03 11:40:05 PM UTC 24
Peak memory 214308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973377816 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.2973377816
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/40.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.1212684354
Short name T707
Test name
Test status
Simulation time 158689927 ps
CPU time 4.83 seconds
Started Sep 03 11:35:24 PM UTC 24
Finished Sep 03 11:35:29 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212684354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.1212684354
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/40.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_error_random.4278973492
Short name T706
Test name
Test status
Simulation time 41344243 ps
CPU time 3.95 seconds
Started Sep 03 11:35:23 PM UTC 24
Finished Sep 03 11:35:28 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278973492 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.4278973492
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/40.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random.2061380467
Short name T705
Test name
Test status
Simulation time 393623296 ps
CPU time 7.82 seconds
Started Sep 03 11:35:18 PM UTC 24
Finished Sep 03 11:35:27 PM UTC 24
Peak memory 212316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061380467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.2061380467
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/40.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.1657134681
Short name T862
Test name
Test status
Simulation time 66972255965 ps
CPU time 125.06 seconds
Started Sep 03 11:35:20 PM UTC 24
Finished Sep 03 11:37:27 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657134681 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.1657134681
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/40.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.3464251795
Short name T117
Test name
Test status
Simulation time 67328490234 ps
CPU time 146.16 seconds
Started Sep 03 11:35:20 PM UTC 24
Finished Sep 03 11:37:48 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464251795 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.3464251795
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/40.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_zero_delays.2227229334
Short name T698
Test name
Test status
Simulation time 15360995 ps
CPU time 1.48 seconds
Started Sep 03 11:35:20 PM UTC 24
Finished Sep 03 11:35:22 PM UTC 24
Peak memory 211140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227229334 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.2227229334
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/40.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_same_source.537793812
Short name T701
Test name
Test status
Simulation time 16142463 ps
CPU time 1.91 seconds
Started Sep 03 11:35:22 PM UTC 24
Finished Sep 03 11:35:25 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537793812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.537793812
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/40.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke.4118933388
Short name T691
Test name
Test status
Simulation time 12177383 ps
CPU time 1.68 seconds
Started Sep 03 11:35:16 PM UTC 24
Finished Sep 03 11:35:18 PM UTC 24
Peak memory 211244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118933388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.4118933388
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/40.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_large_delays.1983728802
Short name T711
Test name
Test status
Simulation time 4707147083 ps
CPU time 13.04 seconds
Started Sep 03 11:35:18 PM UTC 24
Finished Sep 03 11:35:32 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983728802 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.1983728802
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/40.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.2641745672
Short name T699
Test name
Test status
Simulation time 777008215 ps
CPU time 5.51 seconds
Started Sep 03 11:35:18 PM UTC 24
Finished Sep 03 11:35:24 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641745672 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.2641745672
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/40.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.518773344
Short name T695
Test name
Test status
Simulation time 16047147 ps
CPU time 1.65 seconds
Started Sep 03 11:35:18 PM UTC 24
Finished Sep 03 11:35:20 PM UTC 24
Peak memory 211232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518773344 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.518773344
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/40.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.591092074
Short name T748
Test name
Test status
Simulation time 1473469668 ps
CPU time 33.27 seconds
Started Sep 03 11:35:25 PM UTC 24
Finished Sep 03 11:36:00 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591092074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.591092074
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/40.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.3383092341
Short name T714
Test name
Test status
Simulation time 87034881 ps
CPU time 8.15 seconds
Started Sep 03 11:35:25 PM UTC 24
Finished Sep 03 11:35:35 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383092341 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3383092341
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/40.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.4130024524
Short name T729
Test name
Test status
Simulation time 136792924 ps
CPU time 19.41 seconds
Started Sep 03 11:35:25 PM UTC 24
Finished Sep 03 11:35:46 PM UTC 24
Peak memory 214376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130024524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.4130024524
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/40.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.2838497304
Short name T732
Test name
Test status
Simulation time 281308771 ps
CPU time 20.39 seconds
Started Sep 03 11:35:28 PM UTC 24
Finished Sep 03 11:35:50 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838497304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.2838497304
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/40.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_unmapped_addr.2527971058
Short name T719
Test name
Test status
Simulation time 518036967 ps
CPU time 13.15 seconds
Started Sep 03 11:35:23 PM UTC 24
Finished Sep 03 11:35:38 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527971058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2527971058
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/40.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device.860350429
Short name T724
Test name
Test status
Simulation time 48987988 ps
CPU time 9.12 seconds
Started Sep 03 11:35:33 PM UTC 24
Finished Sep 03 11:35:43 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860350429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.860350429
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/41.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1552850032
Short name T109
Test name
Test status
Simulation time 30537656325 ps
CPU time 229.23 seconds
Started Sep 03 11:35:33 PM UTC 24
Finished Sep 03 11:39:25 PM UTC 24
Peak memory 214240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552850032 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.1552850032
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/41.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.2193203178
Short name T731
Test name
Test status
Simulation time 1665679584 ps
CPU time 10.74 seconds
Started Sep 03 11:35:37 PM UTC 24
Finished Sep 03 11:35:49 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193203178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.2193203178
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/41.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_error_random.3399544446
Short name T728
Test name
Test status
Simulation time 1602973251 ps
CPU time 9.2 seconds
Started Sep 03 11:35:35 PM UTC 24
Finished Sep 03 11:35:45 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399544446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3399544446
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/41.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random.186963061
Short name T712
Test name
Test status
Simulation time 108435499 ps
CPU time 1.95 seconds
Started Sep 03 11:35:30 PM UTC 24
Finished Sep 03 11:35:33 PM UTC 24
Peak memory 211140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186963061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.186963061
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/41.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.3904242745
Short name T816
Test name
Test status
Simulation time 15896076219 ps
CPU time 76.71 seconds
Started Sep 03 11:35:33 PM UTC 24
Finished Sep 03 11:36:52 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904242745 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.3904242745
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/41.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1042767577
Short name T871
Test name
Test status
Simulation time 23185284813 ps
CPU time 120.83 seconds
Started Sep 03 11:35:33 PM UTC 24
Finished Sep 03 11:37:36 PM UTC 24
Peak memory 212456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042767577 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1042767577
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/41.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_zero_delays.227455129
Short name T715
Test name
Test status
Simulation time 26042215 ps
CPU time 3.73 seconds
Started Sep 03 11:35:30 PM UTC 24
Finished Sep 03 11:35:35 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227455129 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.227455129
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/41.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_same_source.1665407012
Short name T737
Test name
Test status
Simulation time 2962059281 ps
CPU time 15.95 seconds
Started Sep 03 11:35:35 PM UTC 24
Finished Sep 03 11:35:52 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665407012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1665407012
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/41.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke.3665016278
Short name T709
Test name
Test status
Simulation time 34136978 ps
CPU time 1.87 seconds
Started Sep 03 11:35:28 PM UTC 24
Finished Sep 03 11:35:31 PM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665016278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3665016278
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/41.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_large_delays.3474168963
Short name T718
Test name
Test status
Simulation time 1495533682 ps
CPU time 7.87 seconds
Started Sep 03 11:35:28 PM UTC 24
Finished Sep 03 11:35:37 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474168963 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3474168963
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/41.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.691321421
Short name T723
Test name
Test status
Simulation time 1335051588 ps
CPU time 13.01 seconds
Started Sep 03 11:35:28 PM UTC 24
Finished Sep 03 11:35:43 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691321421 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.691321421
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/41.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.451581705
Short name T708
Test name
Test status
Simulation time 8863226 ps
CPU time 1.55 seconds
Started Sep 03 11:35:28 PM UTC 24
Finished Sep 03 11:35:31 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451581705 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.451581705
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/41.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.537624110
Short name T758
Test name
Test status
Simulation time 1502926203 ps
CPU time 28.56 seconds
Started Sep 03 11:35:37 PM UTC 24
Finished Sep 03 11:36:07 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537624110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.537624110
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/41.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.3660585936
Short name T750
Test name
Test status
Simulation time 4204519888 ps
CPU time 21.02 seconds
Started Sep 03 11:35:39 PM UTC 24
Finished Sep 03 11:36:01 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660585936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3660585936
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/41.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1415986493
Short name T763
Test name
Test status
Simulation time 235012100 ps
CPU time 27.7 seconds
Started Sep 03 11:35:39 PM UTC 24
Finished Sep 03 11:36:08 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415986493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.1415986493
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/41.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.1501356390
Short name T756
Test name
Test status
Simulation time 320317318 ps
CPU time 25.41 seconds
Started Sep 03 11:35:39 PM UTC 24
Finished Sep 03 11:36:06 PM UTC 24
Peak memory 212140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501356390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.1501356390
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/41.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_unmapped_addr.1014947671
Short name T726
Test name
Test status
Simulation time 135572949 ps
CPU time 5.99 seconds
Started Sep 03 11:35:37 PM UTC 24
Finished Sep 03 11:35:44 PM UTC 24
Peak memory 212332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014947671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1014947671
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/41.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device.3074821391
Short name T735
Test name
Test status
Simulation time 20373917 ps
CPU time 4.16 seconds
Started Sep 03 11:35:46 PM UTC 24
Finished Sep 03 11:35:52 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074821391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.3074821391
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/42.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.819061029
Short name T883
Test name
Test status
Simulation time 60684136041 ps
CPU time 150.79 seconds
Started Sep 03 11:35:47 PM UTC 24
Finished Sep 03 11:38:20 PM UTC 24
Peak memory 214248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819061029 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.819061029
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/42.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.913578717
Short name T745
Test name
Test status
Simulation time 213586535 ps
CPU time 4.76 seconds
Started Sep 03 11:35:51 PM UTC 24
Finished Sep 03 11:35:57 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913578717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.913578717
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/42.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_error_random.122512478
Short name T761
Test name
Test status
Simulation time 1378089148 ps
CPU time 16.99 seconds
Started Sep 03 11:35:49 PM UTC 24
Finished Sep 03 11:36:07 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122512478 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.122512478
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/42.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random.1634211305
Short name T266
Test name
Test status
Simulation time 994216995 ps
CPU time 6.4 seconds
Started Sep 03 11:35:44 PM UTC 24
Finished Sep 03 11:35:52 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634211305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.1634211305
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/42.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.3883697180
Short name T886
Test name
Test status
Simulation time 87114795328 ps
CPU time 166.45 seconds
Started Sep 03 11:35:45 PM UTC 24
Finished Sep 03 11:38:34 PM UTC 24
Peak memory 212264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883697180 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3883697180
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/42.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.3276236417
Short name T876
Test name
Test status
Simulation time 21997803874 ps
CPU time 120.73 seconds
Started Sep 03 11:35:46 PM UTC 24
Finished Sep 03 11:37:49 PM UTC 24
Peak memory 212456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276236417 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.3276236417
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/42.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_zero_delays.801780653
Short name T740
Test name
Test status
Simulation time 226907352 ps
CPU time 8.56 seconds
Started Sep 03 11:35:45 PM UTC 24
Finished Sep 03 11:35:54 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801780653 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.801780653
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/42.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_same_source.1084578841
Short name T747
Test name
Test status
Simulation time 1195071443 ps
CPU time 8.94 seconds
Started Sep 03 11:35:48 PM UTC 24
Finished Sep 03 11:35:58 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084578841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.1084578841
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/42.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke.2344677463
Short name T727
Test name
Test status
Simulation time 140813724 ps
CPU time 1.77 seconds
Started Sep 03 11:35:41 PM UTC 24
Finished Sep 03 11:35:44 PM UTC 24
Peak memory 211140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344677463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2344677463
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/42.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_large_delays.596852092
Short name T739
Test name
Test status
Simulation time 2831401557 ps
CPU time 11.25 seconds
Started Sep 03 11:35:41 PM UTC 24
Finished Sep 03 11:35:54 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596852092 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.596852092
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/42.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.2473385134
Short name T738
Test name
Test status
Simulation time 4219175088 ps
CPU time 8.57 seconds
Started Sep 03 11:35:43 PM UTC 24
Finished Sep 03 11:35:52 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473385134 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.2473385134
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/42.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.3932373785
Short name T725
Test name
Test status
Simulation time 8468321 ps
CPU time 1.6 seconds
Started Sep 03 11:35:41 PM UTC 24
Finished Sep 03 11:35:44 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932373785 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.3932373785
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/42.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.2667190879
Short name T789
Test name
Test status
Simulation time 1940208754 ps
CPU time 32.8 seconds
Started Sep 03 11:35:54 PM UTC 24
Finished Sep 03 11:36:28 PM UTC 24
Peak memory 214248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667190879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2667190879
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/42.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.329887909
Short name T812
Test name
Test status
Simulation time 15409866329 ps
CPU time 53.43 seconds
Started Sep 03 11:35:54 PM UTC 24
Finished Sep 03 11:36:49 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329887909 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.329887909
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/42.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.4170039894
Short name T794
Test name
Test status
Simulation time 3414879420 ps
CPU time 36.87 seconds
Started Sep 03 11:35:54 PM UTC 24
Finished Sep 03 11:36:32 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170039894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.4170039894
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/42.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.1944121447
Short name T869
Test name
Test status
Simulation time 975036091 ps
CPU time 95.65 seconds
Started Sep 03 11:35:54 PM UTC 24
Finished Sep 03 11:37:31 PM UTC 24
Peak memory 216232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944121447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.1944121447
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/42.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_unmapped_addr.1983770746
Short name T742
Test name
Test status
Simulation time 68323820 ps
CPU time 3.7 seconds
Started Sep 03 11:35:51 PM UTC 24
Finished Sep 03 11:35:56 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983770746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.1983770746
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/42.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.3842201798
Short name T174
Test name
Test status
Simulation time 269032252 ps
CPU time 8.97 seconds
Started Sep 03 11:35:58 PM UTC 24
Finished Sep 03 11:36:08 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842201798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.3842201798
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/43.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.435688486
Short name T211
Test name
Test status
Simulation time 57231650356 ps
CPU time 67.87 seconds
Started Sep 03 11:35:58 PM UTC 24
Finished Sep 03 11:37:07 PM UTC 24
Peak memory 214440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435688486 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.435688486
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/43.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.2706782980
Short name T757
Test name
Test status
Simulation time 200101446 ps
CPU time 4.65 seconds
Started Sep 03 11:36:01 PM UTC 24
Finished Sep 03 11:36:06 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706782980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.2706782980
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/43.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.56882179
Short name T753
Test name
Test status
Simulation time 32825872 ps
CPU time 4.12 seconds
Started Sep 03 11:35:58 PM UTC 24
Finished Sep 03 11:36:03 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56882179 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.56882179
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/43.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random.224888452
Short name T749
Test name
Test status
Simulation time 127655280 ps
CPU time 4.14 seconds
Started Sep 03 11:35:55 PM UTC 24
Finished Sep 03 11:36:01 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224888452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.224888452
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/43.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.280020764
Short name T881
Test name
Test status
Simulation time 34533283818 ps
CPU time 131.56 seconds
Started Sep 03 11:35:58 PM UTC 24
Finished Sep 03 11:38:11 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280020764 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.280020764
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/43.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.2380773366
Short name T791
Test name
Test status
Simulation time 7178483995 ps
CPU time 29.88 seconds
Started Sep 03 11:35:58 PM UTC 24
Finished Sep 03 11:36:29 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380773366 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.2380773366
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/43.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.4090328103
Short name T754
Test name
Test status
Simulation time 98526415 ps
CPU time 8.2 seconds
Started Sep 03 11:35:55 PM UTC 24
Finished Sep 03 11:36:05 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090328103 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.4090328103
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/43.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.2117488404
Short name T768
Test name
Test status
Simulation time 1238176728 ps
CPU time 11.02 seconds
Started Sep 03 11:35:58 PM UTC 24
Finished Sep 03 11:36:10 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117488404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.2117488404
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/43.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke.2433944960
Short name T746
Test name
Test status
Simulation time 62970251 ps
CPU time 2.19 seconds
Started Sep 03 11:35:54 PM UTC 24
Finished Sep 03 11:35:57 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433944960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.2433944960
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/43.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.1304815773
Short name T755
Test name
Test status
Simulation time 3793177096 ps
CPU time 10.14 seconds
Started Sep 03 11:35:54 PM UTC 24
Finished Sep 03 11:36:05 PM UTC 24
Peak memory 212452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304815773 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1304815773
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/43.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.2112984615
Short name T767
Test name
Test status
Simulation time 1696624411 ps
CPU time 13.18 seconds
Started Sep 03 11:35:55 PM UTC 24
Finished Sep 03 11:36:10 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112984615 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2112984615
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/43.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.3463884243
Short name T744
Test name
Test status
Simulation time 15039372 ps
CPU time 1.87 seconds
Started Sep 03 11:35:54 PM UTC 24
Finished Sep 03 11:35:57 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463884243 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.3463884243
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/43.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.868602589
Short name T781
Test name
Test status
Simulation time 1022036749 ps
CPU time 20.85 seconds
Started Sep 03 11:36:02 PM UTC 24
Finished Sep 03 11:36:24 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868602589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.868602589
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/43.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1767817832
Short name T846
Test name
Test status
Simulation time 16674585787 ps
CPU time 71.83 seconds
Started Sep 03 11:36:05 PM UTC 24
Finished Sep 03 11:37:18 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767817832 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1767817832
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/43.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.2058568430
Short name T765
Test name
Test status
Simulation time 45275069 ps
CPU time 6.15 seconds
Started Sep 03 11:36:02 PM UTC 24
Finished Sep 03 11:36:09 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058568430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.2058568430
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/43.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.2942954986
Short name T854
Test name
Test status
Simulation time 5338925448 ps
CPU time 75.25 seconds
Started Sep 03 11:36:05 PM UTC 24
Finished Sep 03 11:37:21 PM UTC 24
Peak memory 218344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942954986 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.2942954986
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/43.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.1225216888
Short name T764
Test name
Test status
Simulation time 336182806 ps
CPU time 8.02 seconds
Started Sep 03 11:35:59 PM UTC 24
Finished Sep 03 11:36:08 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225216888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1225216888
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/43.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.1048519917
Short name T774
Test name
Test status
Simulation time 42636544 ps
CPU time 7.27 seconds
Started Sep 03 11:36:09 PM UTC 24
Finished Sep 03 11:36:17 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048519917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.1048519917
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/44.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3358812648
Short name T900
Test name
Test status
Simulation time 148771146306 ps
CPU time 305.5 seconds
Started Sep 03 11:36:09 PM UTC 24
Finished Sep 03 11:41:18 PM UTC 24
Peak memory 219988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358812648 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.3358812648
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/44.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.723607652
Short name T776
Test name
Test status
Simulation time 88115434 ps
CPU time 5.25 seconds
Started Sep 03 11:36:12 PM UTC 24
Finished Sep 03 11:36:19 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723607652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.723607652
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/44.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.2691482672
Short name T785
Test name
Test status
Simulation time 1430991840 ps
CPU time 12.11 seconds
Started Sep 03 11:36:12 PM UTC 24
Finished Sep 03 11:36:25 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691482672 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2691482672
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/44.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random.951167005
Short name T771
Test name
Test status
Simulation time 300125206 ps
CPU time 5.66 seconds
Started Sep 03 11:36:09 PM UTC 24
Finished Sep 03 11:36:15 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951167005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.951167005
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/44.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.3793672962
Short name T775
Test name
Test status
Simulation time 1485916610 ps
CPU time 7.97 seconds
Started Sep 03 11:36:09 PM UTC 24
Finished Sep 03 11:36:18 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793672962 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.3793672962
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/44.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.4020620479
Short name T884
Test name
Test status
Simulation time 21890589228 ps
CPU time 128.79 seconds
Started Sep 03 11:36:09 PM UTC 24
Finished Sep 03 11:38:20 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020620479 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.4020620479
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/44.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.3808568075
Short name T769
Test name
Test status
Simulation time 24701108 ps
CPU time 3.26 seconds
Started Sep 03 11:36:09 PM UTC 24
Finished Sep 03 11:36:13 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808568075 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.3808568075
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/44.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.2508187901
Short name T772
Test name
Test status
Simulation time 93959587 ps
CPU time 2.82 seconds
Started Sep 03 11:36:12 PM UTC 24
Finished Sep 03 11:36:16 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508187901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.2508187901
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/44.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.695262006
Short name T759
Test name
Test status
Simulation time 10841953 ps
CPU time 1.65 seconds
Started Sep 03 11:36:05 PM UTC 24
Finished Sep 03 11:36:07 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695262006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.695262006
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/44.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1607939397
Short name T779
Test name
Test status
Simulation time 2553748301 ps
CPU time 13.32 seconds
Started Sep 03 11:36:06 PM UTC 24
Finished Sep 03 11:36:21 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607939397 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1607939397
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/44.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.3704409302
Short name T780
Test name
Test status
Simulation time 1252718336 ps
CPU time 14.77 seconds
Started Sep 03 11:36:06 PM UTC 24
Finished Sep 03 11:36:22 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704409302 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.3704409302
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/44.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.515815509
Short name T760
Test name
Test status
Simulation time 18578731 ps
CPU time 1.67 seconds
Started Sep 03 11:36:05 PM UTC 24
Finished Sep 03 11:36:07 PM UTC 24
Peak memory 211128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515815509 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.515815509
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/44.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.3364493379
Short name T784
Test name
Test status
Simulation time 62661098 ps
CPU time 11.94 seconds
Started Sep 03 11:36:12 PM UTC 24
Finished Sep 03 11:36:25 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364493379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.3364493379
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/44.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.553828653
Short name T825
Test name
Test status
Simulation time 3075742352 ps
CPU time 46.4 seconds
Started Sep 03 11:36:12 PM UTC 24
Finished Sep 03 11:37:00 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553828653 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.553828653
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/44.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.505523857
Short name T811
Test name
Test status
Simulation time 228136838 ps
CPU time 33.82 seconds
Started Sep 03 11:36:12 PM UTC 24
Finished Sep 03 11:36:47 PM UTC 24
Peak memory 214372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505523857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.505523857
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/44.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2292063306
Short name T887
Test name
Test status
Simulation time 7935500763 ps
CPU time 141.55 seconds
Started Sep 03 11:36:12 PM UTC 24
Finished Sep 03 11:38:36 PM UTC 24
Peak memory 218412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292063306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.2292063306
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/44.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.255086187
Short name T770
Test name
Test status
Simulation time 38276425 ps
CPU time 1.72 seconds
Started Sep 03 11:36:12 PM UTC 24
Finished Sep 03 11:36:15 PM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255086187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.255086187
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/44.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.712288878
Short name T802
Test name
Test status
Simulation time 3291984426 ps
CPU time 16.14 seconds
Started Sep 03 11:36:19 PM UTC 24
Finished Sep 03 11:36:36 PM UTC 24
Peak memory 212256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712288878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.712288878
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/45.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.3613292782
Short name T867
Test name
Test status
Simulation time 57138193217 ps
CPU time 68.88 seconds
Started Sep 03 11:36:20 PM UTC 24
Finished Sep 03 11:37:31 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613292782 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.3613292782
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/45.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.1030835579
Short name T797
Test name
Test status
Simulation time 1256902712 ps
CPU time 10.61 seconds
Started Sep 03 11:36:22 PM UTC 24
Finished Sep 03 11:36:34 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030835579 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.1030835579
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/45.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.2006232129
Short name T809
Test name
Test status
Simulation time 1292705637 ps
CPU time 22.87 seconds
Started Sep 03 11:36:20 PM UTC 24
Finished Sep 03 11:36:45 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006232129 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2006232129
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/45.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random.2897245183
Short name T790
Test name
Test status
Simulation time 78412727 ps
CPU time 8.69 seconds
Started Sep 03 11:36:18 PM UTC 24
Finished Sep 03 11:36:28 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897245183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.2897245183
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/45.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.3605864990
Short name T878
Test name
Test status
Simulation time 20835554449 ps
CPU time 96.18 seconds
Started Sep 03 11:36:19 PM UTC 24
Finished Sep 03 11:37:57 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605864990 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3605864990
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/45.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.2052426036
Short name T892
Test name
Test status
Simulation time 41066811460 ps
CPU time 165.33 seconds
Started Sep 03 11:36:19 PM UTC 24
Finished Sep 03 11:39:07 PM UTC 24
Peak memory 212100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052426036 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2052426036
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/45.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.2109255210
Short name T788
Test name
Test status
Simulation time 319786473 ps
CPU time 7.53 seconds
Started Sep 03 11:36:18 PM UTC 24
Finished Sep 03 11:36:27 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109255210 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2109255210
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/45.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.665837452
Short name T783
Test name
Test status
Simulation time 25813966 ps
CPU time 3.45 seconds
Started Sep 03 11:36:20 PM UTC 24
Finished Sep 03 11:36:25 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665837452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.665837452
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/45.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.441833326
Short name T773
Test name
Test status
Simulation time 14107446 ps
CPU time 1.72 seconds
Started Sep 03 11:36:14 PM UTC 24
Finished Sep 03 11:36:17 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441833326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.441833326
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/45.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.579285672
Short name T786
Test name
Test status
Simulation time 2311494411 ps
CPU time 8.09 seconds
Started Sep 03 11:36:16 PM UTC 24
Finished Sep 03 11:36:26 PM UTC 24
Peak memory 212512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579285672 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.579285672
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/45.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.3439795597
Short name T782
Test name
Test status
Simulation time 692805338 ps
CPU time 7.55 seconds
Started Sep 03 11:36:16 PM UTC 24
Finished Sep 03 11:36:25 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439795597 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.3439795597
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/45.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.2916035590
Short name T777
Test name
Test status
Simulation time 9760672 ps
CPU time 1.65 seconds
Started Sep 03 11:36:16 PM UTC 24
Finished Sep 03 11:36:19 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916035590 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.2916035590
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/45.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.2870689129
Short name T810
Test name
Test status
Simulation time 695401690 ps
CPU time 22.12 seconds
Started Sep 03 11:36:23 PM UTC 24
Finished Sep 03 11:36:47 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870689129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.2870689129
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/45.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.2750068783
Short name T800
Test name
Test status
Simulation time 273815549 ps
CPU time 6.85 seconds
Started Sep 03 11:36:27 PM UTC 24
Finished Sep 03 11:36:35 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750068783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.2750068783
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/45.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1180804489
Short name T885
Test name
Test status
Simulation time 3257268329 ps
CPU time 112.55 seconds
Started Sep 03 11:36:27 PM UTC 24
Finished Sep 03 11:38:22 PM UTC 24
Peak memory 216552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180804489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.1180804489
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/45.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.294367050
Short name T847
Test name
Test status
Simulation time 722705045 ps
CPU time 49.41 seconds
Started Sep 03 11:36:28 PM UTC 24
Finished Sep 03 11:37:18 PM UTC 24
Peak memory 214252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294367050 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.294367050
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/45.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.4197863879
Short name T787
Test name
Test status
Simulation time 34233209 ps
CPU time 3.65 seconds
Started Sep 03 11:36:22 PM UTC 24
Finished Sep 03 11:36:27 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197863879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.4197863879
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/45.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.2701597641
Short name T814
Test name
Test status
Simulation time 7149618305 ps
CPU time 17.22 seconds
Started Sep 03 11:36:31 PM UTC 24
Finished Sep 03 11:36:50 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701597641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2701597641
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/46.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1842562183
Short name T880
Test name
Test status
Simulation time 14072665397 ps
CPU time 93.71 seconds
Started Sep 03 11:36:33 PM UTC 24
Finished Sep 03 11:38:09 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842562183 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.1842562183
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/46.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.729955029
Short name T808
Test name
Test status
Simulation time 250875787 ps
CPU time 6.27 seconds
Started Sep 03 11:36:36 PM UTC 24
Finished Sep 03 11:36:44 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729955029 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.729955029
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/46.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.318470549
Short name T804
Test name
Test status
Simulation time 71601950 ps
CPU time 3.82 seconds
Started Sep 03 11:36:34 PM UTC 24
Finished Sep 03 11:36:39 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318470549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.318470549
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/46.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random.1732273445
Short name T795
Test name
Test status
Simulation time 1471689653 ps
CPU time 12.23 seconds
Started Sep 03 11:36:29 PM UTC 24
Finished Sep 03 11:36:43 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732273445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.1732273445
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/46.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.3297924111
Short name T874
Test name
Test status
Simulation time 45322092846 ps
CPU time 71.65 seconds
Started Sep 03 11:36:30 PM UTC 24
Finished Sep 03 11:37:43 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297924111 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3297924111
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/46.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3088531603
Short name T851
Test name
Test status
Simulation time 6538015158 ps
CPU time 48.02 seconds
Started Sep 03 11:36:31 PM UTC 24
Finished Sep 03 11:37:21 PM UTC 24
Peak memory 212520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088531603 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.3088531603
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/46.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.213959613
Short name T801
Test name
Test status
Simulation time 77122855 ps
CPU time 4.91 seconds
Started Sep 03 11:36:30 PM UTC 24
Finished Sep 03 11:36:36 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213959613 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.213959613
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/46.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.1309277521
Short name T818
Test name
Test status
Simulation time 2681048361 ps
CPU time 20.38 seconds
Started Sep 03 11:36:33 PM UTC 24
Finished Sep 03 11:36:55 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309277521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1309277521
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/46.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.2076010018
Short name T793
Test name
Test status
Simulation time 41397231 ps
CPU time 2.14 seconds
Started Sep 03 11:36:28 PM UTC 24
Finished Sep 03 11:36:31 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076010018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.2076010018
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/46.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1446884052
Short name T803
Test name
Test status
Simulation time 3857864372 ps
CPU time 8.25 seconds
Started Sep 03 11:36:28 PM UTC 24
Finished Sep 03 11:36:37 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446884052 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1446884052
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/46.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.3077138191
Short name T805
Test name
Test status
Simulation time 2810593402 ps
CPU time 10.57 seconds
Started Sep 03 11:36:28 PM UTC 24
Finished Sep 03 11:36:39 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077138191 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.3077138191
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/46.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.3965993150
Short name T792
Test name
Test status
Simulation time 8984399 ps
CPU time 1.51 seconds
Started Sep 03 11:36:28 PM UTC 24
Finished Sep 03 11:36:30 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965993150 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.3965993150
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/46.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.463832507
Short name T877
Test name
Test status
Simulation time 20002283622 ps
CPU time 78.34 seconds
Started Sep 03 11:36:36 PM UTC 24
Finished Sep 03 11:37:57 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463832507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.463832507
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/46.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1487796503
Short name T834
Test name
Test status
Simulation time 314073416 ps
CPU time 29.02 seconds
Started Sep 03 11:36:38 PM UTC 24
Finished Sep 03 11:37:08 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487796503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1487796503
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/46.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.2989438734
Short name T843
Test name
Test status
Simulation time 323446754 ps
CPU time 36.43 seconds
Started Sep 03 11:36:38 PM UTC 24
Finished Sep 03 11:37:16 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989438734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.2989438734
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/46.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.3633818815
Short name T856
Test name
Test status
Simulation time 293365094 ps
CPU time 42.24 seconds
Started Sep 03 11:36:38 PM UTC 24
Finished Sep 03 11:37:22 PM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633818815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.3633818815
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/46.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.990413944
Short name T815
Test name
Test status
Simulation time 2001571378 ps
CPU time 12.49 seconds
Started Sep 03 11:36:36 PM UTC 24
Finished Sep 03 11:36:50 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990413944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.990413944
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/46.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.4287881455
Short name T185
Test name
Test status
Simulation time 985541446 ps
CPU time 6.39 seconds
Started Sep 03 11:36:48 PM UTC 24
Finished Sep 03 11:36:56 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287881455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.4287881455
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/47.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.2504352758
Short name T898
Test name
Test status
Simulation time 32390939012 ps
CPU time 193.82 seconds
Started Sep 03 11:36:49 PM UTC 24
Finished Sep 03 11:40:05 PM UTC 24
Peak memory 214240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504352758 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.2504352758
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/47.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2376144738
Short name T823
Test name
Test status
Simulation time 257116014 ps
CPU time 5.23 seconds
Started Sep 03 11:36:52 PM UTC 24
Finished Sep 03 11:36:58 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376144738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.2376144738
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/47.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.1099866397
Short name T820
Test name
Test status
Simulation time 94841163 ps
CPU time 4.56 seconds
Started Sep 03 11:36:50 PM UTC 24
Finished Sep 03 11:36:56 PM UTC 24
Peak memory 212260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099866397 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1099866397
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/47.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random.3842659746
Short name T821
Test name
Test status
Simulation time 401724546 ps
CPU time 10.29 seconds
Started Sep 03 11:36:45 PM UTC 24
Finished Sep 03 11:36:57 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842659746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.3842659746
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/47.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.3871566382
Short name T176
Test name
Test status
Simulation time 44571195053 ps
CPU time 143.37 seconds
Started Sep 03 11:36:45 PM UTC 24
Finished Sep 03 11:39:11 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871566382 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3871566382
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/47.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.4158097427
Short name T888
Test name
Test status
Simulation time 56944567297 ps
CPU time 112.33 seconds
Started Sep 03 11:36:47 PM UTC 24
Finished Sep 03 11:38:41 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158097427 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.4158097427
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/47.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.3408011609
Short name T813
Test name
Test status
Simulation time 15856078 ps
CPU time 2.86 seconds
Started Sep 03 11:36:45 PM UTC 24
Finished Sep 03 11:36:49 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408011609 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.3408011609
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/47.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.576357898
Short name T830
Test name
Test status
Simulation time 1495248682 ps
CPU time 13.9 seconds
Started Sep 03 11:36:49 PM UTC 24
Finished Sep 03 11:37:04 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576357898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.576357898
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/47.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.1876455311
Short name T806
Test name
Test status
Simulation time 76372893 ps
CPU time 2.2 seconds
Started Sep 03 11:36:38 PM UTC 24
Finished Sep 03 11:36:42 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876455311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.1876455311
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/47.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.4278963604
Short name T817
Test name
Test status
Simulation time 2420683489 ps
CPU time 10.29 seconds
Started Sep 03 11:36:41 PM UTC 24
Finished Sep 03 11:36:52 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278963604 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.4278963604
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/47.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3212913665
Short name T822
Test name
Test status
Simulation time 6430670857 ps
CPU time 14.48 seconds
Started Sep 03 11:36:42 PM UTC 24
Finished Sep 03 11:36:58 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212913665 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3212913665
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/47.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1538821802
Short name T807
Test name
Test status
Simulation time 8984796 ps
CPU time 1.63 seconds
Started Sep 03 11:36:41 PM UTC 24
Finished Sep 03 11:36:44 PM UTC 24
Peak memory 211232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538821802 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.1538821802
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/47.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.4125269546
Short name T833
Test name
Test status
Simulation time 4687270368 ps
CPU time 15.3 seconds
Started Sep 03 11:36:52 PM UTC 24
Finished Sep 03 11:37:08 PM UTC 24
Peak memory 212264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125269546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.4125269546
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/47.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.1049457890
Short name T828
Test name
Test status
Simulation time 1842560028 ps
CPU time 7.65 seconds
Started Sep 03 11:36:54 PM UTC 24
Finished Sep 03 11:37:02 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049457890 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.1049457890
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/47.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2307018534
Short name T850
Test name
Test status
Simulation time 195423373 ps
CPU time 23.94 seconds
Started Sep 03 11:36:54 PM UTC 24
Finished Sep 03 11:37:19 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307018534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.2307018534
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/47.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.2954530914
Short name T827
Test name
Test status
Simulation time 236786133 ps
CPU time 6.02 seconds
Started Sep 03 11:36:54 PM UTC 24
Finished Sep 03 11:37:01 PM UTC 24
Peak memory 212332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954530914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.2954530914
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/47.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.3882576267
Short name T819
Test name
Test status
Simulation time 38386718 ps
CPU time 4.25 seconds
Started Sep 03 11:36:50 PM UTC 24
Finished Sep 03 11:36:55 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882576267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.3882576267
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/47.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.3011680237
Short name T112
Test name
Test status
Simulation time 669066128 ps
CPU time 7.89 seconds
Started Sep 03 11:37:01 PM UTC 24
Finished Sep 03 11:37:10 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011680237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.3011680237
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/48.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.448535755
Short name T899
Test name
Test status
Simulation time 26726442613 ps
CPU time 192.07 seconds
Started Sep 03 11:37:02 PM UTC 24
Finished Sep 03 11:40:18 PM UTC 24
Peak memory 212456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448535755 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.448535755
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/48.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.237671678
Short name T848
Test name
Test status
Simulation time 795681732 ps
CPU time 13.21 seconds
Started Sep 03 11:37:04 PM UTC 24
Finished Sep 03 11:37:19 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237671678 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.237671678
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/48.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.3580438336
Short name T837
Test name
Test status
Simulation time 676906983 ps
CPU time 7.42 seconds
Started Sep 03 11:37:03 PM UTC 24
Finished Sep 03 11:37:11 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580438336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3580438336
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/48.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random.3457176525
Short name T835
Test name
Test status
Simulation time 60741484 ps
CPU time 7.59 seconds
Started Sep 03 11:37:00 PM UTC 24
Finished Sep 03 11:37:09 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457176525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.3457176525
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/48.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.2331687619
Short name T875
Test name
Test status
Simulation time 19281566042 ps
CPU time 41.87 seconds
Started Sep 03 11:37:00 PM UTC 24
Finished Sep 03 11:37:44 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331687619 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2331687619
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/48.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3679420023
Short name T889
Test name
Test status
Simulation time 35979008597 ps
CPU time 103.48 seconds
Started Sep 03 11:37:00 PM UTC 24
Finished Sep 03 11:38:46 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679420023 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3679420023
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/48.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.597516719
Short name T829
Test name
Test status
Simulation time 9502534 ps
CPU time 1.61 seconds
Started Sep 03 11:37:00 PM UTC 24
Finished Sep 03 11:37:03 PM UTC 24
Peak memory 211144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597516719 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.597516719
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/48.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.769136884
Short name T845
Test name
Test status
Simulation time 1102476574 ps
CPU time 14.23 seconds
Started Sep 03 11:37:03 PM UTC 24
Finished Sep 03 11:37:18 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769136884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.769136884
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/48.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.1268457021
Short name T824
Test name
Test status
Simulation time 46581886 ps
CPU time 2.25 seconds
Started Sep 03 11:36:55 PM UTC 24
Finished Sep 03 11:36:58 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268457021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.1268457021
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/48.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.442682836
Short name T836
Test name
Test status
Simulation time 1452341079 ps
CPU time 10.63 seconds
Started Sep 03 11:36:58 PM UTC 24
Finished Sep 03 11:37:09 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442682836 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.442682836
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/48.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.2273976783
Short name T849
Test name
Test status
Simulation time 10875314503 ps
CPU time 19.75 seconds
Started Sep 03 11:36:58 PM UTC 24
Finished Sep 03 11:37:19 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273976783 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.2273976783
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/48.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2715637057
Short name T826
Test name
Test status
Simulation time 39001648 ps
CPU time 1.57 seconds
Started Sep 03 11:36:58 PM UTC 24
Finished Sep 03 11:37:00 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715637057 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.2715637057
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/48.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.1777566214
Short name T832
Test name
Test status
Simulation time 6008613 ps
CPU time 1.15 seconds
Started Sep 03 11:37:06 PM UTC 24
Finished Sep 03 11:37:08 PM UTC 24
Peak memory 202424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777566214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.1777566214
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/48.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1042551398
Short name T866
Test name
Test status
Simulation time 3815391189 ps
CPU time 19.22 seconds
Started Sep 03 11:37:09 PM UTC 24
Finished Sep 03 11:37:29 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042551398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.1042551398
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/48.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.4041649328
Short name T839
Test name
Test status
Simulation time 71199957 ps
CPU time 5.83 seconds
Started Sep 03 11:37:07 PM UTC 24
Finished Sep 03 11:37:14 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041649328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.4041649328
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/48.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.335690087
Short name T893
Test name
Test status
Simulation time 2035344410 ps
CPU time 139.09 seconds
Started Sep 03 11:37:09 PM UTC 24
Finished Sep 03 11:39:30 PM UTC 24
Peak memory 216232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335690087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.335690087
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/48.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.2523675114
Short name T841
Test name
Test status
Simulation time 762926261 ps
CPU time 8.88 seconds
Started Sep 03 11:37:04 PM UTC 24
Finished Sep 03 11:37:14 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523675114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2523675114
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/48.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.4101269180
Short name T860
Test name
Test status
Simulation time 587443726 ps
CPU time 8.79 seconds
Started Sep 03 11:37:16 PM UTC 24
Finished Sep 03 11:37:26 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101269180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.4101269180
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/49.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.440586807
Short name T896
Test name
Test status
Simulation time 28282753281 ps
CPU time 158.76 seconds
Started Sep 03 11:37:16 PM UTC 24
Finished Sep 03 11:39:57 PM UTC 24
Peak memory 214436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440586807 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.440586807
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/49.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1465181077
Short name T857
Test name
Test status
Simulation time 58792446 ps
CPU time 3.63 seconds
Started Sep 03 11:37:18 PM UTC 24
Finished Sep 03 11:37:23 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465181077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.1465181077
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/49.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.132476197
Short name T852
Test name
Test status
Simulation time 49973179 ps
CPU time 4.12 seconds
Started Sep 03 11:37:16 PM UTC 24
Finished Sep 03 11:37:21 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132476197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.132476197
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/49.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random.3001886884
Short name T861
Test name
Test status
Simulation time 3659527436 ps
CPU time 13.08 seconds
Started Sep 03 11:37:12 PM UTC 24
Finished Sep 03 11:37:26 PM UTC 24
Peak memory 212512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001886884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.3001886884
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/49.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.1021382807
Short name T894
Test name
Test status
Simulation time 42617287696 ps
CPU time 145.14 seconds
Started Sep 03 11:37:14 PM UTC 24
Finished Sep 03 11:39:41 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021382807 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.1021382807
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/49.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.1495575665
Short name T890
Test name
Test status
Simulation time 14124643646 ps
CPU time 89.37 seconds
Started Sep 03 11:37:16 PM UTC 24
Finished Sep 03 11:38:47 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495575665 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.1495575665
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/49.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.3805284109
Short name T844
Test name
Test status
Simulation time 113227621 ps
CPU time 3.66 seconds
Started Sep 03 11:37:12 PM UTC 24
Finished Sep 03 11:37:17 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805284109 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.3805284109
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/49.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.374086998
Short name T863
Test name
Test status
Simulation time 1153895356 ps
CPU time 10.28 seconds
Started Sep 03 11:37:16 PM UTC 24
Finished Sep 03 11:37:28 PM UTC 24
Peak memory 212104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374086998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.374086998
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/49.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.1852863863
Short name T840
Test name
Test status
Simulation time 11147608 ps
CPU time 1.21 seconds
Started Sep 03 11:37:12 PM UTC 24
Finished Sep 03 11:37:14 PM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852863863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1852863863
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/49.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.353191362
Short name T859
Test name
Test status
Simulation time 5235250524 ps
CPU time 12.21 seconds
Started Sep 03 11:37:12 PM UTC 24
Finished Sep 03 11:37:25 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353191362 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.353191362
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/49.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1111929542
Short name T855
Test name
Test status
Simulation time 3085386281 ps
CPU time 8.51 seconds
Started Sep 03 11:37:12 PM UTC 24
Finished Sep 03 11:37:22 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111929542 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.1111929542
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/49.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.2077023701
Short name T842
Test name
Test status
Simulation time 10363272 ps
CPU time 1.42 seconds
Started Sep 03 11:37:12 PM UTC 24
Finished Sep 03 11:37:14 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077023701 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.2077023701
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/49.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.2261832152
Short name T873
Test name
Test status
Simulation time 1110301580 ps
CPU time 15.25 seconds
Started Sep 03 11:37:21 PM UTC 24
Finished Sep 03 11:37:38 PM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261832152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.2261832152
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/49.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.765930851
Short name T872
Test name
Test status
Simulation time 147073790 ps
CPU time 13.78 seconds
Started Sep 03 11:37:22 PM UTC 24
Finished Sep 03 11:37:37 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765930851 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.765930851
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/49.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1070700922
Short name T868
Test name
Test status
Simulation time 56892949 ps
CPU time 8.41 seconds
Started Sep 03 11:37:21 PM UTC 24
Finished Sep 03 11:37:31 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070700922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.1070700922
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/49.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.1411820023
Short name T870
Test name
Test status
Simulation time 47638842 ps
CPU time 10.46 seconds
Started Sep 03 11:37:22 PM UTC 24
Finished Sep 03 11:37:33 PM UTC 24
Peak memory 212332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411820023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.1411820023
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/49.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.3535436372
Short name T858
Test name
Test status
Simulation time 197309811 ps
CPU time 4.88 seconds
Started Sep 03 11:37:18 PM UTC 24
Finished Sep 03 11:37:24 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535436372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3535436372
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/49.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device.1072523546
Short name T256
Test name
Test status
Simulation time 45555392 ps
CPU time 7.21 seconds
Started Sep 03 11:28:37 PM UTC 24
Finished Sep 03 11:28:46 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072523546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1072523546
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/5.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.1862004043
Short name T350
Test name
Test status
Simulation time 477546615 ps
CPU time 8.41 seconds
Started Sep 03 11:28:40 PM UTC 24
Finished Sep 03 11:28:49 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862004043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1862004043
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/5.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_error_random.2181096136
Short name T217
Test name
Test status
Simulation time 2047693963 ps
CPU time 11.85 seconds
Started Sep 03 11:28:40 PM UTC 24
Finished Sep 03 11:28:52 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181096136 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.2181096136
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/5.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random.2949904382
Short name T316
Test name
Test status
Simulation time 2631278572 ps
CPU time 12.59 seconds
Started Sep 03 11:28:35 PM UTC 24
Finished Sep 03 11:28:49 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949904382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.2949904382
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/5.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_large_delays.2655941116
Short name T319
Test name
Test status
Simulation time 16419586074 ps
CPU time 55.59 seconds
Started Sep 03 11:28:35 PM UTC 24
Finished Sep 03 11:29:33 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655941116 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.2655941116
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/5.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_slow_rsp.4093781412
Short name T220
Test name
Test status
Simulation time 3524391449 ps
CPU time 16.9 seconds
Started Sep 03 11:28:35 PM UTC 24
Finished Sep 03 11:28:54 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093781412 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.4093781412
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/5.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_zero_delays.2661226681
Short name T50
Test name
Test status
Simulation time 37687516 ps
CPU time 6.12 seconds
Started Sep 03 11:28:35 PM UTC 24
Finished Sep 03 11:28:43 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661226681 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.2661226681
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/5.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke.782322162
Short name T172
Test name
Test status
Simulation time 10109176 ps
CPU time 1.35 seconds
Started Sep 03 11:28:34 PM UTC 24
Finished Sep 03 11:28:36 PM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782322162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.782322162
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/5.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_large_delays.2443927176
Short name T60
Test name
Test status
Simulation time 1817835256 ps
CPU time 10.96 seconds
Started Sep 03 11:28:34 PM UTC 24
Finished Sep 03 11:28:46 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443927176 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.2443927176
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/5.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.600389195
Short name T348
Test name
Test status
Simulation time 1419645141 ps
CPU time 11.79 seconds
Started Sep 03 11:28:35 PM UTC 24
Finished Sep 03 11:28:48 PM UTC 24
Peak memory 212316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600389195 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.600389195
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/5.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.2075836134
Short name T49
Test name
Test status
Simulation time 16331235 ps
CPU time 1.54 seconds
Started Sep 03 11:28:34 PM UTC 24
Finished Sep 03 11:28:37 PM UTC 24
Peak memory 211128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075836134 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.2075836134
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/5.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all.2580570629
Short name T212
Test name
Test status
Simulation time 72390115 ps
CPU time 7.61 seconds
Started Sep 03 11:28:41 PM UTC 24
Finished Sep 03 11:28:49 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580570629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.2580570629
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/5.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_error.1664405787
Short name T91
Test name
Test status
Simulation time 6176492236 ps
CPU time 78.09 seconds
Started Sep 03 11:28:43 PM UTC 24
Finished Sep 03 11:30:03 PM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664405787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.1664405787
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/5.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.4010116349
Short name T329
Test name
Test status
Simulation time 3439672919 ps
CPU time 82.12 seconds
Started Sep 03 11:28:42 PM UTC 24
Finished Sep 03 11:30:06 PM UTC 24
Peak memory 216296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010116349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.4010116349
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/5.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.3737564441
Short name T334
Test name
Test status
Simulation time 427353035 ps
CPU time 43.67 seconds
Started Sep 03 11:28:43 PM UTC 24
Finished Sep 03 11:29:28 PM UTC 24
Peak memory 216232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737564441 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.3737564441
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/5.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_unmapped_addr.2350974740
Short name T51
Test name
Test status
Simulation time 36042068 ps
CPU time 2.2 seconds
Started Sep 03 11:28:40 PM UTC 24
Finished Sep 03 11:28:43 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350974740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.2350974740
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/5.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device.2859786685
Short name T292
Test name
Test status
Simulation time 4662558486 ps
CPU time 23.58 seconds
Started Sep 03 11:28:47 PM UTC 24
Finished Sep 03 11:29:12 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859786685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2859786685
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/6.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.1398715659
Short name T285
Test name
Test status
Simulation time 14497817805 ps
CPU time 84.67 seconds
Started Sep 03 11:28:48 PM UTC 24
Finished Sep 03 11:30:15 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398715659 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.1398715659
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/6.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.4090370430
Short name T354
Test name
Test status
Simulation time 1671604414 ps
CPU time 10.92 seconds
Started Sep 03 11:28:49 PM UTC 24
Finished Sep 03 11:29:01 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090370430 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.4090370430
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/6.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_error_random.1806751996
Short name T219
Test name
Test status
Simulation time 329245069 ps
CPU time 4.05 seconds
Started Sep 03 11:28:48 PM UTC 24
Finished Sep 03 11:28:54 PM UTC 24
Peak memory 212452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806751996 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1806751996
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/6.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random.3332807424
Short name T349
Test name
Test status
Simulation time 16287653 ps
CPU time 1.33 seconds
Started Sep 03 11:28:47 PM UTC 24
Finished Sep 03 11:28:49 PM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332807424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.3332807424
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/6.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_large_delays.578930906
Short name T428
Test name
Test status
Simulation time 35030910036 ps
CPU time 124.41 seconds
Started Sep 03 11:28:47 PM UTC 24
Finished Sep 03 11:30:53 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578930906 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.578930906
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/6.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_slow_rsp.73742755
Short name T28
Test name
Test status
Simulation time 13027804153 ps
CPU time 22.03 seconds
Started Sep 03 11:28:47 PM UTC 24
Finished Sep 03 11:29:10 PM UTC 24
Peak memory 212184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73742755 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.73742755
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/6.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_zero_delays.4233853176
Short name T214
Test name
Test status
Simulation time 69581876 ps
CPU time 3.54 seconds
Started Sep 03 11:28:47 PM UTC 24
Finished Sep 03 11:28:51 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233853176 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.4233853176
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/6.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_same_source.3500429740
Short name T215
Test name
Test status
Simulation time 15418409 ps
CPU time 2.15 seconds
Started Sep 03 11:28:48 PM UTC 24
Finished Sep 03 11:28:52 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500429740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3500429740
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/6.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke.2994023987
Short name T347
Test name
Test status
Simulation time 13277149 ps
CPU time 1.54 seconds
Started Sep 03 11:28:43 PM UTC 24
Finished Sep 03 11:28:46 PM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994023987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2994023987
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/6.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_large_delays.1702093731
Short name T64
Test name
Test status
Simulation time 2004698994 ps
CPU time 11.83 seconds
Started Sep 03 11:28:45 PM UTC 24
Finished Sep 03 11:28:57 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702093731 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.1702093731
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/6.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.909655193
Short name T309
Test name
Test status
Simulation time 2926578363 ps
CPU time 15.65 seconds
Started Sep 03 11:28:45 PM UTC 24
Finished Sep 03 11:29:01 PM UTC 24
Peak memory 212184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909655193 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.909655193
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/6.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.375387700
Short name T183
Test name
Test status
Simulation time 11273108 ps
CPU time 1.39 seconds
Started Sep 03 11:28:43 PM UTC 24
Finished Sep 03 11:28:46 PM UTC 24
Peak memory 211128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375387700 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.375387700
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/6.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all.1951711823
Short name T341
Test name
Test status
Simulation time 104063919 ps
CPU time 15.9 seconds
Started Sep 03 11:28:50 PM UTC 24
Finished Sep 03 11:29:07 PM UTC 24
Peak memory 214376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951711823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1951711823
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/6.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_error.2958199206
Short name T385
Test name
Test status
Simulation time 15762730148 ps
CPU time 59.62 seconds
Started Sep 03 11:28:50 PM UTC 24
Finished Sep 03 11:29:51 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958199206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.2958199206
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/6.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.1207206956
Short name T321
Test name
Test status
Simulation time 369869370 ps
CPU time 42.65 seconds
Started Sep 03 11:28:50 PM UTC 24
Finished Sep 03 11:29:34 PM UTC 24
Peak memory 216488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207206956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.1207206956
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/6.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.2299061901
Short name T322
Test name
Test status
Simulation time 739116793 ps
CPU time 75 seconds
Started Sep 03 11:28:50 PM UTC 24
Finished Sep 03 11:30:07 PM UTC 24
Peak memory 214380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299061901 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.2299061901
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/6.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_unmapped_addr.3441843887
Short name T351
Test name
Test status
Simulation time 90888173 ps
CPU time 5.71 seconds
Started Sep 03 11:28:49 PM UTC 24
Finished Sep 03 11:28:55 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441843887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3441843887
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/6.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device.522673975
Short name T62
Test name
Test status
Simulation time 1036889660 ps
CPU time 6.66 seconds
Started Sep 03 11:28:55 PM UTC 24
Finished Sep 03 11:29:02 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522673975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.522673975
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/7.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.2825354844
Short name T7
Test name
Test status
Simulation time 88880646 ps
CPU time 2.63 seconds
Started Sep 03 11:28:56 PM UTC 24
Finished Sep 03 11:29:00 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825354844 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.2825354844
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/7.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_error_random.3397765033
Short name T355
Test name
Test status
Simulation time 53923410 ps
CPU time 5.54 seconds
Started Sep 03 11:28:55 PM UTC 24
Finished Sep 03 11:29:01 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397765033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3397765033
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/7.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random.3188207264
Short name T352
Test name
Test status
Simulation time 62657015 ps
CPU time 3.79 seconds
Started Sep 03 11:28:52 PM UTC 24
Finished Sep 03 11:28:57 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188207264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.3188207264
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/7.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_large_delays.3405696756
Short name T401
Test name
Test status
Simulation time 15850522461 ps
CPU time 80.15 seconds
Started Sep 03 11:28:54 PM UTC 24
Finished Sep 03 11:30:15 PM UTC 24
Peak memory 211772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405696756 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3405696756
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/7.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_slow_rsp.3169374469
Short name T94
Test name
Test status
Simulation time 39258025300 ps
CPU time 97.57 seconds
Started Sep 03 11:28:54 PM UTC 24
Finished Sep 03 11:30:33 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169374469 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.3169374469
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/7.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_zero_delays.236144278
Short name T353
Test name
Test status
Simulation time 93853695 ps
CPU time 6 seconds
Started Sep 03 11:28:52 PM UTC 24
Finished Sep 03 11:28:59 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236144278 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.236144278
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/7.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_same_source.44041636
Short name T66
Test name
Test status
Simulation time 790105844 ps
CPU time 11.14 seconds
Started Sep 03 11:28:55 PM UTC 24
Finished Sep 03 11:29:07 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44041636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.44041636
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/7.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke.782526697
Short name T216
Test name
Test status
Simulation time 10856394 ps
CPU time 1.21 seconds
Started Sep 03 11:28:50 PM UTC 24
Finished Sep 03 11:28:52 PM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782526697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.782526697
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/7.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_large_delays.2643105005
Short name T65
Test name
Test status
Simulation time 5321148542 ps
CPU time 7.1 seconds
Started Sep 03 11:28:51 PM UTC 24
Finished Sep 03 11:28:59 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643105005 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2643105005
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/7.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3182095445
Short name T359
Test name
Test status
Simulation time 2874869147 ps
CPU time 11.9 seconds
Started Sep 03 11:28:52 PM UTC 24
Finished Sep 03 11:29:05 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182095445 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3182095445
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/7.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.3246512788
Short name T218
Test name
Test status
Simulation time 18209855 ps
CPU time 1.3 seconds
Started Sep 03 11:28:51 PM UTC 24
Finished Sep 03 11:28:53 PM UTC 24
Peak memory 211176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246512788 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.3246512788
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/7.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all.1410171465
Short name T297
Test name
Test status
Simulation time 7813894063 ps
CPU time 89.85 seconds
Started Sep 03 11:28:57 PM UTC 24
Finished Sep 03 11:30:29 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410171465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1410171465
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/7.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_error.1272296495
Short name T343
Test name
Test status
Simulation time 133127796 ps
CPU time 5.8 seconds
Started Sep 03 11:28:59 PM UTC 24
Finished Sep 03 11:29:06 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272296495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.1272296495
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/7.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.2704917644
Short name T162
Test name
Test status
Simulation time 2709470754 ps
CPU time 116.11 seconds
Started Sep 03 11:28:59 PM UTC 24
Finished Sep 03 11:30:57 PM UTC 24
Peak memory 218340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704917644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.2704917644
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/7.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.3093405468
Short name T272
Test name
Test status
Simulation time 6390525201 ps
CPU time 79.68 seconds
Started Sep 03 11:28:59 PM UTC 24
Finished Sep 03 11:30:20 PM UTC 24
Peak memory 214248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093405468 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.3093405468
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/7.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_unmapped_addr.136322210
Short name T358
Test name
Test status
Simulation time 905408460 ps
CPU time 5.55 seconds
Started Sep 03 11:28:56 PM UTC 24
Finished Sep 03 11:29:03 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136322210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.136322210
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/7.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device.3749952273
Short name T241
Test name
Test status
Simulation time 67580023 ps
CPU time 8.79 seconds
Started Sep 03 11:29:03 PM UTC 24
Finished Sep 03 11:29:13 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749952273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.3749952273
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/8.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.2584049714
Short name T367
Test name
Test status
Simulation time 319450035 ps
CPU time 6.27 seconds
Started Sep 03 11:29:04 PM UTC 24
Finished Sep 03 11:29:11 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584049714 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.2584049714
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/8.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_error_random.234042216
Short name T360
Test name
Test status
Simulation time 204543574 ps
CPU time 3.23 seconds
Started Sep 03 11:29:04 PM UTC 24
Finished Sep 03 11:29:08 PM UTC 24
Peak memory 212116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234042216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.234042216
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/8.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random.9825853
Short name T362
Test name
Test status
Simulation time 85113718 ps
CPU time 6.13 seconds
Started Sep 03 11:29:02 PM UTC 24
Finished Sep 03 11:29:09 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9825853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_T
EST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs
/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.9825853
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/8.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_large_delays.1545316620
Short name T131
Test name
Test status
Simulation time 88277207912 ps
CPU time 145.85 seconds
Started Sep 03 11:29:02 PM UTC 24
Finished Sep 03 11:31:30 PM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545316620 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1545316620
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/8.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_slow_rsp.7899399
Short name T243
Test name
Test status
Simulation time 1980520743 ps
CPU time 10.29 seconds
Started Sep 03 11:29:02 PM UTC 24
Finished Sep 03 11:29:13 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7899399 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.7899399
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/8.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_zero_delays.4293055594
Short name T364
Test name
Test status
Simulation time 57533050 ps
CPU time 6.48 seconds
Started Sep 03 11:29:02 PM UTC 24
Finished Sep 03 11:29:09 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293055594 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.4293055594
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/8.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_same_source.103412601
Short name T166
Test name
Test status
Simulation time 1521808502 ps
CPU time 17.59 seconds
Started Sep 03 11:29:03 PM UTC 24
Finished Sep 03 11:29:22 PM UTC 24
Peak memory 212328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103412601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.103412601
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/8.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke.3198362389
Short name T356
Test name
Test status
Simulation time 10777363 ps
CPU time 1.4 seconds
Started Sep 03 11:29:00 PM UTC 24
Finished Sep 03 11:29:03 PM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198362389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3198362389
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/8.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_large_delays.2506173683
Short name T173
Test name
Test status
Simulation time 2122867854 ps
CPU time 11.34 seconds
Started Sep 03 11:29:00 PM UTC 24
Finished Sep 03 11:29:13 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506173683 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.2506173683
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/8.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.1299587888
Short name T361
Test name
Test status
Simulation time 1476005516 ps
CPU time 7.2 seconds
Started Sep 03 11:29:00 PM UTC 24
Finished Sep 03 11:29:09 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299587888 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.1299587888
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/8.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.727088128
Short name T357
Test name
Test status
Simulation time 9197928 ps
CPU time 1.55 seconds
Started Sep 03 11:29:00 PM UTC 24
Finished Sep 03 11:29:03 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727088128 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.727088128
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/8.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all.3069361735
Short name T69
Test name
Test status
Simulation time 918528978 ps
CPU time 12.64 seconds
Started Sep 03 11:29:05 PM UTC 24
Finished Sep 03 11:29:19 PM UTC 24
Peak memory 212324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069361735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.3069361735
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/8.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_error.4121546975
Short name T384
Test name
Test status
Simulation time 878939255 ps
CPU time 42.17 seconds
Started Sep 03 11:29:07 PM UTC 24
Finished Sep 03 11:29:50 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121546975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.4121546975
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/8.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.877564760
Short name T326
Test name
Test status
Simulation time 2135226339 ps
CPU time 126.32 seconds
Started Sep 03 11:29:05 PM UTC 24
Finished Sep 03 11:31:14 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877564760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.877564760
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/8.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.3688532740
Short name T323
Test name
Test status
Simulation time 711209414 ps
CPU time 74.93 seconds
Started Sep 03 11:29:07 PM UTC 24
Finished Sep 03 11:30:23 PM UTC 24
Peak memory 218280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688532740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.3688532740
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/8.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_unmapped_addr.1827669028
Short name T363
Test name
Test status
Simulation time 29933008 ps
CPU time 3.72 seconds
Started Sep 03 11:29:04 PM UTC 24
Finished Sep 03 11:29:09 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827669028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1827669028
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/8.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device.1112211900
Short name T168
Test name
Test status
Simulation time 98462478 ps
CPU time 11.91 seconds
Started Sep 03 11:29:12 PM UTC 24
Finished Sep 03 11:29:25 PM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112211900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1112211900
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/9.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.1204838220
Short name T181
Test name
Test status
Simulation time 37643735941 ps
CPU time 170.94 seconds
Started Sep 03 11:29:12 PM UTC 24
Finished Sep 03 11:32:05 PM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204838220 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.1204838220
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/9.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.2806994951
Short name T246
Test name
Test status
Simulation time 54350306 ps
CPU time 2.54 seconds
Started Sep 03 11:29:14 PM UTC 24
Finished Sep 03 11:29:18 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806994951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.2806994951
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/9.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_error_random.2414730239
Short name T164
Test name
Test status
Simulation time 527349037 ps
CPU time 4.67 seconds
Started Sep 03 11:29:14 PM UTC 24
Finished Sep 03 11:29:20 PM UTC 24
Peak memory 212132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414730239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2414730239
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/9.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random.2210511184
Short name T68
Test name
Test status
Simulation time 348547563 ps
CPU time 5.9 seconds
Started Sep 03 11:29:10 PM UTC 24
Finished Sep 03 11:29:17 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210511184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.2210511184
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/9.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_large_delays.4064790906
Short name T85
Test name
Test status
Simulation time 16175112693 ps
CPU time 75.65 seconds
Started Sep 03 11:29:10 PM UTC 24
Finished Sep 03 11:30:28 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064790906 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.4064790906
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/9.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_slow_rsp.3938028261
Short name T476
Test name
Test status
Simulation time 25956239084 ps
CPU time 161.03 seconds
Started Sep 03 11:29:10 PM UTC 24
Finished Sep 03 11:31:54 PM UTC 24
Peak memory 212456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938028261 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.3938028261
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/9.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_zero_delays.453148664
Short name T247
Test name
Test status
Simulation time 228382725 ps
CPU time 7.01 seconds
Started Sep 03 11:29:10 PM UTC 24
Finished Sep 03 11:29:18 PM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453148664 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.453148664
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/9.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_same_source.1269682427
Short name T245
Test name
Test status
Simulation time 34925514 ps
CPU time 3.25 seconds
Started Sep 03 11:29:12 PM UTC 24
Finished Sep 03 11:29:16 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269682427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1269682427
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/9.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke.3716287575
Short name T366
Test name
Test status
Simulation time 72639240 ps
CPU time 2.33 seconds
Started Sep 03 11:29:08 PM UTC 24
Finished Sep 03 11:29:11 PM UTC 24
Peak memory 212128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716287575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3716287575
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/9.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_large_delays.3037775174
Short name T70
Test name
Test status
Simulation time 2281699501 ps
CPU time 10.84 seconds
Started Sep 03 11:29:09 PM UTC 24
Finished Sep 03 11:29:21 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037775174 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3037775174
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/9.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.2654273473
Short name T163
Test name
Test status
Simulation time 4251272872 ps
CPU time 8.54 seconds
Started Sep 03 11:29:10 PM UTC 24
Finished Sep 03 11:29:20 PM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654273473 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2654273473
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/9.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.908085666
Short name T365
Test name
Test status
Simulation time 10959075 ps
CPU time 1.61 seconds
Started Sep 03 11:29:08 PM UTC 24
Finished Sep 03 11:29:10 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908085666 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.908085666
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/9.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all.1149803262
Short name T244
Test name
Test status
Simulation time 286085514 ps
CPU time 33.12 seconds
Started Sep 03 11:29:14 PM UTC 24
Finished Sep 03 11:29:49 PM UTC 24
Peak memory 214372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149803262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1149803262
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/9.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_error.749824796
Short name T278
Test name
Test status
Simulation time 3851555902 ps
CPU time 54.03 seconds
Started Sep 03 11:29:16 PM UTC 24
Finished Sep 03 11:30:11 PM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749824796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.749824796
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/9.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.2713953890
Short name T335
Test name
Test status
Simulation time 266473845 ps
CPU time 39.09 seconds
Started Sep 03 11:29:16 PM UTC 24
Finished Sep 03 11:29:56 PM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713953890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.2713953890
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/9.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.3595022912
Short name T336
Test name
Test status
Simulation time 833427629 ps
CPU time 124.42 seconds
Started Sep 03 11:29:16 PM UTC 24
Finished Sep 03 11:31:22 PM UTC 24
Peak memory 218476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595022912 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.3595022912
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/9.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_unmapped_addr.3601470149
Short name T167
Test name
Test status
Simulation time 187330085 ps
CPU time 6.89 seconds
Started Sep 03 11:29:14 PM UTC 24
Finished Sep 03 11:29:22 PM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601470149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3601470149
Directory /workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/9.xbar_unmapped_addr/latest
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