Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	446	1			T45	2		T28	1		T175	3
all_values[1]	475	1			T53	1		T59	2		T77	4
all_values[2]	432	1			T53	2		T45	1		T28	2
all_values[3]	470	1			T53	2		T26	1		T77	1
all_values[4]	463	1			T53	3		T28	2		T77	2
all_values[5]	466	1			T53	1		T45	1		T77	2
all_values[6]	453	1			T53	4		T28	1		T77	1
all_values[7]	452	1			T18	2		T28	2		T75	1
all_values[8]	468	1			T30	1		T53	2		T26	1
all_values[9]	464	1			T53	2		T28	2		T175	1
all_values[10]	434	1			T30	1		T53	1		T175	1
all_values[11]	429	1			T45	2		T28	2		T59	1
all_values[12]	429	1			T28	1		T175	1		T177	1
all_values[13]	470	1			T30	2		T26	2		T59	2
all_values[14]	461	1			T53	3		T26	3		T45	3
all_values[15]	439	1			T18	1		T26	1		T28	1
all_values[16]	466	1			T18	1		T26	1		T45	1
all_values[17]	466	1			T45	1		T28	2		T59	1
all_values[18]	409	1			T18	1		T53	1		T28	1
all_values[19]	394	1			T53	1		T45	1		T75	1
all_values[20]	451	1			T26	1		T77	3		T177	1
all_values[21]	460	1			T18	1		T53	1		T77	2
all_values[22]	415	1			T30	1		T175	1		T77	2
all_values[23]	442	1			T53	1		T26	1		T59	1
all_values[24]	417	1			T53	1		T45	3		T28	1
all_values[25]	449	1			T18	2		T57	1		T53	1
all_values[26]	460	1			T53	1		T45	2		T175	5