Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	471	1			T30	1		T265	1		T269	1
all_values[1]	443	1			T49	2		T8	2		T265	2
all_values[2]	474	1			T42	1		T8	5		T241	3
all_values[3]	414	1			T23	1		T8	2		T241	3
all_values[4]	463	1			T30	1		T41	1		T8	2
all_values[5]	473	1			T30	1		T41	1		T49	1
all_values[6]	442	1			T30	1		T49	1		T8	1
all_values[7]	481	1			T30	4		T42	1		T8	1
all_values[8]	448	1			T8	1		T265	2		T241	4
all_values[9]	460	1			T23	1		T265	1		T53	1
all_values[10]	425	1			T41	1		T8	1		T241	1
all_values[11]	423	1			T23	1		T30	1		T41	1
all_values[12]	446	1			T30	1		T8	3		T241	1
all_values[13]	442	1			T42	5		T49	2		T8	1
all_values[14]	466	1			T23	1		T41	1		T42	1
all_values[15]	443	1			T30	2		T41	2		T49	2
all_values[16]	423	1			T23	1		T42	1		T49	1
all_values[17]	466	1			T23	1		T41	3		T8	4
all_values[18]	415	1			T42	2		T8	4		T265	1
all_values[19]	456	1			T42	2		T49	2		T8	2
all_values[20]	451	1			T42	2		T242	2		T155	2
all_values[21]	424	1			T23	1		T30	1		T42	1
all_values[22]	428	1			T23	1		T49	1		T265	2
all_values[23]	439	1			T42	1		T49	2		T8	3
all_values[24]	481	1			T30	1		T8	2		T53	2
all_values[25]	408	1			T30	1		T42	1		T8	4
all_values[26]	454	1			T41	2		T265	1		T241	1