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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.24 100.00 95.42 100.00 100.00 100.00 100.00


Total test records in report: 900
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T773 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.2524032414 Sep 11 02:50:25 AM UTC 24 Sep 11 02:51:32 AM UTC 24 3651511337 ps
T774 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.1012681091 Sep 11 02:51:26 AM UTC 24 Sep 11 02:51:33 AM UTC 24 1868378785 ps
T775 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.3724940275 Sep 11 02:51:13 AM UTC 24 Sep 11 02:51:33 AM UTC 24 158823239 ps
T776 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.1722129393 Sep 11 02:51:29 AM UTC 24 Sep 11 02:51:34 AM UTC 24 154835342 ps
T777 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.874945337 Sep 11 02:51:13 AM UTC 24 Sep 11 02:51:35 AM UTC 24 1052853729 ps
T778 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.191156029 Sep 11 02:51:20 AM UTC 24 Sep 11 02:51:36 AM UTC 24 976401622 ps
T779 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.3301295403 Sep 11 02:51:05 AM UTC 24 Sep 11 02:51:36 AM UTC 24 6226081074 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.2126603790 Sep 11 02:48:53 AM UTC 24 Sep 11 02:51:36 AM UTC 24 300867521339 ps
T780 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.3340928528 Sep 11 02:51:33 AM UTC 24 Sep 11 02:51:37 AM UTC 24 105775332 ps
T781 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.778076614 Sep 11 02:51:35 AM UTC 24 Sep 11 02:51:38 AM UTC 24 28571511 ps
T782 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.3442377122 Sep 11 02:51:23 AM UTC 24 Sep 11 02:51:38 AM UTC 24 8365473150 ps
T783 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2714145018 Sep 11 02:51:31 AM UTC 24 Sep 11 02:51:39 AM UTC 24 168141863 ps
T784 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.3113323824 Sep 11 02:50:15 AM UTC 24 Sep 11 02:51:39 AM UTC 24 17634790007 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2403135747 Sep 11 02:49:31 AM UTC 24 Sep 11 02:51:40 AM UTC 24 149497893511 ps
T785 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.1992923345 Sep 11 02:50:23 AM UTC 24 Sep 11 02:51:41 AM UTC 24 399371321 ps
T786 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.4268690331 Sep 11 02:50:06 AM UTC 24 Sep 11 02:51:41 AM UTC 24 20245451200 ps
T787 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.590699550 Sep 11 02:51:29 AM UTC 24 Sep 11 02:51:42 AM UTC 24 1447009931 ps
T788 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.3551045244 Sep 11 02:51:31 AM UTC 24 Sep 11 02:51:43 AM UTC 24 229441223 ps
T789 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.123842163 Sep 11 02:51:40 AM UTC 24 Sep 11 02:51:43 AM UTC 24 14524728 ps
T790 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.4024539956 Sep 11 02:51:39 AM UTC 24 Sep 11 02:51:44 AM UTC 24 22489370 ps
T791 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random.3440162532 Sep 11 02:51:35 AM UTC 24 Sep 11 02:51:44 AM UTC 24 52675399 ps
T792 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.3700839910 Sep 11 02:51:35 AM UTC 24 Sep 11 02:51:45 AM UTC 24 2767992303 ps
T793 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.2254409909 Sep 11 02:51:40 AM UTC 24 Sep 11 02:51:45 AM UTC 24 173289022 ps
T794 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.1331538306 Sep 11 02:51:37 AM UTC 24 Sep 11 02:51:46 AM UTC 24 114033679 ps
T795 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.32707919 Sep 11 02:51:46 AM UTC 24 Sep 11 02:51:49 AM UTC 24 15680670 ps
T796 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.1572536911 Sep 11 02:51:46 AM UTC 24 Sep 11 02:51:49 AM UTC 24 13035829 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.3638792313 Sep 11 02:50:06 AM UTC 24 Sep 11 02:51:49 AM UTC 24 4261852638 ps
T797 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.2037647387 Sep 11 02:51:44 AM UTC 24 Sep 11 02:51:49 AM UTC 24 26029525 ps
T798 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.3973729394 Sep 11 02:51:35 AM UTC 24 Sep 11 02:51:50 AM UTC 24 2919310851 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.469576244 Sep 11 02:49:41 AM UTC 24 Sep 11 02:51:50 AM UTC 24 30443307344 ps
T799 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.4037813068 Sep 11 02:51:46 AM UTC 24 Sep 11 02:51:51 AM UTC 24 219910612 ps
T800 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random.1810529940 Sep 11 02:51:48 AM UTC 24 Sep 11 02:51:52 AM UTC 24 54328011 ps
T801 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.230489487 Sep 11 02:51:53 AM UTC 24 Sep 11 02:51:56 AM UTC 24 12900825 ps
T802 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.226094000 Sep 11 02:51:48 AM UTC 24 Sep 11 02:51:56 AM UTC 24 649026819 ps
T803 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.2363221942 Sep 11 02:50:25 AM UTC 24 Sep 11 02:51:57 AM UTC 24 896294535 ps
T804 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.3180543242 Sep 11 02:51:53 AM UTC 24 Sep 11 02:51:58 AM UTC 24 219374045 ps
T805 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.3969209106 Sep 11 02:51:33 AM UTC 24 Sep 11 02:51:58 AM UTC 24 433837347 ps
T806 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.1588887100 Sep 11 02:51:53 AM UTC 24 Sep 11 02:51:59 AM UTC 24 246702746 ps
T807 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.3333563388 Sep 11 02:51:53 AM UTC 24 Sep 11 02:51:59 AM UTC 24 681690976 ps
T808 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3857139663 Sep 11 02:51:33 AM UTC 24 Sep 11 02:52:01 AM UTC 24 706619842 ps
T809 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.1685292228 Sep 11 02:51:49 AM UTC 24 Sep 11 02:52:01 AM UTC 24 287814540 ps
T810 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.2031596345 Sep 11 02:51:10 AM UTC 24 Sep 11 02:52:02 AM UTC 24 253810419 ps
T811 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.830175349 Sep 11 02:52:00 AM UTC 24 Sep 11 02:52:02 AM UTC 24 12724963 ps
T812 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1562556691 Sep 11 02:52:00 AM UTC 24 Sep 11 02:52:02 AM UTC 24 14526945 ps
T813 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.3156547795 Sep 11 02:51:46 AM UTC 24 Sep 11 02:52:04 AM UTC 24 1069431754 ps
T814 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.2169383125 Sep 11 02:51:48 AM UTC 24 Sep 11 02:52:04 AM UTC 24 7265584902 ps
T815 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1154075328 Sep 11 02:52:00 AM UTC 24 Sep 11 02:52:05 AM UTC 24 151867688 ps
T816 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.1407497207 Sep 11 02:50:43 AM UTC 24 Sep 11 02:52:05 AM UTC 24 29560662077 ps
T817 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.4281526494 Sep 11 02:52:04 AM UTC 24 Sep 11 02:52:09 AM UTC 24 28439370 ps
T818 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.752611006 Sep 11 02:51:46 AM UTC 24 Sep 11 02:52:11 AM UTC 24 1357563790 ps
T819 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.2753481776 Sep 11 02:46:04 AM UTC 24 Sep 11 02:52:11 AM UTC 24 277564837122 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1228170528 Sep 11 02:50:18 AM UTC 24 Sep 11 02:52:12 AM UTC 24 16971874426 ps
T820 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.2872264943 Sep 11 02:49:39 AM UTC 24 Sep 11 02:52:12 AM UTC 24 102835583653 ps
T821 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random.4179852958 Sep 11 02:52:04 AM UTC 24 Sep 11 02:52:12 AM UTC 24 57727788 ps
T822 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3612943883 Sep 11 02:51:53 AM UTC 24 Sep 11 02:52:12 AM UTC 24 5507623776 ps
T823 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.3744647829 Sep 11 02:52:00 AM UTC 24 Sep 11 02:52:13 AM UTC 24 2243800300 ps
T824 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.1182497174 Sep 11 02:52:05 AM UTC 24 Sep 11 02:52:14 AM UTC 24 304909964 ps
T825 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.2032877187 Sep 11 02:50:39 AM UTC 24 Sep 11 02:52:14 AM UTC 24 11381918494 ps
T826 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.1819049065 Sep 11 02:52:09 AM UTC 24 Sep 11 02:52:14 AM UTC 24 208804418 ps
T827 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.1370946496 Sep 11 02:52:04 AM UTC 24 Sep 11 02:52:15 AM UTC 24 1116910635 ps
T828 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.2865422238 Sep 11 02:52:09 AM UTC 24 Sep 11 02:52:15 AM UTC 24 91267877 ps
T829 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.10189192 Sep 11 02:51:46 AM UTC 24 Sep 11 02:52:15 AM UTC 24 167976689 ps
T830 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.3079583069 Sep 11 02:52:09 AM UTC 24 Sep 11 02:52:15 AM UTC 24 266365731 ps
T831 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.557134127 Sep 11 02:50:02 AM UTC 24 Sep 11 02:52:15 AM UTC 24 27761039651 ps
T832 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.1095287849 Sep 11 02:52:09 AM UTC 24 Sep 11 02:52:17 AM UTC 24 569654687 ps
T833 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.987922638 Sep 11 02:52:17 AM UTC 24 Sep 11 02:52:20 AM UTC 24 8897490 ps
T834 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.4138717183 Sep 11 02:51:18 AM UTC 24 Sep 11 02:52:20 AM UTC 24 9941110452 ps
T835 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.978678408 Sep 11 02:52:17 AM UTC 24 Sep 11 02:52:20 AM UTC 24 39490409 ps
T836 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.1606372617 Sep 11 02:51:05 AM UTC 24 Sep 11 02:52:21 AM UTC 24 13571684028 ps
T837 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.2716036279 Sep 11 02:51:21 AM UTC 24 Sep 11 02:52:21 AM UTC 24 4796652972 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.3760732527 Sep 11 02:47:18 AM UTC 24 Sep 11 02:52:23 AM UTC 24 91419846837 ps
T838 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.3120694761 Sep 11 02:52:17 AM UTC 24 Sep 11 02:52:23 AM UTC 24 128437952 ps
T839 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.1709253980 Sep 11 02:51:21 AM UTC 24 Sep 11 02:52:24 AM UTC 24 5231422735 ps
T840 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.2672105212 Sep 11 02:52:21 AM UTC 24 Sep 11 02:52:25 AM UTC 24 69497435 ps
T841 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.4162171593 Sep 11 02:50:36 AM UTC 24 Sep 11 02:52:25 AM UTC 24 10552611020 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.3686366308 Sep 11 02:48:19 AM UTC 24 Sep 11 02:52:27 AM UTC 24 37032347310 ps
T842 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.3917866827 Sep 11 02:52:21 AM UTC 24 Sep 11 02:52:27 AM UTC 24 60166814 ps
T843 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.4121216293 Sep 11 02:51:26 AM UTC 24 Sep 11 02:52:28 AM UTC 24 8095145442 ps
T844 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1454592758 Sep 11 02:52:26 AM UTC 24 Sep 11 02:52:29 AM UTC 24 8700245 ps
T845 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.2504299715 Sep 11 02:52:26 AM UTC 24 Sep 11 02:52:29 AM UTC 24 9041618 ps
T846 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3792998865 Sep 11 02:51:23 AM UTC 24 Sep 11 02:52:30 AM UTC 24 5724716197 ps
T847 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3753436010 Sep 11 02:52:21 AM UTC 24 Sep 11 02:52:30 AM UTC 24 483703680 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.546553015 Sep 11 02:52:11 AM UTC 24 Sep 11 02:52:31 AM UTC 24 2433497578 ps
T848 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.3823109167 Sep 11 02:52:17 AM UTC 24 Sep 11 02:52:31 AM UTC 24 4057045947 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.4140524510 Sep 11 02:48:03 AM UTC 24 Sep 11 02:52:32 AM UTC 24 35063544547 ps
T849 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.133005190 Sep 11 02:52:26 AM UTC 24 Sep 11 02:52:32 AM UTC 24 70474796 ps
T850 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.2734953733 Sep 11 02:52:26 AM UTC 24 Sep 11 02:52:34 AM UTC 24 1557549208 ps
T851 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.4006971577 Sep 11 02:52:17 AM UTC 24 Sep 11 02:52:34 AM UTC 24 3486374634 ps
T852 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.1052105859 Sep 11 02:52:21 AM UTC 24 Sep 11 02:52:34 AM UTC 24 1741067541 ps
T853 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.168836883 Sep 11 02:51:54 AM UTC 24 Sep 11 02:52:34 AM UTC 24 335488809 ps
T854 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3020358326 Sep 11 02:52:17 AM UTC 24 Sep 11 02:52:34 AM UTC 24 1141518688 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.1686550865 Sep 11 02:52:31 AM UTC 24 Sep 11 02:52:34 AM UTC 24 66079049 ps
T855 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random.3715179246 Sep 11 02:52:17 AM UTC 24 Sep 11 02:52:35 AM UTC 24 682362671 ps
T856 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.2177965391 Sep 11 02:52:31 AM UTC 24 Sep 11 02:52:37 AM UTC 24 50053293 ps
T857 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.3539348811 Sep 11 02:52:21 AM UTC 24 Sep 11 02:52:38 AM UTC 24 5058067087 ps
T858 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.294444015 Sep 11 02:52:36 AM UTC 24 Sep 11 02:52:41 AM UTC 24 74294858 ps
T859 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.4136623385 Sep 11 02:50:29 AM UTC 24 Sep 11 02:52:42 AM UTC 24 30777770020 ps
T860 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3658496521 Sep 11 02:52:26 AM UTC 24 Sep 11 02:52:42 AM UTC 24 2183707381 ps
T861 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.2813095277 Sep 11 02:52:36 AM UTC 24 Sep 11 02:52:43 AM UTC 24 362907599 ps
T862 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random.2528959134 Sep 11 02:52:31 AM UTC 24 Sep 11 02:52:44 AM UTC 24 684606202 ps
T863 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.1517294377 Sep 11 02:49:47 AM UTC 24 Sep 11 02:52:45 AM UTC 24 1168579582 ps
T864 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.174423184 Sep 11 02:52:36 AM UTC 24 Sep 11 02:52:46 AM UTC 24 365651602 ps
T865 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1173156257 Sep 11 02:52:26 AM UTC 24 Sep 11 02:52:46 AM UTC 24 203301566 ps
T866 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.2444214679 Sep 11 02:52:36 AM UTC 24 Sep 11 02:52:48 AM UTC 24 2454783396 ps
T867 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.3152125954 Sep 11 02:51:26 AM UTC 24 Sep 11 02:52:49 AM UTC 24 20672410214 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.2436672125 Sep 11 02:50:36 AM UTC 24 Sep 11 02:52:52 AM UTC 24 7460261278 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.2707909737 Sep 11 02:50:57 AM UTC 24 Sep 11 02:52:52 AM UTC 24 8109967192 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.2554585424 Sep 11 02:49:24 AM UTC 24 Sep 11 02:52:53 AM UTC 24 12942311451 ps
T868 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.649384426 Sep 11 02:52:36 AM UTC 24 Sep 11 02:52:56 AM UTC 24 2839914420 ps
T869 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.547942105 Sep 11 02:51:18 AM UTC 24 Sep 11 02:52:57 AM UTC 24 21799702667 ps
T870 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.1745345860 Sep 11 02:52:16 AM UTC 24 Sep 11 02:53:01 AM UTC 24 284841176 ps
T871 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.2798051221 Sep 11 02:52:26 AM UTC 24 Sep 11 02:53:04 AM UTC 24 1302620522 ps
T872 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.2938491007 Sep 11 02:52:05 AM UTC 24 Sep 11 02:53:05 AM UTC 24 47408344836 ps
T873 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.368689876 Sep 11 02:52:21 AM UTC 24 Sep 11 02:53:05 AM UTC 24 588695256 ps
T874 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.4119304775 Sep 11 02:52:36 AM UTC 24 Sep 11 02:53:07 AM UTC 24 539517409 ps
T875 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.4050282777 Sep 11 02:52:17 AM UTC 24 Sep 11 02:53:07 AM UTC 24 2026465988 ps
T876 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.3133424603 Sep 11 02:51:49 AM UTC 24 Sep 11 02:53:10 AM UTC 24 116069802289 ps
T877 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.2907150738 Sep 11 02:51:39 AM UTC 24 Sep 11 02:53:12 AM UTC 24 20963841943 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.3129880440 Sep 11 02:48:32 AM UTC 24 Sep 11 02:53:13 AM UTC 24 83306288479 ps
T878 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.25357118 Sep 11 02:51:21 AM UTC 24 Sep 11 02:53:13 AM UTC 24 779786337 ps
T879 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.853612867 Sep 11 02:51:46 AM UTC 24 Sep 11 02:53:13 AM UTC 24 468823937 ps
T880 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.2018663818 Sep 11 02:51:18 AM UTC 24 Sep 11 02:53:17 AM UTC 24 16683516857 ps
T881 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.3655435112 Sep 11 02:48:42 AM UTC 24 Sep 11 02:53:18 AM UTC 24 101944127756 ps
T882 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.669662542 Sep 11 02:52:17 AM UTC 24 Sep 11 02:53:27 AM UTC 24 10567906556 ps
T883 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.3712104262 Sep 11 02:52:36 AM UTC 24 Sep 11 02:53:31 AM UTC 24 4117462845 ps
T884 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.1448285573 Sep 11 02:52:31 AM UTC 24 Sep 11 02:53:31 AM UTC 24 15118073950 ps
T885 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.2023886873 Sep 11 02:52:00 AM UTC 24 Sep 11 02:53:33 AM UTC 24 844588052 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1557913391 Sep 11 02:49:43 AM UTC 24 Sep 11 02:53:36 AM UTC 24 16927560590 ps
T886 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.2463647405 Sep 11 02:52:36 AM UTC 24 Sep 11 02:53:44 AM UTC 24 541959858 ps
T887 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.584581284 Sep 11 02:50:45 AM UTC 24 Sep 11 02:53:45 AM UTC 24 141815805304 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.1780236375 Sep 11 02:51:31 AM UTC 24 Sep 11 02:53:51 AM UTC 24 7440502004 ps
T888 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.719210357 Sep 11 02:49:55 AM UTC 24 Sep 11 02:53:52 AM UTC 24 228245735599 ps
T889 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.2295917817 Sep 11 02:52:17 AM UTC 24 Sep 11 02:53:57 AM UTC 24 26218819093 ps
T890 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.230348643 Sep 11 02:51:10 AM UTC 24 Sep 11 02:54:00 AM UTC 24 4619504961 ps
T891 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.174994423 Sep 11 02:52:00 AM UTC 24 Sep 11 02:54:05 AM UTC 24 2018192002 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.254668023 Sep 11 02:47:53 AM UTC 24 Sep 11 02:54:24 AM UTC 24 40867008532 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1930621027 Sep 11 02:50:47 AM UTC 24 Sep 11 02:54:34 AM UTC 24 44513858019 ps
T892 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.1518148223 Sep 11 02:50:31 AM UTC 24 Sep 11 02:54:47 AM UTC 24 78917524682 ps
T893 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.2072375192 Sep 11 02:51:37 AM UTC 24 Sep 11 02:54:57 AM UTC 24 409040189075 ps
T894 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.3429143282 Sep 11 02:52:31 AM UTC 24 Sep 11 02:55:02 AM UTC 24 49318945359 ps
T895 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2269115481 Sep 11 02:52:31 AM UTC 24 Sep 11 02:55:09 AM UTC 24 96144541326 ps
T896 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.3265545786 Sep 11 02:49:16 AM UTC 24 Sep 11 02:55:14 AM UTC 24 111667085748 ps
T897 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.3503478910 Sep 11 02:52:05 AM UTC 24 Sep 11 02:55:26 AM UTC 24 108273364804 ps
T898 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.2182911115 Sep 11 02:51:53 AM UTC 24 Sep 11 02:55:29 AM UTC 24 32994429833 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.3638258174 Sep 11 02:48:54 AM UTC 24 Sep 11 02:55:33 AM UTC 24 165386748971 ps
T899 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.357188711 Sep 11 02:51:06 AM UTC 24 Sep 11 02:55:55 AM UTC 24 362233032845 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.203333519 Sep 11 02:52:09 AM UTC 24 Sep 11 02:56:21 AM UTC 24 150542448091 ps
T900 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.4082062345 Sep 11 02:51:39 AM UTC 24 Sep 11 02:56:47 AM UTC 24 179032342835 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2393315220 Sep 11 02:52:21 AM UTC 24 Sep 11 02:56:50 AM UTC 24 42785093336 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.31459038 Sep 11 02:51:27 AM UTC 24 Sep 11 02:56:57 AM UTC 24 54465732687 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random.49137626
Short name T11
Test name
Test status
Simulation time 1008546146 ps
CPU time 9.62 seconds
Started Sep 11 02:41:10 AM UTC 24
Finished Sep 11 02:41:21 AM UTC 24
Peak memory 211756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49137626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.49137626
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/0.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.1269010774
Short name T244
Test name
Test status
Simulation time 69807366754 ps
CPU time 331.13 seconds
Started Sep 11 02:42:54 AM UTC 24
Finished Sep 11 02:48:29 AM UTC 24
Peak memory 216480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269010774 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.1269010774
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/6.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.3212314901
Short name T250
Test name
Test status
Simulation time 50411320529 ps
CPU time 297.7 seconds
Started Sep 11 02:46:16 AM UTC 24
Finished Sep 11 02:51:17 AM UTC 24
Peak memory 216188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212314901 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.3212314901
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/20.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.3671448322
Short name T251
Test name
Test status
Simulation time 28338400429 ps
CPU time 133.76 seconds
Started Sep 11 02:41:26 AM UTC 24
Finished Sep 11 02:43:42 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671448322 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.3671448322
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/1.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.2642003612
Short name T243
Test name
Test status
Simulation time 56585007959 ps
CPU time 317.48 seconds
Started Sep 11 02:41:59 AM UTC 24
Finished Sep 11 02:47:21 AM UTC 24
Peak memory 214560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642003612 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.2642003612
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/3.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_error.3113193809
Short name T113
Test name
Test status
Simulation time 6029107135 ps
CPU time 84.01 seconds
Started Sep 11 02:41:20 AM UTC 24
Finished Sep 11 02:42:46 AM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113193809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3113193809
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/0.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.2267920549
Short name T14
Test name
Test status
Simulation time 81422130 ps
CPU time 5.78 seconds
Started Sep 11 02:41:28 AM UTC 24
Finished Sep 11 02:41:36 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267920549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.2267920549
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/1.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.3242957583
Short name T128
Test name
Test status
Simulation time 139158442800 ps
CPU time 224.31 seconds
Started Sep 11 02:43:08 AM UTC 24
Finished Sep 11 02:46:56 AM UTC 24
Peak memory 214232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242957583 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.3242957583
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/7.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.3760732527
Short name T266
Test name
Test status
Simulation time 91419846837 ps
CPU time 300.86 seconds
Started Sep 11 02:47:18 AM UTC 24
Finished Sep 11 02:52:23 AM UTC 24
Peak memory 217944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760732527 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.3760732527
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/24.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.1023077382
Short name T8
Test name
Test status
Simulation time 288411307 ps
CPU time 41.32 seconds
Started Sep 11 02:41:20 AM UTC 24
Finished Sep 11 02:42:03 AM UTC 24
Peak memory 214436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023077382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.1023077382
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/0.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.1445550606
Short name T5
Test name
Test status
Simulation time 3259730509 ps
CPU time 102.24 seconds
Started Sep 11 02:43:29 AM UTC 24
Finished Sep 11 02:45:14 AM UTC 24
Peak memory 214240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445550606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.1445550606
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/8.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_large_delays.1768461337
Short name T237
Test name
Test status
Simulation time 1661631400 ps
CPU time 12.3 seconds
Started Sep 11 02:41:32 AM UTC 24
Finished Sep 11 02:41:46 AM UTC 24
Peak memory 211860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768461337 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1768461337
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/2.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device.2002968219
Short name T42
Test name
Test status
Simulation time 1846954051 ps
CPU time 21.47 seconds
Started Sep 11 02:41:36 AM UTC 24
Finished Sep 11 02:41:59 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002968219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.2002968219
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/2.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.2133812207
Short name T134
Test name
Test status
Simulation time 162094190193 ps
CPU time 260.4 seconds
Started Sep 11 02:44:52 AM UTC 24
Finished Sep 11 02:49:16 AM UTC 24
Peak memory 214492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133812207 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.2133812207
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/14.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_unmapped_addr.3744137996
Short name T12
Test name
Test status
Simulation time 506827467 ps
CPU time 5.3 seconds
Started Sep 11 02:41:17 AM UTC 24
Finished Sep 11 02:41:24 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744137996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3744137996
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/0.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.1258179815
Short name T9
Test name
Test status
Simulation time 447202157 ps
CPU time 80.22 seconds
Started Sep 11 02:45:40 AM UTC 24
Finished Sep 11 02:47:02 AM UTC 24
Peak memory 214368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258179815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.1258179815
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/17.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.31459038
Short name T139
Test name
Test status
Simulation time 54465732687 ps
CPU time 325.88 seconds
Started Sep 11 02:51:27 AM UTC 24
Finished Sep 11 02:56:57 AM UTC 24
Peak memory 217948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31459038 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.31459038
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/44.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device.1418514525
Short name T71
Test name
Test status
Simulation time 2064310441 ps
CPU time 28.55 seconds
Started Sep 11 02:42:35 AM UTC 24
Finished Sep 11 02:43:05 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418514525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1418514525
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/5.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_zero_delays.2676514379
Short name T3
Test name
Test status
Simulation time 61076452 ps
CPU time 4.73 seconds
Started Sep 11 02:41:10 AM UTC 24
Finished Sep 11 02:41:16 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676514379 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.2676514379
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/0.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.2554585424
Short name T7
Test name
Test status
Simulation time 12942311451 ps
CPU time 206.22 seconds
Started Sep 11 02:49:24 AM UTC 24
Finished Sep 11 02:52:53 AM UTC 24
Peak memory 218336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554585424 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.2554585424
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/34.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.186158085
Short name T73
Test name
Test status
Simulation time 661493960 ps
CPU time 94.47 seconds
Started Sep 11 02:41:28 AM UTC 24
Finished Sep 11 02:43:06 AM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186158085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.186158085
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/1.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.2383717418
Short name T162
Test name
Test status
Simulation time 22676419334 ps
CPU time 193.04 seconds
Started Sep 11 02:44:42 AM UTC 24
Finished Sep 11 02:47:58 AM UTC 24
Peak memory 218528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383717418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.2383717418
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/13.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.696784420
Short name T449
Test name
Test status
Simulation time 11861876075 ps
CPU time 145.18 seconds
Started Sep 11 02:44:44 AM UTC 24
Finished Sep 11 02:47:12 AM UTC 24
Peak memory 218336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696784420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.696784420
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/13.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_error_random.1745071227
Short name T56
Test name
Test status
Simulation time 229849749 ps
CPU time 3.95 seconds
Started Sep 11 02:41:28 AM UTC 24
Finished Sep 11 02:41:34 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745071227 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1745071227
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/1.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.3538439486
Short name T275
Test name
Test status
Simulation time 6794818632 ps
CPU time 109.84 seconds
Started Sep 11 02:41:30 AM UTC 24
Finished Sep 11 02:43:22 AM UTC 24
Peak memory 218336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538439486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.3538439486
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/1.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.2359846132
Short name T221
Test name
Test status
Simulation time 6544721908 ps
CPU time 166.69 seconds
Started Sep 11 02:44:58 AM UTC 24
Finished Sep 11 02:47:47 AM UTC 24
Peak memory 218336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359846132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.2359846132
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/14.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all.1893574021
Short name T88
Test name
Test status
Simulation time 8508005284 ps
CPU time 55.1 seconds
Started Sep 11 02:44:12 AM UTC 24
Finished Sep 11 02:45:08 AM UTC 24
Peak memory 214416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893574021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1893574021
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/11.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_slow_rsp.2701874951
Short name T112
Test name
Test status
Simulation time 13086567942 ps
CPU time 89.03 seconds
Started Sep 11 02:41:11 AM UTC 24
Finished Sep 11 02:42:42 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701874951 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.2701874951
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/0.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device.1162664980
Short name T23
Test name
Test status
Simulation time 2004482898 ps
CPU time 14.15 seconds
Started Sep 11 02:41:15 AM UTC 24
Finished Sep 11 02:41:30 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162664980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.1162664980
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/0.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.4174526028
Short name T246
Test name
Test status
Simulation time 83777064936 ps
CPU time 279.63 seconds
Started Sep 11 02:41:15 AM UTC 24
Finished Sep 11 02:45:58 AM UTC 24
Peak memory 214240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174526028 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.4174526028
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/0.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.701866102
Short name T13
Test name
Test status
Simulation time 555556818 ps
CPU time 6.63 seconds
Started Sep 11 02:41:20 AM UTC 24
Finished Sep 11 02:41:27 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701866102 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.701866102
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/0.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_error_random.2569788882
Short name T19
Test name
Test status
Simulation time 298608815 ps
CPU time 6.63 seconds
Started Sep 11 02:41:17 AM UTC 24
Finished Sep 11 02:41:25 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569788882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.2569788882
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/0.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_large_delays.1415109263
Short name T298
Test name
Test status
Simulation time 28844432465 ps
CPU time 127.48 seconds
Started Sep 11 02:41:11 AM UTC 24
Finished Sep 11 02:43:21 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415109263 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1415109263
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/0.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_same_source.3087733493
Short name T15
Test name
Test status
Simulation time 382368470 ps
CPU time 8.65 seconds
Started Sep 11 02:41:15 AM UTC 24
Finished Sep 11 02:41:24 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087733493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.3087733493
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/0.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke.1743055899
Short name T1
Test name
Test status
Simulation time 150618149 ps
CPU time 1.91 seconds
Started Sep 11 02:41:06 AM UTC 24
Finished Sep 11 02:41:09 AM UTC 24
Peak memory 211668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743055899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.1743055899
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/0.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_large_delays.3067303905
Short name T21
Test name
Test status
Simulation time 2851734121 ps
CPU time 18.15 seconds
Started Sep 11 02:41:08 AM UTC 24
Finished Sep 11 02:41:28 AM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067303905 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.3067303905
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/0.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.1229108385
Short name T4
Test name
Test status
Simulation time 2050542069 ps
CPU time 8.57 seconds
Started Sep 11 02:41:10 AM UTC 24
Finished Sep 11 02:41:20 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229108385 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1229108385
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/0.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.632735814
Short name T2
Test name
Test status
Simulation time 13951513 ps
CPU time 1.23 seconds
Started Sep 11 02:41:08 AM UTC 24
Finished Sep 11 02:41:10 AM UTC 24
Peak memory 211228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632735814 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.632735814
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/0.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all.1490644388
Short name T107
Test name
Test status
Simulation time 4662462584 ps
CPU time 72.1 seconds
Started Sep 11 02:41:20 AM UTC 24
Finished Sep 11 02:42:34 AM UTC 24
Peak memory 214240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490644388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1490644388
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/0.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1422241729
Short name T17
Test name
Test status
Simulation time 7628586 ps
CPU time 3.63 seconds
Started Sep 11 02:41:20 AM UTC 24
Finished Sep 11 02:41:24 AM UTC 24
Peak memory 212056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422241729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.1422241729
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/0.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device.1262832389
Short name T30
Test name
Test status
Simulation time 1715870653 ps
CPU time 19.71 seconds
Started Sep 11 02:41:26 AM UTC 24
Finished Sep 11 02:41:47 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262832389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.1262832389
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/1.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random.307319066
Short name T20
Test name
Test status
Simulation time 34105846 ps
CPU time 1.75 seconds
Started Sep 11 02:41:24 AM UTC 24
Finished Sep 11 02:41:27 AM UTC 24
Peak memory 211176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307319066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.307319066
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/1.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_large_delays.715498246
Short name T77
Test name
Test status
Simulation time 63243654891 ps
CPU time 98.12 seconds
Started Sep 11 02:41:26 AM UTC 24
Finished Sep 11 02:43:06 AM UTC 24
Peak memory 212380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715498246 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.715498246
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/1.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_slow_rsp.3295086053
Short name T238
Test name
Test status
Simulation time 7723706423 ps
CPU time 49.07 seconds
Started Sep 11 02:41:26 AM UTC 24
Finished Sep 11 02:42:17 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295086053 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3295086053
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/1.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_zero_delays.3999537623
Short name T22
Test name
Test status
Simulation time 14112800 ps
CPU time 1.49 seconds
Started Sep 11 02:41:26 AM UTC 24
Finished Sep 11 02:41:29 AM UTC 24
Peak memory 211128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999537623 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.3999537623
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/1.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_same_source.3688945916
Short name T24
Test name
Test status
Simulation time 28315836 ps
CPU time 3.83 seconds
Started Sep 11 02:41:26 AM UTC 24
Finished Sep 11 02:41:31 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688945916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.3688945916
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/1.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke.1047915798
Short name T18
Test name
Test status
Simulation time 51671216 ps
CPU time 2.14 seconds
Started Sep 11 02:41:21 AM UTC 24
Finished Sep 11 02:41:24 AM UTC 24
Peak memory 212380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047915798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1047915798
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/1.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_large_delays.3328647443
Short name T25
Test name
Test status
Simulation time 7257129078 ps
CPU time 9.71 seconds
Started Sep 11 02:41:21 AM UTC 24
Finished Sep 11 02:41:32 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328647443 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3328647443
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/1.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.1398667785
Short name T26
Test name
Test status
Simulation time 2026196217 ps
CPU time 12.99 seconds
Started Sep 11 02:41:23 AM UTC 24
Finished Sep 11 02:41:37 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398667785 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1398667785
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/1.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1026774215
Short name T16
Test name
Test status
Simulation time 10813613 ps
CPU time 1.62 seconds
Started Sep 11 02:41:21 AM UTC 24
Finished Sep 11 02:41:24 AM UTC 24
Peak memory 211124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026774215 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.1026774215
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/1.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all.1326051053
Short name T49
Test name
Test status
Simulation time 191328363 ps
CPU time 31.87 seconds
Started Sep 11 02:41:28 AM UTC 24
Finished Sep 11 02:42:02 AM UTC 24
Peak memory 214172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326051053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1326051053
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/1.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_error.4012738577
Short name T155
Test name
Test status
Simulation time 8193413065 ps
CPU time 88.07 seconds
Started Sep 11 02:41:30 AM UTC 24
Finished Sep 11 02:43:01 AM UTC 24
Peak memory 214228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012738577 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.4012738577
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/1.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_unmapped_addr.3154783119
Short name T27
Test name
Test status
Simulation time 463755434 ps
CPU time 7.49 seconds
Started Sep 11 02:41:28 AM UTC 24
Finished Sep 11 02:41:37 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154783119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3154783119
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/1.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device.101101048
Short name T253
Test name
Test status
Simulation time 2882018384 ps
CPU time 16.95 seconds
Started Sep 11 02:43:52 AM UTC 24
Finished Sep 11 02:44:10 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101101048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.101101048
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/10.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.2422131114
Short name T144
Test name
Test status
Simulation time 17105629109 ps
CPU time 86.77 seconds
Started Sep 11 02:43:53 AM UTC 24
Finished Sep 11 02:45:22 AM UTC 24
Peak memory 214428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422131114 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.2422131114
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/10.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.2186599755
Short name T339
Test name
Test status
Simulation time 56324866 ps
CPU time 7.32 seconds
Started Sep 11 02:43:59 AM UTC 24
Finished Sep 11 02:44:07 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186599755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2186599755
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/10.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_error_random.2355634422
Short name T97
Test name
Test status
Simulation time 2875861993 ps
CPU time 20.43 seconds
Started Sep 11 02:43:56 AM UTC 24
Finished Sep 11 02:44:17 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355634422 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2355634422
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/10.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random.2021843154
Short name T331
Test name
Test status
Simulation time 68117138 ps
CPU time 10.19 seconds
Started Sep 11 02:43:48 AM UTC 24
Finished Sep 11 02:44:00 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021843154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.2021843154
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/10.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_large_delays.2050760654
Short name T87
Test name
Test status
Simulation time 16827344550 ps
CPU time 62.84 seconds
Started Sep 11 02:43:51 AM UTC 24
Finished Sep 11 02:44:55 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050760654 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2050760654
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/10.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_slow_rsp.230959001
Short name T98
Test name
Test status
Simulation time 14374550893 ps
CPU time 24.58 seconds
Started Sep 11 02:43:52 AM UTC 24
Finished Sep 11 02:44:18 AM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230959001 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.230959001
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/10.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_zero_delays.2514693168
Short name T326
Test name
Test status
Simulation time 35491198 ps
CPU time 5.59 seconds
Started Sep 11 02:43:49 AM UTC 24
Finished Sep 11 02:43:56 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514693168 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.2514693168
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/10.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_same_source.1893260662
Short name T332
Test name
Test status
Simulation time 77110888 ps
CPU time 4.22 seconds
Started Sep 11 02:43:54 AM UTC 24
Finished Sep 11 02:44:00 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893260662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1893260662
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/10.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke.109214013
Short name T322
Test name
Test status
Simulation time 9730532 ps
CPU time 1.69 seconds
Started Sep 11 02:43:45 AM UTC 24
Finished Sep 11 02:43:48 AM UTC 24
Peak memory 211228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109214013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.109214013
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/10.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3742175992
Short name T335
Test name
Test status
Simulation time 4442712387 ps
CPU time 14.94 seconds
Started Sep 11 02:43:47 AM UTC 24
Finished Sep 11 02:44:03 AM UTC 24
Peak memory 212028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742175992 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3742175992
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/10.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.2466620021
Short name T330
Test name
Test status
Simulation time 1049863029 ps
CPU time 10.38 seconds
Started Sep 11 02:43:47 AM UTC 24
Finished Sep 11 02:43:59 AM UTC 24
Peak memory 212256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466620021 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.2466620021
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/10.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.3523831956
Short name T324
Test name
Test status
Simulation time 13737384 ps
CPU time 1.65 seconds
Started Sep 11 02:43:47 AM UTC 24
Finished Sep 11 02:43:50 AM UTC 24
Peak memory 211020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523831956 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.3523831956
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/10.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all.3375547973
Short name T353
Test name
Test status
Simulation time 2861651335 ps
CPU time 40.1 seconds
Started Sep 11 02:43:59 AM UTC 24
Finished Sep 11 02:44:40 AM UTC 24
Peak memory 214432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375547973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3375547973
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/10.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_error.2540179639
Short name T142
Test name
Test status
Simulation time 6449964177 ps
CPU time 76.17 seconds
Started Sep 11 02:43:59 AM UTC 24
Finished Sep 11 02:45:17 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540179639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2540179639
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/10.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.1069836464
Short name T276
Test name
Test status
Simulation time 284274441 ps
CPU time 49.2 seconds
Started Sep 11 02:43:59 AM UTC 24
Finished Sep 11 02:44:49 AM UTC 24
Peak memory 216220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069836464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.1069836464
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/10.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.3366631860
Short name T281
Test name
Test status
Simulation time 3476440571 ps
CPU time 92.57 seconds
Started Sep 11 02:44:00 AM UTC 24
Finished Sep 11 02:45:34 AM UTC 24
Peak memory 216484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366631860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.3366631860
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/10.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_unmapped_addr.2420946375
Short name T338
Test name
Test status
Simulation time 466723021 ps
CPU time 5.99 seconds
Started Sep 11 02:43:57 AM UTC 24
Finished Sep 11 02:44:04 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420946375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.2420946375
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/10.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device.4286415853
Short name T343
Test name
Test status
Simulation time 57821488 ps
CPU time 6.67 seconds
Started Sep 11 02:44:05 AM UTC 24
Finished Sep 11 02:44:13 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286415853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.4286415853
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/11.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.1434969103
Short name T261
Test name
Test status
Simulation time 301100635498 ps
CPU time 316.94 seconds
Started Sep 11 02:44:06 AM UTC 24
Finished Sep 11 02:49:27 AM UTC 24
Peak memory 216080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434969103 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.1434969103
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/11.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.3507684681
Short name T345
Test name
Test status
Simulation time 933835946 ps
CPU time 9.71 seconds
Started Sep 11 02:44:10 AM UTC 24
Finished Sep 11 02:44:21 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507684681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.3507684681
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/11.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_error_random.1911031945
Short name T95
Test name
Test status
Simulation time 172096005 ps
CPU time 7.06 seconds
Started Sep 11 02:44:08 AM UTC 24
Finished Sep 11 02:44:16 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911031945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1911031945
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/11.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random.3355245857
Short name T346
Test name
Test status
Simulation time 1361347711 ps
CPU time 15.95 seconds
Started Sep 11 02:44:05 AM UTC 24
Finished Sep 11 02:44:22 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355245857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.3355245857
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/11.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_large_delays.748937144
Short name T395
Test name
Test status
Simulation time 82006163942 ps
CPU time 102.95 seconds
Started Sep 11 02:44:05 AM UTC 24
Finished Sep 11 02:45:50 AM UTC 24
Peak memory 212196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748937144 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.748937144
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/11.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_slow_rsp.1027245380
Short name T447
Test name
Test status
Simulation time 97235253785 ps
CPU time 182.33 seconds
Started Sep 11 02:44:05 AM UTC 24
Finished Sep 11 02:47:11 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027245380 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.1027245380
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/11.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_zero_delays.2890309382
Short name T340
Test name
Test status
Simulation time 19399304 ps
CPU time 2.9 seconds
Started Sep 11 02:44:05 AM UTC 24
Finished Sep 11 02:44:09 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890309382 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.2890309382
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/11.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_same_source.2412753113
Short name T344
Test name
Test status
Simulation time 1101327816 ps
CPU time 12.75 seconds
Started Sep 11 02:44:07 AM UTC 24
Finished Sep 11 02:44:21 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412753113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2412753113
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/11.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke.4221652604
Short name T297
Test name
Test status
Simulation time 8955250 ps
CPU time 1.88 seconds
Started Sep 11 02:44:01 AM UTC 24
Finished Sep 11 02:44:04 AM UTC 24
Peak memory 211176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221652604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.4221652604
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/11.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_large_delays.594416371
Short name T31
Test name
Test status
Simulation time 5766343026 ps
CPU time 11.34 seconds
Started Sep 11 02:44:01 AM UTC 24
Finished Sep 11 02:44:14 AM UTC 24
Peak memory 212380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594416371 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.594416371
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/11.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.1749925645
Short name T342
Test name
Test status
Simulation time 1340221972 ps
CPU time 7.88 seconds
Started Sep 11 02:44:02 AM UTC 24
Finished Sep 11 02:44:11 AM UTC 24
Peak memory 212320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749925645 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.1749925645
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/11.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2026903924
Short name T337
Test name
Test status
Simulation time 8168003 ps
CPU time 1.61 seconds
Started Sep 11 02:44:01 AM UTC 24
Finished Sep 11 02:44:04 AM UTC 24
Peak memory 211120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026903924 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2026903924
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/11.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_error.3501894831
Short name T228
Test name
Test status
Simulation time 3840778042 ps
CPU time 43.25 seconds
Started Sep 11 02:44:14 AM UTC 24
Finished Sep 11 02:44:59 AM UTC 24
Peak memory 212380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501894831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.3501894831
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/11.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.301855168
Short name T208
Test name
Test status
Simulation time 232849219 ps
CPU time 43.06 seconds
Started Sep 11 02:44:12 AM UTC 24
Finished Sep 11 02:44:56 AM UTC 24
Peak memory 214364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301855168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.301855168
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/11.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.1375591518
Short name T277
Test name
Test status
Simulation time 9876878714 ps
CPU time 120.74 seconds
Started Sep 11 02:44:14 AM UTC 24
Finished Sep 11 02:46:17 AM UTC 24
Peak memory 218336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375591518 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.1375591518
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/11.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_unmapped_addr.1782512968
Short name T94
Test name
Test status
Simulation time 21337692 ps
CPU time 3.48 seconds
Started Sep 11 02:44:10 AM UTC 24
Finished Sep 11 02:44:15 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782512968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1782512968
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/11.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device.38296973
Short name T85
Test name
Test status
Simulation time 1250863038 ps
CPU time 13.47 seconds
Started Sep 11 02:44:18 AM UTC 24
Finished Sep 11 02:44:33 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38296973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.38296973
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/12.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.2325156827
Short name T260
Test name
Test status
Simulation time 18178871396 ps
CPU time 71.27 seconds
Started Sep 11 02:44:19 AM UTC 24
Finished Sep 11 02:45:33 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325156827 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.2325156827
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/12.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.3409396435
Short name T347
Test name
Test status
Simulation time 15503253 ps
CPU time 2.13 seconds
Started Sep 11 02:44:22 AM UTC 24
Finished Sep 11 02:44:25 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409396435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.3409396435
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/12.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_error_random.2869081617
Short name T172
Test name
Test status
Simulation time 947238912 ps
CPU time 14.26 seconds
Started Sep 11 02:44:21 AM UTC 24
Finished Sep 11 02:44:37 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869081617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.2869081617
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/12.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random.4123728221
Short name T86
Test name
Test status
Simulation time 1061823000 ps
CPU time 16.18 seconds
Started Sep 11 02:44:16 AM UTC 24
Finished Sep 11 02:44:34 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123728221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.4123728221
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/12.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_large_delays.1110629082
Short name T401
Test name
Test status
Simulation time 24820188993 ps
CPU time 101.37 seconds
Started Sep 11 02:44:17 AM UTC 24
Finished Sep 11 02:46:01 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110629082 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1110629082
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/12.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_slow_rsp.2976256347
Short name T356
Test name
Test status
Simulation time 4853766648 ps
CPU time 24.44 seconds
Started Sep 11 02:44:18 AM UTC 24
Finished Sep 11 02:44:44 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976256347 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2976256347
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/12.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_zero_delays.613988485
Short name T348
Test name
Test status
Simulation time 145361114 ps
CPU time 7.41 seconds
Started Sep 11 02:44:17 AM UTC 24
Finished Sep 11 02:44:26 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613988485 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.613988485
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/12.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_same_source.4215234205
Short name T352
Test name
Test status
Simulation time 68743468 ps
CPU time 9.04 seconds
Started Sep 11 02:44:21 AM UTC 24
Finished Sep 11 02:44:31 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215234205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.4215234205
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/12.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke.1516127725
Short name T96
Test name
Test status
Simulation time 13465245 ps
CPU time 1.74 seconds
Started Sep 11 02:44:14 AM UTC 24
Finished Sep 11 02:44:17 AM UTC 24
Peak memory 211236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516127725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.1516127725
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/12.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_large_delays.4080689849
Short name T169
Test name
Test status
Simulation time 3547179451 ps
CPU time 16.28 seconds
Started Sep 11 02:44:16 AM UTC 24
Finished Sep 11 02:44:34 AM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080689849 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.4080689849
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/12.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.2747035825
Short name T350
Test name
Test status
Simulation time 2094675002 ps
CPU time 9.2 seconds
Started Sep 11 02:44:16 AM UTC 24
Finished Sep 11 02:44:27 AM UTC 24
Peak memory 212320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747035825 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.2747035825
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/12.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.2404979436
Short name T99
Test name
Test status
Simulation time 9158629 ps
CPU time 1.69 seconds
Started Sep 11 02:44:16 AM UTC 24
Finished Sep 11 02:44:19 AM UTC 24
Peak memory 211228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404979436 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.2404979436
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/12.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all.1648381077
Short name T229
Test name
Test status
Simulation time 6482311809 ps
CPU time 34.52 seconds
Started Sep 11 02:44:23 AM UTC 24
Finished Sep 11 02:44:59 AM UTC 24
Peak memory 214432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648381077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1648381077
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/12.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_error.2253406302
Short name T258
Test name
Test status
Simulation time 3512819328 ps
CPU time 37.59 seconds
Started Sep 11 02:44:26 AM UTC 24
Finished Sep 11 02:45:05 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253406302 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.2253406302
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/12.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.2587420430
Short name T115
Test name
Test status
Simulation time 4174310821 ps
CPU time 116.17 seconds
Started Sep 11 02:44:26 AM UTC 24
Finished Sep 11 02:46:25 AM UTC 24
Peak memory 214236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587420430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.2587420430
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/12.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3215028999
Short name T173
Test name
Test status
Simulation time 65039450 ps
CPU time 8.83 seconds
Started Sep 11 02:44:27 AM UTC 24
Finished Sep 11 02:44:37 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215028999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.3215028999
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/12.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_unmapped_addr.838275057
Short name T349
Test name
Test status
Simulation time 57546805 ps
CPU time 2.48 seconds
Started Sep 11 02:44:22 AM UTC 24
Finished Sep 11 02:44:26 AM UTC 24
Peak memory 212388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838275057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.838275057
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/12.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device.3820413474
Short name T365
Test name
Test status
Simulation time 426629154 ps
CPU time 14.19 seconds
Started Sep 11 02:44:37 AM UTC 24
Finished Sep 11 02:44:53 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820413474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.3820413474
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/13.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.1496368514
Short name T264
Test name
Test status
Simulation time 48860788129 ps
CPU time 95.44 seconds
Started Sep 11 02:44:37 AM UTC 24
Finished Sep 11 02:46:15 AM UTC 24
Peak memory 214492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496368514 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.1496368514
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/13.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.364997081
Short name T360
Test name
Test status
Simulation time 256210372 ps
CPU time 5.59 seconds
Started Sep 11 02:44:41 AM UTC 24
Finished Sep 11 02:44:47 AM UTC 24
Peak memory 212320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364997081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.364997081
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/13.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_error_random.729030088
Short name T358
Test name
Test status
Simulation time 1328850677 ps
CPU time 4.98 seconds
Started Sep 11 02:44:39 AM UTC 24
Finished Sep 11 02:44:46 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729030088 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.729030088
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/13.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random.3309928774
Short name T176
Test name
Test status
Simulation time 149885900 ps
CPU time 4.47 seconds
Started Sep 11 02:44:34 AM UTC 24
Finished Sep 11 02:44:40 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309928774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.3309928774
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/13.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_large_delays.2691217854
Short name T91
Test name
Test status
Simulation time 7251210402 ps
CPU time 43.72 seconds
Started Sep 11 02:44:35 AM UTC 24
Finished Sep 11 02:45:20 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691217854 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2691217854
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/13.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_slow_rsp.1136333213
Short name T389
Test name
Test status
Simulation time 73986079240 ps
CPU time 66.97 seconds
Started Sep 11 02:44:35 AM UTC 24
Finished Sep 11 02:45:44 AM UTC 24
Peak memory 212356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136333213 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.1136333213
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/13.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_zero_delays.2008496918
Short name T357
Test name
Test status
Simulation time 46851335 ps
CPU time 8.09 seconds
Started Sep 11 02:44:35 AM UTC 24
Finished Sep 11 02:44:44 AM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008496918 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.2008496918
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/13.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_same_source.1326567569
Short name T354
Test name
Test status
Simulation time 164593599 ps
CPU time 3.32 seconds
Started Sep 11 02:44:38 AM UTC 24
Finished Sep 11 02:44:43 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326567569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1326567569
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/13.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke.2559661085
Short name T351
Test name
Test status
Simulation time 73694438 ps
CPU time 1.97 seconds
Started Sep 11 02:44:27 AM UTC 24
Finished Sep 11 02:44:30 AM UTC 24
Peak memory 211236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559661085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.2559661085
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/13.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_large_delays.2993083596
Short name T175
Test name
Test status
Simulation time 1415244208 ps
CPU time 5.6 seconds
Started Sep 11 02:44:33 AM UTC 24
Finished Sep 11 02:44:39 AM UTC 24
Peak memory 212112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993083596 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2993083596
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/13.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.3213790365
Short name T355
Test name
Test status
Simulation time 2387968582 ps
CPU time 9.39 seconds
Started Sep 11 02:44:33 AM UTC 24
Finished Sep 11 02:44:43 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213790365 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.3213790365
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/13.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.2313318928
Short name T170
Test name
Test status
Simulation time 8017594 ps
CPU time 1.53 seconds
Started Sep 11 02:44:32 AM UTC 24
Finished Sep 11 02:44:34 AM UTC 24
Peak memory 211228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313318928 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.2313318928
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/13.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all.3217574463
Short name T230
Test name
Test status
Simulation time 995471755 ps
CPU time 17.82 seconds
Started Sep 11 02:44:41 AM UTC 24
Finished Sep 11 02:45:00 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217574463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3217574463
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/13.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_error.1063930593
Short name T364
Test name
Test status
Simulation time 49542515 ps
CPU time 6.88 seconds
Started Sep 11 02:44:44 AM UTC 24
Finished Sep 11 02:44:52 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063930593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.1063930593
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/13.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_unmapped_addr.3220719392
Short name T359
Test name
Test status
Simulation time 127455291 ps
CPU time 4.44 seconds
Started Sep 11 02:44:41 AM UTC 24
Finished Sep 11 02:44:46 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220719392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3220719392
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/13.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device.2234372273
Short name T226
Test name
Test status
Simulation time 24597580 ps
CPU time 5.09 seconds
Started Sep 11 02:44:50 AM UTC 24
Finished Sep 11 02:44:56 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234372273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.2234372273
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/14.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.592972528
Short name T232
Test name
Test status
Simulation time 125403383 ps
CPU time 4.59 seconds
Started Sep 11 02:44:55 AM UTC 24
Finished Sep 11 02:45:01 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592972528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.592972528
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/14.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_error_random.3758586977
Short name T231
Test name
Test status
Simulation time 38780754 ps
CPU time 5.1 seconds
Started Sep 11 02:44:54 AM UTC 24
Finished Sep 11 02:45:00 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758586977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.3758586977
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/14.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random.1204059192
Short name T89
Test name
Test status
Simulation time 1958994215 ps
CPU time 19.22 seconds
Started Sep 11 02:44:48 AM UTC 24
Finished Sep 11 02:45:08 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204059192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.1204059192
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/14.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_large_delays.3347283487
Short name T204
Test name
Test status
Simulation time 31117103420 ps
CPU time 117.91 seconds
Started Sep 11 02:44:49 AM UTC 24
Finished Sep 11 02:46:49 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347283487 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3347283487
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/14.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_slow_rsp.1715328890
Short name T435
Test name
Test status
Simulation time 39325695607 ps
CPU time 118.83 seconds
Started Sep 11 02:44:49 AM UTC 24
Finished Sep 11 02:46:50 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715328890 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1715328890
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/14.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_zero_delays.2410845087
Short name T366
Test name
Test status
Simulation time 111469511 ps
CPU time 5.34 seconds
Started Sep 11 02:44:48 AM UTC 24
Finished Sep 11 02:44:54 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410845087 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2410845087
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/14.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_same_source.1827052628
Short name T370
Test name
Test status
Simulation time 57623795 ps
CPU time 8.48 seconds
Started Sep 11 02:44:53 AM UTC 24
Finished Sep 11 02:45:03 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827052628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1827052628
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/14.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke.3612594001
Short name T363
Test name
Test status
Simulation time 11048046 ps
CPU time 1.82 seconds
Started Sep 11 02:44:45 AM UTC 24
Finished Sep 11 02:44:48 AM UTC 24
Peak memory 211236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612594001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3612594001
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/14.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_large_delays.3493727644
Short name T227
Test name
Test status
Simulation time 2205382928 ps
CPU time 10.07 seconds
Started Sep 11 02:44:46 AM UTC 24
Finished Sep 11 02:44:57 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493727644 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3493727644
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/14.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2322482833
Short name T233
Test name
Test status
Simulation time 1394996930 ps
CPU time 12.41 seconds
Started Sep 11 02:44:48 AM UTC 24
Finished Sep 11 02:45:01 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322482833 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2322482833
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/14.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.2041542205
Short name T361
Test name
Test status
Simulation time 9485384 ps
CPU time 1.47 seconds
Started Sep 11 02:44:45 AM UTC 24
Finished Sep 11 02:44:48 AM UTC 24
Peak memory 211124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041542205 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.2041542205
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/14.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all.386987377
Short name T384
Test name
Test status
Simulation time 2845542922 ps
CPU time 40.05 seconds
Started Sep 11 02:44:57 AM UTC 24
Finished Sep 11 02:45:39 AM UTC 24
Peak memory 214428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386987377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.386987377
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/14.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_error.483005345
Short name T393
Test name
Test status
Simulation time 19115536518 ps
CPU time 46.09 seconds
Started Sep 11 02:44:59 AM UTC 24
Finished Sep 11 02:45:46 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483005345 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.483005345
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/14.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.1399623092
Short name T386
Test name
Test status
Simulation time 2154782301 ps
CPU time 39.36 seconds
Started Sep 11 02:45:00 AM UTC 24
Finished Sep 11 02:45:41 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399623092 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.1399623092
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/14.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_unmapped_addr.1602004324
Short name T368
Test name
Test status
Simulation time 37507790 ps
CPU time 5.97 seconds
Started Sep 11 02:44:55 AM UTC 24
Finished Sep 11 02:45:02 AM UTC 24
Peak memory 212256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602004324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1602004324
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/14.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device.2770319362
Short name T259
Test name
Test status
Simulation time 248981008 ps
CPU time 3.62 seconds
Started Sep 11 02:45:03 AM UTC 24
Finished Sep 11 02:45:08 AM UTC 24
Peak memory 212320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770319362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.2770319362
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/15.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.2588219254
Short name T254
Test name
Test status
Simulation time 12893938168 ps
CPU time 68.03 seconds
Started Sep 11 02:45:05 AM UTC 24
Finished Sep 11 02:46:14 AM UTC 24
Peak memory 212504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588219254 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.2588219254
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/15.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.2120676264
Short name T140
Test name
Test status
Simulation time 65957690 ps
CPU time 4.01 seconds
Started Sep 11 02:45:09 AM UTC 24
Finished Sep 11 02:45:14 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120676264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2120676264
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/15.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_error_random.439618920
Short name T143
Test name
Test status
Simulation time 595249541 ps
CPU time 9.2 seconds
Started Sep 11 02:45:07 AM UTC 24
Finished Sep 11 02:45:17 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439618920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.439618920
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/15.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random.436348986
Short name T102
Test name
Test status
Simulation time 1268580055 ps
CPU time 6.6 seconds
Started Sep 11 02:45:02 AM UTC 24
Finished Sep 11 02:45:10 AM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436348986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.436348986
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/15.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_large_delays.1206898314
Short name T476
Test name
Test status
Simulation time 70392957421 ps
CPU time 151.44 seconds
Started Sep 11 02:45:03 AM UTC 24
Finished Sep 11 02:47:37 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206898314 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1206898314
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/15.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_slow_rsp.1705210953
Short name T437
Test name
Test status
Simulation time 23067137283 ps
CPU time 106.91 seconds
Started Sep 11 02:45:03 AM UTC 24
Finished Sep 11 02:46:52 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705210953 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1705210953
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/15.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_zero_delays.4112168856
Short name T373
Test name
Test status
Simulation time 31999087 ps
CPU time 1.59 seconds
Started Sep 11 02:45:03 AM UTC 24
Finished Sep 11 02:45:06 AM UTC 24
Peak memory 211128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112168856 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.4112168856
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/15.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_same_source.868144812
Short name T90
Test name
Test status
Simulation time 797208366 ps
CPU time 14.17 seconds
Started Sep 11 02:45:05 AM UTC 24
Finished Sep 11 02:45:20 AM UTC 24
Peak memory 212112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868144812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.868144812
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/15.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke.834933007
Short name T367
Test name
Test status
Simulation time 11876500 ps
CPU time 1.18 seconds
Started Sep 11 02:45:00 AM UTC 24
Finished Sep 11 02:45:02 AM UTC 24
Peak memory 211124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834933007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.834933007
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/15.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_large_delays.2437978550
Short name T362
Test name
Test status
Simulation time 2039716282 ps
CPU time 10.96 seconds
Started Sep 11 02:45:01 AM UTC 24
Finished Sep 11 02:45:13 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437978550 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2437978550
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/15.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.418132017
Short name T211
Test name
Test status
Simulation time 1914236555 ps
CPU time 7.59 seconds
Started Sep 11 02:45:02 AM UTC 24
Finished Sep 11 02:45:11 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418132017 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.418132017
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/15.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.3164274610
Short name T371
Test name
Test status
Simulation time 9460341 ps
CPU time 1.25 seconds
Started Sep 11 02:45:01 AM UTC 24
Finished Sep 11 02:45:03 AM UTC 24
Peak memory 211228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164274610 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.3164274610
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/15.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all.1020882702
Short name T103
Test name
Test status
Simulation time 1410656311 ps
CPU time 19.98 seconds
Started Sep 11 02:45:09 AM UTC 24
Finished Sep 11 02:45:31 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020882702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1020882702
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/15.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3550693516
Short name T406
Test name
Test status
Simulation time 25811917153 ps
CPU time 52.98 seconds
Started Sep 11 02:45:09 AM UTC 24
Finished Sep 11 02:46:04 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550693516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3550693516
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/15.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.1255529953
Short name T213
Test name
Test status
Simulation time 7581770 ps
CPU time 2.73 seconds
Started Sep 11 02:45:09 AM UTC 24
Finished Sep 11 02:45:13 AM UTC 24
Peak memory 212056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255529953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.1255529953
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/15.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.1610601864
Short name T284
Test name
Test status
Simulation time 733617198 ps
CPU time 117.01 seconds
Started Sep 11 02:45:11 AM UTC 24
Finished Sep 11 02:47:10 AM UTC 24
Peak memory 218272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610601864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.1610601864
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/15.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_unmapped_addr.915662136
Short name T209
Test name
Test status
Simulation time 515238547 ps
CPU time 4.6 seconds
Started Sep 11 02:45:07 AM UTC 24
Finished Sep 11 02:45:12 AM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915662136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.915662136
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/15.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device.1586213879
Short name T146
Test name
Test status
Simulation time 33582720 ps
CPU time 4.53 seconds
Started Sep 11 02:45:18 AM UTC 24
Finished Sep 11 02:45:23 AM UTC 24
Peak memory 212132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586213879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.1586213879
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/16.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.97758377
Short name T206
Test name
Test status
Simulation time 25904182819 ps
CPU time 126.7 seconds
Started Sep 11 02:45:18 AM UTC 24
Finished Sep 11 02:47:26 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97758377 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.97758377
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/16.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.1356508498
Short name T376
Test name
Test status
Simulation time 1198489111 ps
CPU time 6.54 seconds
Started Sep 11 02:45:22 AM UTC 24
Finished Sep 11 02:45:29 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356508498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.1356508498
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/16.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_error_random.1662621310
Short name T383
Test name
Test status
Simulation time 1420657285 ps
CPU time 14.84 seconds
Started Sep 11 02:45:21 AM UTC 24
Finished Sep 11 02:45:37 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662621310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1662621310
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/16.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random.2052714234
Short name T377
Test name
Test status
Simulation time 810293629 ps
CPU time 15.03 seconds
Started Sep 11 02:45:14 AM UTC 24
Finished Sep 11 02:45:30 AM UTC 24
Peak memory 212304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052714234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.2052714234
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/16.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_large_delays.1560659877
Short name T582
Test name
Test status
Simulation time 66446371195 ps
CPU time 222.62 seconds
Started Sep 11 02:45:15 AM UTC 24
Finished Sep 11 02:49:01 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560659877 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.1560659877
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/16.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_slow_rsp.2270977123
Short name T413
Test name
Test status
Simulation time 18730820817 ps
CPU time 52.28 seconds
Started Sep 11 02:45:15 AM UTC 24
Finished Sep 11 02:46:09 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270977123 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2270977123
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/16.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_zero_delays.3681172027
Short name T145
Test name
Test status
Simulation time 68828967 ps
CPU time 6.69 seconds
Started Sep 11 02:45:15 AM UTC 24
Finished Sep 11 02:45:23 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681172027 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.3681172027
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/16.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_same_source.1859943178
Short name T374
Test name
Test status
Simulation time 221745336 ps
CPU time 4.66 seconds
Started Sep 11 02:45:18 AM UTC 24
Finished Sep 11 02:45:23 AM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859943178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.1859943178
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/16.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke.2903064690
Short name T210
Test name
Test status
Simulation time 25336319 ps
CPU time 1.66 seconds
Started Sep 11 02:45:12 AM UTC 24
Finished Sep 11 02:45:14 AM UTC 24
Peak memory 211128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903064690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.2903064690
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/16.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_large_delays.1175560143
Short name T92
Test name
Test status
Simulation time 6295162770 ps
CPU time 15.61 seconds
Started Sep 11 02:45:14 AM UTC 24
Finished Sep 11 02:45:31 AM UTC 24
Peak memory 212268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175560143 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1175560143
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/16.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.1424955072
Short name T378
Test name
Test status
Simulation time 2076230618 ps
CPU time 15.13 seconds
Started Sep 11 02:45:14 AM UTC 24
Finished Sep 11 02:45:30 AM UTC 24
Peak memory 212032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424955072 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1424955072
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/16.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.4214882122
Short name T141
Test name
Test status
Simulation time 16978447 ps
CPU time 1.32 seconds
Started Sep 11 02:45:14 AM UTC 24
Finished Sep 11 02:45:16 AM UTC 24
Peak memory 211096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214882122 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.4214882122
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/16.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all.930677166
Short name T104
Test name
Test status
Simulation time 918923772 ps
CPU time 12.95 seconds
Started Sep 11 02:45:24 AM UTC 24
Finished Sep 11 02:45:38 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930677166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.930677166
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/16.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_error.1971762571
Short name T411
Test name
Test status
Simulation time 5071292317 ps
CPU time 42.9 seconds
Started Sep 11 02:45:24 AM UTC 24
Finished Sep 11 02:46:08 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971762571 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1971762571
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/16.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.729241777
Short name T131
Test name
Test status
Simulation time 17786542932 ps
CPU time 189.05 seconds
Started Sep 11 02:45:24 AM UTC 24
Finished Sep 11 02:48:36 AM UTC 24
Peak memory 216280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729241777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.729241777
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/16.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.3052420892
Short name T415
Test name
Test status
Simulation time 1884218710 ps
CPU time 40.64 seconds
Started Sep 11 02:45:28 AM UTC 24
Finished Sep 11 02:46:10 AM UTC 24
Peak memory 214244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052420892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.3052420892
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/16.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_unmapped_addr.2774481570
Short name T375
Test name
Test status
Simulation time 134091229 ps
CPU time 5.45 seconds
Started Sep 11 02:45:21 AM UTC 24
Finished Sep 11 02:45:27 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774481570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.2774481570
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/16.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device.2482389609
Short name T385
Test name
Test status
Simulation time 22747116 ps
CPU time 3.06 seconds
Started Sep 11 02:45:35 AM UTC 24
Finished Sep 11 02:45:39 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482389609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2482389609
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/17.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.988356056
Short name T252
Test name
Test status
Simulation time 28403423458 ps
CPU time 186.28 seconds
Started Sep 11 02:45:35 AM UTC 24
Finished Sep 11 02:48:44 AM UTC 24
Peak memory 214236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988356056 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.988356056
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/17.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.370485519
Short name T390
Test name
Test status
Simulation time 147405538 ps
CPU time 5.41 seconds
Started Sep 11 02:45:39 AM UTC 24
Finished Sep 11 02:45:45 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370485519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.370485519
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/17.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_error_random.2366379192
Short name T387
Test name
Test status
Simulation time 486186501 ps
CPU time 3.96 seconds
Started Sep 11 02:45:37 AM UTC 24
Finished Sep 11 02:45:42 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366379192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2366379192
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/17.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random.2980911193
Short name T381
Test name
Test status
Simulation time 160998107 ps
CPU time 3.61 seconds
Started Sep 11 02:45:32 AM UTC 24
Finished Sep 11 02:45:36 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980911193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.2980911193
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/17.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_large_delays.2386694513
Short name T408
Test name
Test status
Simulation time 9433934762 ps
CPU time 43.39 seconds
Started Sep 11 02:45:34 AM UTC 24
Finished Sep 11 02:46:19 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386694513 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.2386694513
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/17.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_slow_rsp.4232804007
Short name T420
Test name
Test status
Simulation time 5194076622 ps
CPU time 37.87 seconds
Started Sep 11 02:45:35 AM UTC 24
Finished Sep 11 02:46:14 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232804007 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.4232804007
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/17.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_zero_delays.1052802574
Short name T382
Test name
Test status
Simulation time 45237465 ps
CPU time 2.92 seconds
Started Sep 11 02:45:33 AM UTC 24
Finished Sep 11 02:45:37 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052802574 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.1052802574
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/17.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_same_source.43965873
Short name T106
Test name
Test status
Simulation time 4250587277 ps
CPU time 10.47 seconds
Started Sep 11 02:45:37 AM UTC 24
Finished Sep 11 02:45:49 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43965873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.43965873
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/17.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke.3200883092
Short name T379
Test name
Test status
Simulation time 134038767 ps
CPU time 2.47 seconds
Started Sep 11 02:45:30 AM UTC 24
Finished Sep 11 02:45:34 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200883092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3200883092
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/17.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_large_delays.4109343027
Short name T105
Test name
Test status
Simulation time 1151160837 ps
CPU time 11.36 seconds
Started Sep 11 02:45:32 AM UTC 24
Finished Sep 11 02:45:44 AM UTC 24
Peak memory 211992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109343027 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.4109343027
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/17.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.3897172737
Short name T397
Test name
Test status
Simulation time 3257325862 ps
CPU time 17.97 seconds
Started Sep 11 02:45:32 AM UTC 24
Finished Sep 11 02:45:51 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897172737 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.3897172737
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/17.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.32910859
Short name T380
Test name
Test status
Simulation time 28634593 ps
CPU time 1.52 seconds
Started Sep 11 02:45:32 AM UTC 24
Finished Sep 11 02:45:34 AM UTC 24
Peak memory 211232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32910859 -assert nopostproc +UVM_TESTNAME=xbar_
base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.32910859
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/17.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all.824840549
Short name T426
Test name
Test status
Simulation time 342223370 ps
CPU time 40.41 seconds
Started Sep 11 02:45:40 AM UTC 24
Finished Sep 11 02:46:22 AM UTC 24
Peak memory 214176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824840549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.824840549
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/17.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_error.3778081831
Short name T506
Test name
Test status
Simulation time 7259534957 ps
CPU time 131.06 seconds
Started Sep 11 02:45:42 AM UTC 24
Finished Sep 11 02:47:56 AM UTC 24
Peak memory 216284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778081831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3778081831
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/17.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.2143108745
Short name T280
Test name
Test status
Simulation time 3757826304 ps
CPU time 56.72 seconds
Started Sep 11 02:45:43 AM UTC 24
Finished Sep 11 02:46:41 AM UTC 24
Peak memory 214436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143108745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.2143108745
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/17.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_unmapped_addr.2340871686
Short name T391
Test name
Test status
Simulation time 78013969 ps
CPU time 6.86 seconds
Started Sep 11 02:45:37 AM UTC 24
Finished Sep 11 02:45:45 AM UTC 24
Peak memory 212260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340871686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2340871686
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/17.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device.2052203747
Short name T126
Test name
Test status
Simulation time 618306586 ps
CPU time 12.94 seconds
Started Sep 11 02:45:48 AM UTC 24
Finished Sep 11 02:46:03 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052203747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.2052203747
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/18.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.2913163915
Short name T163
Test name
Test status
Simulation time 162438414515 ps
CPU time 236.47 seconds
Started Sep 11 02:45:50 AM UTC 24
Finished Sep 11 02:49:50 AM UTC 24
Peak memory 214304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913163915 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.2913163915
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/18.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.723335010
Short name T400
Test name
Test status
Simulation time 383369651 ps
CPU time 6.14 seconds
Started Sep 11 02:45:53 AM UTC 24
Finished Sep 11 02:46:01 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723335010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.723335010
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/18.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_error_random.2826898368
Short name T404
Test name
Test status
Simulation time 643428067 ps
CPU time 10.52 seconds
Started Sep 11 02:45:52 AM UTC 24
Finished Sep 11 02:46:03 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826898368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.2826898368
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/18.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random.111981708
Short name T190
Test name
Test status
Simulation time 1327635357 ps
CPU time 16.21 seconds
Started Sep 11 02:45:46 AM UTC 24
Finished Sep 11 02:46:04 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111981708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.111981708
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/18.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_large_delays.213039388
Short name T504
Test name
Test status
Simulation time 56667016186 ps
CPU time 122.78 seconds
Started Sep 11 02:45:47 AM UTC 24
Finished Sep 11 02:47:52 AM UTC 24
Peak memory 212048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213039388 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.213039388
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/18.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_slow_rsp.3372606659
Short name T489
Test name
Test status
Simulation time 12090344995 ps
CPU time 116.92 seconds
Started Sep 11 02:45:47 AM UTC 24
Finished Sep 11 02:47:47 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372606659 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.3372606659
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/18.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_zero_delays.3340998148
Short name T396
Test name
Test status
Simulation time 19887537 ps
CPU time 3.15 seconds
Started Sep 11 02:45:46 AM UTC 24
Finished Sep 11 02:45:51 AM UTC 24
Peak memory 212248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340998148 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.3340998148
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/18.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_same_source.3344367681
Short name T402
Test name
Test status
Simulation time 1926780916 ps
CPU time 9.49 seconds
Started Sep 11 02:45:51 AM UTC 24
Finished Sep 11 02:46:02 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344367681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3344367681
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/18.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke.4048077731
Short name T392
Test name
Test status
Simulation time 9696097 ps
CPU time 1.77 seconds
Started Sep 11 02:45:43 AM UTC 24
Finished Sep 11 02:45:46 AM UTC 24
Peak memory 211232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048077731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.4048077731
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/18.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_large_delays.2548818190
Short name T398
Test name
Test status
Simulation time 4041967874 ps
CPU time 6.98 seconds
Started Sep 11 02:45:45 AM UTC 24
Finished Sep 11 02:45:54 AM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548818190 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.2548818190
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/18.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.3364867333
Short name T399
Test name
Test status
Simulation time 6102466965 ps
CPU time 12.26 seconds
Started Sep 11 02:45:45 AM UTC 24
Finished Sep 11 02:45:59 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364867333 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.3364867333
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/18.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.4226093918
Short name T394
Test name
Test status
Simulation time 19299523 ps
CPU time 1.66 seconds
Started Sep 11 02:45:45 AM UTC 24
Finished Sep 11 02:45:48 AM UTC 24
Peak memory 211120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226093918 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.4226093918
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/18.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all.2530008952
Short name T178
Test name
Test status
Simulation time 5248633393 ps
CPU time 107.29 seconds
Started Sep 11 02:45:53 AM UTC 24
Finished Sep 11 02:47:43 AM UTC 24
Peak memory 214432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530008952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2530008952
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/18.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_error.2226603649
Short name T453
Test name
Test status
Simulation time 3821864060 ps
CPU time 76.22 seconds
Started Sep 11 02:45:58 AM UTC 24
Finished Sep 11 02:47:17 AM UTC 24
Peak memory 214236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226603649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.2226603649
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/18.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.2937842437
Short name T532
Test name
Test status
Simulation time 1419990928 ps
CPU time 139.49 seconds
Started Sep 11 02:45:54 AM UTC 24
Finished Sep 11 02:48:16 AM UTC 24
Peak memory 218268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937842437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.2937842437
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/18.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.282509842
Short name T534
Test name
Test status
Simulation time 5708499008 ps
CPU time 136.29 seconds
Started Sep 11 02:45:58 AM UTC 24
Finished Sep 11 02:48:18 AM UTC 24
Peak memory 218532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282509842 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.282509842
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/18.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_unmapped_addr.2687570509
Short name T201
Test name
Test status
Simulation time 1534940474 ps
CPU time 16.92 seconds
Started Sep 11 02:45:52 AM UTC 24
Finished Sep 11 02:46:10 AM UTC 24
Peak memory 212448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687570509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.2687570509
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/18.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device.938459519
Short name T127
Test name
Test status
Simulation time 1177398470 ps
CPU time 17.2 seconds
Started Sep 11 02:46:04 AM UTC 24
Finished Sep 11 02:46:23 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938459519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.938459519
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/19.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.2753481776
Short name T819
Test name
Test status
Simulation time 277564837122 ps
CPU time 362.07 seconds
Started Sep 11 02:46:04 AM UTC 24
Finished Sep 11 02:52:11 AM UTC 24
Peak memory 217940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753481776 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.2753481776
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/19.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.2873584446
Short name T425
Test name
Test status
Simulation time 2737856742 ps
CPU time 13.8 seconds
Started Sep 11 02:46:07 AM UTC 24
Finished Sep 11 02:46:22 AM UTC 24
Peak memory 212380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873584446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.2873584446
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/19.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_error_random.2494633419
Short name T422
Test name
Test status
Simulation time 503428435 ps
CPU time 8.45 seconds
Started Sep 11 02:46:05 AM UTC 24
Finished Sep 11 02:46:15 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494633419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.2494633419
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/19.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random.3705384735
Short name T410
Test name
Test status
Simulation time 188754294 ps
CPU time 3.92 seconds
Started Sep 11 02:46:02 AM UTC 24
Finished Sep 11 02:46:07 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705384735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.3705384735
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/19.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_large_delays.4230630542
Short name T198
Test name
Test status
Simulation time 48288207843 ps
CPU time 142.83 seconds
Started Sep 11 02:46:04 AM UTC 24
Finished Sep 11 02:48:29 AM UTC 24
Peak memory 212448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230630542 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.4230630542
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/19.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_slow_rsp.3564639892
Short name T488
Test name
Test status
Simulation time 34243233732 ps
CPU time 99.17 seconds
Started Sep 11 02:46:04 AM UTC 24
Finished Sep 11 02:47:46 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564639892 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.3564639892
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/19.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_zero_delays.1429658595
Short name T409
Test name
Test status
Simulation time 10802583 ps
CPU time 1.68 seconds
Started Sep 11 02:46:03 AM UTC 24
Finished Sep 11 02:46:06 AM UTC 24
Peak memory 211232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429658595 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.1429658595
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/19.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_same_source.1249514712
Short name T414
Test name
Test status
Simulation time 154042868 ps
CPU time 2.69 seconds
Started Sep 11 02:46:05 AM UTC 24
Finished Sep 11 02:46:09 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249514712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.1249514712
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/19.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke.4063885170
Short name T405
Test name
Test status
Simulation time 12013725 ps
CPU time 1.5 seconds
Started Sep 11 02:46:00 AM UTC 24
Finished Sep 11 02:46:03 AM UTC 24
Peak memory 211128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063885170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.4063885170
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/19.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_large_delays.2779744167
Short name T412
Test name
Test status
Simulation time 5005694933 ps
CPU time 6.91 seconds
Started Sep 11 02:46:00 AM UTC 24
Finished Sep 11 02:46:09 AM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779744167 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2779744167
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/19.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.1198795288
Short name T417
Test name
Test status
Simulation time 1722603822 ps
CPU time 8.63 seconds
Started Sep 11 02:46:02 AM UTC 24
Finished Sep 11 02:46:12 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198795288 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1198795288
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/19.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.1121433415
Short name T403
Test name
Test status
Simulation time 8773039 ps
CPU time 1.23 seconds
Started Sep 11 02:46:00 AM UTC 24
Finished Sep 11 02:46:03 AM UTC 24
Peak memory 211228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121433415 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.1121433415
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/19.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all.4065498955
Short name T436
Test name
Test status
Simulation time 578756696 ps
CPU time 41.54 seconds
Started Sep 11 02:46:08 AM UTC 24
Finished Sep 11 02:46:51 AM UTC 24
Peak memory 214176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065498955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.4065498955
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/19.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_error.4086149849
Short name T457
Test name
Test status
Simulation time 27465622189 ps
CPU time 69.43 seconds
Started Sep 11 02:46:09 AM UTC 24
Finished Sep 11 02:47:20 AM UTC 24
Peak memory 214232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086149849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.4086149849
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/19.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.2427937331
Short name T177
Test name
Test status
Simulation time 361734438 ps
CPU time 58.29 seconds
Started Sep 11 02:46:08 AM UTC 24
Finished Sep 11 02:47:08 AM UTC 24
Peak memory 214176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427937331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.2427937331
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/19.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.2282283864
Short name T279
Test name
Test status
Simulation time 120908233 ps
CPU time 25.29 seconds
Started Sep 11 02:46:10 AM UTC 24
Finished Sep 11 02:46:37 AM UTC 24
Peak memory 214176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282283864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.2282283864
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/19.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_unmapped_addr.3543033831
Short name T416
Test name
Test status
Simulation time 205574026 ps
CPU time 3.58 seconds
Started Sep 11 02:46:07 AM UTC 24
Finished Sep 11 02:46:11 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543033831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3543033831
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/19.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.3571392008
Short name T133
Test name
Test status
Simulation time 394533752086 ps
CPU time 449.51 seconds
Started Sep 11 02:41:37 AM UTC 24
Finished Sep 11 02:49:12 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571392008 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.3571392008
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/2.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.1777991130
Short name T240
Test name
Test status
Simulation time 644460985 ps
CPU time 7.7 seconds
Started Sep 11 02:41:43 AM UTC 24
Finished Sep 11 02:41:52 AM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777991130 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.1777991130
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/2.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_error_random.744625474
Short name T57
Test name
Test status
Simulation time 53912817 ps
CPU time 4.9 seconds
Started Sep 11 02:41:38 AM UTC 24
Finished Sep 11 02:41:44 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744625474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.744625474
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/2.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random.3044219065
Short name T46
Test name
Test status
Simulation time 452668512 ps
CPU time 10.48 seconds
Started Sep 11 02:41:33 AM UTC 24
Finished Sep 11 02:41:45 AM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044219065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.3044219065
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/2.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_large_delays.902411903
Short name T159
Test name
Test status
Simulation time 184658728349 ps
CPU time 234.07 seconds
Started Sep 11 02:41:34 AM UTC 24
Finished Sep 11 02:45:32 AM UTC 24
Peak memory 212096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902411903 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.902411903
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/2.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_slow_rsp.2685056722
Short name T64
Test name
Test status
Simulation time 3365785229 ps
CPU time 47.59 seconds
Started Sep 11 02:41:34 AM UTC 24
Finished Sep 11 02:42:24 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685056722 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2685056722
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/2.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_zero_delays.807675394
Short name T28
Test name
Test status
Simulation time 183155460 ps
CPU time 6.68 seconds
Started Sep 11 02:41:34 AM UTC 24
Finished Sep 11 02:41:43 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807675394 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.807675394
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/2.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_same_source.3939256794
Short name T29
Test name
Test status
Simulation time 198258957 ps
CPU time 3.87 seconds
Started Sep 11 02:41:38 AM UTC 24
Finished Sep 11 02:41:43 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939256794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3939256794
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/2.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke.3160935148
Short name T44
Test name
Test status
Simulation time 288214694 ps
CPU time 1.89 seconds
Started Sep 11 02:41:31 AM UTC 24
Finished Sep 11 02:41:33 AM UTC 24
Peak memory 211232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160935148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3160935148
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/2.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.77981356
Short name T58
Test name
Test status
Simulation time 1166915670 ps
CPU time 11.33 seconds
Started Sep 11 02:41:32 AM UTC 24
Finished Sep 11 02:41:45 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77981356 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.77981356
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/2.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.1614293499
Short name T45
Test name
Test status
Simulation time 9558630 ps
CPU time 1.93 seconds
Started Sep 11 02:41:31 AM UTC 24
Finished Sep 11 02:41:34 AM UTC 24
Peak memory 211228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614293499 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.1614293499
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/2.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all.970660311
Short name T41
Test name
Test status
Simulation time 127422235 ps
CPU time 11.23 seconds
Started Sep 11 02:41:44 AM UTC 24
Finished Sep 11 02:41:57 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970660311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.970660311
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/2.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_error.410810862
Short name T269
Test name
Test status
Simulation time 8144447226 ps
CPU time 31.43 seconds
Started Sep 11 02:41:45 AM UTC 24
Finished Sep 11 02:42:18 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410810862 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.410810862
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/2.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.70967684
Short name T241
Test name
Test status
Simulation time 116378416 ps
CPU time 19.96 seconds
Started Sep 11 02:41:45 AM UTC 24
Finished Sep 11 02:42:07 AM UTC 24
Peak memory 214168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70967684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.70967684
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/2.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.978899528
Short name T265
Test name
Test status
Simulation time 152129591 ps
CPU time 14.64 seconds
Started Sep 11 02:41:46 AM UTC 24
Finished Sep 11 02:42:03 AM UTC 24
Peak memory 212132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978899528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.978899528
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/2.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_unmapped_addr.2548405936
Short name T47
Test name
Test status
Simulation time 38445369 ps
CPU time 5.04 seconds
Started Sep 11 02:41:40 AM UTC 24
Finished Sep 11 02:41:46 AM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548405936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2548405936
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/2.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device.2360378926
Short name T122
Test name
Test status
Simulation time 65541850 ps
CPU time 14.26 seconds
Started Sep 11 02:46:15 AM UTC 24
Finished Sep 11 02:46:31 AM UTC 24
Peak memory 211936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360378926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.2360378926
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/20.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1293880965
Short name T121
Test name
Test status
Simulation time 945941241 ps
CPU time 11.08 seconds
Started Sep 11 02:46:18 AM UTC 24
Finished Sep 11 02:46:30 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293880965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.1293880965
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/20.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_error_random.1752221861
Short name T427
Test name
Test status
Simulation time 201674958 ps
CPU time 6.04 seconds
Started Sep 11 02:46:16 AM UTC 24
Finished Sep 11 02:46:23 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752221861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.1752221861
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/20.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random.4182791488
Short name T421
Test name
Test status
Simulation time 16919530 ps
CPU time 1.92 seconds
Started Sep 11 02:46:12 AM UTC 24
Finished Sep 11 02:46:15 AM UTC 24
Peak memory 211128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182791488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.4182791488
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/20.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_large_delays.409374399
Short name T496
Test name
Test status
Simulation time 21168396692 ps
CPU time 94.61 seconds
Started Sep 11 02:46:14 AM UTC 24
Finished Sep 11 02:47:51 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409374399 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.409374399
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/20.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_slow_rsp.2743333157
Short name T468
Test name
Test status
Simulation time 26350898808 ps
CPU time 74.93 seconds
Started Sep 11 02:46:14 AM UTC 24
Finished Sep 11 02:47:31 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743333157 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.2743333157
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/20.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_zero_delays.370054614
Short name T161
Test name
Test status
Simulation time 73722797 ps
CPU time 9.48 seconds
Started Sep 11 02:46:13 AM UTC 24
Finished Sep 11 02:46:23 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370054614 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.370054614
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/20.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_same_source.1351584209
Short name T124
Test name
Test status
Simulation time 1190128064 ps
CPU time 18.16 seconds
Started Sep 11 02:46:16 AM UTC 24
Finished Sep 11 02:46:35 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351584209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1351584209
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/20.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke.1189955686
Short name T419
Test name
Test status
Simulation time 194699092 ps
CPU time 1.74 seconds
Started Sep 11 02:46:10 AM UTC 24
Finished Sep 11 02:46:13 AM UTC 24
Peak memory 211236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189955686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.1189955686
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/20.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_large_delays.3672329451
Short name T424
Test name
Test status
Simulation time 1843083033 ps
CPU time 8.04 seconds
Started Sep 11 02:46:10 AM UTC 24
Finished Sep 11 02:46:20 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672329451 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.3672329451
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/20.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.101028415
Short name T423
Test name
Test status
Simulation time 809411273 ps
CPU time 5.75 seconds
Started Sep 11 02:46:12 AM UTC 24
Finished Sep 11 02:46:18 AM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101028415 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.101028415
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/20.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.1063089453
Short name T418
Test name
Test status
Simulation time 7881389 ps
CPU time 1.51 seconds
Started Sep 11 02:46:10 AM UTC 24
Finished Sep 11 02:46:13 AM UTC 24
Peak memory 210920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063089453 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.1063089453
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/20.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all.1034736840
Short name T117
Test name
Test status
Simulation time 42409939 ps
CPU time 5.94 seconds
Started Sep 11 02:46:19 AM UTC 24
Finished Sep 11 02:46:26 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034736840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.1034736840
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/20.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_error.3366050683
Short name T439
Test name
Test status
Simulation time 1460147644 ps
CPU time 34.09 seconds
Started Sep 11 02:46:20 AM UTC 24
Finished Sep 11 02:46:56 AM UTC 24
Peak memory 212380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366050683 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.3366050683
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/20.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.2683665968
Short name T454
Test name
Test status
Simulation time 263187747 ps
CPU time 56.65 seconds
Started Sep 11 02:46:19 AM UTC 24
Finished Sep 11 02:47:17 AM UTC 24
Peak memory 214172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683665968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.2683665968
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/20.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.392553360
Short name T592
Test name
Test status
Simulation time 10532431699 ps
CPU time 161.17 seconds
Started Sep 11 02:46:22 AM UTC 24
Finished Sep 11 02:49:07 AM UTC 24
Peak memory 218532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392553360 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.392553360
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/20.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_unmapped_addr.1490772303
Short name T160
Test name
Test status
Simulation time 57089642 ps
CPU time 6.62 seconds
Started Sep 11 02:46:16 AM UTC 24
Finished Sep 11 02:46:23 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490772303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1490772303
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/20.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device.2230608823
Short name T256
Test name
Test status
Simulation time 1385710011 ps
CPU time 25.24 seconds
Started Sep 11 02:46:27 AM UTC 24
Finished Sep 11 02:46:54 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230608823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.2230608823
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/21.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3873547292
Short name T249
Test name
Test status
Simulation time 218933906912 ps
CPU time 189.43 seconds
Started Sep 11 02:46:28 AM UTC 24
Finished Sep 11 02:49:41 AM UTC 24
Peak memory 214232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873547292 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.3873547292
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/21.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.1803701685
Short name T428
Test name
Test status
Simulation time 67020965 ps
CPU time 3.06 seconds
Started Sep 11 02:46:32 AM UTC 24
Finished Sep 11 02:46:36 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803701685 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.1803701685
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/21.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_error_random.4281972153
Short name T429
Test name
Test status
Simulation time 779278230 ps
CPU time 4.08 seconds
Started Sep 11 02:46:31 AM UTC 24
Finished Sep 11 02:46:37 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281972153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.4281972153
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/21.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random.602583086
Short name T119
Test name
Test status
Simulation time 46850935 ps
CPU time 2.59 seconds
Started Sep 11 02:46:25 AM UTC 24
Finished Sep 11 02:46:29 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602583086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.602583086
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/21.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_large_delays.3874514969
Short name T150
Test name
Test status
Simulation time 34379562193 ps
CPU time 145.76 seconds
Started Sep 11 02:46:27 AM UTC 24
Finished Sep 11 02:48:55 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874514969 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3874514969
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/21.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_slow_rsp.3291744279
Short name T222
Test name
Test status
Simulation time 9580650055 ps
CPU time 47.28 seconds
Started Sep 11 02:46:27 AM UTC 24
Finished Sep 11 02:47:16 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291744279 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3291744279
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/21.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_zero_delays.1009119057
Short name T120
Test name
Test status
Simulation time 43801864 ps
CPU time 2.11 seconds
Started Sep 11 02:46:27 AM UTC 24
Finished Sep 11 02:46:30 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009119057 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.1009119057
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/21.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_same_source.3346506820
Short name T203
Test name
Test status
Simulation time 1861359830 ps
CPU time 16.72 seconds
Started Sep 11 02:46:29 AM UTC 24
Finished Sep 11 02:46:47 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346506820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3346506820
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/21.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke.4041920929
Short name T116
Test name
Test status
Simulation time 61209992 ps
CPU time 1.91 seconds
Started Sep 11 02:46:23 AM UTC 24
Finished Sep 11 02:46:26 AM UTC 24
Peak memory 211132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041920929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.4041920929
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/21.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_large_delays.2463719442
Short name T123
Test name
Test status
Simulation time 8975121341 ps
CPU time 9.85 seconds
Started Sep 11 02:46:24 AM UTC 24
Finished Sep 11 02:46:35 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463719442 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2463719442
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/21.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.447156573
Short name T432
Test name
Test status
Simulation time 2348109146 ps
CPU time 16.98 seconds
Started Sep 11 02:46:24 AM UTC 24
Finished Sep 11 02:46:42 AM UTC 24
Peak memory 212380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447156573 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.447156573
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/21.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.3848489117
Short name T118
Test name
Test status
Simulation time 9412037 ps
CPU time 1.75 seconds
Started Sep 11 02:46:24 AM UTC 24
Finished Sep 11 02:46:27 AM UTC 24
Peak memory 211176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848489117 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.3848489117
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/21.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all.3635570636
Short name T218
Test name
Test status
Simulation time 6241372729 ps
CPU time 61 seconds
Started Sep 11 02:46:36 AM UTC 24
Finished Sep 11 02:47:38 AM UTC 24
Peak memory 214060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635570636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.3635570636
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/21.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_error.3886136355
Short name T456
Test name
Test status
Simulation time 3374100579 ps
CPU time 40.45 seconds
Started Sep 11 02:46:38 AM UTC 24
Finished Sep 11 02:47:20 AM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886136355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3886136355
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/21.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.1738569205
Short name T507
Test name
Test status
Simulation time 4952108618 ps
CPU time 78.61 seconds
Started Sep 11 02:46:36 AM UTC 24
Finished Sep 11 02:47:56 AM UTC 24
Peak memory 214040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738569205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.1738569205
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/21.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.2194649294
Short name T573
Test name
Test status
Simulation time 3441768553 ps
CPU time 133.08 seconds
Started Sep 11 02:46:38 AM UTC 24
Finished Sep 11 02:48:54 AM UTC 24
Peak memory 218336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194649294 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.2194649294
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/21.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_unmapped_addr.549041215
Short name T202
Test name
Test status
Simulation time 167707961 ps
CPU time 3.43 seconds
Started Sep 11 02:46:31 AM UTC 24
Finished Sep 11 02:46:36 AM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549041215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.549041215
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/21.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device.904433405
Short name T440
Test name
Test status
Simulation time 48870335 ps
CPU time 6.64 seconds
Started Sep 11 02:46:48 AM UTC 24
Finished Sep 11 02:46:56 AM UTC 24
Peak memory 212320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904433405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.904433405
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/22.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.2627464405
Short name T271
Test name
Test status
Simulation time 10782069693 ps
CPU time 99.87 seconds
Started Sep 11 02:46:50 AM UTC 24
Finished Sep 11 02:48:32 AM UTC 24
Peak memory 212380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627464405 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.2627464405
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/22.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.2070787669
Short name T192
Test name
Test status
Simulation time 625193913 ps
CPU time 5.02 seconds
Started Sep 11 02:46:53 AM UTC 24
Finished Sep 11 02:46:59 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070787669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.2070787669
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/22.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_error_random.2688647533
Short name T441
Test name
Test status
Simulation time 1343428939 ps
CPU time 10.69 seconds
Started Sep 11 02:46:52 AM UTC 24
Finished Sep 11 02:47:03 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688647533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2688647533
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/22.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random.1967406091
Short name T148
Test name
Test status
Simulation time 2977579710 ps
CPU time 13.07 seconds
Started Sep 11 02:46:43 AM UTC 24
Finished Sep 11 02:46:57 AM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967406091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.1967406091
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/22.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_large_delays.2941957678
Short name T455
Test name
Test status
Simulation time 16387508338 ps
CPU time 35.7 seconds
Started Sep 11 02:46:43 AM UTC 24
Finished Sep 11 02:47:20 AM UTC 24
Peak memory 212256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941957678 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2941957678
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/22.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_slow_rsp.1548075552
Short name T197
Test name
Test status
Simulation time 1535046558 ps
CPU time 13.05 seconds
Started Sep 11 02:46:48 AM UTC 24
Finished Sep 11 02:47:02 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548075552 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1548075552
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/22.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_zero_delays.3649948244
Short name T433
Test name
Test status
Simulation time 39998277 ps
CPU time 2.76 seconds
Started Sep 11 02:46:43 AM UTC 24
Finished Sep 11 02:46:47 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649948244 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.3649948244
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/22.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_same_source.1901280458
Short name T191
Test name
Test status
Simulation time 158146772 ps
CPU time 4.19 seconds
Started Sep 11 02:46:51 AM UTC 24
Finished Sep 11 02:46:57 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901280458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1901280458
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/22.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke.3922213023
Short name T431
Test name
Test status
Simulation time 172612408 ps
CPU time 2.79 seconds
Started Sep 11 02:46:38 AM UTC 24
Finished Sep 11 02:46:42 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922213023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.3922213023
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/22.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1012840243
Short name T434
Test name
Test status
Simulation time 3059705035 ps
CPU time 10.62 seconds
Started Sep 11 02:46:38 AM UTC 24
Finished Sep 11 02:46:50 AM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012840243 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1012840243
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/22.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.1850630323
Short name T438
Test name
Test status
Simulation time 3406577826 ps
CPU time 12.22 seconds
Started Sep 11 02:46:41 AM UTC 24
Finished Sep 11 02:46:55 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850630323 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.1850630323
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/22.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.2433182371
Short name T430
Test name
Test status
Simulation time 20985895 ps
CPU time 1.86 seconds
Started Sep 11 02:46:38 AM UTC 24
Finished Sep 11 02:46:41 AM UTC 24
Peak memory 211124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433182371 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.2433182371
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/22.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all.3099405723
Short name T490
Test name
Test status
Simulation time 9604679587 ps
CPU time 50.69 seconds
Started Sep 11 02:46:55 AM UTC 24
Finished Sep 11 02:47:47 AM UTC 24
Peak memory 214236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099405723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.3099405723
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/22.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_error.3433895528
Short name T485
Test name
Test status
Simulation time 13235236625 ps
CPU time 43.76 seconds
Started Sep 11 02:46:57 AM UTC 24
Finished Sep 11 02:47:43 AM UTC 24
Peak memory 214428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433895528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3433895528
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/22.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1809263034
Short name T445
Test name
Test status
Simulation time 87565832 ps
CPU time 10.29 seconds
Started Sep 11 02:46:56 AM UTC 24
Finished Sep 11 02:47:07 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809263034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.1809263034
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/22.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.1068862425
Short name T443
Test name
Test status
Simulation time 39006617 ps
CPU time 6.48 seconds
Started Sep 11 02:46:57 AM UTC 24
Finished Sep 11 02:47:05 AM UTC 24
Peak memory 212132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068862425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.1068862425
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/22.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_unmapped_addr.3566061624
Short name T193
Test name
Test status
Simulation time 151033549 ps
CPU time 6.98 seconds
Started Sep 11 02:46:52 AM UTC 24
Finished Sep 11 02:47:00 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566061624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3566061624
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/22.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device.4132919629
Short name T446
Test name
Test status
Simulation time 775766643 ps
CPU time 5.27 seconds
Started Sep 11 02:47:03 AM UTC 24
Finished Sep 11 02:47:10 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132919629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.4132919629
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/23.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.909596578
Short name T180
Test name
Test status
Simulation time 137880273219 ps
CPU time 120.3 seconds
Started Sep 11 02:47:06 AM UTC 24
Finished Sep 11 02:49:08 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909596578 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.909596578
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/23.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.858908974
Short name T458
Test name
Test status
Simulation time 557842568 ps
CPU time 13.58 seconds
Started Sep 11 02:47:06 AM UTC 24
Finished Sep 11 02:47:21 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858908974 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.858908974
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/23.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_error_random.4112186012
Short name T448
Test name
Test status
Simulation time 54260350 ps
CPU time 4.28 seconds
Started Sep 11 02:47:06 AM UTC 24
Finished Sep 11 02:47:11 AM UTC 24
Peak memory 212320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112186012 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.4112186012
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/23.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random.1405397942
Short name T444
Test name
Test status
Simulation time 614959367 ps
CPU time 3.15 seconds
Started Sep 11 02:47:01 AM UTC 24
Finished Sep 11 02:47:05 AM UTC 24
Peak memory 212308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405397942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.1405397942
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/23.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_large_delays.3623196682
Short name T616
Test name
Test status
Simulation time 36926228004 ps
CPU time 142.63 seconds
Started Sep 11 02:47:01 AM UTC 24
Finished Sep 11 02:49:26 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623196682 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.3623196682
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/23.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_slow_rsp.1712256153
Short name T570
Test name
Test status
Simulation time 28704830998 ps
CPU time 107.57 seconds
Started Sep 11 02:47:02 AM UTC 24
Finished Sep 11 02:48:52 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712256153 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.1712256153
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/23.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_zero_delays.214813794
Short name T442
Test name
Test status
Simulation time 35470208 ps
CPU time 2.27 seconds
Started Sep 11 02:47:01 AM UTC 24
Finished Sep 11 02:47:04 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214813794 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.214813794
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/23.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_same_source.397435007
Short name T34
Test name
Test status
Simulation time 883282210 ps
CPU time 15.78 seconds
Started Sep 11 02:47:06 AM UTC 24
Finished Sep 11 02:47:23 AM UTC 24
Peak memory 212112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397435007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.397435007
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/23.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke.1738873903
Short name T196
Test name
Test status
Simulation time 90180962 ps
CPU time 2.06 seconds
Started Sep 11 02:46:57 AM UTC 24
Finished Sep 11 02:47:01 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738873903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.1738873903
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/23.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_large_delays.1717551512
Short name T460
Test name
Test status
Simulation time 2559341062 ps
CPU time 21.27 seconds
Started Sep 11 02:46:59 AM UTC 24
Finished Sep 11 02:47:21 AM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717551512 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.1717551512
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/23.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.523909570
Short name T33
Test name
Test status
Simulation time 3864466456 ps
CPU time 12.61 seconds
Started Sep 11 02:47:00 AM UTC 24
Finished Sep 11 02:47:14 AM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523909570 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.523909570
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/23.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.1970378636
Short name T195
Test name
Test status
Simulation time 10220389 ps
CPU time 1.86 seconds
Started Sep 11 02:46:58 AM UTC 24
Finished Sep 11 02:47:00 AM UTC 24
Peak memory 211168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970378636 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.1970378636
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/23.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all.3772331555
Short name T466
Test name
Test status
Simulation time 123489895 ps
CPU time 18.08 seconds
Started Sep 11 02:47:08 AM UTC 24
Finished Sep 11 02:47:27 AM UTC 24
Peak memory 214176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772331555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.3772331555
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/23.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_error.1189777847
Short name T604
Test name
Test status
Simulation time 7877781438 ps
CPU time 122.07 seconds
Started Sep 11 02:47:10 AM UTC 24
Finished Sep 11 02:49:15 AM UTC 24
Peak memory 212152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189777847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1189777847
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/23.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.1697426045
Short name T509
Test name
Test status
Simulation time 1574192054 ps
CPU time 47.3 seconds
Started Sep 11 02:47:09 AM UTC 24
Finished Sep 11 02:47:58 AM UTC 24
Peak memory 214368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697426045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.1697426045
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/23.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.201863742
Short name T536
Test name
Test status
Simulation time 1275353760 ps
CPU time 66.57 seconds
Started Sep 11 02:47:10 AM UTC 24
Finished Sep 11 02:48:19 AM UTC 24
Peak memory 214136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201863742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.201863742
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/23.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_unmapped_addr.3713606062
Short name T450
Test name
Test status
Simulation time 105833208 ps
CPU time 8.06 seconds
Started Sep 11 02:47:06 AM UTC 24
Finished Sep 11 02:47:15 AM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713606062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.3713606062
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/23.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device.2310847400
Short name T459
Test name
Test status
Simulation time 30539749 ps
CPU time 1.86 seconds
Started Sep 11 02:47:18 AM UTC 24
Finished Sep 11 02:47:21 AM UTC 24
Peak memory 211240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310847400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.2310847400
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/24.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.2165846088
Short name T194
Test name
Test status
Simulation time 282716869 ps
CPU time 4.22 seconds
Started Sep 11 02:47:22 AM UTC 24
Finished Sep 11 02:47:27 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165846088 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.2165846088
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/24.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_error_random.4244091824
Short name T471
Test name
Test status
Simulation time 2187302117 ps
CPU time 12.41 seconds
Started Sep 11 02:47:21 AM UTC 24
Finished Sep 11 02:47:35 AM UTC 24
Peak memory 212380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244091824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.4244091824
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/24.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random.2484134477
Short name T463
Test name
Test status
Simulation time 96832929 ps
CPU time 8.56 seconds
Started Sep 11 02:47:15 AM UTC 24
Finished Sep 11 02:47:25 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484134477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.2484134477
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/24.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_large_delays.1928325433
Short name T612
Test name
Test status
Simulation time 128995805106 ps
CPU time 124.24 seconds
Started Sep 11 02:47:17 AM UTC 24
Finished Sep 11 02:49:23 AM UTC 24
Peak memory 212368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928325433 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1928325433
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/24.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_slow_rsp.668011383
Short name T505
Test name
Test status
Simulation time 3271032903 ps
CPU time 36.4 seconds
Started Sep 11 02:47:17 AM UTC 24
Finished Sep 11 02:47:55 AM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668011383 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.668011383
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/24.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_zero_delays.3977532068
Short name T464
Test name
Test status
Simulation time 152312850 ps
CPU time 9.01 seconds
Started Sep 11 02:47:17 AM UTC 24
Finished Sep 11 02:47:27 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977532068 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.3977532068
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/24.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_same_source.4014846224
Short name T470
Test name
Test status
Simulation time 1051533553 ps
CPU time 12 seconds
Started Sep 11 02:47:21 AM UTC 24
Finished Sep 11 02:47:35 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014846224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.4014846224
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/24.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke.1640096151
Short name T451
Test name
Test status
Simulation time 81642848 ps
CPU time 2.05 seconds
Started Sep 11 02:47:12 AM UTC 24
Finished Sep 11 02:47:15 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640096151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1640096151
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/24.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_large_delays.1904497269
Short name T462
Test name
Test status
Simulation time 2874980253 ps
CPU time 8.96 seconds
Started Sep 11 02:47:13 AM UTC 24
Finished Sep 11 02:47:23 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904497269 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1904497269
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/24.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.2695079575
Short name T461
Test name
Test status
Simulation time 3439775402 ps
CPU time 7.56 seconds
Started Sep 11 02:47:14 AM UTC 24
Finished Sep 11 02:47:23 AM UTC 24
Peak memory 212444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695079575 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2695079575
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/24.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1780089535
Short name T452
Test name
Test status
Simulation time 14219207 ps
CPU time 1.56 seconds
Started Sep 11 02:47:12 AM UTC 24
Finished Sep 11 02:47:16 AM UTC 24
Peak memory 211124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780089535 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1780089535
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/24.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all.1467459282
Short name T493
Test name
Test status
Simulation time 352777330 ps
CPU time 26.69 seconds
Started Sep 11 02:47:22 AM UTC 24
Finished Sep 11 02:47:50 AM UTC 24
Peak memory 214368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467459282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.1467459282
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/24.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_error.2437398273
Short name T557
Test name
Test status
Simulation time 8673601634 ps
CPU time 76.21 seconds
Started Sep 11 02:47:23 AM UTC 24
Finished Sep 11 02:48:41 AM UTC 24
Peak memory 214492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437398273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2437398273
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/24.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.3300281338
Short name T474
Test name
Test status
Simulation time 80206274 ps
CPU time 12.7 seconds
Started Sep 11 02:47:23 AM UTC 24
Finished Sep 11 02:47:37 AM UTC 24
Peak memory 214172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300281338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.3300281338
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/24.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.657773934
Short name T478
Test name
Test status
Simulation time 82134250 ps
CPU time 11.79 seconds
Started Sep 11 02:47:24 AM UTC 24
Finished Sep 11 02:47:37 AM UTC 24
Peak memory 212132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657773934 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.657773934
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/24.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_unmapped_addr.1972690731
Short name T469
Test name
Test status
Simulation time 614046395 ps
CPU time 11.01 seconds
Started Sep 11 02:47:22 AM UTC 24
Finished Sep 11 02:47:34 AM UTC 24
Peak memory 212448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972690731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1972690731
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/24.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device.3507258711
Short name T479
Test name
Test status
Simulation time 436403343 ps
CPU time 9.4 seconds
Started Sep 11 02:47:28 AM UTC 24
Finished Sep 11 02:47:39 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507258711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3507258711
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/25.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.2431679021
Short name T207
Test name
Test status
Simulation time 14004765634 ps
CPU time 66.62 seconds
Started Sep 11 02:47:31 AM UTC 24
Finished Sep 11 02:48:40 AM UTC 24
Peak memory 212380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431679021 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.2431679021
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/25.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.690748415
Short name T482
Test name
Test status
Simulation time 135369627 ps
CPU time 3.93 seconds
Started Sep 11 02:47:36 AM UTC 24
Finished Sep 11 02:47:41 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690748415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.690748415
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/25.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_error_random.3056782267
Short name T486
Test name
Test status
Simulation time 567439095 ps
CPU time 8.26 seconds
Started Sep 11 02:47:36 AM UTC 24
Finished Sep 11 02:47:45 AM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056782267 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.3056782267
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/25.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random.1665743683
Short name T473
Test name
Test status
Simulation time 230491317 ps
CPU time 7.69 seconds
Started Sep 11 02:47:28 AM UTC 24
Finished Sep 11 02:47:37 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665743683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.1665743683
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/25.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_large_delays.2579669742
Short name T149
Test name
Test status
Simulation time 18928502265 ps
CPU time 64.01 seconds
Started Sep 11 02:47:28 AM UTC 24
Finished Sep 11 02:48:34 AM UTC 24
Peak memory 212512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579669742 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2579669742
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/25.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_slow_rsp.3079626480
Short name T715
Test name
Test status
Simulation time 46486434909 ps
CPU time 193.96 seconds
Started Sep 11 02:47:28 AM UTC 24
Finished Sep 11 02:50:45 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079626480 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.3079626480
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/25.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_zero_delays.2264638975
Short name T472
Test name
Test status
Simulation time 185596891 ps
CPU time 5.65 seconds
Started Sep 11 02:47:28 AM UTC 24
Finished Sep 11 02:47:35 AM UTC 24
Peak memory 212308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264638975 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.2264638975
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/25.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_same_source.2097521453
Short name T494
Test name
Test status
Simulation time 3429750561 ps
CPU time 14.71 seconds
Started Sep 11 02:47:34 AM UTC 24
Finished Sep 11 02:47:50 AM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097521453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2097521453
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/25.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke.1045737944
Short name T465
Test name
Test status
Simulation time 9655644 ps
CPU time 1.55 seconds
Started Sep 11 02:47:24 AM UTC 24
Finished Sep 11 02:47:27 AM UTC 24
Peak memory 211236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045737944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.1045737944
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/25.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_large_delays.3233660497
Short name T480
Test name
Test status
Simulation time 3085647772 ps
CPU time 12.12 seconds
Started Sep 11 02:47:26 AM UTC 24
Finished Sep 11 02:47:40 AM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233660497 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3233660497
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/25.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.1448647427
Short name T475
Test name
Test status
Simulation time 2605435254 ps
CPU time 8.11 seconds
Started Sep 11 02:47:28 AM UTC 24
Finished Sep 11 02:47:37 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448647427 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.1448647427
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/25.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.2816334896
Short name T467
Test name
Test status
Simulation time 9576340 ps
CPU time 1.81 seconds
Started Sep 11 02:47:24 AM UTC 24
Finished Sep 11 02:47:27 AM UTC 24
Peak memory 211224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816334896 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.2816334896
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/25.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all.2340915243
Short name T132
Test name
Test status
Simulation time 36057799467 ps
CPU time 90.33 seconds
Started Sep 11 02:47:36 AM UTC 24
Finished Sep 11 02:49:08 AM UTC 24
Peak memory 214236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340915243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.2340915243
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/25.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_error.3857047916
Short name T580
Test name
Test status
Simulation time 7189289809 ps
CPU time 77.99 seconds
Started Sep 11 02:47:38 AM UTC 24
Finished Sep 11 02:48:58 AM UTC 24
Peak memory 212380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857047916 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.3857047916
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/25.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.3196901587
Short name T168
Test name
Test status
Simulation time 859977276 ps
CPU time 49.53 seconds
Started Sep 11 02:47:37 AM UTC 24
Finished Sep 11 02:48:28 AM UTC 24
Peak memory 214176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196901587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.3196901587
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/25.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.4088161415
Short name T520
Test name
Test status
Simulation time 200422443 ps
CPU time 28.35 seconds
Started Sep 11 02:47:38 AM UTC 24
Finished Sep 11 02:48:08 AM UTC 24
Peak memory 214180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088161415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.4088161415
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/25.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_unmapped_addr.3812890029
Short name T481
Test name
Test status
Simulation time 134612436 ps
CPU time 3.9 seconds
Started Sep 11 02:47:36 AM UTC 24
Finished Sep 11 02:47:41 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812890029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3812890029
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/25.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device.1064148236
Short name T495
Test name
Test status
Simulation time 205482065 ps
CPU time 7.13 seconds
Started Sep 11 02:47:42 AM UTC 24
Finished Sep 11 02:47:50 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064148236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.1064148236
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/26.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.1496639983
Short name T544
Test name
Test status
Simulation time 5829996235 ps
CPU time 45.83 seconds
Started Sep 11 02:47:42 AM UTC 24
Finished Sep 11 02:48:30 AM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496639983 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.1496639983
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/26.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.530899417
Short name T497
Test name
Test status
Simulation time 415949653 ps
CPU time 4.14 seconds
Started Sep 11 02:47:46 AM UTC 24
Finished Sep 11 02:47:51 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530899417 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.530899417
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/26.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_error_random.3961277753
Short name T502
Test name
Test status
Simulation time 325861809 ps
CPU time 7.39 seconds
Started Sep 11 02:47:44 AM UTC 24
Finished Sep 11 02:47:52 AM UTC 24
Peak memory 212380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961277753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3961277753
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/26.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random.2947709025
Short name T503
Test name
Test status
Simulation time 1067177781 ps
CPU time 11.23 seconds
Started Sep 11 02:47:40 AM UTC 24
Finished Sep 11 02:47:52 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947709025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.2947709025
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/26.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_large_delays.3558347979
Short name T595
Test name
Test status
Simulation time 26344343151 ps
CPU time 84.87 seconds
Started Sep 11 02:47:42 AM UTC 24
Finished Sep 11 02:49:09 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558347979 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.3558347979
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/26.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_slow_rsp.29163066
Short name T40
Test name
Test status
Simulation time 127345080897 ps
CPU time 175.08 seconds
Started Sep 11 02:47:42 AM UTC 24
Finished Sep 11 02:50:40 AM UTC 24
Peak memory 212176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29163066 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.29163066
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/26.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_zero_delays.3688505688
Short name T487
Test name
Test status
Simulation time 55403306 ps
CPU time 3.41 seconds
Started Sep 11 02:47:41 AM UTC 24
Finished Sep 11 02:47:45 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688505688 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.3688505688
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/26.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_same_source.37473269
Short name T499
Test name
Test status
Simulation time 268932956 ps
CPU time 6.76 seconds
Started Sep 11 02:47:44 AM UTC 24
Finished Sep 11 02:47:51 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37473269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.37473269
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/26.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke.3256796784
Short name T484
Test name
Test status
Simulation time 18933566 ps
CPU time 1.8 seconds
Started Sep 11 02:47:38 AM UTC 24
Finished Sep 11 02:47:41 AM UTC 24
Peak memory 211236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256796784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.3256796784
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/26.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_large_delays.673018084
Short name T491
Test name
Test status
Simulation time 1810915885 ps
CPU time 7.65 seconds
Started Sep 11 02:47:39 AM UTC 24
Finished Sep 11 02:47:47 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673018084 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.673018084
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/26.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.2556299820
Short name T492
Test name
Test status
Simulation time 1017165765 ps
CPU time 8.05 seconds
Started Sep 11 02:47:40 AM UTC 24
Finished Sep 11 02:47:49 AM UTC 24
Peak memory 212320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556299820 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.2556299820
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/26.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.2412984841
Short name T483
Test name
Test status
Simulation time 13123021 ps
CPU time 1.49 seconds
Started Sep 11 02:47:39 AM UTC 24
Finished Sep 11 02:47:41 AM UTC 24
Peak memory 211224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412984841 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.2412984841
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/26.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all.3461430309
Short name T528
Test name
Test status
Simulation time 216112625 ps
CPU time 28.11 seconds
Started Sep 11 02:47:46 AM UTC 24
Finished Sep 11 02:48:15 AM UTC 24
Peak memory 214172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461430309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3461430309
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/26.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_error.251788099
Short name T533
Test name
Test status
Simulation time 753950453 ps
CPU time 29.16 seconds
Started Sep 11 02:47:47 AM UTC 24
Finished Sep 11 02:48:18 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251788099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.251788099
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/26.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.3254226903
Short name T575
Test name
Test status
Simulation time 519520284 ps
CPU time 67.61 seconds
Started Sep 11 02:47:46 AM UTC 24
Finished Sep 11 02:48:56 AM UTC 24
Peak memory 214172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254226903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.3254226903
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/26.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.2124114990
Short name T658
Test name
Test status
Simulation time 1075364543 ps
CPU time 122.6 seconds
Started Sep 11 02:47:48 AM UTC 24
Finished Sep 11 02:49:53 AM UTC 24
Peak memory 218272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124114990 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.2124114990
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/26.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_unmapped_addr.1728768344
Short name T501
Test name
Test status
Simulation time 467766889 ps
CPU time 7.33 seconds
Started Sep 11 02:47:44 AM UTC 24
Finished Sep 11 02:47:52 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728768344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.1728768344
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/26.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device.2460670430
Short name T214
Test name
Test status
Simulation time 389198220 ps
CPU time 8.15 seconds
Started Sep 11 02:47:53 AM UTC 24
Finished Sep 11 02:48:02 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460670430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.2460670430
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/27.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.254668023
Short name T200
Test name
Test status
Simulation time 40867008532 ps
CPU time 386.46 seconds
Started Sep 11 02:47:53 AM UTC 24
Finished Sep 11 02:54:24 AM UTC 24
Peak memory 217944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254668023 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.254668023
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/27.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.3179474542
Short name T519
Test name
Test status
Simulation time 935563787 ps
CPU time 12.57 seconds
Started Sep 11 02:47:53 AM UTC 24
Finished Sep 11 02:48:07 AM UTC 24
Peak memory 212380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179474542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.3179474542
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/27.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_error_random.2971402659
Short name T511
Test name
Test status
Simulation time 249057198 ps
CPU time 5.23 seconds
Started Sep 11 02:47:53 AM UTC 24
Finished Sep 11 02:47:59 AM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971402659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2971402659
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/27.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random.4159699664
Short name T518
Test name
Test status
Simulation time 983495559 ps
CPU time 13.11 seconds
Started Sep 11 02:47:51 AM UTC 24
Finished Sep 11 02:48:06 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159699664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.4159699664
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/27.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_large_delays.696598004
Short name T537
Test name
Test status
Simulation time 9181218711 ps
CPU time 26.86 seconds
Started Sep 11 02:47:51 AM UTC 24
Finished Sep 11 02:48:20 AM UTC 24
Peak memory 212440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696598004 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.696598004
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/27.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_slow_rsp.635754682
Short name T522
Test name
Test status
Simulation time 5746391890 ps
CPU time 15.02 seconds
Started Sep 11 02:47:53 AM UTC 24
Finished Sep 11 02:48:09 AM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635754682 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.635754682
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/27.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_zero_delays.1919458606
Short name T508
Test name
Test status
Simulation time 27585054 ps
CPU time 4.38 seconds
Started Sep 11 02:47:51 AM UTC 24
Finished Sep 11 02:47:57 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919458606 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.1919458606
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/27.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_same_source.292102568
Short name T510
Test name
Test status
Simulation time 1254808554 ps
CPU time 4.3 seconds
Started Sep 11 02:47:53 AM UTC 24
Finished Sep 11 02:47:58 AM UTC 24
Peak memory 212368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292102568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.292102568
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/27.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke.930788935
Short name T500
Test name
Test status
Simulation time 53829805 ps
CPU time 2.48 seconds
Started Sep 11 02:47:49 AM UTC 24
Finished Sep 11 02:47:52 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930788935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.930788935
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/27.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_large_delays.1578204033
Short name T513
Test name
Test status
Simulation time 2648223583 ps
CPU time 9.4 seconds
Started Sep 11 02:47:50 AM UTC 24
Finished Sep 11 02:48:00 AM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578204033 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1578204033
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/27.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3797232714
Short name T512
Test name
Test status
Simulation time 623519275 ps
CPU time 7.33 seconds
Started Sep 11 02:47:51 AM UTC 24
Finished Sep 11 02:48:00 AM UTC 24
Peak memory 212320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797232714 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3797232714
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/27.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.644794661
Short name T498
Test name
Test status
Simulation time 15058425 ps
CPU time 1.81 seconds
Started Sep 11 02:47:49 AM UTC 24
Finished Sep 11 02:47:51 AM UTC 24
Peak memory 211224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644794661 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.644794661
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/27.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all.253338914
Short name T526
Test name
Test status
Simulation time 145280435 ps
CPU time 17.33 seconds
Started Sep 11 02:47:54 AM UTC 24
Finished Sep 11 02:48:13 AM UTC 24
Peak memory 214168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253338914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.253338914
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/27.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_error.1710159708
Short name T578
Test name
Test status
Simulation time 1142785741 ps
CPU time 58.61 seconds
Started Sep 11 02:47:57 AM UTC 24
Finished Sep 11 02:48:57 AM UTC 24
Peak memory 214172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710159708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.1710159708
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/27.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.3476462421
Short name T671
Test name
Test status
Simulation time 4432015944 ps
CPU time 124.51 seconds
Started Sep 11 02:47:56 AM UTC 24
Finished Sep 11 02:50:02 AM UTC 24
Peak memory 218528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476462421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.3476462421
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/27.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.2064166535
Short name T611
Test name
Test status
Simulation time 729065286 ps
CPU time 84.19 seconds
Started Sep 11 02:47:57 AM UTC 24
Finished Sep 11 02:49:23 AM UTC 24
Peak memory 216224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064166535 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.2064166535
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/27.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_unmapped_addr.2730382228
Short name T516
Test name
Test status
Simulation time 1609033584 ps
CPU time 8.55 seconds
Started Sep 11 02:47:53 AM UTC 24
Finished Sep 11 02:48:03 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730382228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2730382228
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/27.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device.88332028
Short name T524
Test name
Test status
Simulation time 1768156337 ps
CPU time 6.44 seconds
Started Sep 11 02:48:03 AM UTC 24
Finished Sep 11 02:48:11 AM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88332028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.88332028
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/28.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.4140524510
Short name T270
Test name
Test status
Simulation time 35063544547 ps
CPU time 264.87 seconds
Started Sep 11 02:48:03 AM UTC 24
Finished Sep 11 02:52:32 AM UTC 24
Peak memory 216280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140524510 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.4140524510
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/28.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.1420054949
Short name T525
Test name
Test status
Simulation time 111309621 ps
CPU time 3.84 seconds
Started Sep 11 02:48:08 AM UTC 24
Finished Sep 11 02:48:13 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420054949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.1420054949
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/28.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_error_random.2403571111
Short name T538
Test name
Test status
Simulation time 953111870 ps
CPU time 16.38 seconds
Started Sep 11 02:48:04 AM UTC 24
Finished Sep 11 02:48:22 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403571111 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.2403571111
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/28.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random.2510706500
Short name T521
Test name
Test status
Simulation time 361717571 ps
CPU time 6.57 seconds
Started Sep 11 02:48:01 AM UTC 24
Finished Sep 11 02:48:08 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510706500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.2510706500
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/28.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_large_delays.1014169935
Short name T632
Test name
Test status
Simulation time 55955125393 ps
CPU time 92.97 seconds
Started Sep 11 02:48:01 AM UTC 24
Finished Sep 11 02:49:36 AM UTC 24
Peak memory 212444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014169935 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1014169935
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/28.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_slow_rsp.2423650214
Short name T726
Test name
Test status
Simulation time 67170179679 ps
CPU time 175.67 seconds
Started Sep 11 02:48:01 AM UTC 24
Finished Sep 11 02:50:59 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423650214 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2423650214
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/28.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_zero_delays.1535861662
Short name T517
Test name
Test status
Simulation time 9359652 ps
CPU time 1.66 seconds
Started Sep 11 02:48:01 AM UTC 24
Finished Sep 11 02:48:03 AM UTC 24
Peak memory 211132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535861662 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.1535861662
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/28.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_same_source.4152706759
Short name T527
Test name
Test status
Simulation time 66421807 ps
CPU time 9.03 seconds
Started Sep 11 02:48:04 AM UTC 24
Finished Sep 11 02:48:14 AM UTC 24
Peak memory 212444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152706759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.4152706759
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/28.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke.2818844934
Short name T514
Test name
Test status
Simulation time 9768722 ps
CPU time 1.43 seconds
Started Sep 11 02:47:58 AM UTC 24
Finished Sep 11 02:48:00 AM UTC 24
Peak memory 211236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818844934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.2818844934
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/28.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_large_delays.4171364915
Short name T529
Test name
Test status
Simulation time 2329867823 ps
CPU time 15.36 seconds
Started Sep 11 02:47:59 AM UTC 24
Finished Sep 11 02:48:16 AM UTC 24
Peak memory 211852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171364915 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.4171364915
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/28.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.970857931
Short name T539
Test name
Test status
Simulation time 11754448352 ps
CPU time 22.1 seconds
Started Sep 11 02:48:00 AM UTC 24
Finished Sep 11 02:48:23 AM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970857931 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.970857931
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/28.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.1110570530
Short name T515
Test name
Test status
Simulation time 19948009 ps
CPU time 1.71 seconds
Started Sep 11 02:47:59 AM UTC 24
Finished Sep 11 02:48:02 AM UTC 24
Peak memory 210732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110570530 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.1110570530
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/28.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all.300426459
Short name T625
Test name
Test status
Simulation time 4124467534 ps
CPU time 80.08 seconds
Started Sep 11 02:48:09 AM UTC 24
Finished Sep 11 02:49:31 AM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300426459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.300426459
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/28.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_error.3065052445
Short name T542
Test name
Test status
Simulation time 990442191 ps
CPU time 15.66 seconds
Started Sep 11 02:48:10 AM UTC 24
Finished Sep 11 02:48:27 AM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065052445 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.3065052445
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/28.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.3242637986
Short name T199
Test name
Test status
Simulation time 6318989633 ps
CPU time 144.08 seconds
Started Sep 11 02:48:09 AM UTC 24
Finished Sep 11 02:50:36 AM UTC 24
Peak memory 216544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242637986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.3242637986
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/28.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.4153701781
Short name T548
Test name
Test status
Simulation time 335878967 ps
CPU time 18.84 seconds
Started Sep 11 02:48:11 AM UTC 24
Finished Sep 11 02:48:31 AM UTC 24
Peak memory 214176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153701781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.4153701781
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/28.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_unmapped_addr.682034378
Short name T477
Test name
Test status
Simulation time 1379066993 ps
CPU time 11.67 seconds
Started Sep 11 02:48:07 AM UTC 24
Finished Sep 11 02:48:19 AM UTC 24
Peak memory 212320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682034378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.682034378
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/28.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device.16768369
Short name T540
Test name
Test status
Simulation time 46484948 ps
CPU time 6.01 seconds
Started Sep 11 02:48:19 AM UTC 24
Finished Sep 11 02:48:26 AM UTC 24
Peak memory 212024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16768369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.16768369
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/29.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.3686366308
Short name T273
Test name
Test status
Simulation time 37032347310 ps
CPU time 244.84 seconds
Started Sep 11 02:48:19 AM UTC 24
Finished Sep 11 02:52:27 AM UTC 24
Peak memory 214228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686366308 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.3686366308
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/29.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.4272257147
Short name T549
Test name
Test status
Simulation time 2752419770 ps
CPU time 8.65 seconds
Started Sep 11 02:48:23 AM UTC 24
Finished Sep 11 02:48:33 AM UTC 24
Peak memory 212140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272257147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.4272257147
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/29.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_error_random.947445834
Short name T546
Test name
Test status
Simulation time 69843230 ps
CPU time 9.13 seconds
Started Sep 11 02:48:20 AM UTC 24
Finished Sep 11 02:48:30 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947445834 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.947445834
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/29.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random.922813485
Short name T523
Test name
Test status
Simulation time 161545493 ps
CPU time 4.24 seconds
Started Sep 11 02:48:17 AM UTC 24
Finished Sep 11 02:48:22 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922813485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.922813485
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/29.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_large_delays.1723424126
Short name T566
Test name
Test status
Simulation time 6021566850 ps
CPU time 31.54 seconds
Started Sep 11 02:48:17 AM UTC 24
Finished Sep 11 02:48:50 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723424126 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.1723424126
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/29.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_slow_rsp.107366349
Short name T720
Test name
Test status
Simulation time 39878715966 ps
CPU time 154.39 seconds
Started Sep 11 02:48:17 AM UTC 24
Finished Sep 11 02:50:54 AM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107366349 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.107366349
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/29.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_zero_delays.1408928458
Short name T541
Test name
Test status
Simulation time 92100395 ps
CPU time 7.4 seconds
Started Sep 11 02:48:17 AM UTC 24
Finished Sep 11 02:48:26 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408928458 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.1408928458
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/29.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_same_source.1632410050
Short name T543
Test name
Test status
Simulation time 594454254 ps
CPU time 7.6 seconds
Started Sep 11 02:48:20 AM UTC 24
Finished Sep 11 02:48:29 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632410050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1632410050
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/29.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke.2236360002
Short name T530
Test name
Test status
Simulation time 15994480 ps
CPU time 1.47 seconds
Started Sep 11 02:48:13 AM UTC 24
Finished Sep 11 02:48:16 AM UTC 24
Peak memory 211128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236360002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2236360002
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/29.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_large_delays.2153045115
Short name T550
Test name
Test status
Simulation time 3786715916 ps
CPU time 16.64 seconds
Started Sep 11 02:48:16 AM UTC 24
Finished Sep 11 02:48:33 AM UTC 24
Peak memory 212248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153045115 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.2153045115
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/29.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.3408864980
Short name T35
Test name
Test status
Simulation time 1337608313 ps
CPU time 11.99 seconds
Started Sep 11 02:48:17 AM UTC 24
Finished Sep 11 02:48:30 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408864980 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.3408864980
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/29.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.2563811785
Short name T531
Test name
Test status
Simulation time 8899873 ps
CPU time 1.59 seconds
Started Sep 11 02:48:14 AM UTC 24
Finished Sep 11 02:48:16 AM UTC 24
Peak memory 211124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563811785 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.2563811785
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/29.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all.732255672
Short name T535
Test name
Test status
Simulation time 35432839 ps
CPU time 4.89 seconds
Started Sep 11 02:48:23 AM UTC 24
Finished Sep 11 02:48:29 AM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732255672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.732255672
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/29.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_error.1924433614
Short name T579
Test name
Test status
Simulation time 344316482 ps
CPU time 28.54 seconds
Started Sep 11 02:48:28 AM UTC 24
Finished Sep 11 02:48:57 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924433614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1924433614
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/29.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.10959291
Short name T627
Test name
Test status
Simulation time 411230535 ps
CPU time 67.71 seconds
Started Sep 11 02:48:23 AM UTC 24
Finished Sep 11 02:49:33 AM UTC 24
Peak memory 214172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10959291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.10959291
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/29.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.1071925564
Short name T6
Test name
Test status
Simulation time 7524955078 ps
CPU time 159.35 seconds
Started Sep 11 02:48:28 AM UTC 24
Finished Sep 11 02:51:10 AM UTC 24
Peak memory 216292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071925564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.1071925564
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/29.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_unmapped_addr.3064473305
Short name T219
Test name
Test status
Simulation time 2320598911 ps
CPU time 12.31 seconds
Started Sep 11 02:48:20 AM UTC 24
Finished Sep 11 02:48:33 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064473305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.3064473305
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/29.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device.1378335766
Short name T53
Test name
Test status
Simulation time 1025343020 ps
CPU time 17.45 seconds
Started Sep 11 02:41:59 AM UTC 24
Finished Sep 11 02:42:18 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378335766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.1378335766
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/3.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.465574268
Short name T286
Test name
Test status
Simulation time 121074115 ps
CPU time 5.61 seconds
Started Sep 11 02:42:03 AM UTC 24
Finished Sep 11 02:42:09 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465574268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.465574268
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/3.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_error_random.2483302630
Short name T287
Test name
Test status
Simulation time 101713140 ps
CPU time 7.48 seconds
Started Sep 11 02:42:01 AM UTC 24
Finished Sep 11 02:42:10 AM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483302630 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2483302630
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/3.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random.685825028
Short name T48
Test name
Test status
Simulation time 87939743 ps
CPU time 5.79 seconds
Started Sep 11 02:41:52 AM UTC 24
Finished Sep 11 02:41:59 AM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685825028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.685825028
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/3.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_large_delays.1517394905
Short name T305
Test name
Test status
Simulation time 20263474760 ps
CPU time 89.26 seconds
Started Sep 11 02:41:57 AM UTC 24
Finished Sep 11 02:43:28 AM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517394905 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1517394905
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/3.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_slow_rsp.3615466900
Short name T235
Test name
Test status
Simulation time 13528841166 ps
CPU time 75.21 seconds
Started Sep 11 02:41:58 AM UTC 24
Finished Sep 11 02:43:15 AM UTC 24
Peak memory 212380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615466900 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3615466900
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/3.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_zero_delays.1348715548
Short name T50
Test name
Test status
Simulation time 307945984 ps
CPU time 8.41 seconds
Started Sep 11 02:41:53 AM UTC 24
Finished Sep 11 02:42:02 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348715548 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.1348715548
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/3.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_same_source.1168551010
Short name T285
Test name
Test status
Simulation time 38008691 ps
CPU time 6.03 seconds
Started Sep 11 02:42:00 AM UTC 24
Finished Sep 11 02:42:07 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168551010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1168551010
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/3.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke.3825625064
Short name T59
Test name
Test status
Simulation time 76320977 ps
CPU time 1.98 seconds
Started Sep 11 02:41:47 AM UTC 24
Finished Sep 11 02:41:50 AM UTC 24
Peak memory 211132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825625064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3825625064
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/3.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_large_delays.3110114705
Short name T239
Test name
Test status
Simulation time 2503221677 ps
CPU time 14.38 seconds
Started Sep 11 02:41:48 AM UTC 24
Finished Sep 11 02:42:03 AM UTC 24
Peak memory 212104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110114705 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3110114705
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/3.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1689123423
Short name T43
Test name
Test status
Simulation time 781210233 ps
CPU time 9.73 seconds
Started Sep 11 02:41:51 AM UTC 24
Finished Sep 11 02:42:02 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689123423 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1689123423
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/3.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.612725879
Short name T179
Test name
Test status
Simulation time 14487690 ps
CPU time 1.73 seconds
Started Sep 11 02:41:48 AM UTC 24
Finished Sep 11 02:41:51 AM UTC 24
Peak memory 211072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612725879 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.612725879
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/3.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all.2314589447
Short name T114
Test name
Test status
Simulation time 261181601 ps
CPU time 42.12 seconds
Started Sep 11 02:42:03 AM UTC 24
Finished Sep 11 02:42:47 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314589447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2314589447
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/3.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_error.4056796109
Short name T257
Test name
Test status
Simulation time 13415645299 ps
CPU time 100.57 seconds
Started Sep 11 02:42:04 AM UTC 24
Finished Sep 11 02:43:47 AM UTC 24
Peak memory 216140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056796109 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.4056796109
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/3.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.1903447316
Short name T82
Test name
Test status
Simulation time 515227486 ps
CPU time 74.44 seconds
Started Sep 11 02:42:03 AM UTC 24
Finished Sep 11 02:43:19 AM UTC 24
Peak memory 214176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903447316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.1903447316
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/3.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.3445893676
Short name T274
Test name
Test status
Simulation time 786682953 ps
CPU time 71.24 seconds
Started Sep 11 02:42:04 AM UTC 24
Finished Sep 11 02:43:17 AM UTC 24
Peak memory 214372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445893676 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.3445893676
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/3.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_unmapped_addr.2397631110
Short name T51
Test name
Test status
Simulation time 28733648 ps
CPU time 2.59 seconds
Started Sep 11 02:42:03 AM UTC 24
Finished Sep 11 02:42:06 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397631110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.2397631110
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/3.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device.3110011340
Short name T559
Test name
Test status
Simulation time 55170672 ps
CPU time 9 seconds
Started Sep 11 02:48:31 AM UTC 24
Finished Sep 11 02:48:42 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110011340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.3110011340
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/30.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.3129880440
Short name T267
Test name
Test status
Simulation time 83306288479 ps
CPU time 277.45 seconds
Started Sep 11 02:48:32 AM UTC 24
Finished Sep 11 02:53:13 AM UTC 24
Peak memory 214428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129880440 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.3129880440
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/30.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3039198315
Short name T556
Test name
Test status
Simulation time 73374453 ps
CPU time 7 seconds
Started Sep 11 02:48:33 AM UTC 24
Finished Sep 11 02:48:41 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039198315 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3039198315
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/30.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_error_random.755849095
Short name T552
Test name
Test status
Simulation time 61971874 ps
CPU time 2.25 seconds
Started Sep 11 02:48:32 AM UTC 24
Finished Sep 11 02:48:35 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755849095 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.755849095
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/30.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random.789993300
Short name T555
Test name
Test status
Simulation time 255141628 ps
CPU time 7.35 seconds
Started Sep 11 02:48:31 AM UTC 24
Finished Sep 11 02:48:40 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789993300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.789993300
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/30.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.4027152632
Short name T737
Test name
Test status
Simulation time 214260730322 ps
CPU time 155.02 seconds
Started Sep 11 02:48:31 AM UTC 24
Finished Sep 11 02:51:09 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027152632 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.4027152632
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/30.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1870663257
Short name T38
Test name
Test status
Simulation time 8897725864 ps
CPU time 80.59 seconds
Started Sep 11 02:48:31 AM UTC 24
Finished Sep 11 02:49:54 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870663257 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1870663257
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/30.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_zero_delays.1626249409
Short name T551
Test name
Test status
Simulation time 26166741 ps
CPU time 2.3 seconds
Started Sep 11 02:48:31 AM UTC 24
Finished Sep 11 02:48:35 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626249409 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.1626249409
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/30.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_same_source.1066745184
Short name T561
Test name
Test status
Simulation time 1488578609 ps
CPU time 10.58 seconds
Started Sep 11 02:48:32 AM UTC 24
Finished Sep 11 02:48:44 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066745184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.1066745184
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/30.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke.1642854932
Short name T547
Test name
Test status
Simulation time 59324671 ps
CPU time 2.15 seconds
Started Sep 11 02:48:28 AM UTC 24
Finished Sep 11 02:48:31 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642854932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1642854932
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/30.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_large_delays.4165451740
Short name T560
Test name
Test status
Simulation time 3321019716 ps
CPU time 12.7 seconds
Started Sep 11 02:48:29 AM UTC 24
Finished Sep 11 02:48:43 AM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165451740 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.4165451740
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/30.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.1498129770
Short name T37
Test name
Test status
Simulation time 7335073899 ps
CPU time 8 seconds
Started Sep 11 02:48:31 AM UTC 24
Finished Sep 11 02:48:40 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498129770 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.1498129770
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/30.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.2895964387
Short name T545
Test name
Test status
Simulation time 8855332 ps
CPU time 1.34 seconds
Started Sep 11 02:48:28 AM UTC 24
Finished Sep 11 02:48:30 AM UTC 24
Peak memory 211228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895964387 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2895964387
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/30.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all.1111690017
Short name T587
Test name
Test status
Simulation time 1355605357 ps
CPU time 28.91 seconds
Started Sep 11 02:48:33 AM UTC 24
Finished Sep 11 02:49:03 AM UTC 24
Peak memory 214368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111690017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1111690017
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/30.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_error.2558345001
Short name T605
Test name
Test status
Simulation time 2204453147 ps
CPU time 39.71 seconds
Started Sep 11 02:48:34 AM UTC 24
Finished Sep 11 02:49:15 AM UTC 24
Peak memory 212444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558345001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2558345001
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/30.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.665527179
Short name T629
Test name
Test status
Simulation time 812384301 ps
CPU time 58.1 seconds
Started Sep 11 02:48:34 AM UTC 24
Finished Sep 11 02:49:34 AM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665527179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.665527179
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/30.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.2343892261
Short name T642
Test name
Test status
Simulation time 987844247 ps
CPU time 68.83 seconds
Started Sep 11 02:48:34 AM UTC 24
Finished Sep 11 02:49:45 AM UTC 24
Peak memory 214372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343892261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.2343892261
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/30.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_unmapped_addr.943922152
Short name T553
Test name
Test status
Simulation time 83991760 ps
CPU time 4.8 seconds
Started Sep 11 02:48:32 AM UTC 24
Finished Sep 11 02:48:38 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943922152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.943922152
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/30.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device.3239985870
Short name T568
Test name
Test status
Simulation time 57200751 ps
CPU time 9.07 seconds
Started Sep 11 02:48:41 AM UTC 24
Finished Sep 11 02:48:51 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239985870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.3239985870
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/31.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.3655435112
Short name T881
Test name
Test status
Simulation time 101944127756 ps
CPU time 272.82 seconds
Started Sep 11 02:48:42 AM UTC 24
Finished Sep 11 02:53:18 AM UTC 24
Peak memory 214428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655435112 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.3655435112
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/31.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.1767504366
Short name T564
Test name
Test status
Simulation time 576102426 ps
CPU time 3.86 seconds
Started Sep 11 02:48:43 AM UTC 24
Finished Sep 11 02:48:49 AM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767504366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.1767504366
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/31.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_error_random.3477280803
Short name T567
Test name
Test status
Simulation time 337381073 ps
CPU time 7.95 seconds
Started Sep 11 02:48:42 AM UTC 24
Finished Sep 11 02:48:51 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477280803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3477280803
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/31.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random.4178639505
Short name T563
Test name
Test status
Simulation time 41775377 ps
CPU time 7.58 seconds
Started Sep 11 02:48:39 AM UTC 24
Finished Sep 11 02:48:48 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178639505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.4178639505
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/31.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_large_delays.3723385740
Short name T707
Test name
Test status
Simulation time 42334795714 ps
CPU time 113.71 seconds
Started Sep 11 02:48:39 AM UTC 24
Finished Sep 11 02:50:35 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723385740 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3723385740
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/31.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_slow_rsp.3367439826
Short name T576
Test name
Test status
Simulation time 1960552505 ps
CPU time 13.65 seconds
Started Sep 11 02:48:41 AM UTC 24
Finished Sep 11 02:48:56 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367439826 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.3367439826
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/31.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_zero_delays.1301009739
Short name T558
Test name
Test status
Simulation time 10880885 ps
CPU time 1.48 seconds
Started Sep 11 02:48:39 AM UTC 24
Finished Sep 11 02:48:42 AM UTC 24
Peak memory 211132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301009739 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.1301009739
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/31.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_same_source.2581643987
Short name T562
Test name
Test status
Simulation time 51885657 ps
CPU time 4.81 seconds
Started Sep 11 02:48:42 AM UTC 24
Finished Sep 11 02:48:48 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581643987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.2581643987
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/31.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke.866364578
Short name T554
Test name
Test status
Simulation time 51530198 ps
CPU time 2.22 seconds
Started Sep 11 02:48:35 AM UTC 24
Finished Sep 11 02:48:39 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866364578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.866364578
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/31.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_large_delays.3402100165
Short name T574
Test name
Test status
Simulation time 9161652093 ps
CPU time 18.65 seconds
Started Sep 11 02:48:36 AM UTC 24
Finished Sep 11 02:48:55 AM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402100165 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.3402100165
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/31.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.1964476581
Short name T572
Test name
Test status
Simulation time 2806809940 ps
CPU time 14.56 seconds
Started Sep 11 02:48:38 AM UTC 24
Finished Sep 11 02:48:54 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964476581 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.1964476581
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/31.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.3498625382
Short name T36
Test name
Test status
Simulation time 10422691 ps
CPU time 1.83 seconds
Started Sep 11 02:48:36 AM UTC 24
Finished Sep 11 02:48:38 AM UTC 24
Peak memory 211124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498625382 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.3498625382
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/31.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all.345003086
Short name T615
Test name
Test status
Simulation time 472272339 ps
CPU time 38.18 seconds
Started Sep 11 02:48:45 AM UTC 24
Finished Sep 11 02:49:25 AM UTC 24
Peak memory 214380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345003086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.345003086
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/31.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_error.169378058
Short name T628
Test name
Test status
Simulation time 430886640 ps
CPU time 45.27 seconds
Started Sep 11 02:48:46 AM UTC 24
Finished Sep 11 02:49:33 AM UTC 24
Peak memory 214176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169378058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.169378058
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/31.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.3347446691
Short name T705
Test name
Test status
Simulation time 1058925990 ps
CPU time 107.11 seconds
Started Sep 11 02:48:45 AM UTC 24
Finished Sep 11 02:50:35 AM UTC 24
Peak memory 216332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347446691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.3347446691
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/31.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.2356390240
Short name T678
Test name
Test status
Simulation time 759436684 ps
CPU time 77.77 seconds
Started Sep 11 02:48:49 AM UTC 24
Finished Sep 11 02:50:09 AM UTC 24
Peak memory 214180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356390240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.2356390240
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/31.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_unmapped_addr.1059291870
Short name T565
Test name
Test status
Simulation time 175370363 ps
CPU time 5 seconds
Started Sep 11 02:48:43 AM UTC 24
Finished Sep 11 02:48:50 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059291870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1059291870
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/31.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device.1746232442
Short name T577
Test name
Test status
Simulation time 12075012 ps
CPU time 2.04 seconds
Started Sep 11 02:48:53 AM UTC 24
Finished Sep 11 02:48:56 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746232442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.1746232442
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/32.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.3638258174
Short name T182
Test name
Test status
Simulation time 165386748971 ps
CPU time 394.31 seconds
Started Sep 11 02:48:54 AM UTC 24
Finished Sep 11 02:55:33 AM UTC 24
Peak memory 217944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638258174 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.3638258174
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/32.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3293837075
Short name T589
Test name
Test status
Simulation time 1941763415 ps
CPU time 5.83 seconds
Started Sep 11 02:48:58 AM UTC 24
Finished Sep 11 02:49:05 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293837075 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.3293837075
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/32.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_error_random.1825148313
Short name T591
Test name
Test status
Simulation time 84993780 ps
CPU time 6.34 seconds
Started Sep 11 02:48:58 AM UTC 24
Finished Sep 11 02:49:05 AM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825148313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1825148313
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/32.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random.843108557
Short name T594
Test name
Test status
Simulation time 867439868 ps
CPU time 15.98 seconds
Started Sep 11 02:48:52 AM UTC 24
Finished Sep 11 02:49:09 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843108557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.843108557
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/32.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.2126603790
Short name T225
Test name
Test status
Simulation time 300867521339 ps
CPU time 160.74 seconds
Started Sep 11 02:48:53 AM UTC 24
Finished Sep 11 02:51:36 AM UTC 24
Peak memory 212056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126603790 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.2126603790
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/32.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.3250051190
Short name T39
Test name
Test status
Simulation time 56735333219 ps
CPU time 92.39 seconds
Started Sep 11 02:48:53 AM UTC 24
Finished Sep 11 02:50:27 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250051190 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3250051190
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/32.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_zero_delays.3772569701
Short name T581
Test name
Test status
Simulation time 184935767 ps
CPU time 7.5 seconds
Started Sep 11 02:48:52 AM UTC 24
Finished Sep 11 02:49:00 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772569701 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.3772569701
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/32.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_same_source.2444427456
Short name T588
Test name
Test status
Simulation time 877570195 ps
CPU time 6.88 seconds
Started Sep 11 02:48:55 AM UTC 24
Finished Sep 11 02:49:03 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444427456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.2444427456
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/32.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke.1448177217
Short name T571
Test name
Test status
Simulation time 54043965 ps
CPU time 1.99 seconds
Started Sep 11 02:48:49 AM UTC 24
Finished Sep 11 02:48:52 AM UTC 24
Peak memory 211236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448177217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.1448177217
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/32.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_large_delays.1625460789
Short name T586
Test name
Test status
Simulation time 5346743566 ps
CPU time 11.67 seconds
Started Sep 11 02:48:50 AM UTC 24
Finished Sep 11 02:49:03 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625460789 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.1625460789
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/32.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.3517107567
Short name T583
Test name
Test status
Simulation time 4225645967 ps
CPU time 9.01 seconds
Started Sep 11 02:48:52 AM UTC 24
Finished Sep 11 02:49:02 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517107567 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3517107567
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/32.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.743417169
Short name T569
Test name
Test status
Simulation time 11507626 ps
CPU time 1.68 seconds
Started Sep 11 02:48:49 AM UTC 24
Finished Sep 11 02:48:52 AM UTC 24
Peak memory 211228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743417169 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.743417169
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/32.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all.232834968
Short name T620
Test name
Test status
Simulation time 5897626761 ps
CPU time 28.84 seconds
Started Sep 11 02:48:58 AM UTC 24
Finished Sep 11 02:49:28 AM UTC 24
Peak memory 214236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232834968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.232834968
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/32.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_error.2760012995
Short name T598
Test name
Test status
Simulation time 2764992310 ps
CPU time 11.7 seconds
Started Sep 11 02:48:58 AM UTC 24
Finished Sep 11 02:49:11 AM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760012995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.2760012995
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/32.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2483507093
Short name T234
Test name
Test status
Simulation time 12219494501 ps
CPU time 85.81 seconds
Started Sep 11 02:48:58 AM UTC 24
Finished Sep 11 02:50:26 AM UTC 24
Peak memory 216288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483507093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.2483507093
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/32.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.597079361
Short name T723
Test name
Test status
Simulation time 14726358634 ps
CPU time 116.15 seconds
Started Sep 11 02:48:59 AM UTC 24
Finished Sep 11 02:50:58 AM UTC 24
Peak memory 218336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597079361 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.597079361
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/32.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_unmapped_addr.4100385730
Short name T590
Test name
Test status
Simulation time 74395459 ps
CPU time 6.19 seconds
Started Sep 11 02:48:58 AM UTC 24
Finished Sep 11 02:49:05 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100385730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.4100385730
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/32.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device.3478334475
Short name T617
Test name
Test status
Simulation time 2485421974 ps
CPU time 21.06 seconds
Started Sep 11 02:49:04 AM UTC 24
Finished Sep 11 02:49:26 AM UTC 24
Peak memory 212420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478334475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.3478334475
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/33.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.4283231385
Short name T215
Test name
Test status
Simulation time 19611326753 ps
CPU time 120.72 seconds
Started Sep 11 02:49:04 AM UTC 24
Finished Sep 11 02:51:07 AM UTC 24
Peak memory 214204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283231385 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.4283231385
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/33.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.2373932599
Short name T607
Test name
Test status
Simulation time 737854144 ps
CPU time 9.09 seconds
Started Sep 11 02:49:08 AM UTC 24
Finished Sep 11 02:49:18 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373932599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.2373932599
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/33.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_error_random.752878069
Short name T606
Test name
Test status
Simulation time 468609902 ps
CPU time 10.1 seconds
Started Sep 11 02:49:06 AM UTC 24
Finished Sep 11 02:49:18 AM UTC 24
Peak memory 211852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752878069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.752878069
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/33.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random.431827905
Short name T597
Test name
Test status
Simulation time 243436661 ps
CPU time 6.71 seconds
Started Sep 11 02:49:03 AM UTC 24
Finished Sep 11 02:49:11 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431827905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.431827905
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/33.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_large_delays.882058420
Short name T624
Test name
Test status
Simulation time 5552200041 ps
CPU time 26.43 seconds
Started Sep 11 02:49:03 AM UTC 24
Finished Sep 11 02:49:31 AM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882058420 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.882058420
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/33.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_slow_rsp.356559587
Short name T644
Test name
Test status
Simulation time 13277796318 ps
CPU time 41.84 seconds
Started Sep 11 02:49:04 AM UTC 24
Finished Sep 11 02:49:47 AM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356559587 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.356559587
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/33.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_zero_delays.67067890
Short name T596
Test name
Test status
Simulation time 390559446 ps
CPU time 4.93 seconds
Started Sep 11 02:49:03 AM UTC 24
Finished Sep 11 02:49:09 AM UTC 24
Peak memory 212308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67067890 -assert nopostproc +UVM_TESTNAME=xbar_
base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.67067890
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/33.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_same_source.3933729617
Short name T602
Test name
Test status
Simulation time 1170885397 ps
CPU time 8.11 seconds
Started Sep 11 02:49:05 AM UTC 24
Finished Sep 11 02:49:14 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933729617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3933729617
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/33.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke.3426128982
Short name T584
Test name
Test status
Simulation time 14701744 ps
CPU time 1.64 seconds
Started Sep 11 02:48:59 AM UTC 24
Finished Sep 11 02:49:02 AM UTC 24
Peak memory 211128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426128982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.3426128982
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/33.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_large_delays.836762813
Short name T600
Test name
Test status
Simulation time 1767141585 ps
CPU time 10.16 seconds
Started Sep 11 02:49:01 AM UTC 24
Finished Sep 11 02:49:13 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836762813 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.836762813
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/33.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.2844013789
Short name T593
Test name
Test status
Simulation time 3498557929 ps
CPU time 4.82 seconds
Started Sep 11 02:49:03 AM UTC 24
Finished Sep 11 02:49:09 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844013789 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.2844013789
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/33.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.2057985383
Short name T585
Test name
Test status
Simulation time 8022131 ps
CPU time 1.52 seconds
Started Sep 11 02:48:59 AM UTC 24
Finished Sep 11 02:49:02 AM UTC 24
Peak memory 211224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057985383 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.2057985383
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/33.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all.3332333894
Short name T656
Test name
Test status
Simulation time 511326311 ps
CPU time 42.27 seconds
Started Sep 11 02:49:09 AM UTC 24
Finished Sep 11 02:49:53 AM UTC 24
Peak memory 214368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332333894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3332333894
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/33.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_error.2257560731
Short name T609
Test name
Test status
Simulation time 272282110 ps
CPU time 10.78 seconds
Started Sep 11 02:49:10 AM UTC 24
Finished Sep 11 02:49:22 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257560731 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.2257560731
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/33.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.4081149668
Short name T167
Test name
Test status
Simulation time 885098832 ps
CPU time 113.17 seconds
Started Sep 11 02:49:09 AM UTC 24
Finished Sep 11 02:51:04 AM UTC 24
Peak memory 218268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081149668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.4081149668
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/33.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.680279429
Short name T652
Test name
Test status
Simulation time 185871265 ps
CPU time 40.01 seconds
Started Sep 11 02:49:10 AM UTC 24
Finished Sep 11 02:49:52 AM UTC 24
Peak memory 214176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680279429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.680279429
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/33.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_unmapped_addr.3087592172
Short name T603
Test name
Test status
Simulation time 73795563 ps
CPU time 7.49 seconds
Started Sep 11 02:49:07 AM UTC 24
Finished Sep 11 02:49:15 AM UTC 24
Peak memory 211836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087592172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3087592172
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/33.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device.2623854779
Short name T618
Test name
Test status
Simulation time 3695843981 ps
CPU time 10.6 seconds
Started Sep 11 02:49:16 AM UTC 24
Finished Sep 11 02:49:28 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623854779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.2623854779
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/34.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.3265545786
Short name T896
Test name
Test status
Simulation time 111667085748 ps
CPU time 353.24 seconds
Started Sep 11 02:49:16 AM UTC 24
Finished Sep 11 02:55:14 AM UTC 24
Peak memory 217940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265545786 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.3265545786
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/34.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.4086848962
Short name T626
Test name
Test status
Simulation time 1405577554 ps
CPU time 10.28 seconds
Started Sep 11 02:49:20 AM UTC 24
Finished Sep 11 02:49:31 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086848962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.4086848962
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/34.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_error_random.2707980413
Short name T623
Test name
Test status
Simulation time 1128810642 ps
CPU time 10.2 seconds
Started Sep 11 02:49:18 AM UTC 24
Finished Sep 11 02:49:29 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707980413 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.2707980413
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/34.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random.4225562421
Short name T608
Test name
Test status
Simulation time 26501809 ps
CPU time 2.95 seconds
Started Sep 11 02:49:14 AM UTC 24
Finished Sep 11 02:49:18 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225562421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.4225562421
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/34.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.2645397279
Short name T660
Test name
Test status
Simulation time 14060605290 ps
CPU time 40.13 seconds
Started Sep 11 02:49:15 AM UTC 24
Finished Sep 11 02:49:56 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645397279 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.2645397279
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/34.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_slow_rsp.2929602097
Short name T751
Test name
Test status
Simulation time 15577276060 ps
CPU time 122.45 seconds
Started Sep 11 02:49:15 AM UTC 24
Finished Sep 11 02:51:19 AM UTC 24
Peak memory 212380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929602097 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2929602097
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/34.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_zero_delays.596041524
Short name T610
Test name
Test status
Simulation time 145779084 ps
CPU time 6.87 seconds
Started Sep 11 02:49:14 AM UTC 24
Finished Sep 11 02:49:22 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596041524 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.596041524
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/34.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_same_source.710676758
Short name T614
Test name
Test status
Simulation time 39361637 ps
CPU time 5.48 seconds
Started Sep 11 02:49:18 AM UTC 24
Finished Sep 11 02:49:24 AM UTC 24
Peak memory 212112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710676758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.710676758
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/34.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke.3303126848
Short name T599
Test name
Test status
Simulation time 13962106 ps
CPU time 1.39 seconds
Started Sep 11 02:49:10 AM UTC 24
Finished Sep 11 02:49:13 AM UTC 24
Peak memory 211132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303126848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.3303126848
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/34.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_large_delays.3934038430
Short name T613
Test name
Test status
Simulation time 2711959519 ps
CPU time 11.59 seconds
Started Sep 11 02:49:12 AM UTC 24
Finished Sep 11 02:49:24 AM UTC 24
Peak memory 212248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934038430 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.3934038430
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/34.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.2147875986
Short name T619
Test name
Test status
Simulation time 6484508807 ps
CPU time 14.94 seconds
Started Sep 11 02:49:12 AM UTC 24
Finished Sep 11 02:49:28 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147875986 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.2147875986
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/34.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.3879841040
Short name T601
Test name
Test status
Simulation time 8599718 ps
CPU time 1.58 seconds
Started Sep 11 02:49:10 AM UTC 24
Finished Sep 11 02:49:13 AM UTC 24
Peak memory 211124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879841040 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.3879841040
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/34.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all.1365765863
Short name T718
Test name
Test status
Simulation time 6308029137 ps
CPU time 87.62 seconds
Started Sep 11 02:49:20 AM UTC 24
Finished Sep 11 02:50:49 AM UTC 24
Peak memory 214240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365765863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1365765863
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/34.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_error.1858761899
Short name T690
Test name
Test status
Simulation time 10193451739 ps
CPU time 56.51 seconds
Started Sep 11 02:49:23 AM UTC 24
Finished Sep 11 02:50:21 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858761899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1858761899
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/34.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.2980297361
Short name T702
Test name
Test status
Simulation time 3489072572 ps
CPU time 69.47 seconds
Started Sep 11 02:49:20 AM UTC 24
Finished Sep 11 02:50:31 AM UTC 24
Peak memory 214496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980297361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.2980297361
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/34.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_unmapped_addr.2330086492
Short name T183
Test name
Test status
Simulation time 490318640 ps
CPU time 10.25 seconds
Started Sep 11 02:49:18 AM UTC 24
Finished Sep 11 02:49:29 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330086492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.2330086492
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/34.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device.1116702735
Short name T135
Test name
Test status
Simulation time 1277413586 ps
CPU time 20.05 seconds
Started Sep 11 02:49:31 AM UTC 24
Finished Sep 11 02:49:52 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116702735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.1116702735
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/35.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2403135747
Short name T236
Test name
Test status
Simulation time 149497893511 ps
CPU time 126.22 seconds
Started Sep 11 02:49:31 AM UTC 24
Finished Sep 11 02:51:40 AM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403135747 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.2403135747
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/35.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.4259166508
Short name T634
Test name
Test status
Simulation time 215207472 ps
CPU time 3.85 seconds
Started Sep 11 02:49:31 AM UTC 24
Finished Sep 11 02:49:36 AM UTC 24
Peak memory 212096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259166508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.4259166508
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/35.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_error_random.1014160500
Short name T640
Test name
Test status
Simulation time 86001088 ps
CPU time 6.64 seconds
Started Sep 11 02:49:31 AM UTC 24
Finished Sep 11 02:49:39 AM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014160500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.1014160500
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/35.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random.957171977
Short name T639
Test name
Test status
Simulation time 886746764 ps
CPU time 10.54 seconds
Started Sep 11 02:49:27 AM UTC 24
Finished Sep 11 02:49:39 AM UTC 24
Peak memory 212372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957171977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.957171977
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/35.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.3754948240
Short name T649
Test name
Test status
Simulation time 14541462589 ps
CPU time 21.09 seconds
Started Sep 11 02:49:28 AM UTC 24
Finished Sep 11 02:49:50 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754948240 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3754948240
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/35.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.1546742294
Short name T748
Test name
Test status
Simulation time 17879402884 ps
CPU time 103.15 seconds
Started Sep 11 02:49:31 AM UTC 24
Finished Sep 11 02:51:16 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546742294 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.1546742294
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/35.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_zero_delays.155682425
Short name T633
Test name
Test status
Simulation time 58414148 ps
CPU time 7.31 seconds
Started Sep 11 02:49:27 AM UTC 24
Finished Sep 11 02:49:36 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155682425 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.155682425
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/35.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_same_source.2593896021
Short name T630
Test name
Test status
Simulation time 11686343 ps
CPU time 1.78 seconds
Started Sep 11 02:49:31 AM UTC 24
Finished Sep 11 02:49:34 AM UTC 24
Peak memory 211224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593896021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.2593896021
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/35.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke.1249389553
Short name T622
Test name
Test status
Simulation time 47285358 ps
CPU time 2.22 seconds
Started Sep 11 02:49:26 AM UTC 24
Finished Sep 11 02:49:29 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249389553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1249389553
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/35.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1309839406
Short name T635
Test name
Test status
Simulation time 2133862080 ps
CPU time 10.75 seconds
Started Sep 11 02:49:26 AM UTC 24
Finished Sep 11 02:49:38 AM UTC 24
Peak memory 212440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309839406 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1309839406
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/35.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.2082600571
Short name T631
Test name
Test status
Simulation time 2928439754 ps
CPU time 8.51 seconds
Started Sep 11 02:49:26 AM UTC 24
Finished Sep 11 02:49:35 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082600571 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.2082600571
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/35.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.1515049364
Short name T621
Test name
Test status
Simulation time 11928765 ps
CPU time 1.81 seconds
Started Sep 11 02:49:26 AM UTC 24
Finished Sep 11 02:49:29 AM UTC 24
Peak memory 211224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515049364 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.1515049364
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/35.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all.413277687
Short name T688
Test name
Test status
Simulation time 2743172932 ps
CPU time 45.06 seconds
Started Sep 11 02:49:31 AM UTC 24
Finished Sep 11 02:50:18 AM UTC 24
Peak memory 214232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413277687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.413277687
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/35.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_error.32396264
Short name T664
Test name
Test status
Simulation time 388805045 ps
CPU time 21.9 seconds
Started Sep 11 02:49:33 AM UTC 24
Finished Sep 11 02:49:57 AM UTC 24
Peak memory 212136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32396264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.32396264
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/35.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.4092721398
Short name T651
Test name
Test status
Simulation time 150729546 ps
CPU time 16.32 seconds
Started Sep 11 02:49:33 AM UTC 24
Finished Sep 11 02:49:51 AM UTC 24
Peak memory 214172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092721398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.4092721398
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/35.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.369337535
Short name T661
Test name
Test status
Simulation time 2691083365 ps
CPU time 21.69 seconds
Started Sep 11 02:49:33 AM UTC 24
Finished Sep 11 02:49:56 AM UTC 24
Peak memory 214244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369337535 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.369337535
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/35.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_unmapped_addr.4058170290
Short name T636
Test name
Test status
Simulation time 62538271 ps
CPU time 6.14 seconds
Started Sep 11 02:49:31 AM UTC 24
Finished Sep 11 02:49:39 AM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058170290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.4058170290
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/35.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device.1818659109
Short name T650
Test name
Test status
Simulation time 87205404 ps
CPU time 8.52 seconds
Started Sep 11 02:49:41 AM UTC 24
Finished Sep 11 02:49:51 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818659109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.1818659109
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/36.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.469576244
Short name T255
Test name
Test status
Simulation time 30443307344 ps
CPU time 126.37 seconds
Started Sep 11 02:49:41 AM UTC 24
Finished Sep 11 02:51:50 AM UTC 24
Peak memory 214432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469576244 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.469576244
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/36.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.3499125992
Short name T646
Test name
Test status
Simulation time 105199027 ps
CPU time 5.09 seconds
Started Sep 11 02:49:42 AM UTC 24
Finished Sep 11 02:49:48 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499125992 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.3499125992
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/36.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_error_random.1979094054
Short name T665
Test name
Test status
Simulation time 747786369 ps
CPU time 14.15 seconds
Started Sep 11 02:49:42 AM UTC 24
Finished Sep 11 02:49:57 AM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979094054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1979094054
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/36.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random.343420506
Short name T645
Test name
Test status
Simulation time 63691067 ps
CPU time 7.85 seconds
Started Sep 11 02:49:39 AM UTC 24
Finished Sep 11 02:49:47 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343420506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.343420506
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/36.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.2872264943
Short name T820
Test name
Test status
Simulation time 102835583653 ps
CPU time 150.71 seconds
Started Sep 11 02:49:39 AM UTC 24
Finished Sep 11 02:52:12 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872264943 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2872264943
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/36.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.4105414918
Short name T727
Test name
Test status
Simulation time 8557849509 ps
CPU time 80.22 seconds
Started Sep 11 02:49:39 AM UTC 24
Finished Sep 11 02:51:01 AM UTC 24
Peak memory 211980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105414918 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.4105414918
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/36.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_zero_delays.1563748055
Short name T641
Test name
Test status
Simulation time 45411791 ps
CPU time 2.37 seconds
Started Sep 11 02:49:39 AM UTC 24
Finished Sep 11 02:49:42 AM UTC 24
Peak memory 211880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563748055 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.1563748055
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/36.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_same_source.2642569482
Short name T643
Test name
Test status
Simulation time 44078567 ps
CPU time 4.04 seconds
Started Sep 11 02:49:41 AM UTC 24
Finished Sep 11 02:49:46 AM UTC 24
Peak memory 212112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642569482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2642569482
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/36.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke.3643034103
Short name T638
Test name
Test status
Simulation time 286046831 ps
CPU time 1.97 seconds
Started Sep 11 02:49:36 AM UTC 24
Finished Sep 11 02:49:39 AM UTC 24
Peak memory 211236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643034103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.3643034103
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/36.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_large_delays.1300207914
Short name T657
Test name
Test status
Simulation time 11429027942 ps
CPU time 15.83 seconds
Started Sep 11 02:49:36 AM UTC 24
Finished Sep 11 02:49:53 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300207914 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.1300207914
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/36.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.2240907916
Short name T648
Test name
Test status
Simulation time 801030372 ps
CPU time 11.1 seconds
Started Sep 11 02:49:36 AM UTC 24
Finished Sep 11 02:49:49 AM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240907916 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.2240907916
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/36.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.669733478
Short name T637
Test name
Test status
Simulation time 13864781 ps
CPU time 1.76 seconds
Started Sep 11 02:49:36 AM UTC 24
Finished Sep 11 02:49:39 AM UTC 24
Peak memory 211124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669733478 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.669733478
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/36.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all.392938712
Short name T654
Test name
Test status
Simulation time 89866853 ps
CPU time 8.24 seconds
Started Sep 11 02:49:43 AM UTC 24
Finished Sep 11 02:49:53 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392938712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.392938712
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/36.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_error.1604830152
Short name T677
Test name
Test status
Simulation time 356687615 ps
CPU time 20.36 seconds
Started Sep 11 02:49:46 AM UTC 24
Finished Sep 11 02:50:07 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604830152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1604830152
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/36.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1557913391
Short name T10
Test name
Test status
Simulation time 16927560590 ps
CPU time 229.57 seconds
Started Sep 11 02:49:43 AM UTC 24
Finished Sep 11 02:53:36 AM UTC 24
Peak memory 214236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557913391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.1557913391
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/36.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.1517294377
Short name T863
Test name
Test status
Simulation time 1168579582 ps
CPU time 175.1 seconds
Started Sep 11 02:49:47 AM UTC 24
Finished Sep 11 02:52:45 AM UTC 24
Peak memory 218272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517294377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.1517294377
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/36.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_unmapped_addr.4158395321
Short name T647
Test name
Test status
Simulation time 143162378 ps
CPU time 5.45 seconds
Started Sep 11 02:49:42 AM UTC 24
Finished Sep 11 02:49:48 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158395321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.4158395321
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/36.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device.2845720440
Short name T662
Test name
Test status
Simulation time 24506736 ps
CPU time 3.01 seconds
Started Sep 11 02:49:52 AM UTC 24
Finished Sep 11 02:49:57 AM UTC 24
Peak memory 212320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845720440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.2845720440
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/37.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.719210357
Short name T888
Test name
Test status
Simulation time 228245735599 ps
CPU time 234.23 seconds
Started Sep 11 02:49:55 AM UTC 24
Finished Sep 11 02:53:52 AM UTC 24
Peak memory 214236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719210357 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.719210357
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/37.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.3682081141
Short name T676
Test name
Test status
Simulation time 1645711244 ps
CPU time 9.25 seconds
Started Sep 11 02:49:55 AM UTC 24
Finished Sep 11 02:50:05 AM UTC 24
Peak memory 212380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682081141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.3682081141
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/37.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_error_random.2931794131
Short name T666
Test name
Test status
Simulation time 74155510 ps
CPU time 2.98 seconds
Started Sep 11 02:49:55 AM UTC 24
Finished Sep 11 02:49:59 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931794131 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2931794131
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/37.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random.323572545
Short name T663
Test name
Test status
Simulation time 30824612 ps
CPU time 3.54 seconds
Started Sep 11 02:49:52 AM UTC 24
Finished Sep 11 02:49:57 AM UTC 24
Peak memory 212040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323572545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.323572545
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/37.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.2395343777
Short name T749
Test name
Test status
Simulation time 19227947370 ps
CPU time 82.38 seconds
Started Sep 11 02:49:52 AM UTC 24
Finished Sep 11 02:51:17 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395343777 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2395343777
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/37.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.2083473354
Short name T757
Test name
Test status
Simulation time 31503472503 ps
CPU time 88.53 seconds
Started Sep 11 02:49:52 AM UTC 24
Finished Sep 11 02:51:23 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083473354 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2083473354
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/37.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_zero_delays.3413295005
Short name T672
Test name
Test status
Simulation time 94095610 ps
CPU time 9.29 seconds
Started Sep 11 02:49:52 AM UTC 24
Finished Sep 11 02:50:03 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413295005 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.3413295005
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/37.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_same_source.3653212874
Short name T659
Test name
Test status
Simulation time 274334427 ps
CPU time 2.64 seconds
Started Sep 11 02:49:55 AM UTC 24
Finished Sep 11 02:49:59 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653212874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3653212874
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/37.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke.1356559483
Short name T653
Test name
Test status
Simulation time 100110436 ps
CPU time 1.74 seconds
Started Sep 11 02:49:50 AM UTC 24
Finished Sep 11 02:49:52 AM UTC 24
Peak memory 211236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356559483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.1356559483
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/37.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_large_delays.3042246710
Short name T667
Test name
Test status
Simulation time 1752508019 ps
CPU time 8.34 seconds
Started Sep 11 02:49:50 AM UTC 24
Finished Sep 11 02:49:59 AM UTC 24
Peak memory 211884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042246710 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.3042246710
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/37.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.656274862
Short name T675
Test name
Test status
Simulation time 1939432995 ps
CPU time 13.89 seconds
Started Sep 11 02:49:50 AM UTC 24
Finished Sep 11 02:50:05 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656274862 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.656274862
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/37.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.549959206
Short name T655
Test name
Test status
Simulation time 9813015 ps
CPU time 1.76 seconds
Started Sep 11 02:49:50 AM UTC 24
Finished Sep 11 02:49:53 AM UTC 24
Peak memory 211124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549959206 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.549959206
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/37.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.2734711316
Short name T136
Test name
Test status
Simulation time 12978726111 ps
CPU time 25.69 seconds
Started Sep 11 02:49:55 AM UTC 24
Finished Sep 11 02:50:22 AM UTC 24
Peak memory 214236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734711316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.2734711316
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/37.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_error.2337666024
Short name T758
Test name
Test status
Simulation time 31788793329 ps
CPU time 84.17 seconds
Started Sep 11 02:49:58 AM UTC 24
Finished Sep 11 02:51:24 AM UTC 24
Peak memory 214236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337666024 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2337666024
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/37.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.1739367518
Short name T685
Test name
Test status
Simulation time 135967242 ps
CPU time 19.38 seconds
Started Sep 11 02:49:55 AM UTC 24
Finished Sep 11 02:50:16 AM UTC 24
Peak memory 214172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739367518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.1739367518
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/37.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.4133896503
Short name T681
Test name
Test status
Simulation time 65695912 ps
CPU time 13.46 seconds
Started Sep 11 02:49:58 AM UTC 24
Finished Sep 11 02:50:13 AM UTC 24
Peak memory 214372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133896503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.4133896503
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/37.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_unmapped_addr.981386888
Short name T670
Test name
Test status
Simulation time 471852742 ps
CPU time 5.5 seconds
Started Sep 11 02:49:55 AM UTC 24
Finished Sep 11 02:50:02 AM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981386888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.981386888
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/37.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device.3255784114
Short name T694
Test name
Test status
Simulation time 7416393897 ps
CPU time 20.7 seconds
Started Sep 11 02:50:02 AM UTC 24
Finished Sep 11 02:50:24 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255784114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.3255784114
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/38.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.557134127
Short name T831
Test name
Test status
Simulation time 27761039651 ps
CPU time 131.19 seconds
Started Sep 11 02:50:02 AM UTC 24
Finished Sep 11 02:52:15 AM UTC 24
Peak memory 214496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557134127 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.557134127
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/38.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.1297469442
Short name T686
Test name
Test status
Simulation time 1093150443 ps
CPU time 11.1 seconds
Started Sep 11 02:50:04 AM UTC 24
Finished Sep 11 02:50:16 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297469442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.1297469442
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/38.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_error_random.2375052878
Short name T684
Test name
Test status
Simulation time 75217509 ps
CPU time 8.15 seconds
Started Sep 11 02:50:04 AM UTC 24
Finished Sep 11 02:50:13 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375052878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2375052878
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/38.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random.809202961
Short name T683
Test name
Test status
Simulation time 889634436 ps
CPU time 13.89 seconds
Started Sep 11 02:49:58 AM UTC 24
Finished Sep 11 02:50:13 AM UTC 24
Peak memory 212308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809202961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.809202961
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/38.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.4016718238
Short name T689
Test name
Test status
Simulation time 4082267879 ps
CPU time 17.42 seconds
Started Sep 11 02:50:00 AM UTC 24
Finished Sep 11 02:50:19 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016718238 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.4016718238
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/38.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.3597492089
Short name T735
Test name
Test status
Simulation time 24563332641 ps
CPU time 66.36 seconds
Started Sep 11 02:50:00 AM UTC 24
Finished Sep 11 02:51:08 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597492089 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.3597492089
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/38.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_zero_delays.1062750233
Short name T673
Test name
Test status
Simulation time 77747409 ps
CPU time 4.79 seconds
Started Sep 11 02:49:58 AM UTC 24
Finished Sep 11 02:50:04 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062750233 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.1062750233
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/38.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_same_source.3664059168
Short name T674
Test name
Test status
Simulation time 10506872 ps
CPU time 1.57 seconds
Started Sep 11 02:50:02 AM UTC 24
Finished Sep 11 02:50:05 AM UTC 24
Peak memory 211104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664059168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.3664059168
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/38.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke.458234030
Short name T669
Test name
Test status
Simulation time 11150095 ps
CPU time 1.83 seconds
Started Sep 11 02:49:58 AM UTC 24
Finished Sep 11 02:50:01 AM UTC 24
Peak memory 211228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458234030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.458234030
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/38.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_large_delays.2979909244
Short name T687
Test name
Test status
Simulation time 2177329966 ps
CPU time 18.81 seconds
Started Sep 11 02:49:58 AM UTC 24
Finished Sep 11 02:50:18 AM UTC 24
Peak memory 212176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979909244 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2979909244
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/38.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.2547500670
Short name T679
Test name
Test status
Simulation time 8011059956 ps
CPU time 10.25 seconds
Started Sep 11 02:49:58 AM UTC 24
Finished Sep 11 02:50:10 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547500670 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2547500670
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/38.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.3594339273
Short name T668
Test name
Test status
Simulation time 12967192 ps
CPU time 1.75 seconds
Started Sep 11 02:49:58 AM UTC 24
Finished Sep 11 02:50:01 AM UTC 24
Peak memory 211124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594339273 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.3594339273
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/38.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.2563045325
Short name T184
Test name
Test status
Simulation time 4822570600 ps
CPU time 65.75 seconds
Started Sep 11 02:50:06 AM UTC 24
Finished Sep 11 02:51:13 AM UTC 24
Peak memory 214432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563045325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.2563045325
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/38.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.4268690331
Short name T786
Test name
Test status
Simulation time 20245451200 ps
CPU time 93.1 seconds
Started Sep 11 02:50:06 AM UTC 24
Finished Sep 11 02:51:41 AM UTC 24
Peak memory 214300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268690331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.4268690331
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/38.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.3638792313
Short name T164
Test name
Test status
Simulation time 4261852638 ps
CPU time 100.96 seconds
Started Sep 11 02:50:06 AM UTC 24
Finished Sep 11 02:51:49 AM UTC 24
Peak memory 214244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638792313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.3638792313
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/38.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.3333278472
Short name T739
Test name
Test status
Simulation time 637565066 ps
CPU time 60.26 seconds
Started Sep 11 02:50:07 AM UTC 24
Finished Sep 11 02:51:09 AM UTC 24
Peak memory 216420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333278472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.3333278472
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/38.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_unmapped_addr.2505122514
Short name T691
Test name
Test status
Simulation time 1427617036 ps
CPU time 16.17 seconds
Started Sep 11 02:50:04 AM UTC 24
Finished Sep 11 02:50:22 AM UTC 24
Peak memory 212320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505122514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.2505122514
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/38.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device.1380949247
Short name T701
Test name
Test status
Simulation time 3855045139 ps
CPU time 11.51 seconds
Started Sep 11 02:50:17 AM UTC 24
Finished Sep 11 02:50:29 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380949247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.1380949247
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/39.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1228170528
Short name T220
Test name
Test status
Simulation time 16971874426 ps
CPU time 111.55 seconds
Started Sep 11 02:50:18 AM UTC 24
Finished Sep 11 02:52:12 AM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228170528 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.1228170528
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/39.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.892906998
Short name T706
Test name
Test status
Simulation time 831397497 ps
CPU time 11.37 seconds
Started Sep 11 02:50:23 AM UTC 24
Finished Sep 11 02:50:35 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892906998 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.892906998
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/39.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_error_random.1991839017
Short name T709
Test name
Test status
Simulation time 2520363099 ps
CPU time 15.34 seconds
Started Sep 11 02:50:20 AM UTC 24
Finished Sep 11 02:50:36 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991839017 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1991839017
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/39.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random.1446555067
Short name T692
Test name
Test status
Simulation time 319812388 ps
CPU time 7.02 seconds
Started Sep 11 02:50:15 AM UTC 24
Finished Sep 11 02:50:23 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446555067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.1446555067
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/39.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.1535259894
Short name T216
Test name
Test status
Simulation time 30039919287 ps
CPU time 57.23 seconds
Started Sep 11 02:50:15 AM UTC 24
Finished Sep 11 02:51:14 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535259894 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1535259894
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/39.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.3113323824
Short name T784
Test name
Test status
Simulation time 17634790007 ps
CPU time 82.43 seconds
Started Sep 11 02:50:15 AM UTC 24
Finished Sep 11 02:51:39 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113323824 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3113323824
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/39.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_zero_delays.4078501732
Short name T695
Test name
Test status
Simulation time 112530101 ps
CPU time 8.72 seconds
Started Sep 11 02:50:15 AM UTC 24
Finished Sep 11 02:50:25 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078501732 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.4078501732
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/39.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_same_source.3114836859
Short name T698
Test name
Test status
Simulation time 404208700 ps
CPU time 6.62 seconds
Started Sep 11 02:50:20 AM UTC 24
Finished Sep 11 02:50:28 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114836859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3114836859
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/39.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke.135894866
Short name T680
Test name
Test status
Simulation time 11223109 ps
CPU time 1.62 seconds
Started Sep 11 02:50:09 AM UTC 24
Finished Sep 11 02:50:11 AM UTC 24
Peak memory 211124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135894866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.135894866
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/39.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_large_delays.849584116
Short name T693
Test name
Test status
Simulation time 5976736547 ps
CPU time 11.99 seconds
Started Sep 11 02:50:11 AM UTC 24
Finished Sep 11 02:50:24 AM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849584116 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.849584116
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/39.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.3046479340
Short name T696
Test name
Test status
Simulation time 2855682382 ps
CPU time 12.77 seconds
Started Sep 11 02:50:13 AM UTC 24
Finished Sep 11 02:50:27 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046479340 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.3046479340
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/39.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.1812987527
Short name T682
Test name
Test status
Simulation time 8853593 ps
CPU time 1.48 seconds
Started Sep 11 02:50:11 AM UTC 24
Finished Sep 11 02:50:13 AM UTC 24
Peak memory 211124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812987527 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.1812987527
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/39.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.3536969788
Short name T736
Test name
Test status
Simulation time 2785272415 ps
CPU time 44.22 seconds
Started Sep 11 02:50:23 AM UTC 24
Finished Sep 11 02:51:08 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536969788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3536969788
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/39.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.2524032414
Short name T773
Test name
Test status
Simulation time 3651511337 ps
CPU time 66.14 seconds
Started Sep 11 02:50:25 AM UTC 24
Finished Sep 11 02:51:32 AM UTC 24
Peak memory 212252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524032414 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2524032414
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/39.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.1992923345
Short name T785
Test name
Test status
Simulation time 399371321 ps
CPU time 76.32 seconds
Started Sep 11 02:50:23 AM UTC 24
Finished Sep 11 02:51:41 AM UTC 24
Peak memory 214368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992923345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.1992923345
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/39.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.2363221942
Short name T803
Test name
Test status
Simulation time 896294535 ps
CPU time 89.98 seconds
Started Sep 11 02:50:25 AM UTC 24
Finished Sep 11 02:51:57 AM UTC 24
Peak memory 218276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363221942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.2363221942
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/39.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_unmapped_addr.556609441
Short name T699
Test name
Test status
Simulation time 465701426 ps
CPU time 7.88 seconds
Started Sep 11 02:50:20 AM UTC 24
Finished Sep 11 02:50:29 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556609441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.556609441
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/39.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device.1073562728
Short name T81
Test name
Test status
Simulation time 911585371 ps
CPU time 15.73 seconds
Started Sep 11 02:42:13 AM UTC 24
Finished Sep 11 02:42:30 AM UTC 24
Peak memory 212320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073562728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.1073562728
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/4.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.2045791599
Short name T130
Test name
Test status
Simulation time 36474590475 ps
CPU time 313.65 seconds
Started Sep 11 02:42:17 AM UTC 24
Finished Sep 11 02:47:35 AM UTC 24
Peak memory 214240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045791599 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.2045791599
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/4.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.565590386
Short name T288
Test name
Test status
Simulation time 16598587 ps
CPU time 2.3 seconds
Started Sep 11 02:42:20 AM UTC 24
Finished Sep 11 02:42:23 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565590386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.565590386
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/4.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_error_random.2976728208
Short name T187
Test name
Test status
Simulation time 632178383 ps
CPU time 8.74 seconds
Started Sep 11 02:42:19 AM UTC 24
Finished Sep 11 02:42:28 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976728208 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.2976728208
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/4.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random.1638488568
Short name T61
Test name
Test status
Simulation time 494093756 ps
CPU time 8.73 seconds
Started Sep 11 02:42:09 AM UTC 24
Finished Sep 11 02:42:18 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638488568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.1638488568
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/4.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_large_delays.1015280235
Short name T32
Test name
Test status
Simulation time 30585201586 ps
CPU time 138.37 seconds
Started Sep 11 02:42:11 AM UTC 24
Finished Sep 11 02:44:31 AM UTC 24
Peak memory 212176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015280235 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1015280235
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/4.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_slow_rsp.40036555
Short name T292
Test name
Test status
Simulation time 7243685283 ps
CPU time 60.47 seconds
Started Sep 11 02:42:11 AM UTC 24
Finished Sep 11 02:43:13 AM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40036555 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.40036555
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/4.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_zero_delays.1291694622
Short name T54
Test name
Test status
Simulation time 284259960 ps
CPU time 6.21 seconds
Started Sep 11 02:42:11 AM UTC 24
Finished Sep 11 02:42:18 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291694622 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.1291694622
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/4.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_same_source.3139167198
Short name T62
Test name
Test status
Simulation time 155364197 ps
CPU time 3.68 seconds
Started Sep 11 02:42:19 AM UTC 24
Finished Sep 11 02:42:23 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139167198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3139167198
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/4.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke.3556995781
Short name T60
Test name
Test status
Simulation time 49496432 ps
CPU time 2.22 seconds
Started Sep 11 02:42:04 AM UTC 24
Finished Sep 11 02:42:07 AM UTC 24
Peak memory 212108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556995781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.3556995781
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/4.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_large_delays.1698329560
Short name T63
Test name
Test status
Simulation time 8344683612 ps
CPU time 14.74 seconds
Started Sep 11 02:42:07 AM UTC 24
Finished Sep 11 02:42:23 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698329560 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1698329560
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/4.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.1067976652
Short name T65
Test name
Test status
Simulation time 1425032741 ps
CPU time 15.92 seconds
Started Sep 11 02:42:07 AM UTC 24
Finished Sep 11 02:42:25 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067976652 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1067976652
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/4.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.3522668425
Short name T52
Test name
Test status
Simulation time 19620228 ps
CPU time 1.77 seconds
Started Sep 11 02:42:07 AM UTC 24
Finished Sep 11 02:42:10 AM UTC 24
Peak memory 211124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522668425 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.3522668425
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/4.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all.3141363720
Short name T303
Test name
Test status
Simulation time 532148056 ps
CPU time 63.67 seconds
Started Sep 11 02:42:21 AM UTC 24
Finished Sep 11 02:43:26 AM UTC 24
Peak memory 214176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141363720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.3141363720
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/4.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_error.4255875074
Short name T110
Test name
Test status
Simulation time 709789087 ps
CPU time 11.28 seconds
Started Sep 11 02:42:24 AM UTC 24
Finished Sep 11 02:42:36 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255875074 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.4255875074
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/4.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.3474333533
Short name T84
Test name
Test status
Simulation time 624332524 ps
CPU time 67.19 seconds
Started Sep 11 02:42:24 AM UTC 24
Finished Sep 11 02:43:33 AM UTC 24
Peak memory 214432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474333533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.3474333533
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/4.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.1843877142
Short name T242
Test name
Test status
Simulation time 979025976 ps
CPU time 22.77 seconds
Started Sep 11 02:42:24 AM UTC 24
Finished Sep 11 02:42:48 AM UTC 24
Peak memory 214308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843877142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.1843877142
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/4.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_unmapped_addr.140054440
Short name T189
Test name
Test status
Simulation time 287144856 ps
CPU time 8.23 seconds
Started Sep 11 02:42:20 AM UTC 24
Finished Sep 11 02:42:29 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140054440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.140054440
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/4.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device.1909491646
Short name T717
Test name
Test status
Simulation time 2401316488 ps
CPU time 13.18 seconds
Started Sep 11 02:50:31 AM UTC 24
Finished Sep 11 02:50:46 AM UTC 24
Peak memory 212256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909491646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.1909491646
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/40.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.1518148223
Short name T892
Test name
Test status
Simulation time 78917524682 ps
CPU time 251.99 seconds
Started Sep 11 02:50:31 AM UTC 24
Finished Sep 11 02:54:47 AM UTC 24
Peak memory 214236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518148223 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.1518148223
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/40.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.3907796903
Short name T710
Test name
Test status
Simulation time 43142615 ps
CPU time 3.58 seconds
Started Sep 11 02:50:34 AM UTC 24
Finished Sep 11 02:50:39 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907796903 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.3907796903
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/40.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_error_random.3586280419
Short name T708
Test name
Test status
Simulation time 25710307 ps
CPU time 2.1 seconds
Started Sep 11 02:50:33 AM UTC 24
Finished Sep 11 02:50:36 AM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586280419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3586280419
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/40.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random.4223268515
Short name T703
Test name
Test status
Simulation time 14943385 ps
CPU time 1.72 seconds
Started Sep 11 02:50:29 AM UTC 24
Finished Sep 11 02:50:32 AM UTC 24
Peak memory 211192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223268515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.4223268515
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/40.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.4136623385
Short name T859
Test name
Test status
Simulation time 30777770020 ps
CPU time 130.19 seconds
Started Sep 11 02:50:29 AM UTC 24
Finished Sep 11 02:52:42 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136623385 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.4136623385
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/40.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.361427978
Short name T738
Test name
Test status
Simulation time 5921225377 ps
CPU time 38.16 seconds
Started Sep 11 02:50:29 AM UTC 24
Finished Sep 11 02:51:09 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361427978 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.361427978
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/40.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_zero_delays.1286172887
Short name T704
Test name
Test status
Simulation time 20580795 ps
CPU time 2.52 seconds
Started Sep 11 02:50:29 AM UTC 24
Finished Sep 11 02:50:33 AM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286172887 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.1286172887
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/40.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_same_source.941736611
Short name T716
Test name
Test status
Simulation time 1547248257 ps
CPU time 13.13 seconds
Started Sep 11 02:50:31 AM UTC 24
Finished Sep 11 02:50:46 AM UTC 24
Peak memory 212176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941736611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.941736611
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/40.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke.2706085832
Short name T697
Test name
Test status
Simulation time 9193304 ps
CPU time 1.72 seconds
Started Sep 11 02:50:25 AM UTC 24
Finished Sep 11 02:50:27 AM UTC 24
Peak memory 211132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706085832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2706085832
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/40.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_large_delays.2756225439
Short name T711
Test name
Test status
Simulation time 2830098681 ps
CPU time 13.07 seconds
Started Sep 11 02:50:26 AM UTC 24
Finished Sep 11 02:50:41 AM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756225439 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.2756225439
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/40.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.3316683296
Short name T721
Test name
Test status
Simulation time 2132132104 ps
CPU time 24.28 seconds
Started Sep 11 02:50:29 AM UTC 24
Finished Sep 11 02:50:55 AM UTC 24
Peak memory 212096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316683296 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.3316683296
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/40.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.686366449
Short name T700
Test name
Test status
Simulation time 14197635 ps
CPU time 1.75 seconds
Started Sep 11 02:50:26 AM UTC 24
Finished Sep 11 02:50:29 AM UTC 24
Peak memory 211120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686366449 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.686366449
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/40.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.4162171593
Short name T841
Test name
Test status
Simulation time 10552611020 ps
CPU time 106.7 seconds
Started Sep 11 02:50:36 AM UTC 24
Finished Sep 11 02:52:25 AM UTC 24
Peak memory 214240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162171593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.4162171593
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/40.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.2032877187
Short name T825
Test name
Test status
Simulation time 11381918494 ps
CPU time 93.52 seconds
Started Sep 11 02:50:39 AM UTC 24
Finished Sep 11 02:52:14 AM UTC 24
Peak memory 214236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032877187 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.2032877187
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/40.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.2436672125
Short name T224
Test name
Test status
Simulation time 7460261278 ps
CPU time 132.84 seconds
Started Sep 11 02:50:36 AM UTC 24
Finished Sep 11 02:52:52 AM UTC 24
Peak memory 216284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436672125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.2436672125
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/40.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.3533157551
Short name T743
Test name
Test status
Simulation time 609870342 ps
CPU time 34.51 seconds
Started Sep 11 02:50:39 AM UTC 24
Finished Sep 11 02:51:15 AM UTC 24
Peak memory 214180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533157551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.3533157551
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/40.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_unmapped_addr.797564555
Short name T714
Test name
Test status
Simulation time 1038525530 ps
CPU time 9.39 seconds
Started Sep 11 02:50:33 AM UTC 24
Finished Sep 11 02:50:44 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797564555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.797564555
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/40.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device.696776353
Short name T205
Test name
Test status
Simulation time 434208654 ps
CPU time 7.05 seconds
Started Sep 11 02:50:47 AM UTC 24
Finished Sep 11 02:50:55 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696776353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.696776353
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/41.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1930621027
Short name T181
Test name
Test status
Simulation time 44513858019 ps
CPU time 223.5 seconds
Started Sep 11 02:50:47 AM UTC 24
Finished Sep 11 02:54:34 AM UTC 24
Peak memory 214236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930621027 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.1930621027
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/41.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.2565682130
Short name T724
Test name
Test status
Simulation time 224484405 ps
CPU time 1.94 seconds
Started Sep 11 02:50:55 AM UTC 24
Finished Sep 11 02:50:58 AM UTC 24
Peak memory 211232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565682130 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.2565682130
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/41.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_error_random.563185494
Short name T741
Test name
Test status
Simulation time 1356199948 ps
CPU time 20.22 seconds
Started Sep 11 02:50:50 AM UTC 24
Finished Sep 11 02:51:12 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563185494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.563185494
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/41.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random.4114370777
Short name T728
Test name
Test status
Simulation time 796698815 ps
CPU time 18.61 seconds
Started Sep 11 02:50:42 AM UTC 24
Finished Sep 11 02:51:02 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114370777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.4114370777
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/41.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.1407497207
Short name T816
Test name
Test status
Simulation time 29560662077 ps
CPU time 80.07 seconds
Started Sep 11 02:50:43 AM UTC 24
Finished Sep 11 02:52:05 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407497207 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1407497207
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/41.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.584581284
Short name T887
Test name
Test status
Simulation time 141815805304 ps
CPU time 177.1 seconds
Started Sep 11 02:50:45 AM UTC 24
Finished Sep 11 02:53:45 AM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584581284 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.584581284
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/41.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_zero_delays.3269596366
Short name T719
Test name
Test status
Simulation time 34223924 ps
CPU time 5.63 seconds
Started Sep 11 02:50:43 AM UTC 24
Finished Sep 11 02:50:50 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269596366 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.3269596366
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/41.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_same_source.1570516510
Short name T733
Test name
Test status
Simulation time 4507559004 ps
CPU time 16.4 seconds
Started Sep 11 02:50:47 AM UTC 24
Finished Sep 11 02:51:05 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570516510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1570516510
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/41.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke.3550428947
Short name T713
Test name
Test status
Simulation time 76268525 ps
CPU time 2.45 seconds
Started Sep 11 02:50:39 AM UTC 24
Finished Sep 11 02:50:42 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550428947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3550428947
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/41.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_large_delays.3006042785
Short name T722
Test name
Test status
Simulation time 2083413810 ps
CPU time 12.69 seconds
Started Sep 11 02:50:42 AM UTC 24
Finished Sep 11 02:50:55 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006042785 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3006042785
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/41.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.2719054050
Short name T725
Test name
Test status
Simulation time 1393987741 ps
CPU time 15.67 seconds
Started Sep 11 02:50:42 AM UTC 24
Finished Sep 11 02:50:58 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719054050 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2719054050
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/41.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.1408174436
Short name T712
Test name
Test status
Simulation time 10667197 ps
CPU time 1.47 seconds
Started Sep 11 02:50:39 AM UTC 24
Finished Sep 11 02:50:41 AM UTC 24
Peak memory 211168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408174436 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.1408174436
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/41.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.2208119162
Short name T765
Test name
Test status
Simulation time 8228147611 ps
CPU time 29.52 seconds
Started Sep 11 02:50:57 AM UTC 24
Finished Sep 11 02:51:28 AM UTC 24
Peak memory 214432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208119162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.2208119162
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/41.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2089382447
Short name T756
Test name
Test status
Simulation time 1799685849 ps
CPU time 23.55 seconds
Started Sep 11 02:50:57 AM UTC 24
Finished Sep 11 02:51:22 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089382447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2089382447
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/41.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.2707909737
Short name T185
Test name
Test status
Simulation time 8109967192 ps
CPU time 113.01 seconds
Started Sep 11 02:50:57 AM UTC 24
Finished Sep 11 02:52:52 AM UTC 24
Peak memory 216284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707909737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.2707909737
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/41.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.25834654
Short name T731
Test name
Test status
Simulation time 6895435 ps
CPU time 2.77 seconds
Started Sep 11 02:50:59 AM UTC 24
Finished Sep 11 02:51:03 AM UTC 24
Peak memory 212248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25834654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.25834654
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/41.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_unmapped_addr.2177734544
Short name T730
Test name
Test status
Simulation time 529009012 ps
CPU time 9.04 seconds
Started Sep 11 02:50:52 AM UTC 24
Finished Sep 11 02:51:02 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177734544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2177734544
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/41.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device.2893904234
Short name T137
Test name
Test status
Simulation time 559523892 ps
CPU time 11.47 seconds
Started Sep 11 02:51:05 AM UTC 24
Finished Sep 11 02:51:17 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893904234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.2893904234
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/42.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.357188711
Short name T899
Test name
Test status
Simulation time 362233032845 ps
CPU time 284.64 seconds
Started Sep 11 02:51:06 AM UTC 24
Finished Sep 11 02:55:55 AM UTC 24
Peak memory 217876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357188711 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.357188711
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/42.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.2590619085
Short name T750
Test name
Test status
Simulation time 104119579 ps
CPU time 6 seconds
Started Sep 11 02:51:10 AM UTC 24
Finished Sep 11 02:51:17 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590619085 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.2590619085
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/42.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_error_random.2007278382
Short name T745
Test name
Test status
Simulation time 554511470 ps
CPU time 5.67 seconds
Started Sep 11 02:51:08 AM UTC 24
Finished Sep 11 02:51:15 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007278382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.2007278382
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/42.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random.2534026789
Short name T752
Test name
Test status
Simulation time 2577219735 ps
CPU time 15.59 seconds
Started Sep 11 02:51:03 AM UTC 24
Finished Sep 11 02:51:19 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534026789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2534026789
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/42.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.3301295403
Short name T779
Test name
Test status
Simulation time 6226081074 ps
CPU time 30.13 seconds
Started Sep 11 02:51:05 AM UTC 24
Finished Sep 11 02:51:36 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301295403 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3301295403
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/42.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.1606372617
Short name T836
Test name
Test status
Simulation time 13571684028 ps
CPU time 74.48 seconds
Started Sep 11 02:51:05 AM UTC 24
Finished Sep 11 02:52:21 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606372617 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.1606372617
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/42.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_zero_delays.1794587308
Short name T734
Test name
Test status
Simulation time 30346949 ps
CPU time 2.77 seconds
Started Sep 11 02:51:03 AM UTC 24
Finished Sep 11 02:51:06 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794587308 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.1794587308
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/42.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_same_source.1913923344
Short name T740
Test name
Test status
Simulation time 33571318 ps
CPU time 3.3 seconds
Started Sep 11 02:51:07 AM UTC 24
Finished Sep 11 02:51:11 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913923344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.1913923344
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/42.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke.3864063909
Short name T729
Test name
Test status
Simulation time 10218413 ps
CPU time 1.73 seconds
Started Sep 11 02:50:59 AM UTC 24
Finished Sep 11 02:51:02 AM UTC 24
Peak memory 211236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864063909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.3864063909
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/42.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_large_delays.291985313
Short name T744
Test name
Test status
Simulation time 3229275035 ps
CPU time 13.3 seconds
Started Sep 11 02:51:01 AM UTC 24
Finished Sep 11 02:51:15 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291985313 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.291985313
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/42.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.508464028
Short name T753
Test name
Test status
Simulation time 2631782254 ps
CPU time 16.6 seconds
Started Sep 11 02:51:02 AM UTC 24
Finished Sep 11 02:51:20 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508464028 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.508464028
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/42.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.3070660914
Short name T732
Test name
Test status
Simulation time 8382595 ps
CPU time 1.46 seconds
Started Sep 11 02:51:00 AM UTC 24
Finished Sep 11 02:51:03 AM UTC 24
Peak memory 211124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070660914 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.3070660914
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/42.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.2031596345
Short name T810
Test name
Test status
Simulation time 253810419 ps
CPU time 50.22 seconds
Started Sep 11 02:51:10 AM UTC 24
Finished Sep 11 02:52:02 AM UTC 24
Peak memory 216220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031596345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2031596345
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/42.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.874945337
Short name T777
Test name
Test status
Simulation time 1052853729 ps
CPU time 20.35 seconds
Started Sep 11 02:51:13 AM UTC 24
Finished Sep 11 02:51:35 AM UTC 24
Peak memory 212040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874945337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.874945337
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/42.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.230348643
Short name T890
Test name
Test status
Simulation time 4619504961 ps
CPU time 167.51 seconds
Started Sep 11 02:51:10 AM UTC 24
Finished Sep 11 02:54:00 AM UTC 24
Peak memory 216284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230348643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.230348643
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/42.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.3724940275
Short name T775
Test name
Test status
Simulation time 158823239 ps
CPU time 18.54 seconds
Started Sep 11 02:51:13 AM UTC 24
Finished Sep 11 02:51:33 AM UTC 24
Peak memory 212032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724940275 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.3724940275
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/42.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_unmapped_addr.330841136
Short name T742
Test name
Test status
Simulation time 1188679860 ps
CPU time 3.93 seconds
Started Sep 11 02:51:08 AM UTC 24
Finished Sep 11 02:51:13 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330841136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.330841136
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/42.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.2949137124
Short name T760
Test name
Test status
Simulation time 51620455 ps
CPU time 5.58 seconds
Started Sep 11 02:51:18 AM UTC 24
Finished Sep 11 02:51:25 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949137124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.2949137124
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/43.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.2018663818
Short name T880
Test name
Test status
Simulation time 16683516857 ps
CPU time 116.38 seconds
Started Sep 11 02:51:18 AM UTC 24
Finished Sep 11 02:53:17 AM UTC 24
Peak memory 214428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018663818 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.2018663818
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/43.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.3797391330
Short name T768
Test name
Test status
Simulation time 370116134 ps
CPU time 7.88 seconds
Started Sep 11 02:51:20 AM UTC 24
Finished Sep 11 02:51:29 AM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797391330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.3797391330
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/43.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.3065830086
Short name T759
Test name
Test status
Simulation time 36240741 ps
CPU time 3.2 seconds
Started Sep 11 02:51:20 AM UTC 24
Finished Sep 11 02:51:25 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065830086 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.3065830086
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/43.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random.2690838505
Short name T754
Test name
Test status
Simulation time 944432524 ps
CPU time 5.51 seconds
Started Sep 11 02:51:15 AM UTC 24
Finished Sep 11 02:51:22 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690838505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.2690838505
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/43.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.547942105
Short name T869
Test name
Test status
Simulation time 21799702667 ps
CPU time 97.7 seconds
Started Sep 11 02:51:18 AM UTC 24
Finished Sep 11 02:52:57 AM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547942105 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.547942105
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/43.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.4138717183
Short name T834
Test name
Test status
Simulation time 9941110452 ps
CPU time 60.36 seconds
Started Sep 11 02:51:18 AM UTC 24
Finished Sep 11 02:52:20 AM UTC 24
Peak memory 212444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138717183 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.4138717183
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/43.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.433744580
Short name T755
Test name
Test status
Simulation time 332724045 ps
CPU time 5.72 seconds
Started Sep 11 02:51:15 AM UTC 24
Finished Sep 11 02:51:22 AM UTC 24
Peak memory 212448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433744580 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.433744580
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/43.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.926317139
Short name T764
Test name
Test status
Simulation time 683833677 ps
CPU time 8.39 seconds
Started Sep 11 02:51:18 AM UTC 24
Finished Sep 11 02:51:28 AM UTC 24
Peak memory 212112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926317139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.926317139
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/43.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke.1943282249
Short name T747
Test name
Test status
Simulation time 71031927 ps
CPU time 2.09 seconds
Started Sep 11 02:51:13 AM UTC 24
Finished Sep 11 02:51:16 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943282249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1943282249
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/43.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.2408826999
Short name T770
Test name
Test status
Simulation time 13629768571 ps
CPU time 16.87 seconds
Started Sep 11 02:51:13 AM UTC 24
Finished Sep 11 02:51:31 AM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408826999 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2408826999
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/43.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.2659887842
Short name T766
Test name
Test status
Simulation time 2069304072 ps
CPU time 11.95 seconds
Started Sep 11 02:51:15 AM UTC 24
Finished Sep 11 02:51:28 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659887842 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2659887842
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/43.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.3645228468
Short name T746
Test name
Test status
Simulation time 10326875 ps
CPU time 1.52 seconds
Started Sep 11 02:51:13 AM UTC 24
Finished Sep 11 02:51:16 AM UTC 24
Peak memory 211124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645228468 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.3645228468
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/43.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.1709253980
Short name T839
Test name
Test status
Simulation time 5231422735 ps
CPU time 61.41 seconds
Started Sep 11 02:51:21 AM UTC 24
Finished Sep 11 02:52:24 AM UTC 24
Peak memory 214236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709253980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.1709253980
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/43.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.2716036279
Short name T837
Test name
Test status
Simulation time 4796652972 ps
CPU time 58.65 seconds
Started Sep 11 02:51:21 AM UTC 24
Finished Sep 11 02:52:21 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716036279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2716036279
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/43.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.25357118
Short name T878
Test name
Test status
Simulation time 779786337 ps
CPU time 110 seconds
Started Sep 11 02:51:21 AM UTC 24
Finished Sep 11 02:53:13 AM UTC 24
Peak memory 216224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25357118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.25357118
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/43.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3792998865
Short name T846
Test name
Test status
Simulation time 5724716197 ps
CPU time 65.1 seconds
Started Sep 11 02:51:23 AM UTC 24
Finished Sep 11 02:52:30 AM UTC 24
Peak memory 214240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792998865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.3792998865
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/43.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.191156029
Short name T778
Test name
Test status
Simulation time 976401622 ps
CPU time 14.38 seconds
Started Sep 11 02:51:20 AM UTC 24
Finished Sep 11 02:51:36 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191156029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.191156029
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/43.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.1606424212
Short name T769
Test name
Test status
Simulation time 23312440 ps
CPU time 3.34 seconds
Started Sep 11 02:51:26 AM UTC 24
Finished Sep 11 02:51:30 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606424212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.1606424212
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/44.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2714145018
Short name T783
Test name
Test status
Simulation time 168141863 ps
CPU time 6.99 seconds
Started Sep 11 02:51:31 AM UTC 24
Finished Sep 11 02:51:39 AM UTC 24
Peak memory 212380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714145018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.2714145018
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/44.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.1701068552
Short name T772
Test name
Test status
Simulation time 12595706 ps
CPU time 1.91 seconds
Started Sep 11 02:51:29 AM UTC 24
Finished Sep 11 02:51:32 AM UTC 24
Peak memory 210876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701068552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1701068552
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/44.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random.150419792
Short name T767
Test name
Test status
Simulation time 63603823 ps
CPU time 2.34 seconds
Started Sep 11 02:51:26 AM UTC 24
Finished Sep 11 02:51:29 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150419792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.150419792
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/44.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.3152125954
Short name T867
Test name
Test status
Simulation time 20672410214 ps
CPU time 81.8 seconds
Started Sep 11 02:51:26 AM UTC 24
Finished Sep 11 02:52:49 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152125954 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.3152125954
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/44.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.4121216293
Short name T843
Test name
Test status
Simulation time 8095145442 ps
CPU time 60.65 seconds
Started Sep 11 02:51:26 AM UTC 24
Finished Sep 11 02:52:28 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121216293 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.4121216293
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/44.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.3375508648
Short name T771
Test name
Test status
Simulation time 40403960 ps
CPU time 5.1 seconds
Started Sep 11 02:51:26 AM UTC 24
Finished Sep 11 02:51:32 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375508648 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.3375508648
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/44.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.590699550
Short name T787
Test name
Test status
Simulation time 1447009931 ps
CPU time 11.57 seconds
Started Sep 11 02:51:29 AM UTC 24
Finished Sep 11 02:51:42 AM UTC 24
Peak memory 211788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590699550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.590699550
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/44.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.2745235437
Short name T762
Test name
Test status
Simulation time 12008572 ps
CPU time 1.43 seconds
Started Sep 11 02:51:23 AM UTC 24
Finished Sep 11 02:51:25 AM UTC 24
Peak memory 211232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745235437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.2745235437
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/44.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.3442377122
Short name T782
Test name
Test status
Simulation time 8365473150 ps
CPU time 13.89 seconds
Started Sep 11 02:51:23 AM UTC 24
Finished Sep 11 02:51:38 AM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442377122 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.3442377122
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/44.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.1012681091
Short name T774
Test name
Test status
Simulation time 1868378785 ps
CPU time 5.86 seconds
Started Sep 11 02:51:26 AM UTC 24
Finished Sep 11 02:51:33 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012681091 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.1012681091
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/44.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.2365959236
Short name T761
Test name
Test status
Simulation time 8366298 ps
CPU time 1.04 seconds
Started Sep 11 02:51:23 AM UTC 24
Finished Sep 11 02:51:25 AM UTC 24
Peak memory 211120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365959236 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.2365959236
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/44.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.3551045244
Short name T788
Test name
Test status
Simulation time 229441223 ps
CPU time 10.19 seconds
Started Sep 11 02:51:31 AM UTC 24
Finished Sep 11 02:51:43 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551045244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.3551045244
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/44.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3857139663
Short name T808
Test name
Test status
Simulation time 706619842 ps
CPU time 26.21 seconds
Started Sep 11 02:51:33 AM UTC 24
Finished Sep 11 02:52:01 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857139663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3857139663
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/44.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.1780236375
Short name T165
Test name
Test status
Simulation time 7440502004 ps
CPU time 137.09 seconds
Started Sep 11 02:51:31 AM UTC 24
Finished Sep 11 02:53:51 AM UTC 24
Peak memory 216288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780236375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.1780236375
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/44.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.3969209106
Short name T805
Test name
Test status
Simulation time 433837347 ps
CPU time 23.83 seconds
Started Sep 11 02:51:33 AM UTC 24
Finished Sep 11 02:51:58 AM UTC 24
Peak memory 214176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969209106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.3969209106
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/44.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.1722129393
Short name T776
Test name
Test status
Simulation time 154835342 ps
CPU time 3.02 seconds
Started Sep 11 02:51:29 AM UTC 24
Finished Sep 11 02:51:34 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722129393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.1722129393
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/44.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.4024539956
Short name T790
Test name
Test status
Simulation time 22489370 ps
CPU time 3.76 seconds
Started Sep 11 02:51:39 AM UTC 24
Finished Sep 11 02:51:44 AM UTC 24
Peak memory 212320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024539956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.4024539956
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/45.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.4082062345
Short name T900
Test name
Test status
Simulation time 179032342835 ps
CPU time 303.93 seconds
Started Sep 11 02:51:39 AM UTC 24
Finished Sep 11 02:56:47 AM UTC 24
Peak memory 214236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082062345 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.4082062345
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/45.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.4037813068
Short name T799
Test name
Test status
Simulation time 219910612 ps
CPU time 4.27 seconds
Started Sep 11 02:51:46 AM UTC 24
Finished Sep 11 02:51:51 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037813068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.4037813068
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/45.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.2254409909
Short name T793
Test name
Test status
Simulation time 173289022 ps
CPU time 4.34 seconds
Started Sep 11 02:51:40 AM UTC 24
Finished Sep 11 02:51:45 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254409909 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2254409909
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/45.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random.3440162532
Short name T791
Test name
Test status
Simulation time 52675399 ps
CPU time 8.03 seconds
Started Sep 11 02:51:35 AM UTC 24
Finished Sep 11 02:51:44 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440162532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.3440162532
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/45.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.2072375192
Short name T893
Test name
Test status
Simulation time 409040189075 ps
CPU time 196.93 seconds
Started Sep 11 02:51:37 AM UTC 24
Finished Sep 11 02:54:57 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072375192 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2072375192
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/45.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.2907150738
Short name T877
Test name
Test status
Simulation time 20963841943 ps
CPU time 90.37 seconds
Started Sep 11 02:51:39 AM UTC 24
Finished Sep 11 02:53:12 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907150738 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2907150738
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/45.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.1331538306
Short name T794
Test name
Test status
Simulation time 114033679 ps
CPU time 7.92 seconds
Started Sep 11 02:51:37 AM UTC 24
Finished Sep 11 02:51:46 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331538306 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.1331538306
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/45.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.123842163
Short name T789
Test name
Test status
Simulation time 14524728 ps
CPU time 2.28 seconds
Started Sep 11 02:51:40 AM UTC 24
Finished Sep 11 02:51:43 AM UTC 24
Peak memory 212112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123842163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.123842163
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/45.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.3340928528
Short name T780
Test name
Test status
Simulation time 105775332 ps
CPU time 2.39 seconds
Started Sep 11 02:51:33 AM UTC 24
Finished Sep 11 02:51:37 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340928528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.3340928528
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/45.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.3973729394
Short name T798
Test name
Test status
Simulation time 2919310851 ps
CPU time 13.34 seconds
Started Sep 11 02:51:35 AM UTC 24
Finished Sep 11 02:51:50 AM UTC 24
Peak memory 212324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973729394 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.3973729394
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/45.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.3700839910
Short name T792
Test name
Test status
Simulation time 2767992303 ps
CPU time 8.53 seconds
Started Sep 11 02:51:35 AM UTC 24
Finished Sep 11 02:51:45 AM UTC 24
Peak memory 212144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700839910 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.3700839910
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/45.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.778076614
Short name T781
Test name
Test status
Simulation time 28571511 ps
CPU time 1.52 seconds
Started Sep 11 02:51:35 AM UTC 24
Finished Sep 11 02:51:38 AM UTC 24
Peak memory 211120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778076614 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.778076614
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/45.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.3156547795
Short name T813
Test name
Test status
Simulation time 1069431754 ps
CPU time 16.73 seconds
Started Sep 11 02:51:46 AM UTC 24
Finished Sep 11 02:52:04 AM UTC 24
Peak memory 212112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156547795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3156547795
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/45.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.752611006
Short name T818
Test name
Test status
Simulation time 1357563790 ps
CPU time 24.25 seconds
Started Sep 11 02:51:46 AM UTC 24
Finished Sep 11 02:52:11 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752611006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.752611006
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/45.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.853612867
Short name T879
Test name
Test status
Simulation time 468823937 ps
CPU time 85.5 seconds
Started Sep 11 02:51:46 AM UTC 24
Finished Sep 11 02:53:13 AM UTC 24
Peak memory 214172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853612867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.853612867
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/45.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.10189192
Short name T829
Test name
Test status
Simulation time 167976689 ps
CPU time 27.7 seconds
Started Sep 11 02:51:46 AM UTC 24
Finished Sep 11 02:52:15 AM UTC 24
Peak memory 214368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10189192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.10189192
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/45.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.2037647387
Short name T797
Test name
Test status
Simulation time 26029525 ps
CPU time 3.93 seconds
Started Sep 11 02:51:44 AM UTC 24
Finished Sep 11 02:51:49 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037647387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.2037647387
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/45.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.3333563388
Short name T807
Test name
Test status
Simulation time 681690976 ps
CPU time 4.99 seconds
Started Sep 11 02:51:53 AM UTC 24
Finished Sep 11 02:51:59 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333563388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.3333563388
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/46.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.2182911115
Short name T898
Test name
Test status
Simulation time 32994429833 ps
CPU time 212.82 seconds
Started Sep 11 02:51:53 AM UTC 24
Finished Sep 11 02:55:29 AM UTC 24
Peak memory 214236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182911115 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.2182911115
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/46.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.1588887100
Short name T806
Test name
Test status
Simulation time 246702746 ps
CPU time 4.44 seconds
Started Sep 11 02:51:53 AM UTC 24
Finished Sep 11 02:51:59 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588887100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.1588887100
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/46.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.2064079051
Short name T763
Test name
Test status
Simulation time 19982647 ps
CPU time 2.31 seconds
Started Sep 11 02:51:53 AM UTC 24
Finished Sep 11 02:51:57 AM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064079051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2064079051
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/46.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random.1810529940
Short name T800
Test name
Test status
Simulation time 54328011 ps
CPU time 2.87 seconds
Started Sep 11 02:51:48 AM UTC 24
Finished Sep 11 02:51:52 AM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810529940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.1810529940
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/46.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.3133424603
Short name T876
Test name
Test status
Simulation time 116069802289 ps
CPU time 79.79 seconds
Started Sep 11 02:51:49 AM UTC 24
Finished Sep 11 02:53:10 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133424603 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3133424603
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/46.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3612943883
Short name T822
Test name
Test status
Simulation time 5507623776 ps
CPU time 18.19 seconds
Started Sep 11 02:51:53 AM UTC 24
Finished Sep 11 02:52:12 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612943883 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.3612943883
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/46.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.1685292228
Short name T809
Test name
Test status
Simulation time 287814540 ps
CPU time 11.31 seconds
Started Sep 11 02:51:49 AM UTC 24
Finished Sep 11 02:52:01 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685292228 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.1685292228
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/46.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.3180543242
Short name T804
Test name
Test status
Simulation time 219374045 ps
CPU time 3.88 seconds
Started Sep 11 02:51:53 AM UTC 24
Finished Sep 11 02:51:58 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180543242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3180543242
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/46.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.1572536911
Short name T796
Test name
Test status
Simulation time 13035829 ps
CPU time 1.65 seconds
Started Sep 11 02:51:46 AM UTC 24
Finished Sep 11 02:51:49 AM UTC 24
Peak memory 211236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572536911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.1572536911
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/46.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.2169383125
Short name T814
Test name
Test status
Simulation time 7265584902 ps
CPU time 14.35 seconds
Started Sep 11 02:51:48 AM UTC 24
Finished Sep 11 02:52:04 AM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169383125 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.2169383125
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/46.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.226094000
Short name T802
Test name
Test status
Simulation time 649026819 ps
CPU time 6.87 seconds
Started Sep 11 02:51:48 AM UTC 24
Finished Sep 11 02:51:56 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226094000 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.226094000
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/46.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.32707919
Short name T795
Test name
Test status
Simulation time 15680670 ps
CPU time 1.44 seconds
Started Sep 11 02:51:46 AM UTC 24
Finished Sep 11 02:51:49 AM UTC 24
Peak memory 211232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32707919 -assert nopostproc +UVM_TESTNAME=xbar_
base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.32707919
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/46.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.168836883
Short name T853
Test name
Test status
Simulation time 335488809 ps
CPU time 39.25 seconds
Started Sep 11 02:51:54 AM UTC 24
Finished Sep 11 02:52:34 AM UTC 24
Peak memory 214168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168836883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.168836883
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/46.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1154075328
Short name T815
Test name
Test status
Simulation time 151867688 ps
CPU time 4.6 seconds
Started Sep 11 02:52:00 AM UTC 24
Finished Sep 11 02:52:05 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154075328 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1154075328
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/46.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.174994423
Short name T891
Test name
Test status
Simulation time 2018192002 ps
CPU time 122.99 seconds
Started Sep 11 02:52:00 AM UTC 24
Finished Sep 11 02:54:05 AM UTC 24
Peak memory 218460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174994423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.174994423
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/46.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.2023886873
Short name T885
Test name
Test status
Simulation time 844588052 ps
CPU time 91.11 seconds
Started Sep 11 02:52:00 AM UTC 24
Finished Sep 11 02:53:33 AM UTC 24
Peak memory 216224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023886873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.2023886873
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/46.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.230489487
Short name T801
Test name
Test status
Simulation time 12900825 ps
CPU time 1.97 seconds
Started Sep 11 02:51:53 AM UTC 24
Finished Sep 11 02:51:56 AM UTC 24
Peak memory 211172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230489487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.230489487
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/46.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.1182497174
Short name T824
Test name
Test status
Simulation time 304909964 ps
CPU time 7.88 seconds
Started Sep 11 02:52:05 AM UTC 24
Finished Sep 11 02:52:14 AM UTC 24
Peak memory 212320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182497174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.1182497174
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/47.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.203333519
Short name T268
Test name
Test status
Simulation time 150542448091 ps
CPU time 249.35 seconds
Started Sep 11 02:52:09 AM UTC 24
Finished Sep 11 02:56:21 AM UTC 24
Peak memory 214240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203333519 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.203333519
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/47.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.1095287849
Short name T832
Test name
Test status
Simulation time 569654687 ps
CPU time 6.76 seconds
Started Sep 11 02:52:09 AM UTC 24
Finished Sep 11 02:52:17 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095287849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.1095287849
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/47.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.1819049065
Short name T826
Test name
Test status
Simulation time 208804418 ps
CPU time 4.76 seconds
Started Sep 11 02:52:09 AM UTC 24
Finished Sep 11 02:52:14 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819049065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1819049065
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/47.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random.4179852958
Short name T821
Test name
Test status
Simulation time 57727788 ps
CPU time 6.75 seconds
Started Sep 11 02:52:04 AM UTC 24
Finished Sep 11 02:52:12 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179852958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.4179852958
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/47.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.3503478910
Short name T897
Test name
Test status
Simulation time 108273364804 ps
CPU time 199.07 seconds
Started Sep 11 02:52:05 AM UTC 24
Finished Sep 11 02:55:26 AM UTC 24
Peak memory 212512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503478910 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3503478910
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/47.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.2938491007
Short name T872
Test name
Test status
Simulation time 47408344836 ps
CPU time 58.88 seconds
Started Sep 11 02:52:05 AM UTC 24
Finished Sep 11 02:53:05 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938491007 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.2938491007
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/47.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.4281526494
Short name T817
Test name
Test status
Simulation time 28439370 ps
CPU time 3.52 seconds
Started Sep 11 02:52:04 AM UTC 24
Finished Sep 11 02:52:09 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281526494 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.4281526494
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/47.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.2865422238
Short name T828
Test name
Test status
Simulation time 91267877 ps
CPU time 5.29 seconds
Started Sep 11 02:52:09 AM UTC 24
Finished Sep 11 02:52:15 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865422238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2865422238
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/47.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.830175349
Short name T811
Test name
Test status
Simulation time 12724963 ps
CPU time 1.56 seconds
Started Sep 11 02:52:00 AM UTC 24
Finished Sep 11 02:52:02 AM UTC 24
Peak memory 211132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830175349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.830175349
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/47.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.3744647829
Short name T823
Test name
Test status
Simulation time 2243800300 ps
CPU time 11.9 seconds
Started Sep 11 02:52:00 AM UTC 24
Finished Sep 11 02:52:13 AM UTC 24
Peak memory 212440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744647829 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.3744647829
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/47.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.1370946496
Short name T827
Test name
Test status
Simulation time 1116910635 ps
CPU time 9.33 seconds
Started Sep 11 02:52:04 AM UTC 24
Finished Sep 11 02:52:15 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370946496 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1370946496
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/47.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1562556691
Short name T812
Test name
Test status
Simulation time 14526945 ps
CPU time 1.71 seconds
Started Sep 11 02:52:00 AM UTC 24
Finished Sep 11 02:52:02 AM UTC 24
Peak memory 211124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562556691 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.1562556691
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/47.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.546553015
Short name T138
Test name
Test status
Simulation time 2433497578 ps
CPU time 18.18 seconds
Started Sep 11 02:52:11 AM UTC 24
Finished Sep 11 02:52:31 AM UTC 24
Peak memory 214232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546553015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.546553015
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/47.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3020358326
Short name T854
Test name
Test status
Simulation time 1141518688 ps
CPU time 16.23 seconds
Started Sep 11 02:52:17 AM UTC 24
Finished Sep 11 02:52:34 AM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020358326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3020358326
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/47.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.1745345860
Short name T870
Test name
Test status
Simulation time 284841176 ps
CPU time 42.48 seconds
Started Sep 11 02:52:16 AM UTC 24
Finished Sep 11 02:53:01 AM UTC 24
Peak memory 214432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745345860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.1745345860
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/47.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.4050282777
Short name T875
Test name
Test status
Simulation time 2026465988 ps
CPU time 48.53 seconds
Started Sep 11 02:52:17 AM UTC 24
Finished Sep 11 02:53:07 AM UTC 24
Peak memory 214148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050282777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.4050282777
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/47.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.3079583069
Short name T830
Test name
Test status
Simulation time 266365731 ps
CPU time 5.44 seconds
Started Sep 11 02:52:09 AM UTC 24
Finished Sep 11 02:52:15 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079583069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.3079583069
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/47.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.3539348811
Short name T857
Test name
Test status
Simulation time 5058067087 ps
CPU time 15.02 seconds
Started Sep 11 02:52:21 AM UTC 24
Finished Sep 11 02:52:38 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539348811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.3539348811
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/48.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2393315220
Short name T166
Test name
Test status
Simulation time 42785093336 ps
CPU time 264.64 seconds
Started Sep 11 02:52:21 AM UTC 24
Finished Sep 11 02:56:50 AM UTC 24
Peak memory 214232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393315220 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.2393315220
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/48.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3753436010
Short name T847
Test name
Test status
Simulation time 483703680 ps
CPU time 7.16 seconds
Started Sep 11 02:52:21 AM UTC 24
Finished Sep 11 02:52:30 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753436010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.3753436010
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/48.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.3917866827
Short name T842
Test name
Test status
Simulation time 60166814 ps
CPU time 3.85 seconds
Started Sep 11 02:52:21 AM UTC 24
Finished Sep 11 02:52:27 AM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917866827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3917866827
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/48.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random.3715179246
Short name T855
Test name
Test status
Simulation time 682362671 ps
CPU time 17.04 seconds
Started Sep 11 02:52:17 AM UTC 24
Finished Sep 11 02:52:35 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715179246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.3715179246
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/48.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.2295917817
Short name T889
Test name
Test status
Simulation time 26218819093 ps
CPU time 97.38 seconds
Started Sep 11 02:52:17 AM UTC 24
Finished Sep 11 02:53:57 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295917817 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2295917817
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/48.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.669662542
Short name T882
Test name
Test status
Simulation time 10567906556 ps
CPU time 67.8 seconds
Started Sep 11 02:52:17 AM UTC 24
Finished Sep 11 02:53:27 AM UTC 24
Peak memory 212176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669662542 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.669662542
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/48.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.3120694761
Short name T838
Test name
Test status
Simulation time 128437952 ps
CPU time 4.77 seconds
Started Sep 11 02:52:17 AM UTC 24
Finished Sep 11 02:52:23 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120694761 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.3120694761
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/48.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.1052105859
Short name T852
Test name
Test status
Simulation time 1741067541 ps
CPU time 10.89 seconds
Started Sep 11 02:52:21 AM UTC 24
Finished Sep 11 02:52:34 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052105859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1052105859
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/48.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.987922638
Short name T833
Test name
Test status
Simulation time 8897490 ps
CPU time 1.58 seconds
Started Sep 11 02:52:17 AM UTC 24
Finished Sep 11 02:52:20 AM UTC 24
Peak memory 211168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987922638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.987922638
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/48.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.3823109167
Short name T848
Test name
Test status
Simulation time 4057045947 ps
CPU time 12.77 seconds
Started Sep 11 02:52:17 AM UTC 24
Finished Sep 11 02:52:31 AM UTC 24
Peak memory 212440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823109167 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.3823109167
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/48.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.4006971577
Short name T851
Test name
Test status
Simulation time 3486374634 ps
CPU time 15.52 seconds
Started Sep 11 02:52:17 AM UTC 24
Finished Sep 11 02:52:34 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006971577 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.4006971577
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/48.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.978678408
Short name T835
Test name
Test status
Simulation time 39490409 ps
CPU time 1.74 seconds
Started Sep 11 02:52:17 AM UTC 24
Finished Sep 11 02:52:20 AM UTC 24
Peak memory 211224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978678408 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.978678408
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/48.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.368689876
Short name T873
Test name
Test status
Simulation time 588695256 ps
CPU time 41.72 seconds
Started Sep 11 02:52:21 AM UTC 24
Finished Sep 11 02:53:05 AM UTC 24
Peak memory 214172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368689876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.368689876
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/48.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1173156257
Short name T865
Test name
Test status
Simulation time 203301566 ps
CPU time 18.52 seconds
Started Sep 11 02:52:26 AM UTC 24
Finished Sep 11 02:52:46 AM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173156257 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.1173156257
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/48.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.133005190
Short name T849
Test name
Test status
Simulation time 70474796 ps
CPU time 4.84 seconds
Started Sep 11 02:52:26 AM UTC 24
Finished Sep 11 02:52:32 AM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133005190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.133005190
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/48.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.2798051221
Short name T871
Test name
Test status
Simulation time 1302620522 ps
CPU time 36.17 seconds
Started Sep 11 02:52:26 AM UTC 24
Finished Sep 11 02:53:04 AM UTC 24
Peak memory 214176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798051221 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.2798051221
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/48.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.2672105212
Short name T840
Test name
Test status
Simulation time 69497435 ps
CPU time 1.88 seconds
Started Sep 11 02:52:21 AM UTC 24
Finished Sep 11 02:52:25 AM UTC 24
Peak memory 211180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672105212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2672105212
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/48.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.1686550865
Short name T223
Test name
Test status
Simulation time 66079049 ps
CPU time 2.25 seconds
Started Sep 11 02:52:31 AM UTC 24
Finished Sep 11 02:52:34 AM UTC 24
Peak memory 211932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686550865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.1686550865
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/49.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2269115481
Short name T895
Test name
Test status
Simulation time 96144541326 ps
CPU time 155.24 seconds
Started Sep 11 02:52:31 AM UTC 24
Finished Sep 11 02:55:09 AM UTC 24
Peak memory 214188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269115481 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.2269115481
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/49.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.294444015
Short name T858
Test name
Test status
Simulation time 74294858 ps
CPU time 3.87 seconds
Started Sep 11 02:52:36 AM UTC 24
Finished Sep 11 02:52:41 AM UTC 24
Peak memory 212140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294444015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.294444015
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/49.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.2813095277
Short name T861
Test name
Test status
Simulation time 362907599 ps
CPU time 5.14 seconds
Started Sep 11 02:52:36 AM UTC 24
Finished Sep 11 02:52:43 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813095277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.2813095277
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/49.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random.2528959134
Short name T862
Test name
Test status
Simulation time 684606202 ps
CPU time 11.98 seconds
Started Sep 11 02:52:31 AM UTC 24
Finished Sep 11 02:52:44 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528959134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.2528959134
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/49.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.3429143282
Short name T894
Test name
Test status
Simulation time 49318945359 ps
CPU time 148.44 seconds
Started Sep 11 02:52:31 AM UTC 24
Finished Sep 11 02:55:02 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429143282 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.3429143282
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/49.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.1448285573
Short name T884
Test name
Test status
Simulation time 15118073950 ps
CPU time 58.31 seconds
Started Sep 11 02:52:31 AM UTC 24
Finished Sep 11 02:53:31 AM UTC 24
Peak memory 212252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448285573 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.1448285573
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/49.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.2177965391
Short name T856
Test name
Test status
Simulation time 50053293 ps
CPU time 5.45 seconds
Started Sep 11 02:52:31 AM UTC 24
Finished Sep 11 02:52:37 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177965391 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.2177965391
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/49.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.2444214679
Short name T866
Test name
Test status
Simulation time 2454783396 ps
CPU time 9.98 seconds
Started Sep 11 02:52:36 AM UTC 24
Finished Sep 11 02:52:48 AM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444214679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2444214679
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/49.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.2504299715
Short name T845
Test name
Test status
Simulation time 9041618 ps
CPU time 1.55 seconds
Started Sep 11 02:52:26 AM UTC 24
Finished Sep 11 02:52:29 AM UTC 24
Peak memory 211232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504299715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.2504299715
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/49.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3658496521
Short name T860
Test name
Test status
Simulation time 2183707381 ps
CPU time 14.53 seconds
Started Sep 11 02:52:26 AM UTC 24
Finished Sep 11 02:52:42 AM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658496521 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3658496521
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/49.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.2734953733
Short name T850
Test name
Test status
Simulation time 1557549208 ps
CPU time 5.95 seconds
Started Sep 11 02:52:26 AM UTC 24
Finished Sep 11 02:52:34 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734953733 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.2734953733
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/49.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1454592758
Short name T844
Test name
Test status
Simulation time 8700245 ps
CPU time 1.59 seconds
Started Sep 11 02:52:26 AM UTC 24
Finished Sep 11 02:52:29 AM UTC 24
Peak memory 211124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454592758 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.1454592758
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/49.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.649384426
Short name T868
Test name
Test status
Simulation time 2839914420 ps
CPU time 18.55 seconds
Started Sep 11 02:52:36 AM UTC 24
Finished Sep 11 02:52:56 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649384426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.649384426
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/49.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.4119304775
Short name T874
Test name
Test status
Simulation time 539517409 ps
CPU time 29 seconds
Started Sep 11 02:52:36 AM UTC 24
Finished Sep 11 02:53:07 AM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119304775 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.4119304775
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/49.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.2463647405
Short name T886
Test name
Test status
Simulation time 541959858 ps
CPU time 65.77 seconds
Started Sep 11 02:52:36 AM UTC 24
Finished Sep 11 02:53:44 AM UTC 24
Peak memory 214172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463647405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.2463647405
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/49.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.3712104262
Short name T883
Test name
Test status
Simulation time 4117462845 ps
CPU time 52.31 seconds
Started Sep 11 02:52:36 AM UTC 24
Finished Sep 11 02:53:31 AM UTC 24
Peak memory 214240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712104262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.3712104262
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/49.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.174423184
Short name T864
Test name
Test status
Simulation time 365651602 ps
CPU time 8.02 seconds
Started Sep 11 02:52:36 AM UTC 24
Finished Sep 11 02:52:46 AM UTC 24
Peak memory 212292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174423184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.174423184
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/49.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.555653918
Short name T262
Test name
Test status
Simulation time 10231597659 ps
CPU time 66.03 seconds
Started Sep 11 02:42:35 AM UTC 24
Finished Sep 11 02:43:42 AM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555653918 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.555653918
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/5.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.2009681713
Short name T290
Test name
Test status
Simulation time 203971678 ps
CPU time 3.61 seconds
Started Sep 11 02:42:42 AM UTC 24
Finished Sep 11 02:42:47 AM UTC 24
Peak memory 212320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009681713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.2009681713
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/5.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_error_random.775118613
Short name T289
Test name
Test status
Simulation time 112502583 ps
CPU time 8.66 seconds
Started Sep 11 02:42:37 AM UTC 24
Finished Sep 11 02:42:47 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775118613 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.775118613
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/5.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random.3218876085
Short name T108
Test name
Test status
Simulation time 18383562 ps
CPU time 3.54 seconds
Started Sep 11 02:42:29 AM UTC 24
Finished Sep 11 02:42:34 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218876085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.3218876085
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/5.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_large_delays.2349081190
Short name T67
Test name
Test status
Simulation time 12464760162 ps
CPU time 16.41 seconds
Started Sep 11 02:42:30 AM UTC 24
Finished Sep 11 02:42:47 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349081190 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.2349081190
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/5.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_slow_rsp.3580962396
Short name T272
Test name
Test status
Simulation time 86193634998 ps
CPU time 98.78 seconds
Started Sep 11 02:42:32 AM UTC 24
Finished Sep 11 02:44:12 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580962396 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.3580962396
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/5.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_zero_delays.2038140800
Short name T109
Test name
Test status
Simulation time 59786262 ps
CPU time 6.36 seconds
Started Sep 11 02:42:30 AM UTC 24
Finished Sep 11 02:42:37 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038140800 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.2038140800
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/5.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_same_source.779353745
Short name T66
Test name
Test status
Simulation time 116140719 ps
CPU time 2.98 seconds
Started Sep 11 02:42:37 AM UTC 24
Finished Sep 11 02:42:41 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779353745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.779353745
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/5.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke.2708996470
Short name T188
Test name
Test status
Simulation time 122697057 ps
CPU time 2.31 seconds
Started Sep 11 02:42:25 AM UTC 24
Finished Sep 11 02:42:29 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708996470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2708996470
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/5.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_large_delays.3244363663
Short name T111
Test name
Test status
Simulation time 7194027526 ps
CPU time 7.01 seconds
Started Sep 11 02:42:28 AM UTC 24
Finished Sep 11 02:42:37 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244363663 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.3244363663
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/5.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.2862340159
Short name T70
Test name
Test status
Simulation time 5671109341 ps
CPU time 22.01 seconds
Started Sep 11 02:42:29 AM UTC 24
Finished Sep 11 02:42:53 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862340159 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.2862340159
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/5.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.645525588
Short name T55
Test name
Test status
Simulation time 12959281 ps
CPU time 1.8 seconds
Started Sep 11 02:42:25 AM UTC 24
Finished Sep 11 02:42:28 AM UTC 24
Peak memory 211124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645525588 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.645525588
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/5.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all.531279446
Short name T247
Test name
Test status
Simulation time 4171860272 ps
CPU time 88.62 seconds
Started Sep 11 02:42:42 AM UTC 24
Finished Sep 11 02:44:13 AM UTC 24
Peak memory 214228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531279446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.531279446
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/5.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_error.1968082841
Short name T158
Test name
Test status
Simulation time 261223405 ps
CPU time 14.9 seconds
Started Sep 11 02:42:46 AM UTC 24
Finished Sep 11 02:43:02 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968082841 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.1968082841
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/5.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.301792901
Short name T278
Test name
Test status
Simulation time 1206604610 ps
CPU time 115.18 seconds
Started Sep 11 02:42:43 AM UTC 24
Finished Sep 11 02:44:41 AM UTC 24
Peak memory 218268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301792901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.301792901
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/5.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.1744880942
Short name T212
Test name
Test status
Simulation time 37085231923 ps
CPU time 141.27 seconds
Started Sep 11 02:42:49 AM UTC 24
Finished Sep 11 02:45:13 AM UTC 24
Peak memory 214500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744880942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.1744880942
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/5.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_unmapped_addr.4200481985
Short name T68
Test name
Test status
Simulation time 506953141 ps
CPU time 12.53 seconds
Started Sep 11 02:42:38 AM UTC 24
Finished Sep 11 02:42:52 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200481985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.4200481985
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/5.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device.3409728520
Short name T72
Test name
Test status
Simulation time 547252708 ps
CPU time 10.28 seconds
Started Sep 11 02:42:53 AM UTC 24
Finished Sep 11 02:43:05 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409728520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.3409728520
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/6.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.1639644534
Short name T78
Test name
Test status
Simulation time 151225390 ps
CPU time 5.55 seconds
Started Sep 11 02:43:00 AM UTC 24
Finished Sep 11 02:43:07 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639644534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.1639644534
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/6.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_error_random.4150918265
Short name T153
Test name
Test status
Simulation time 177339893 ps
CPU time 3.41 seconds
Started Sep 11 02:42:55 AM UTC 24
Finished Sep 11 02:43:00 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150918265 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.4150918265
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/6.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random.1944341400
Short name T154
Test name
Test status
Simulation time 106089524 ps
CPU time 10.16 seconds
Started Sep 11 02:42:49 AM UTC 24
Finished Sep 11 02:43:01 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944341400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.1944341400
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/6.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_large_delays.4257430388
Short name T341
Test name
Test status
Simulation time 67229982356 ps
CPU time 76.44 seconds
Started Sep 11 02:42:52 AM UTC 24
Finished Sep 11 02:44:11 AM UTC 24
Peak memory 212248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257430388 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.4257430388
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/6.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_slow_rsp.3977364644
Short name T388
Test name
Test status
Simulation time 20265040248 ps
CPU time 167.47 seconds
Started Sep 11 02:42:52 AM UTC 24
Finished Sep 11 02:45:43 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977364644 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3977364644
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/6.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_zero_delays.2724790355
Short name T151
Test name
Test status
Simulation time 20014654 ps
CPU time 2.15 seconds
Started Sep 11 02:42:51 AM UTC 24
Finished Sep 11 02:42:54 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724790355 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.2724790355
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/6.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_same_source.4152677806
Short name T157
Test name
Test status
Simulation time 100908081 ps
CPU time 4.83 seconds
Started Sep 11 02:42:55 AM UTC 24
Finished Sep 11 02:43:01 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152677806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.4152677806
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/6.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke.2627976096
Short name T69
Test name
Test status
Simulation time 54085245 ps
CPU time 2.5 seconds
Started Sep 11 02:42:49 AM UTC 24
Finished Sep 11 02:42:53 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627976096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2627976096
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/6.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_large_delays.2990087663
Short name T156
Test name
Test status
Simulation time 2148929282 ps
CPU time 10.82 seconds
Started Sep 11 02:42:49 AM UTC 24
Finished Sep 11 02:43:01 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990087663 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.2990087663
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/6.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.3396016117
Short name T152
Test name
Test status
Simulation time 576695150 ps
CPU time 6.94 seconds
Started Sep 11 02:42:49 AM UTC 24
Finished Sep 11 02:42:57 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396016117 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3396016117
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/6.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.256690024
Short name T291
Test name
Test status
Simulation time 20013226 ps
CPU time 1.85 seconds
Started Sep 11 02:42:49 AM UTC 24
Finished Sep 11 02:42:52 AM UTC 24
Peak memory 211120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256690024 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.256690024
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/6.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all.971598468
Short name T263
Test name
Test status
Simulation time 5222481484 ps
CPU time 51.11 seconds
Started Sep 11 02:43:02 AM UTC 24
Finished Sep 11 02:43:54 AM UTC 24
Peak memory 216284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971598468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.971598468
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/6.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_error.2074076033
Short name T302
Test name
Test status
Simulation time 1344237277 ps
CPU time 19.58 seconds
Started Sep 11 02:43:02 AM UTC 24
Finished Sep 11 02:43:23 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074076033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.2074076033
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/6.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.1348746674
Short name T83
Test name
Test status
Simulation time 133683757 ps
CPU time 18.57 seconds
Started Sep 11 02:43:02 AM UTC 24
Finished Sep 11 02:43:22 AM UTC 24
Peak memory 214172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348746674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.1348746674
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/6.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.2936854565
Short name T101
Test name
Test status
Simulation time 1343458824 ps
CPU time 75.96 seconds
Started Sep 11 02:43:02 AM UTC 24
Finished Sep 11 02:44:20 AM UTC 24
Peak memory 216420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936854565 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.2936854565
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/6.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_unmapped_addr.3018757802
Short name T74
Test name
Test status
Simulation time 71215620 ps
CPU time 6.06 seconds
Started Sep 11 02:42:58 AM UTC 24
Finished Sep 11 02:43:06 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018757802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3018757802
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/6.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device.2854339337
Short name T79
Test name
Test status
Simulation time 56313932 ps
CPU time 2.58 seconds
Started Sep 11 02:43:07 AM UTC 24
Finished Sep 11 02:43:10 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854339337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.2854339337
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/7.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.859033502
Short name T301
Test name
Test status
Simulation time 56468224 ps
CPU time 5.86 seconds
Started Sep 11 02:43:15 AM UTC 24
Finished Sep 11 02:43:22 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859033502 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.859033502
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/7.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_error_random.4257971861
Short name T295
Test name
Test status
Simulation time 304783481 ps
CPU time 4.54 seconds
Started Sep 11 02:43:12 AM UTC 24
Finished Sep 11 02:43:18 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257971861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.4257971861
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/7.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random.4206799312
Short name T293
Test name
Test status
Simulation time 147661794 ps
CPU time 6.67 seconds
Started Sep 11 02:43:07 AM UTC 24
Finished Sep 11 02:43:14 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206799312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.4206799312
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/7.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_large_delays.345919724
Short name T323
Test name
Test status
Simulation time 13820658829 ps
CPU time 40.31 seconds
Started Sep 11 02:43:07 AM UTC 24
Finished Sep 11 02:43:48 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345919724 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.345919724
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/7.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_slow_rsp.2938580721
Short name T333
Test name
Test status
Simulation time 6837840659 ps
CPU time 51.72 seconds
Started Sep 11 02:43:07 AM UTC 24
Finished Sep 11 02:44:00 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938580721 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.2938580721
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/7.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_zero_delays.1744782799
Short name T80
Test name
Test status
Simulation time 33680156 ps
CPU time 3.79 seconds
Started Sep 11 02:43:07 AM UTC 24
Finished Sep 11 02:43:12 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744782799 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.1744782799
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/7.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_same_source.2506945145
Short name T296
Test name
Test status
Simulation time 51183926 ps
CPU time 6.62 seconds
Started Sep 11 02:43:11 AM UTC 24
Finished Sep 11 02:43:19 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506945145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2506945145
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/7.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke.4109980499
Short name T75
Test name
Test status
Simulation time 9593578 ps
CPU time 1.53 seconds
Started Sep 11 02:43:03 AM UTC 24
Finished Sep 11 02:43:06 AM UTC 24
Peak memory 211236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109980499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.4109980499
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/7.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_large_delays.359245988
Short name T307
Test name
Test status
Simulation time 3990630449 ps
CPU time 22.23 seconds
Started Sep 11 02:43:05 AM UTC 24
Finished Sep 11 02:43:29 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359245988 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.359245988
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/7.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.2812709480
Short name T294
Test name
Test status
Simulation time 923021210 ps
CPU time 8.34 seconds
Started Sep 11 02:43:07 AM UTC 24
Finished Sep 11 02:43:16 AM UTC 24
Peak memory 212320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812709480 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.2812709480
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/7.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.514047603
Short name T76
Test name
Test status
Simulation time 17110897 ps
CPU time 1.64 seconds
Started Sep 11 02:43:03 AM UTC 24
Finished Sep 11 02:43:06 AM UTC 24
Peak memory 211224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514047603 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.514047603
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/7.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all.1655435097
Short name T325
Test name
Test status
Simulation time 735960815 ps
CPU time 34.93 seconds
Started Sep 11 02:43:15 AM UTC 24
Finished Sep 11 02:43:51 AM UTC 24
Peak memory 212320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655435097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1655435097
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/7.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_error.2874102447
Short name T100
Test name
Test status
Simulation time 7141851237 ps
CPU time 60.36 seconds
Started Sep 11 02:43:18 AM UTC 24
Finished Sep 11 02:44:20 AM UTC 24
Peak memory 216280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874102447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2874102447
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/7.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.286895638
Short name T125
Test name
Test status
Simulation time 6454853425 ps
CPU time 152.25 seconds
Started Sep 11 02:43:18 AM UTC 24
Finished Sep 11 02:45:52 AM UTC 24
Peak memory 218332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286895638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.286895638
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/7.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.2315477572
Short name T282
Test name
Test status
Simulation time 167074223 ps
CPU time 31.43 seconds
Started Sep 11 02:43:18 AM UTC 24
Finished Sep 11 02:43:50 AM UTC 24
Peak memory 214176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315477572 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.2315477572
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/7.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_unmapped_addr.1520896052
Short name T300
Test name
Test status
Simulation time 44292793 ps
CPU time 5.52 seconds
Started Sep 11 02:43:15 AM UTC 24
Finished Sep 11 02:43:22 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520896052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1520896052
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/7.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device.152647719
Short name T315
Test name
Test status
Simulation time 55966421 ps
CPU time 16.51 seconds
Started Sep 11 02:43:23 AM UTC 24
Finished Sep 11 02:43:40 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152647719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.152647719
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/8.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.557082919
Short name T129
Test name
Test status
Simulation time 126754568829 ps
CPU time 248.28 seconds
Started Sep 11 02:43:23 AM UTC 24
Finished Sep 11 02:47:34 AM UTC 24
Peak memory 214232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557082919 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.557082919
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/8.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.1465279309
Short name T309
Test name
Test status
Simulation time 56895128 ps
CPU time 2.1 seconds
Started Sep 11 02:43:28 AM UTC 24
Finished Sep 11 02:43:31 AM UTC 24
Peak memory 212320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465279309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.1465279309
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/8.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_error_random.923624041
Short name T310
Test name
Test status
Simulation time 483842992 ps
CPU time 6.51 seconds
Started Sep 11 02:43:24 AM UTC 24
Finished Sep 11 02:43:32 AM UTC 24
Peak memory 212320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923624041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.923624041
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/8.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random.859295278
Short name T311
Test name
Test status
Simulation time 432615163 ps
CPU time 11.38 seconds
Started Sep 11 02:43:21 AM UTC 24
Finished Sep 11 02:43:34 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859295278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.859295278
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/8.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_large_delays.425444123
Short name T147
Test name
Test status
Simulation time 35635658436 ps
CPU time 162.19 seconds
Started Sep 11 02:43:22 AM UTC 24
Finished Sep 11 02:46:07 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425444123 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.425444123
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/8.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_slow_rsp.1181521727
Short name T407
Test name
Test status
Simulation time 19997529711 ps
CPU time 160.64 seconds
Started Sep 11 02:43:23 AM UTC 24
Finished Sep 11 02:46:06 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181521727 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1181521727
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/8.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_zero_delays.1205028900
Short name T304
Test name
Test status
Simulation time 175146584 ps
CPU time 4.04 seconds
Started Sep 11 02:43:22 AM UTC 24
Finished Sep 11 02:43:27 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205028900 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.1205028900
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/8.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_same_source.1436045783
Short name T306
Test name
Test status
Simulation time 38912815 ps
CPU time 3.9 seconds
Started Sep 11 02:43:24 AM UTC 24
Finished Sep 11 02:43:29 AM UTC 24
Peak memory 212112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436045783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.1436045783
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/8.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke.1063715408
Short name T186
Test name
Test status
Simulation time 45601706 ps
CPU time 1.68 seconds
Started Sep 11 02:43:18 AM UTC 24
Finished Sep 11 02:43:20 AM UTC 24
Peak memory 211228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063715408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1063715408
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/8.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_large_delays.1574137060
Short name T217
Test name
Test status
Simulation time 1040369254 ps
CPU time 8.62 seconds
Started Sep 11 02:43:20 AM UTC 24
Finished Sep 11 02:43:30 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574137060 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.1574137060
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/8.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.746634133
Short name T308
Test name
Test status
Simulation time 1088865769 ps
CPU time 9.17 seconds
Started Sep 11 02:43:20 AM UTC 24
Finished Sep 11 02:43:30 AM UTC 24
Peak memory 212308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746634133 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.746634133
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/8.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.1745414957
Short name T299
Test name
Test status
Simulation time 13124995 ps
CPU time 1.67 seconds
Started Sep 11 02:43:19 AM UTC 24
Finished Sep 11 02:43:22 AM UTC 24
Peak memory 211228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745414957 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.1745414957
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/8.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all.2211604538
Short name T317
Test name
Test status
Simulation time 97426484 ps
CPU time 11.81 seconds
Started Sep 11 02:43:29 AM UTC 24
Finished Sep 11 02:43:42 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211604538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.2211604538
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/8.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_error.3977993454
Short name T171
Test name
Test status
Simulation time 3072335919 ps
CPU time 64.74 seconds
Started Sep 11 02:43:29 AM UTC 24
Finished Sep 11 02:44:36 AM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977993454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.3977993454
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/8.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.3166863142
Short name T283
Test name
Test status
Simulation time 152701129 ps
CPU time 18.86 seconds
Started Sep 11 02:43:31 AM UTC 24
Finished Sep 11 02:43:51 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166863142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.3166863142
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/8.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_unmapped_addr.2873164932
Short name T314
Test name
Test status
Simulation time 2784543725 ps
CPU time 9.99 seconds
Started Sep 11 02:43:27 AM UTC 24
Finished Sep 11 02:43:38 AM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873164932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2873164932
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/8.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device.3237819595
Short name T245
Test name
Test status
Simulation time 1924056732 ps
CPU time 8.32 seconds
Started Sep 11 02:43:36 AM UTC 24
Finished Sep 11 02:43:46 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237819595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.3237819595
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/9.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.160842491
Short name T248
Test name
Test status
Simulation time 152205350264 ps
CPU time 239.49 seconds
Started Sep 11 02:43:39 AM UTC 24
Finished Sep 11 02:47:42 AM UTC 24
Peak memory 214424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160842491 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.160842491
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/9.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.3312434285
Short name T334
Test name
Test status
Simulation time 874332670 ps
CPU time 16.16 seconds
Started Sep 11 02:43:44 AM UTC 24
Finished Sep 11 02:44:01 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312434285 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.3312434285
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/9.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_error_random.632722627
Short name T327
Test name
Test status
Simulation time 1638864478 ps
CPU time 13.78 seconds
Started Sep 11 02:43:41 AM UTC 24
Finished Sep 11 02:43:56 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632722627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.632722627
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/9.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random.1040810359
Short name T318
Test name
Test status
Simulation time 269937086 ps
CPU time 8.38 seconds
Started Sep 11 02:43:34 AM UTC 24
Finished Sep 11 02:43:43 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040810359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.1040810359
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/9.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_large_delays.1383467006
Short name T372
Test name
Test status
Simulation time 43172621571 ps
CPU time 86.95 seconds
Started Sep 11 02:43:35 AM UTC 24
Finished Sep 11 02:45:04 AM UTC 24
Peak memory 212372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383467006 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1383467006
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/9.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_slow_rsp.2468101447
Short name T369
Test name
Test status
Simulation time 12700259170 ps
CPU time 85.62 seconds
Started Sep 11 02:43:35 AM UTC 24
Finished Sep 11 02:45:03 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468101447 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2468101447
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/9.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_zero_delays.1158741896
Short name T316
Test name
Test status
Simulation time 24463764 ps
CPU time 4.78 seconds
Started Sep 11 02:43:35 AM UTC 24
Finished Sep 11 02:43:41 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158741896 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.1158741896
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/9.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_same_source.2985774738
Short name T319
Test name
Test status
Simulation time 30666625 ps
CPU time 3.56 seconds
Started Sep 11 02:43:39 AM UTC 24
Finished Sep 11 02:43:44 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985774738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.2985774738
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/9.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke.2755565194
Short name T313
Test name
Test status
Simulation time 40979972 ps
CPU time 1.91 seconds
Started Sep 11 02:43:31 AM UTC 24
Finished Sep 11 02:43:34 AM UTC 24
Peak memory 211128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755565194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2755565194
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/9.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_large_delays.2099122075
Short name T321
Test name
Test status
Simulation time 8226233008 ps
CPU time 12.24 seconds
Started Sep 11 02:43:32 AM UTC 24
Finished Sep 11 02:43:46 AM UTC 24
Peak memory 212512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099122075 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.2099122075
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/9.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.649570500
Short name T320
Test name
Test status
Simulation time 1799542646 ps
CPU time 10.37 seconds
Started Sep 11 02:43:32 AM UTC 24
Finished Sep 11 02:43:44 AM UTC 24
Peak memory 212372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649570500 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.649570500
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/9.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.966908914
Short name T312
Test name
Test status
Simulation time 14014749 ps
CPU time 1.6 seconds
Started Sep 11 02:43:31 AM UTC 24
Finished Sep 11 02:43:34 AM UTC 24
Peak memory 211228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966908914 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.966908914
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/9.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all.3427927164
Short name T336
Test name
Test status
Simulation time 1125269159 ps
CPU time 18.7 seconds
Started Sep 11 02:43:44 AM UTC 24
Finished Sep 11 02:44:04 AM UTC 24
Peak memory 212056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427927164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3427927164
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/9.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_error.144705201
Short name T329
Test name
Test status
Simulation time 1323656357 ps
CPU time 12.63 seconds
Started Sep 11 02:43:44 AM UTC 24
Finished Sep 11 02:43:58 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144705201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.144705201
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/9.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.1280501299
Short name T93
Test name
Test status
Simulation time 285439074 ps
CPU time 29.18 seconds
Started Sep 11 02:43:44 AM UTC 24
Finished Sep 11 02:44:14 AM UTC 24
Peak memory 214420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280501299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.1280501299
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/9.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.1940683405
Short name T174
Test name
Test status
Simulation time 2197495732 ps
CPU time 52.17 seconds
Started Sep 11 02:43:45 AM UTC 24
Finished Sep 11 02:44:39 AM UTC 24
Peak memory 216484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940683405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.1940683405
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/9.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_unmapped_addr.1260034739
Short name T328
Test name
Test status
Simulation time 940146055 ps
CPU time 13.83 seconds
Started Sep 11 02:43:41 AM UTC 24
Finished Sep 11 02:43:56 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260034739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.1260034739
Directory /workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/9.xbar_unmapped_addr/latest
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