Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	435	1			T26	1		T38	2		T68	1
all_values[1]	435	1			T40	1		T83	3		T48	1
all_values[2]	457	1			T68	1		T83	4		T135	1
all_values[3]	448	1			T17	2		T40	1		T44	1
all_values[4]	442	1			T17	1		T26	1		T40	2
all_values[5]	429	1			T17	2		T68	1		T83	4
all_values[6]	433	1			T15	1		T38	2		T40	2
all_values[7]	438	1			T15	1		T26	1		T38	2
all_values[8]	437	1			T15	2		T17	1		T26	1
all_values[9]	450	1			T15	1		T17	3		T68	1
all_values[10]	467	1			T15	1		T17	1		T40	1
all_values[11]	397	1			T17	1		T68	1		T83	5
all_values[12]	449	1			T15	2		T17	1		T83	3
all_values[13]	433	1			T15	1		T17	2		T40	1
all_values[14]	452	1			T15	1		T17	2		T26	1
all_values[15]	438	1			T17	2		T38	1		T40	1
all_values[16]	478	1			T15	1		T17	1		T38	2
all_values[17]	454	1			T15	1		T17	1		T26	1
all_values[18]	444	1			T15	1		T17	1		T26	1
all_values[19]	441	1			T15	2		T17	2		T26	1
all_values[20]	439	1			T40	1		T68	2		T83	5
all_values[21]	454	1			T17	3		T40	3		T68	1
all_values[22]	431	1			T15	2		T17	1		T38	1
all_values[23]	415	1			T26	1		T38	1		T40	1
all_values[24]	446	1			T17	2		T40	2		T68	1
all_values[25]	466	1			T17	2		T40	3		T44	1
all_values[26]	430	1			T15	1		T17	4		T68	1