Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	501	1			T20	1		T43	1		T44	3
all_values[1]	548	1			T43	1		T44	3		T39	6
all_values[2]	528	1			T25	1		T43	1		T44	3
all_values[3]	541	1			T44	4		T39	3		T5	14
all_values[4]	531	1			T20	1		T44	2		T39	12
all_values[5]	535	1			T20	1		T44	4		T39	3
all_values[6]	525	1			T44	3		T39	4		T5	4
all_values[7]	536	1			T20	1		T44	4		T39	6
all_values[8]	513	1			T44	1		T39	4		T47	2
all_values[9]	559	1			T25	1		T43	1		T44	1
all_values[10]	549	1			T25	1		T44	4		T39	7
all_values[11]	557	1			T43	1		T44	2		T39	3
all_values[12]	514	1			T25	1		T44	5		T39	3
all_values[13]	554	1			T25	1		T43	1		T44	2
all_values[14]	528	1			T39	6		T47	1		T5	7
all_values[15]	476	1			T44	3		T39	8		T5	3
all_values[16]	554	1			T20	1		T44	2		T39	7
all_values[17]	537	1			T25	1		T20	1		T44	2
all_values[18]	491	1			T25	1		T44	1		T39	6
all_values[19]	519	1			T25	1		T29	1		T44	1
all_values[20]	506	1			T29	1		T43	1		T44	6
all_values[21]	561	1			T44	3		T39	7		T71	1
all_values[22]	479	1			T44	3		T39	7		T71	1
all_values[23]	564	1			T25	1		T44	2		T39	10
all_values[24]	564	1			T56	1		T39	5		T46	1
all_values[25]	525	1			T43	1		T44	3		T39	3
all_values[26]	527	1			T29	1		T43	1		T44	4