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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.27 100.00 95.61 100.00 100.00 100.00 100.00


Total test records in report: 900
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T769 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.2436645517 Sep 24 04:58:04 PM UTC 24 Sep 24 04:58:46 PM UTC 24 1773648416 ps
T770 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.3158346043 Sep 24 04:58:34 PM UTC 24 Sep 24 04:58:46 PM UTC 24 11565572929 ps
T771 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.3453644218 Sep 24 04:58:37 PM UTC 24 Sep 24 04:58:46 PM UTC 24 209299919 ps
T772 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.3848246448 Sep 24 04:57:03 PM UTC 24 Sep 24 04:58:47 PM UTC 24 20571810729 ps
T773 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.2041188040 Sep 24 04:58:37 PM UTC 24 Sep 24 04:58:48 PM UTC 24 65302436 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.47069371 Sep 24 04:54:16 PM UTC 24 Sep 24 04:58:50 PM UTC 24 114240845016 ps
T774 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.1537063724 Sep 24 04:58:34 PM UTC 24 Sep 24 04:58:50 PM UTC 24 1784676540 ps
T775 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3868304626 Sep 24 04:58:30 PM UTC 24 Sep 24 04:58:51 PM UTC 24 1706130848 ps
T776 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.228244903 Sep 24 04:58:49 PM UTC 24 Sep 24 04:58:52 PM UTC 24 8758939 ps
T777 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.2963068786 Sep 24 04:58:49 PM UTC 24 Sep 24 04:58:52 PM UTC 24 8350196 ps
T778 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.2804651714 Sep 24 04:58:37 PM UTC 24 Sep 24 04:58:52 PM UTC 24 627876491 ps
T779 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.2392696073 Sep 24 04:58:48 PM UTC 24 Sep 24 04:58:55 PM UTC 24 64831064 ps
T780 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random.2396838339 Sep 24 04:58:51 PM UTC 24 Sep 24 04:58:56 PM UTC 24 65952269 ps
T781 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.2659800970 Sep 24 04:58:52 PM UTC 24 Sep 24 04:58:56 PM UTC 24 65709908 ps
T782 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.2755376247 Sep 24 04:58:52 PM UTC 24 Sep 24 04:58:57 PM UTC 24 26938999 ps
T783 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.31236237 Sep 24 04:56:47 PM UTC 24 Sep 24 04:58:58 PM UTC 24 23708245451 ps
T784 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.3418576516 Sep 24 04:58:25 PM UTC 24 Sep 24 04:59:02 PM UTC 24 293184721 ps
T785 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.446096719 Sep 24 04:57:20 PM UTC 24 Sep 24 04:59:02 PM UTC 24 12210183224 ps
T786 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.3089957562 Sep 24 04:55:01 PM UTC 24 Sep 24 04:59:02 PM UTC 24 52494953878 ps
T787 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.1016429090 Sep 24 04:59:00 PM UTC 24 Sep 24 04:59:03 PM UTC 24 8269250 ps
T788 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.4008257914 Sep 24 04:58:56 PM UTC 24 Sep 24 04:59:05 PM UTC 24 269283321 ps
T789 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.1800344953 Sep 24 04:58:56 PM UTC 24 Sep 24 04:59:05 PM UTC 24 813689123 ps
T790 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.397875297 Sep 24 04:58:49 PM UTC 24 Sep 24 04:59:06 PM UTC 24 621957149 ps
T791 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.1554885543 Sep 24 04:58:49 PM UTC 24 Sep 24 04:59:06 PM UTC 24 1333146641 ps
T792 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.3309865642 Sep 24 04:58:56 PM UTC 24 Sep 24 04:59:06 PM UTC 24 2589339421 ps
T793 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.116043385 Sep 24 04:58:56 PM UTC 24 Sep 24 04:59:07 PM UTC 24 375393313 ps
T794 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.837714465 Sep 24 04:57:23 PM UTC 24 Sep 24 04:59:07 PM UTC 24 17906757964 ps
T795 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.3402169888 Sep 24 04:59:05 PM UTC 24 Sep 24 04:59:08 PM UTC 24 20556344 ps
T796 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.226888411 Sep 24 04:58:49 PM UTC 24 Sep 24 04:59:10 PM UTC 24 13893436612 ps
T797 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.1547282717 Sep 24 04:57:50 PM UTC 24 Sep 24 04:59:11 PM UTC 24 913275363 ps
T798 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.3814052886 Sep 24 04:58:59 PM UTC 24 Sep 24 04:59:13 PM UTC 24 980960122 ps
T799 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random.3271526706 Sep 24 04:59:06 PM UTC 24 Sep 24 04:59:14 PM UTC 24 425822712 ps
T800 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.1966921238 Sep 24 04:59:13 PM UTC 24 Sep 24 04:59:16 PM UTC 24 8751072 ps
T801 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.2054436008 Sep 24 04:59:06 PM UTC 24 Sep 24 04:59:18 PM UTC 24 1145985304 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.2190344752 Sep 24 04:58:37 PM UTC 24 Sep 24 04:59:21 PM UTC 24 13136688729 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3002094673 Sep 24 04:57:59 PM UTC 24 Sep 24 04:59:21 PM UTC 24 49905577943 ps
T802 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.3200337540 Sep 24 04:59:14 PM UTC 24 Sep 24 04:59:23 PM UTC 24 812307917 ps
T803 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.3339821822 Sep 24 04:59:19 PM UTC 24 Sep 24 04:59:24 PM UTC 24 145502521 ps
T804 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.3973924599 Sep 24 04:59:21 PM UTC 24 Sep 24 04:59:24 PM UTC 24 203199670 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.4233709484 Sep 24 04:58:07 PM UTC 24 Sep 24 04:59:24 PM UTC 24 471934217 ps
T805 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.3877485073 Sep 24 04:59:19 PM UTC 24 Sep 24 04:59:25 PM UTC 24 655642661 ps
T806 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1706229320 Sep 24 04:59:23 PM UTC 24 Sep 24 04:59:26 PM UTC 24 9400464 ps
T807 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.4195409667 Sep 24 04:59:13 PM UTC 24 Sep 24 04:59:26 PM UTC 24 693234517 ps
T808 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.2347198783 Sep 24 04:59:13 PM UTC 24 Sep 24 04:59:26 PM UTC 24 328532332 ps
T809 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.666985377 Sep 24 04:59:06 PM UTC 24 Sep 24 04:59:27 PM UTC 24 4661479585 ps
T810 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.4024953680 Sep 24 04:58:06 PM UTC 24 Sep 24 04:59:27 PM UTC 24 776288400 ps
T811 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.485659754 Sep 24 04:58:06 PM UTC 24 Sep 24 04:59:28 PM UTC 24 3618369527 ps
T812 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.10203073 Sep 24 04:58:48 PM UTC 24 Sep 24 04:59:30 PM UTC 24 2645695046 ps
T813 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.2691122825 Sep 24 04:59:26 PM UTC 24 Sep 24 04:59:30 PM UTC 24 15849371 ps
T814 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random.1756963332 Sep 24 04:59:26 PM UTC 24 Sep 24 04:59:31 PM UTC 24 37640634 ps
T815 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.2495292508 Sep 24 04:59:13 PM UTC 24 Sep 24 04:59:32 PM UTC 24 2189397419 ps
T816 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.728662892 Sep 24 04:59:26 PM UTC 24 Sep 24 04:59:34 PM UTC 24 5018131411 ps
T817 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.2395286494 Sep 24 04:58:49 PM UTC 24 Sep 24 04:59:35 PM UTC 24 935396944 ps
T818 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.4144565753 Sep 24 04:59:30 PM UTC 24 Sep 24 04:59:35 PM UTC 24 81553990 ps
T819 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.3430087986 Sep 24 04:57:47 PM UTC 24 Sep 24 04:59:35 PM UTC 24 8373034756 ps
T820 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1800083833 Sep 24 04:59:23 PM UTC 24 Sep 24 04:59:36 PM UTC 24 2414644449 ps
T821 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.321453492 Sep 24 04:58:49 PM UTC 24 Sep 24 04:59:38 PM UTC 24 505146399 ps
T822 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.4051430029 Sep 24 04:56:43 PM UTC 24 Sep 24 04:59:39 PM UTC 24 23332624682 ps
T823 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.2778430210 Sep 24 04:59:19 PM UTC 24 Sep 24 04:59:40 PM UTC 24 1316953126 ps
T824 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3186534426 Sep 24 04:58:52 PM UTC 24 Sep 24 04:59:40 PM UTC 24 25942291605 ps
T825 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.217967869 Sep 24 04:59:35 PM UTC 24 Sep 24 04:59:40 PM UTC 24 64909093 ps
T826 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.4075580118 Sep 24 04:59:30 PM UTC 24 Sep 24 04:59:41 PM UTC 24 1441214818 ps
T827 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.2897468732 Sep 24 04:59:38 PM UTC 24 Sep 24 04:59:41 PM UTC 24 18154227 ps
T828 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.2806320740 Sep 24 04:59:38 PM UTC 24 Sep 24 04:59:41 PM UTC 24 9097728 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1451422481 Sep 24 04:53:50 PM UTC 24 Sep 24 04:59:43 PM UTC 24 68379815720 ps
T829 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.3233948407 Sep 24 04:59:35 PM UTC 24 Sep 24 04:59:44 PM UTC 24 113808923 ps
T830 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.1105948861 Sep 24 04:59:19 PM UTC 24 Sep 24 04:59:45 PM UTC 24 1758577742 ps
T831 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.3703639886 Sep 24 04:57:59 PM UTC 24 Sep 24 04:59:46 PM UTC 24 67584476714 ps
T832 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3765750257 Sep 24 04:59:38 PM UTC 24 Sep 24 04:59:48 PM UTC 24 1582807675 ps
T833 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.3236893972 Sep 24 04:59:38 PM UTC 24 Sep 24 04:59:48 PM UTC 24 1925556749 ps
T834 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.2156857510 Sep 24 04:59:30 PM UTC 24 Sep 24 04:59:49 PM UTC 24 3341915081 ps
T835 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.3419773045 Sep 24 04:59:30 PM UTC 24 Sep 24 04:59:49 PM UTC 24 1720118223 ps
T836 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.3759728530 Sep 24 04:59:45 PM UTC 24 Sep 24 04:59:50 PM UTC 24 31065332 ps
T837 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.880839798 Sep 24 04:59:35 PM UTC 24 Sep 24 04:59:50 PM UTC 24 1240523868 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.938694784 Sep 24 04:56:28 PM UTC 24 Sep 24 04:59:51 PM UTC 24 28029088553 ps
T838 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.189681037 Sep 24 04:59:45 PM UTC 24 Sep 24 04:59:52 PM UTC 24 41499099 ps
T839 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.2000993647 Sep 24 04:59:45 PM UTC 24 Sep 24 04:59:52 PM UTC 24 539489138 ps
T840 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random.2557217373 Sep 24 04:59:39 PM UTC 24 Sep 24 04:59:54 PM UTC 24 741229473 ps
T841 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.1591194174 Sep 24 04:59:55 PM UTC 24 Sep 24 04:59:58 PM UTC 24 10093779 ps
T842 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.1169841660 Sep 24 04:59:45 PM UTC 24 Sep 24 04:59:58 PM UTC 24 931979710 ps
T843 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.1260489761 Sep 24 04:59:55 PM UTC 24 Sep 24 04:59:58 PM UTC 24 43433293 ps
T844 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.1485508826 Sep 24 04:59:55 PM UTC 24 Sep 24 04:59:58 PM UTC 24 36047936 ps
T845 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3424470026 Sep 24 04:59:49 PM UTC 24 Sep 24 04:59:59 PM UTC 24 345783454 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.316271436 Sep 24 04:57:33 PM UTC 24 Sep 24 05:00:00 PM UTC 24 1388665296 ps
T846 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.637079990 Sep 24 04:59:55 PM UTC 24 Sep 24 05:00:02 PM UTC 24 2578504482 ps
T847 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.2642326975 Sep 24 04:59:19 PM UTC 24 Sep 24 05:00:04 PM UTC 24 385747446 ps
T848 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random.1419638312 Sep 24 04:59:55 PM UTC 24 Sep 24 05:00:05 PM UTC 24 445706747 ps
T849 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.3883256763 Sep 24 04:58:59 PM UTC 24 Sep 24 05:00:07 PM UTC 24 714218525 ps
T850 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2853503545 Sep 24 04:58:59 PM UTC 24 Sep 24 05:00:08 PM UTC 24 4208739946 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.4116787153 Sep 24 04:59:45 PM UTC 24 Sep 24 05:00:10 PM UTC 24 1516983335 ps
T851 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.361551791 Sep 24 04:59:49 PM UTC 24 Sep 24 05:00:11 PM UTC 24 192969324 ps
T852 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.3611727877 Sep 24 04:59:49 PM UTC 24 Sep 24 05:00:11 PM UTC 24 204568104 ps
T853 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.1945328527 Sep 24 04:58:30 PM UTC 24 Sep 24 05:00:12 PM UTC 24 673524143 ps
T854 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.1305381949 Sep 24 05:00:10 PM UTC 24 Sep 24 05:00:14 PM UTC 24 19590788 ps
T855 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.2754475415 Sep 24 05:00:04 PM UTC 24 Sep 24 05:00:14 PM UTC 24 76377069 ps
T856 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.1449470007 Sep 24 04:58:59 PM UTC 24 Sep 24 05:00:14 PM UTC 24 3007799799 ps
T857 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.3718721167 Sep 24 04:59:55 PM UTC 24 Sep 24 05:00:15 PM UTC 24 4384696595 ps
T858 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.72919919 Sep 24 05:00:04 PM UTC 24 Sep 24 05:00:15 PM UTC 24 1432767177 ps
T859 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.4102675880 Sep 24 04:59:35 PM UTC 24 Sep 24 05:00:15 PM UTC 24 259890475 ps
T860 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.985706952 Sep 24 05:00:13 PM UTC 24 Sep 24 05:00:16 PM UTC 24 15606330 ps
T861 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.1964851285 Sep 24 05:00:04 PM UTC 24 Sep 24 05:00:17 PM UTC 24 86866523 ps
T862 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.2407340064 Sep 24 04:59:58 PM UTC 24 Sep 24 05:00:20 PM UTC 24 2311345980 ps
T863 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.555814289 Sep 24 05:00:13 PM UTC 24 Sep 24 05:00:23 PM UTC 24 1623772528 ps
T864 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.2183017576 Sep 24 05:00:17 PM UTC 24 Sep 24 05:00:23 PM UTC 24 25300231 ps
T865 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.3570994260 Sep 24 05:00:20 PM UTC 24 Sep 24 05:00:23 PM UTC 24 12684866 ps
T866 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.535900075 Sep 24 05:00:04 PM UTC 24 Sep 24 05:00:24 PM UTC 24 1492377139 ps
T867 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random.1250086125 Sep 24 05:00:13 PM UTC 24 Sep 24 05:00:27 PM UTC 24 68047620 ps
T868 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.1143740755 Sep 24 05:00:18 PM UTC 24 Sep 24 05:00:28 PM UTC 24 189295947 ps
T869 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.3077027763 Sep 24 05:00:18 PM UTC 24 Sep 24 05:00:28 PM UTC 24 714620076 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.3432933230 Sep 24 04:59:13 PM UTC 24 Sep 24 05:00:29 PM UTC 24 34579490074 ps
T870 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.1502625604 Sep 24 05:00:07 PM UTC 24 Sep 24 05:00:29 PM UTC 24 963581251 ps
T871 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.969820705 Sep 24 05:00:13 PM UTC 24 Sep 24 05:00:31 PM UTC 24 13761285699 ps
T872 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1147957500 Sep 24 05:00:20 PM UTC 24 Sep 24 05:00:32 PM UTC 24 754384407 ps
T873 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.540889135 Sep 24 04:59:35 PM UTC 24 Sep 24 05:00:35 PM UTC 24 1283350554 ps
T874 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.117791528 Sep 24 05:00:04 PM UTC 24 Sep 24 05:00:38 PM UTC 24 2819136164 ps
T875 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.913820045 Sep 24 04:58:52 PM UTC 24 Sep 24 05:00:39 PM UTC 24 13952945879 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.3826682804 Sep 24 05:00:17 PM UTC 24 Sep 24 05:00:40 PM UTC 24 1344398962 ps
T876 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2526762412 Sep 24 05:00:28 PM UTC 24 Sep 24 05:00:40 PM UTC 24 156155059 ps
T877 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.1674608057 Sep 24 04:59:35 PM UTC 24 Sep 24 05:00:41 PM UTC 24 6266349158 ps
T878 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.957898324 Sep 24 05:00:17 PM UTC 24 Sep 24 05:00:48 PM UTC 24 3935514702 ps
T879 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.1393547657 Sep 24 04:59:49 PM UTC 24 Sep 24 05:00:48 PM UTC 24 3805174699 ps
T880 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.212307918 Sep 24 04:58:37 PM UTC 24 Sep 24 05:00:52 PM UTC 24 25228334563 ps
T881 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.2191412580 Sep 24 04:59:45 PM UTC 24 Sep 24 05:00:57 PM UTC 24 13264546128 ps
T882 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.809245088 Sep 24 04:59:45 PM UTC 24 Sep 24 05:00:58 PM UTC 24 10343853229 ps
T883 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.528438788 Sep 24 05:00:28 PM UTC 24 Sep 24 05:01:03 PM UTC 24 349649966 ps
T884 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.2765986483 Sep 24 05:00:10 PM UTC 24 Sep 24 05:01:10 PM UTC 24 353221603 ps
T885 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.538052575 Sep 24 05:00:10 PM UTC 24 Sep 24 05:01:16 PM UTC 24 3574591349 ps
T886 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.2704718302 Sep 24 04:57:59 PM UTC 24 Sep 24 05:01:22 PM UTC 24 45567307911 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.3050742106 Sep 24 04:59:49 PM UTC 24 Sep 24 05:01:23 PM UTC 24 5132675078 ps
T887 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.1467921537 Sep 24 04:59:55 PM UTC 24 Sep 24 05:01:25 PM UTC 24 21526578942 ps
T888 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.747429307 Sep 24 04:55:48 PM UTC 24 Sep 24 05:01:25 PM UTC 24 74461694626 ps
T889 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.1378338219 Sep 24 04:57:39 PM UTC 24 Sep 24 05:01:27 PM UTC 24 48031926444 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.2488749567 Sep 24 04:58:52 PM UTC 24 Sep 24 05:01:28 PM UTC 24 28833642077 ps
T890 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.2608510641 Sep 24 05:00:23 PM UTC 24 Sep 24 05:01:29 PM UTC 24 3556829499 ps
T891 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.3304897203 Sep 24 04:58:19 PM UTC 24 Sep 24 05:01:29 PM UTC 24 47949992240 ps
T892 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.516378577 Sep 24 04:59:58 PM UTC 24 Sep 24 05:01:48 PM UTC 24 78466066295 ps
T893 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.2549175459 Sep 24 04:57:50 PM UTC 24 Sep 24 05:01:49 PM UTC 24 7693908259 ps
T894 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.2559359015 Sep 24 04:59:45 PM UTC 24 Sep 24 05:01:59 PM UTC 24 95543049010 ps
T895 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.2508839508 Sep 24 04:58:25 PM UTC 24 Sep 24 05:02:06 PM UTC 24 3223347710 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2872322316 Sep 24 04:59:13 PM UTC 24 Sep 24 05:02:15 PM UTC 24 30270974363 ps
T896 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3812858456 Sep 24 04:58:37 PM UTC 24 Sep 24 05:02:36 PM UTC 24 97907413186 ps
T897 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.340848839 Sep 24 05:00:17 PM UTC 24 Sep 24 05:02:45 PM UTC 24 44211325646 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.3211829755 Sep 24 04:59:30 PM UTC 24 Sep 24 05:02:53 PM UTC 24 98623986998 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1623596639 Sep 24 05:00:28 PM UTC 24 Sep 24 05:02:56 PM UTC 24 2388015551 ps
T898 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1175313378 Sep 24 04:59:19 PM UTC 24 Sep 24 05:03:06 PM UTC 24 1781892261 ps
T899 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3994456903 Sep 24 05:00:10 PM UTC 24 Sep 24 05:03:09 PM UTC 24 1029075323 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.2150875729 Sep 24 04:57:03 PM UTC 24 Sep 24 05:03:34 PM UTC 24 279072860270 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.174790079 Sep 24 04:58:19 PM UTC 24 Sep 24 05:03:45 PM UTC 24 39117810114 ps
T900 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1112598007 Sep 24 04:59:30 PM UTC 24 Sep 24 05:04:30 PM UTC 24 61150037947 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3502107673 Sep 24 05:00:17 PM UTC 24 Sep 24 05:05:45 PM UTC 24 138886995678 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_slow_rsp.4155221886
Short name T17
Test name
Test status
Simulation time 6086476896 ps
CPU time 23.63 seconds
Started Sep 24 04:34:54 PM UTC 24
Finished Sep 24 04:35:19 PM UTC 24
Peak memory 212244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155221886 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.4155221886
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/0.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.2239562019
Short name T161
Test name
Test status
Simulation time 35102493494 ps
CPU time 297.93 seconds
Started Sep 24 04:40:30 PM UTC 24
Finished Sep 24 04:45:32 PM UTC 24
Peak memory 214116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239562019 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.2239562019
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/3.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.1909115601
Short name T206
Test name
Test status
Simulation time 48376975959 ps
CPU time 405.65 seconds
Started Sep 24 04:42:37 PM UTC 24
Finished Sep 24 04:49:28 PM UTC 24
Peak memory 216168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909115601 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.1909115601
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/6.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.1643106512
Short name T210
Test name
Test status
Simulation time 230712549122 ps
CPU time 412.39 seconds
Started Sep 24 04:49:42 PM UTC 24
Finished Sep 24 04:56:39 PM UTC 24
Peak memory 214316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643106512 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.1643106512
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/19.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.2405640652
Short name T44
Test name
Test status
Simulation time 3768853426 ps
CPU time 84.14 seconds
Started Sep 24 04:36:22 PM UTC 24
Finished Sep 24 04:37:48 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405640652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.2405640652
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/0.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random.3471995821
Short name T16
Test name
Test status
Simulation time 37048736 ps
CPU time 3.01 seconds
Started Sep 24 04:34:46 PM UTC 24
Finished Sep 24 04:34:51 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471995821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3471995821
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/0.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.2931103208
Short name T73
Test name
Test status
Simulation time 8181123401 ps
CPU time 224.86 seconds
Started Sep 24 04:38:03 PM UTC 24
Finished Sep 24 04:41:51 PM UTC 24
Peak memory 216236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931103208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.2931103208
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/1.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.104679907
Short name T156
Test name
Test status
Simulation time 94552802804 ps
CPU time 240.97 seconds
Started Sep 24 04:50:07 PM UTC 24
Finished Sep 24 04:54:12 PM UTC 24
Peak memory 214116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104679907 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.104679907
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/20.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.1127405474
Short name T120
Test name
Test status
Simulation time 53110570645 ps
CPU time 209.31 seconds
Started Sep 24 04:52:27 PM UTC 24
Finished Sep 24 04:56:00 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127405474 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.1127405474
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/26.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.4141074338
Short name T113
Test name
Test status
Simulation time 10010752467 ps
CPU time 63.67 seconds
Started Sep 24 04:48:16 PM UTC 24
Finished Sep 24 04:49:21 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141074338 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.4141074338
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/16.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_large_delays.3441785795
Short name T32
Test name
Test status
Simulation time 2847244921 ps
CPU time 8.73 seconds
Started Sep 24 04:37:16 PM UTC 24
Finished Sep 24 04:37:26 PM UTC 24
Peak memory 212264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441785795 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3441785795
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/1.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.47069371
Short name T229
Test name
Test status
Simulation time 114240845016 ps
CPU time 270.13 seconds
Started Sep 24 04:54:16 PM UTC 24
Finished Sep 24 04:58:50 PM UTC 24
Peak memory 214312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47069371 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.47069371
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/30.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.2502685643
Short name T39
Test name
Test status
Simulation time 12699080098 ps
CPU time 142.08 seconds
Started Sep 24 04:36:02 PM UTC 24
Finished Sep 24 04:38:26 PM UTC 24
Peak memory 218216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502685643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.2502685643
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/0.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.1341671976
Short name T66
Test name
Test status
Simulation time 2299365867 ps
CPU time 40.78 seconds
Started Sep 24 04:40:46 PM UTC 24
Finished Sep 24 04:41:28 PM UTC 24
Peak memory 214312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341671976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.1341671976
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/3.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device.3305580549
Short name T6
Test name
Test status
Simulation time 8354801676 ps
CPU time 29.77 seconds
Started Sep 24 04:53:25 PM UTC 24
Finished Sep 24 04:53:56 PM UTC 24
Peak memory 212076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305580549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.3305580549
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/28.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.1681245060
Short name T10
Test name
Test status
Simulation time 3156346655 ps
CPU time 119.78 seconds
Started Sep 24 04:46:56 PM UTC 24
Finished Sep 24 04:48:58 PM UTC 24
Peak memory 216168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681245060 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.1681245060
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/13.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.3087851812
Short name T15
Test name
Test status
Simulation time 627234785 ps
CPU time 138.93 seconds
Started Sep 24 04:39:42 PM UTC 24
Finished Sep 24 04:42:04 PM UTC 24
Peak memory 214024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087851812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.3087851812
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/2.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.1787405406
Short name T7
Test name
Test status
Simulation time 700254837 ps
CPU time 97.67 seconds
Started Sep 24 04:46:19 PM UTC 24
Finished Sep 24 04:47:59 PM UTC 24
Peak memory 216104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787405406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.1787405406
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/12.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.316271436
Short name T12
Test name
Test status
Simulation time 1388665296 ps
CPU time 144.69 seconds
Started Sep 24 04:57:33 PM UTC 24
Finished Sep 24 05:00:00 PM UTC 24
Peak memory 218004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316271436 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.316271436
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/39.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device.3788461856
Short name T25
Test name
Test status
Simulation time 45437537 ps
CPU time 9.17 seconds
Started Sep 24 04:35:20 PM UTC 24
Finished Sep 24 04:35:30 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788461856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.3788461856
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/0.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.1335133769
Short name T116
Test name
Test status
Simulation time 44767772746 ps
CPU time 194.58 seconds
Started Sep 24 04:48:44 PM UTC 24
Finished Sep 24 04:52:02 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335133769 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.1335133769
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/17.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.1042402817
Short name T112
Test name
Test status
Simulation time 13217499461 ps
CPU time 212.27 seconds
Started Sep 24 04:43:42 PM UTC 24
Finished Sep 24 04:47:18 PM UTC 24
Peak memory 216168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042402817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.1042402817
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/7.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device.516361746
Short name T52
Test name
Test status
Simulation time 782921111 ps
CPU time 29.56 seconds
Started Sep 24 04:40:29 PM UTC 24
Finished Sep 24 04:41:00 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516361746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.516361746
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/3.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.4227952648
Short name T503
Test name
Test status
Simulation time 1794482565 ps
CPU time 129.32 seconds
Started Sep 24 04:50:45 PM UTC 24
Finished Sep 24 04:52:57 PM UTC 24
Peak memory 214060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227952648 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.4227952648
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/21.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.3428132038
Short name T128
Test name
Test status
Simulation time 16339280031 ps
CPU time 231.19 seconds
Started Sep 24 04:53:58 PM UTC 24
Finished Sep 24 04:57:52 PM UTC 24
Peak memory 216168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428132038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.3428132038
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/29.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.2147734056
Short name T196
Test name
Test status
Simulation time 29589843123 ps
CPU time 205.8 seconds
Started Sep 24 04:45:05 PM UTC 24
Finished Sep 24 04:48:34 PM UTC 24
Peak memory 214100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147734056 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.2147734056
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/10.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_slow_rsp.1867238839
Short name T65
Test name
Test status
Simulation time 41656266165 ps
CPU time 231.73 seconds
Started Sep 24 04:37:20 PM UTC 24
Finished Sep 24 04:41:15 PM UTC 24
Peak memory 212052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867238839 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.1867238839
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/1.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.1299899219
Short name T238
Test name
Test status
Simulation time 11218521260 ps
CPU time 257.84 seconds
Started Sep 24 04:45:19 PM UTC 24
Finished Sep 24 04:49:41 PM UTC 24
Peak memory 218220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299899219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.1299899219
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/10.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2461794336
Short name T29
Test name
Test status
Simulation time 32985689478 ps
CPU time 48.57 seconds
Started Sep 24 04:35:28 PM UTC 24
Finished Sep 24 04:36:18 PM UTC 24
Peak memory 212328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461794336 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.2461794336
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/0.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.2002666274
Short name T19
Test name
Test status
Simulation time 338067547 ps
CPU time 10.76 seconds
Started Sep 24 04:35:48 PM UTC 24
Finished Sep 24 04:36:00 PM UTC 24
Peak memory 212204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002666274 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.2002666274
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/0.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_error_random.1844933201
Short name T22
Test name
Test status
Simulation time 11979378 ps
CPU time 2.09 seconds
Started Sep 24 04:35:38 PM UTC 24
Finished Sep 24 04:35:41 PM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844933201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1844933201
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/0.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_large_delays.3313933339
Short name T24
Test name
Test status
Simulation time 9511577589 ps
CPU time 33.6 seconds
Started Sep 24 04:34:52 PM UTC 24
Finished Sep 24 04:35:27 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313933339 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3313933339
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/0.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_zero_delays.2667380951
Short name T23
Test name
Test status
Simulation time 45810807 ps
CPU time 2.06 seconds
Started Sep 24 04:34:50 PM UTC 24
Finished Sep 24 04:34:53 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667380951 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.2667380951
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/0.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_same_source.1554462027
Short name T21
Test name
Test status
Simulation time 49878698 ps
CPU time 5.3 seconds
Started Sep 24 04:35:31 PM UTC 24
Finished Sep 24 04:35:37 PM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554462027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.1554462027
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/0.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke.3651554678
Short name T1
Test name
Test status
Simulation time 47253679 ps
CPU time 2.26 seconds
Started Sep 24 04:34:16 PM UTC 24
Finished Sep 24 04:34:20 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651554678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.3651554678
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/0.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_large_delays.1550079403
Short name T4
Test name
Test status
Simulation time 5773857587 ps
CPU time 23.73 seconds
Started Sep 24 04:34:23 PM UTC 24
Finished Sep 24 04:34:49 PM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550079403 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.1550079403
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/0.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.2534830162
Short name T3
Test name
Test status
Simulation time 4140912753 ps
CPU time 12.71 seconds
Started Sep 24 04:34:31 PM UTC 24
Finished Sep 24 04:34:46 PM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534830162 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.2534830162
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/0.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.1731149018
Short name T2
Test name
Test status
Simulation time 11215198 ps
CPU time 1.18 seconds
Started Sep 24 04:34:20 PM UTC 24
Finished Sep 24 04:34:23 PM UTC 24
Peak memory 210936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731149018 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.1731149018
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/0.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all.731362535
Short name T20
Test name
Test status
Simulation time 4270017913 ps
CPU time 29.1 seconds
Started Sep 24 04:35:50 PM UTC 24
Finished Sep 24 04:36:21 PM UTC 24
Peak memory 214100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731362535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.731362535
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/0.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_error.181761336
Short name T40
Test name
Test status
Simulation time 4000973078 ps
CPU time 18.15 seconds
Started Sep 24 04:36:19 PM UTC 24
Finished Sep 24 04:36:38 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181761336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.181761336
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/0.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_unmapped_addr.3430230518
Short name T18
Test name
Test status
Simulation time 143773716 ps
CPU time 3.99 seconds
Started Sep 24 04:35:42 PM UTC 24
Finished Sep 24 04:35:47 PM UTC 24
Peak memory 212200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430230518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3430230518
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/0.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device.3338866233
Short name T43
Test name
Test status
Simulation time 58305273 ps
CPU time 9.31 seconds
Started Sep 24 04:37:26 PM UTC 24
Finished Sep 24 04:37:37 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338866233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.3338866233
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/1.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.2986258474
Short name T56
Test name
Test status
Simulation time 3377607818 ps
CPU time 24.07 seconds
Started Sep 24 04:37:37 PM UTC 24
Finished Sep 24 04:38:03 PM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986258474 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.2986258474
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/1.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.2538700027
Short name T55
Test name
Test status
Simulation time 84128628 ps
CPU time 3.6 seconds
Started Sep 24 04:37:57 PM UTC 24
Finished Sep 24 04:38:02 PM UTC 24
Peak memory 212012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538700027 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.2538700027
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/1.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_error_random.1998612847
Short name T69
Test name
Test status
Simulation time 272445768 ps
CPU time 6.46 seconds
Started Sep 24 04:37:49 PM UTC 24
Finished Sep 24 04:37:56 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998612847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1998612847
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/1.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random.3841495676
Short name T30
Test name
Test status
Simulation time 359610200 ps
CPU time 7.16 seconds
Started Sep 24 04:37:06 PM UTC 24
Finished Sep 24 04:37:15 PM UTC 24
Peak memory 212176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841495676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.3841495676
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/1.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_zero_delays.353851556
Short name T31
Test name
Test status
Simulation time 92946967 ps
CPU time 6.09 seconds
Started Sep 24 04:37:12 PM UTC 24
Finished Sep 24 04:37:19 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353851556 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.353851556
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/1.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_same_source.4198175185
Short name T33
Test name
Test status
Simulation time 1118767541 ps
CPU time 14.58 seconds
Started Sep 24 04:37:42 PM UTC 24
Finished Sep 24 04:37:58 PM UTC 24
Peak memory 211996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198175185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.4198175185
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/1.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke.1947605793
Short name T26
Test name
Test status
Simulation time 65533455 ps
CPU time 2.05 seconds
Started Sep 24 04:36:39 PM UTC 24
Finished Sep 24 04:36:42 PM UTC 24
Peak memory 212200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947605793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1947605793
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/1.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_large_delays.1486514168
Short name T28
Test name
Test status
Simulation time 1979165062 ps
CPU time 16.69 seconds
Started Sep 24 04:36:47 PM UTC 24
Finished Sep 24 04:37:05 PM UTC 24
Peak memory 212200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486514168 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1486514168
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/1.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.844190849
Short name T41
Test name
Test status
Simulation time 1239039258 ps
CPU time 11.36 seconds
Started Sep 24 04:36:58 PM UTC 24
Finished Sep 24 04:37:11 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844190849 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.844190849
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/1.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.2262741349
Short name T27
Test name
Test status
Simulation time 8626033 ps
CPU time 1.89 seconds
Started Sep 24 04:36:43 PM UTC 24
Finished Sep 24 04:36:46 PM UTC 24
Peak memory 210936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262741349 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.2262741349
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/1.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all.1765724992
Short name T46
Test name
Test status
Simulation time 1950136281 ps
CPU time 50.4 seconds
Started Sep 24 04:37:59 PM UTC 24
Finished Sep 24 04:38:51 PM UTC 24
Peak memory 214060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765724992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1765724992
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/1.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_error.376574021
Short name T71
Test name
Test status
Simulation time 8359906471 ps
CPU time 83.67 seconds
Started Sep 24 04:38:04 PM UTC 24
Finished Sep 24 04:39:29 PM UTC 24
Peak memory 212064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376574021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.376574021
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/1.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.2048899848
Short name T5
Test name
Test status
Simulation time 3456191726 ps
CPU time 118.23 seconds
Started Sep 24 04:38:07 PM UTC 24
Finished Sep 24 04:40:08 PM UTC 24
Peak memory 216156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048899848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.2048899848
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/1.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_unmapped_addr.2993274226
Short name T34
Test name
Test status
Simulation time 124430383 ps
CPU time 8.57 seconds
Started Sep 24 04:37:54 PM UTC 24
Finished Sep 24 04:38:04 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993274226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.2993274226
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/1.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device.1990173353
Short name T205
Test name
Test status
Simulation time 1115980814 ps
CPU time 22.17 seconds
Started Sep 24 04:45:01 PM UTC 24
Finished Sep 24 04:45:24 PM UTC 24
Peak memory 212208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990173353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.1990173353
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/10.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.1888499923
Short name T294
Test name
Test status
Simulation time 474497215 ps
CPU time 13.52 seconds
Started Sep 24 04:45:11 PM UTC 24
Finished Sep 24 04:45:25 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888499923 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.1888499923
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/10.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_error_random.2372784506
Short name T291
Test name
Test status
Simulation time 282145664 ps
CPU time 10.77 seconds
Started Sep 24 04:45:07 PM UTC 24
Finished Sep 24 04:45:19 PM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372784506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2372784506
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/10.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random.1239071339
Short name T290
Test name
Test status
Simulation time 2194138889 ps
CPU time 14.81 seconds
Started Sep 24 04:44:59 PM UTC 24
Finished Sep 24 04:45:15 PM UTC 24
Peak memory 212044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239071339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.1239071339
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/10.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_large_delays.2010522243
Short name T329
Test name
Test status
Simulation time 32101525413 ps
CPU time 130.74 seconds
Started Sep 24 04:45:01 PM UTC 24
Finished Sep 24 04:47:14 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010522243 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2010522243
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/10.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_slow_rsp.1311715681
Short name T335
Test name
Test status
Simulation time 16516606285 ps
CPU time 161.39 seconds
Started Sep 24 04:45:01 PM UTC 24
Finished Sep 24 04:47:45 PM UTC 24
Peak memory 212052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311715681 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1311715681
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/10.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_zero_delays.1693253789
Short name T174
Test name
Test status
Simulation time 45533755 ps
CPU time 5.61 seconds
Started Sep 24 04:44:59 PM UTC 24
Finished Sep 24 04:45:06 PM UTC 24
Peak memory 211996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693253789 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.1693253789
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/10.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_same_source.1490680169
Short name T289
Test name
Test status
Simulation time 351410536 ps
CPU time 7.16 seconds
Started Sep 24 04:45:05 PM UTC 24
Finished Sep 24 04:45:13 PM UTC 24
Peak memory 211996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490680169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1490680169
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/10.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke.3972577265
Short name T170
Test name
Test status
Simulation time 25877595 ps
CPU time 1.98 seconds
Started Sep 24 04:44:55 PM UTC 24
Finished Sep 24 04:44:58 PM UTC 24
Peak memory 210924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972577265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3972577265
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/10.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_large_delays.129347136
Short name T288
Test name
Test status
Simulation time 3445702210 ps
CPU time 14.41 seconds
Started Sep 24 04:44:58 PM UTC 24
Finished Sep 24 04:45:13 PM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129347136 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.129347136
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/10.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3653506241
Short name T176
Test name
Test status
Simulation time 5715048751 ps
CPU time 11.44 seconds
Started Sep 24 04:44:58 PM UTC 24
Finished Sep 24 04:45:10 PM UTC 24
Peak memory 212052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653506241 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3653506241
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/10.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.2275428164
Short name T172
Test name
Test status
Simulation time 10573786 ps
CPU time 1.67 seconds
Started Sep 24 04:44:56 PM UTC 24
Finished Sep 24 04:44:59 PM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275428164 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.2275428164
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/10.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all.1582993554
Short name T312
Test name
Test status
Simulation time 2107877115 ps
CPU time 62.45 seconds
Started Sep 24 04:45:14 PM UTC 24
Finished Sep 24 04:46:19 PM UTC 24
Peak memory 214056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582993554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1582993554
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/10.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_error.2414896297
Short name T195
Test name
Test status
Simulation time 10167284319 ps
CPU time 110.83 seconds
Started Sep 24 04:45:17 PM UTC 24
Finished Sep 24 04:47:10 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414896297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2414896297
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/10.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.3009914155
Short name T356
Test name
Test status
Simulation time 3149928881 ps
CPU time 181.09 seconds
Started Sep 24 04:45:14 PM UTC 24
Finished Sep 24 04:48:19 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009914155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.3009914155
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/10.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_unmapped_addr.160993943
Short name T292
Test name
Test status
Simulation time 1156375007 ps
CPU time 13.01 seconds
Started Sep 24 04:45:09 PM UTC 24
Finished Sep 24 04:45:24 PM UTC 24
Peak memory 212012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160993943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.160993943
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/10.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device.2306764759
Short name T160
Test name
Test status
Simulation time 86384150 ps
CPU time 3.09 seconds
Started Sep 24 04:45:27 PM UTC 24
Finished Sep 24 04:45:31 PM UTC 24
Peak memory 212204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306764759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.2306764759
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/11.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.1058974008
Short name T221
Test name
Test status
Simulation time 3403452111 ps
CPU time 21.63 seconds
Started Sep 24 04:45:32 PM UTC 24
Finished Sep 24 04:45:56 PM UTC 24
Peak memory 212332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058974008 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.1058974008
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/11.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.282683793
Short name T298
Test name
Test status
Simulation time 334268170 ps
CPU time 7.86 seconds
Started Sep 24 04:45:43 PM UTC 24
Finished Sep 24 04:45:52 PM UTC 24
Peak memory 212012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282683793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.282683793
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/11.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_error_random.2274608408
Short name T302
Test name
Test status
Simulation time 1682097884 ps
CPU time 21.71 seconds
Started Sep 24 04:45:39 PM UTC 24
Finished Sep 24 04:46:02 PM UTC 24
Peak memory 211920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274608408 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2274608408
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/11.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random.145169951
Short name T297
Test name
Test status
Simulation time 4483786877 ps
CPU time 24.36 seconds
Started Sep 24 04:45:25 PM UTC 24
Finished Sep 24 04:45:51 PM UTC 24
Peak memory 212044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145169951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.145169951
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/11.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_large_delays.1749376355
Short name T308
Test name
Test status
Simulation time 51094286814 ps
CPU time 45.91 seconds
Started Sep 24 04:45:27 PM UTC 24
Finished Sep 24 04:46:14 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749376355 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1749376355
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/11.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_slow_rsp.238140969
Short name T391
Test name
Test status
Simulation time 24584621585 ps
CPU time 248.22 seconds
Started Sep 24 04:45:27 PM UTC 24
Finished Sep 24 04:49:39 PM UTC 24
Peak memory 212048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238140969 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.238140969
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/11.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_zero_delays.2429148308
Short name T162
Test name
Test status
Simulation time 200626847 ps
CPU time 11.65 seconds
Started Sep 24 04:45:25 PM UTC 24
Finished Sep 24 04:45:38 PM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429148308 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.2429148308
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/11.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_same_source.211953676
Short name T164
Test name
Test status
Simulation time 424162596 ps
CPU time 7.17 seconds
Started Sep 24 04:45:34 PM UTC 24
Finished Sep 24 04:45:42 PM UTC 24
Peak memory 211992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211953676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.211953676
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/11.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke.1981415158
Short name T293
Test name
Test status
Simulation time 71570960 ps
CPU time 3.08 seconds
Started Sep 24 04:45:20 PM UTC 24
Finished Sep 24 04:45:24 PM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981415158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.1981415158
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/11.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_large_delays.285635617
Short name T165
Test name
Test status
Simulation time 6338678785 ps
CPU time 15.74 seconds
Started Sep 24 04:45:25 PM UTC 24
Finished Sep 24 04:45:42 PM UTC 24
Peak memory 212036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285635617 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.285635617
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/11.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.874692642
Short name T163
Test name
Test status
Simulation time 1151701859 ps
CPU time 15.49 seconds
Started Sep 24 04:45:25 PM UTC 24
Finished Sep 24 04:45:42 PM UTC 24
Peak memory 211948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874692642 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.874692642
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/11.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.1001951360
Short name T295
Test name
Test status
Simulation time 9880349 ps
CPU time 2.14 seconds
Started Sep 24 04:45:23 PM UTC 24
Finished Sep 24 04:45:26 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001951360 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.1001951360
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/11.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all.4007335645
Short name T296
Test name
Test status
Simulation time 297179894 ps
CPU time 7.02 seconds
Started Sep 24 04:45:43 PM UTC 24
Finished Sep 24 04:45:51 PM UTC 24
Peak memory 212012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007335645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.4007335645
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/11.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_error.2841928556
Short name T306
Test name
Test status
Simulation time 565044097 ps
CPU time 20.2 seconds
Started Sep 24 04:45:47 PM UTC 24
Finished Sep 24 04:46:09 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841928556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2841928556
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/11.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.1111577599
Short name T93
Test name
Test status
Simulation time 12586606591 ps
CPU time 151.48 seconds
Started Sep 24 04:45:44 PM UTC 24
Finished Sep 24 04:48:18 PM UTC 24
Peak memory 216168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111577599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.1111577599
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/11.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.52113642
Short name T303
Test name
Test status
Simulation time 73457124 ps
CPU time 13.3 seconds
Started Sep 24 04:45:49 PM UTC 24
Finished Sep 24 04:46:03 PM UTC 24
Peak memory 214056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52113642 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.52113642
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/11.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_unmapped_addr.3590236256
Short name T167
Test name
Test status
Simulation time 1020913741 ps
CPU time 6.83 seconds
Started Sep 24 04:45:39 PM UTC 24
Finished Sep 24 04:45:47 PM UTC 24
Peak memory 211916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590236256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.3590236256
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/11.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device.2598864416
Short name T311
Test name
Test status
Simulation time 118281095 ps
CPU time 11.09 seconds
Started Sep 24 04:46:05 PM UTC 24
Finished Sep 24 04:46:17 PM UTC 24
Peak memory 212204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598864416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.2598864416
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/12.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.2280611953
Short name T204
Test name
Test status
Simulation time 15033981140 ps
CPU time 151.23 seconds
Started Sep 24 04:46:09 PM UTC 24
Finished Sep 24 04:48:43 PM UTC 24
Peak memory 212268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280611953 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.2280611953
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/12.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.2173855237
Short name T313
Test name
Test status
Simulation time 91845027 ps
CPU time 4.69 seconds
Started Sep 24 04:46:17 PM UTC 24
Finished Sep 24 04:46:23 PM UTC 24
Peak memory 212012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173855237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.2173855237
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/12.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_error_random.535605340
Short name T309
Test name
Test status
Simulation time 78130034 ps
CPU time 2.95 seconds
Started Sep 24 04:46:10 PM UTC 24
Finished Sep 24 04:46:15 PM UTC 24
Peak memory 211980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535605340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.535605340
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/12.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random.2432233990
Short name T310
Test name
Test status
Simulation time 653979236 ps
CPU time 17.28 seconds
Started Sep 24 04:45:58 PM UTC 24
Finished Sep 24 04:46:16 PM UTC 24
Peak memory 212176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432233990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.2432233990
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/12.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_large_delays.1398508746
Short name T325
Test name
Test status
Simulation time 9619051130 ps
CPU time 61.04 seconds
Started Sep 24 04:45:59 PM UTC 24
Finished Sep 24 04:47:02 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398508746 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1398508746
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/12.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_slow_rsp.3237244684
Short name T143
Test name
Test status
Simulation time 14860637691 ps
CPU time 83.18 seconds
Started Sep 24 04:46:03 PM UTC 24
Finished Sep 24 04:47:29 PM UTC 24
Peak memory 212252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237244684 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3237244684
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/12.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_zero_delays.2612595359
Short name T305
Test name
Test status
Simulation time 108754290 ps
CPU time 8.86 seconds
Started Sep 24 04:45:58 PM UTC 24
Finished Sep 24 04:46:08 PM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612595359 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.2612595359
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/12.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_same_source.4268488649
Short name T91
Test name
Test status
Simulation time 287494374 ps
CPU time 7.08 seconds
Started Sep 24 04:46:09 PM UTC 24
Finished Sep 24 04:46:18 PM UTC 24
Peak memory 211996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268488649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.4268488649
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/12.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke.1088921463
Short name T300
Test name
Test status
Simulation time 15628827 ps
CPU time 2.04 seconds
Started Sep 24 04:45:52 PM UTC 24
Finished Sep 24 04:45:55 PM UTC 24
Peak memory 212176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088921463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.1088921463
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/12.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_large_delays.3047979951
Short name T304
Test name
Test status
Simulation time 4786368258 ps
CPU time 12.41 seconds
Started Sep 24 04:45:53 PM UTC 24
Finished Sep 24 04:46:07 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047979951 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3047979951
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/12.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.2481995382
Short name T307
Test name
Test status
Simulation time 1771095393 ps
CPU time 11.4 seconds
Started Sep 24 04:45:58 PM UTC 24
Finished Sep 24 04:46:10 PM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481995382 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.2481995382
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/12.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.971581155
Short name T299
Test name
Test status
Simulation time 11307438 ps
CPU time 1.98 seconds
Started Sep 24 04:45:52 PM UTC 24
Finished Sep 24 04:45:55 PM UTC 24
Peak memory 210940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971581155 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.971581155
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/12.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all.3642850419
Short name T319
Test name
Test status
Simulation time 176892505 ps
CPU time 25.13 seconds
Started Sep 24 04:46:17 PM UTC 24
Finished Sep 24 04:46:43 PM UTC 24
Peak memory 214048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642850419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.3642850419
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/12.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_error.2802488459
Short name T327
Test name
Test status
Simulation time 598523734 ps
CPU time 46.9 seconds
Started Sep 24 04:46:19 PM UTC 24
Finished Sep 24 04:47:07 PM UTC 24
Peak memory 214184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802488459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.2802488459
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/12.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.2568804931
Short name T359
Test name
Test status
Simulation time 396144605 ps
CPU time 125.45 seconds
Started Sep 24 04:46:19 PM UTC 24
Finished Sep 24 04:48:27 PM UTC 24
Peak memory 216092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568804931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.2568804931
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/12.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_unmapped_addr.1941110943
Short name T316
Test name
Test status
Simulation time 576939514 ps
CPU time 18.64 seconds
Started Sep 24 04:46:12 PM UTC 24
Finished Sep 24 04:46:32 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941110943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1941110943
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/12.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device.3529756268
Short name T322
Test name
Test status
Simulation time 313667832 ps
CPU time 4.8 seconds
Started Sep 24 04:46:43 PM UTC 24
Finished Sep 24 04:46:48 PM UTC 24
Peak memory 212012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529756268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.3529756268
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/13.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.2724122897
Short name T114
Test name
Test status
Simulation time 45913648681 ps
CPU time 267.32 seconds
Started Sep 24 04:46:43 PM UTC 24
Finished Sep 24 04:51:14 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724122897 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.2724122897
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/13.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.3452650793
Short name T324
Test name
Test status
Simulation time 606742594 ps
CPU time 10.98 seconds
Started Sep 24 04:46:50 PM UTC 24
Finished Sep 24 04:47:02 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452650793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.3452650793
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/13.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_error_random.1669041517
Short name T320
Test name
Test status
Simulation time 134089912 ps
CPU time 2.41 seconds
Started Sep 24 04:46:44 PM UTC 24
Finished Sep 24 04:46:47 PM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669041517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.1669041517
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/13.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random.894167620
Short name T321
Test name
Test status
Simulation time 198675809 ps
CPU time 12.01 seconds
Started Sep 24 04:46:34 PM UTC 24
Finished Sep 24 04:46:48 PM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894167620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.894167620
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/13.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_large_delays.4241936356
Short name T341
Test name
Test status
Simulation time 15937200999 ps
CPU time 71.32 seconds
Started Sep 24 04:46:42 PM UTC 24
Finished Sep 24 04:47:56 PM UTC 24
Peak memory 211864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241936356 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.4241936356
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/13.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_slow_rsp.189062661
Short name T426
Test name
Test status
Simulation time 39033414660 ps
CPU time 229.03 seconds
Started Sep 24 04:46:42 PM UTC 24
Finished Sep 24 04:50:35 PM UTC 24
Peak memory 211992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189062661 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.189062661
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/13.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_zero_delays.1717586950
Short name T318
Test name
Test status
Simulation time 64103882 ps
CPU time 3.75 seconds
Started Sep 24 04:46:34 PM UTC 24
Finished Sep 24 04:46:39 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717586950 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.1717586950
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/13.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_same_source.3910339412
Short name T323
Test name
Test status
Simulation time 80241712 ps
CPU time 7.91 seconds
Started Sep 24 04:46:43 PM UTC 24
Finished Sep 24 04:46:52 PM UTC 24
Peak memory 211996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910339412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.3910339412
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/13.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke.3424826186
Short name T314
Test name
Test status
Simulation time 206680841 ps
CPU time 2.51 seconds
Started Sep 24 04:46:20 PM UTC 24
Finished Sep 24 04:46:24 PM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424826186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.3424826186
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/13.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_large_delays.786487385
Short name T158
Test name
Test status
Simulation time 2475581106 ps
CPU time 12.49 seconds
Started Sep 24 04:46:25 PM UTC 24
Finished Sep 24 04:46:39 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786487385 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.786487385
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/13.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.3512857300
Short name T317
Test name
Test status
Simulation time 1238850696 ps
CPU time 9.26 seconds
Started Sep 24 04:46:28 PM UTC 24
Finished Sep 24 04:46:38 PM UTC 24
Peak memory 211988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512857300 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.3512857300
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/13.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.2170772364
Short name T315
Test name
Test status
Simulation time 10849056 ps
CPU time 1.56 seconds
Started Sep 24 04:46:24 PM UTC 24
Finished Sep 24 04:46:27 PM UTC 24
Peak memory 210940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170772364 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.2170772364
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/13.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all.450870555
Short name T147
Test name
Test status
Simulation time 285407240 ps
CPU time 42.04 seconds
Started Sep 24 04:46:50 PM UTC 24
Finished Sep 24 04:47:33 PM UTC 24
Peak memory 214056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450870555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.450870555
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/13.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_error.139468737
Short name T332
Test name
Test status
Simulation time 1312269087 ps
CPU time 42.6 seconds
Started Sep 24 04:46:53 PM UTC 24
Finished Sep 24 04:47:37 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139468737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.139468737
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/13.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.142928127
Short name T236
Test name
Test status
Simulation time 612116795 ps
CPU time 120.92 seconds
Started Sep 24 04:46:50 PM UTC 24
Finished Sep 24 04:48:53 PM UTC 24
Peak memory 219972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142928127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.142928127
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/13.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_unmapped_addr.2948369973
Short name T150
Test name
Test status
Simulation time 191256523 ps
CPU time 5.94 seconds
Started Sep 24 04:46:47 PM UTC 24
Finished Sep 24 04:46:54 PM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948369973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.2948369973
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/13.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device.863601922
Short name T142
Test name
Test status
Simulation time 452623417 ps
CPU time 8.24 seconds
Started Sep 24 04:47:19 PM UTC 24
Finished Sep 24 04:47:28 PM UTC 24
Peak memory 212200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863601922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.863601922
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/14.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.3973792684
Short name T201
Test name
Test status
Simulation time 180820546916 ps
CPU time 427.57 seconds
Started Sep 24 04:47:20 PM UTC 24
Finished Sep 24 04:54:34 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973792684 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.3973792684
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/14.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.1057372322
Short name T146
Test name
Test status
Simulation time 87274704 ps
CPU time 2.91 seconds
Started Sep 24 04:47:29 PM UTC 24
Finished Sep 24 04:47:33 PM UTC 24
Peak memory 212012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057372322 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.1057372322
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/14.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_error_random.130172515
Short name T145
Test name
Test status
Simulation time 50772148 ps
CPU time 5.72 seconds
Started Sep 24 04:47:24 PM UTC 24
Finished Sep 24 04:47:31 PM UTC 24
Peak memory 212176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130172515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.130172515
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/14.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random.1371647364
Short name T330
Test name
Test status
Simulation time 706360936 ps
CPU time 6.83 seconds
Started Sep 24 04:47:09 PM UTC 24
Finished Sep 24 04:47:17 PM UTC 24
Peak memory 212240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371647364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.1371647364
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/14.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_large_delays.2739980819
Short name T442
Test name
Test status
Simulation time 39711801305 ps
CPU time 224.67 seconds
Started Sep 24 04:47:15 PM UTC 24
Finished Sep 24 04:51:03 PM UTC 24
Peak memory 212268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739980819 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.2739980819
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/14.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_slow_rsp.2324113113
Short name T187
Test name
Test status
Simulation time 1530494314 ps
CPU time 14.55 seconds
Started Sep 24 04:47:19 PM UTC 24
Finished Sep 24 04:47:34 PM UTC 24
Peak memory 211996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324113113 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.2324113113
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/14.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_zero_delays.1531902595
Short name T331
Test name
Test status
Simulation time 227340799 ps
CPU time 4.9 seconds
Started Sep 24 04:47:11 PM UTC 24
Finished Sep 24 04:47:17 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531902595 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.1531902595
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/14.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_same_source.2981901441
Short name T144
Test name
Test status
Simulation time 466237095 ps
CPU time 5.67 seconds
Started Sep 24 04:47:23 PM UTC 24
Finished Sep 24 04:47:29 PM UTC 24
Peak memory 211996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981901441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.2981901441
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/14.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke.2765933261
Short name T328
Test name
Test status
Simulation time 72145939 ps
CPU time 2.68 seconds
Started Sep 24 04:47:04 PM UTC 24
Finished Sep 24 04:47:07 PM UTC 24
Peak memory 211664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765933261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.2765933261
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/14.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_large_delays.367667082
Short name T140
Test name
Test status
Simulation time 1666248731 ps
CPU time 13.44 seconds
Started Sep 24 04:47:07 PM UTC 24
Finished Sep 24 04:47:22 PM UTC 24
Peak memory 212200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367667082 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.367667082
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/14.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2479184415
Short name T141
Test name
Test status
Simulation time 1879751287 ps
CPU time 16.41 seconds
Started Sep 24 04:47:09 PM UTC 24
Finished Sep 24 04:47:27 PM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479184415 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2479184415
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/14.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.2337736090
Short name T326
Test name
Test status
Simulation time 8189730 ps
CPU time 1.74 seconds
Started Sep 24 04:47:04 PM UTC 24
Finished Sep 24 04:47:06 PM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337736090 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.2337736090
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/14.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all.65201153
Short name T340
Test name
Test status
Simulation time 277026731 ps
CPU time 22.33 seconds
Started Sep 24 04:47:30 PM UTC 24
Finished Sep 24 04:47:54 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65201153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-si
m-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.65201153
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/14.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_error.2452050139
Short name T349
Test name
Test status
Simulation time 756385766 ps
CPU time 35.87 seconds
Started Sep 24 04:47:32 PM UTC 24
Finished Sep 24 04:48:09 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452050139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.2452050139
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/14.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.3317806867
Short name T231
Test name
Test status
Simulation time 957114521 ps
CPU time 120.61 seconds
Started Sep 24 04:47:30 PM UTC 24
Finished Sep 24 04:49:33 PM UTC 24
Peak memory 216108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317806867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.3317806867
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/14.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.3054873521
Short name T399
Test name
Test status
Simulation time 4114360935 ps
CPU time 136.07 seconds
Started Sep 24 04:47:34 PM UTC 24
Finished Sep 24 04:49:53 PM UTC 24
Peak memory 216324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054873521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.3054873521
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/14.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_unmapped_addr.3948665601
Short name T188
Test name
Test status
Simulation time 177297451 ps
CPU time 6.97 seconds
Started Sep 24 04:47:28 PM UTC 24
Finished Sep 24 04:47:36 PM UTC 24
Peak memory 212012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948665601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.3948665601
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/14.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device.898922719
Short name T344
Test name
Test status
Simulation time 18012956 ps
CPU time 4.52 seconds
Started Sep 24 04:47:53 PM UTC 24
Finished Sep 24 04:47:59 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898922719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.898922719
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/15.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.3544117515
Short name T152
Test name
Test status
Simulation time 19683497847 ps
CPU time 145.11 seconds
Started Sep 24 04:47:53 PM UTC 24
Finished Sep 24 04:50:21 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544117515 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.3544117515
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/15.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.2183475709
Short name T346
Test name
Test status
Simulation time 40636887 ps
CPU time 4.28 seconds
Started Sep 24 04:47:57 PM UTC 24
Finished Sep 24 04:48:02 PM UTC 24
Peak memory 212012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183475709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2183475709
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/15.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_error_random.3251269762
Short name T353
Test name
Test status
Simulation time 2406356773 ps
CPU time 17.15 seconds
Started Sep 24 04:47:55 PM UTC 24
Finished Sep 24 04:48:14 PM UTC 24
Peak memory 212244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251269762 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3251269762
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/15.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random.4026809891
Short name T337
Test name
Test status
Simulation time 141017179 ps
CPU time 9.28 seconds
Started Sep 24 04:47:39 PM UTC 24
Finished Sep 24 04:47:49 PM UTC 24
Peak memory 212048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026809891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.4026809891
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/15.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_large_delays.4047818403
Short name T351
Test name
Test status
Simulation time 3248536827 ps
CPU time 24.9 seconds
Started Sep 24 04:47:47 PM UTC 24
Finished Sep 24 04:48:13 PM UTC 24
Peak memory 212268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047818403 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.4047818403
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/15.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_slow_rsp.3394687156
Short name T385
Test name
Test status
Simulation time 11427247809 ps
CPU time 84.76 seconds
Started Sep 24 04:47:48 PM UTC 24
Finished Sep 24 04:49:15 PM UTC 24
Peak memory 212060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394687156 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3394687156
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/15.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_zero_delays.4254816501
Short name T338
Test name
Test status
Simulation time 81276604 ps
CPU time 10.99 seconds
Started Sep 24 04:47:40 PM UTC 24
Finished Sep 24 04:47:52 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254816501 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.4254816501
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/15.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_same_source.2826807222
Short name T345
Test name
Test status
Simulation time 254993979 ps
CPU time 4.87 seconds
Started Sep 24 04:47:55 PM UTC 24
Finished Sep 24 04:48:01 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826807222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2826807222
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/15.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke.3502417366
Short name T333
Test name
Test status
Simulation time 145277554 ps
CPU time 2.35 seconds
Started Sep 24 04:47:34 PM UTC 24
Finished Sep 24 04:47:38 PM UTC 24
Peak memory 211988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502417366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3502417366
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/15.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_large_delays.2576069624
Short name T342
Test name
Test status
Simulation time 2406374648 ps
CPU time 17.51 seconds
Started Sep 24 04:47:37 PM UTC 24
Finished Sep 24 04:47:56 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576069624 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2576069624
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/15.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.4083507694
Short name T343
Test name
Test status
Simulation time 1373299692 ps
CPU time 18.53 seconds
Started Sep 24 04:47:39 PM UTC 24
Finished Sep 24 04:47:59 PM UTC 24
Peak memory 211988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083507694 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.4083507694
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/15.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.767837226
Short name T334
Test name
Test status
Simulation time 10776564 ps
CPU time 1.78 seconds
Started Sep 24 04:47:36 PM UTC 24
Finished Sep 24 04:47:39 PM UTC 24
Peak memory 210940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767837226 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.767837226
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/15.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all.253434353
Short name T362
Test name
Test status
Simulation time 602757100 ps
CPU time 35.24 seconds
Started Sep 24 04:47:57 PM UTC 24
Finished Sep 24 04:48:34 PM UTC 24
Peak memory 214056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253434353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.253434353
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/15.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_error.2142158642
Short name T354
Test name
Test status
Simulation time 108576917 ps
CPU time 13.4 seconds
Started Sep 24 04:47:59 PM UTC 24
Finished Sep 24 04:48:14 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142158642 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2142158642
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/15.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.4075399420
Short name T234
Test name
Test status
Simulation time 497290803 ps
CPU time 18.92 seconds
Started Sep 24 04:47:59 PM UTC 24
Finished Sep 24 04:48:19 PM UTC 24
Peak memory 214316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075399420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.4075399420
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/15.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.3387197803
Short name T420
Test name
Test status
Simulation time 1227959385 ps
CPU time 141.3 seconds
Started Sep 24 04:48:00 PM UTC 24
Finished Sep 24 04:50:25 PM UTC 24
Peak memory 218156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387197803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.3387197803
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/15.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_unmapped_addr.1782661318
Short name T350
Test name
Test status
Simulation time 412840310 ps
CPU time 12.79 seconds
Started Sep 24 04:47:55 PM UTC 24
Finished Sep 24 04:48:09 PM UTC 24
Peak memory 212260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782661318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1782661318
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/15.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device.155468367
Short name T360
Test name
Test status
Simulation time 423994950 ps
CPU time 11.67 seconds
Started Sep 24 04:48:14 PM UTC 24
Finished Sep 24 04:48:27 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155468367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.155468367
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/16.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.1299824339
Short name T365
Test name
Test status
Simulation time 665852837 ps
CPU time 14.35 seconds
Started Sep 24 04:48:21 PM UTC 24
Finished Sep 24 04:48:36 PM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299824339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.1299824339
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/16.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_error_random.2073286459
Short name T370
Test name
Test status
Simulation time 4998795484 ps
CPU time 25.82 seconds
Started Sep 24 04:48:20 PM UTC 24
Finished Sep 24 04:48:48 PM UTC 24
Peak memory 212048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073286459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.2073286459
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/16.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random.1606660819
Short name T355
Test name
Test status
Simulation time 41912094 ps
CPU time 4.52 seconds
Started Sep 24 04:48:11 PM UTC 24
Finished Sep 24 04:48:16 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606660819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.1606660819
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/16.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_large_delays.3324071543
Short name T363
Test name
Test status
Simulation time 5259559054 ps
CPU time 19.45 seconds
Started Sep 24 04:48:14 PM UTC 24
Finished Sep 24 04:48:35 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324071543 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3324071543
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/16.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_slow_rsp.3407718627
Short name T95
Test name
Test status
Simulation time 9763644920 ps
CPU time 75.8 seconds
Started Sep 24 04:48:14 PM UTC 24
Finished Sep 24 04:49:32 PM UTC 24
Peak memory 212252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407718627 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.3407718627
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/16.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_zero_delays.2905774862
Short name T352
Test name
Test status
Simulation time 10560149 ps
CPU time 1.51 seconds
Started Sep 24 04:48:11 PM UTC 24
Finished Sep 24 04:48:13 PM UTC 24
Peak memory 210940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905774862 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.2905774862
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/16.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_same_source.1957112316
Short name T357
Test name
Test status
Simulation time 148288117 ps
CPU time 4.24 seconds
Started Sep 24 04:48:17 PM UTC 24
Finished Sep 24 04:48:23 PM UTC 24
Peak memory 211996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957112316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.1957112316
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/16.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke.3903641536
Short name T348
Test name
Test status
Simulation time 68538675 ps
CPU time 2.61 seconds
Started Sep 24 04:48:03 PM UTC 24
Finished Sep 24 04:48:07 PM UTC 24
Peak memory 211988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903641536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.3903641536
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/16.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_large_delays.2606956824
Short name T191
Test name
Test status
Simulation time 9310897137 ps
CPU time 12.47 seconds
Started Sep 24 04:48:08 PM UTC 24
Finished Sep 24 04:48:21 PM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606956824 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2606956824
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/16.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.1329664080
Short name T358
Test name
Test status
Simulation time 1653816310 ps
CPU time 15.8 seconds
Started Sep 24 04:48:09 PM UTC 24
Finished Sep 24 04:48:26 PM UTC 24
Peak memory 211988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329664080 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1329664080
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/16.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.3471653337
Short name T347
Test name
Test status
Simulation time 8731233 ps
CPU time 1.82 seconds
Started Sep 24 04:48:03 PM UTC 24
Finished Sep 24 04:48:07 PM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471653337 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.3471653337
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/16.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all.887195822
Short name T366
Test name
Test status
Simulation time 831817452 ps
CPU time 13.94 seconds
Started Sep 24 04:48:23 PM UTC 24
Finished Sep 24 04:48:38 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887195822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.887195822
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/16.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_error.686643082
Short name T373
Test name
Test status
Simulation time 452578012 ps
CPU time 22.71 seconds
Started Sep 24 04:48:28 PM UTC 24
Finished Sep 24 04:48:52 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686643082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.686643082
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/16.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.1609208395
Short name T369
Test name
Test status
Simulation time 418380642 ps
CPU time 20.88 seconds
Started Sep 24 04:48:24 PM UTC 24
Finished Sep 24 04:48:47 PM UTC 24
Peak memory 214056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609208395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.1609208395
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/16.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.2295891214
Short name T398
Test name
Test status
Simulation time 8669064082 ps
CPU time 78.99 seconds
Started Sep 24 04:48:28 PM UTC 24
Finished Sep 24 04:49:49 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295891214 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.2295891214
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/16.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_unmapped_addr.3666507038
Short name T367
Test name
Test status
Simulation time 516650629 ps
CPU time 17.79 seconds
Started Sep 24 04:48:20 PM UTC 24
Finished Sep 24 04:48:40 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666507038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3666507038
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/16.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device.2200280883
Short name T372
Test name
Test status
Simulation time 41926352 ps
CPU time 6.02 seconds
Started Sep 24 04:48:41 PM UTC 24
Finished Sep 24 04:48:48 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200280883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2200280883
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/17.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.461958023
Short name T380
Test name
Test status
Simulation time 448985134 ps
CPU time 6.96 seconds
Started Sep 24 04:48:49 PM UTC 24
Finished Sep 24 04:48:57 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461958023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.461958023
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/17.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_error_random.2840302080
Short name T381
Test name
Test status
Simulation time 3891973394 ps
CPU time 14.06 seconds
Started Sep 24 04:48:46 PM UTC 24
Finished Sep 24 04:49:02 PM UTC 24
Peak memory 212048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840302080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2840302080
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/17.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random.4013729906
Short name T155
Test name
Test status
Simulation time 606131607 ps
CPU time 8.02 seconds
Started Sep 24 04:48:36 PM UTC 24
Finished Sep 24 04:48:46 PM UTC 24
Peak memory 212176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013729906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.4013729906
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/17.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_large_delays.1447533663
Short name T462
Test name
Test status
Simulation time 27418070458 ps
CPU time 185.41 seconds
Started Sep 24 04:48:38 PM UTC 24
Finished Sep 24 04:51:47 PM UTC 24
Peak memory 212268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447533663 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.1447533663
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/17.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_slow_rsp.1291190937
Short name T424
Test name
Test status
Simulation time 17215920002 ps
CPU time 110.93 seconds
Started Sep 24 04:48:39 PM UTC 24
Finished Sep 24 04:50:33 PM UTC 24
Peak memory 212056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291190937 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.1291190937
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/17.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_zero_delays.2698737648
Short name T368
Test name
Test status
Simulation time 32719784 ps
CPU time 4.52 seconds
Started Sep 24 04:48:36 PM UTC 24
Finished Sep 24 04:48:42 PM UTC 24
Peak memory 212036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698737648 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.2698737648
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/17.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_same_source.2817569631
Short name T375
Test name
Test status
Simulation time 213510763 ps
CPU time 7.21 seconds
Started Sep 24 04:48:45 PM UTC 24
Finished Sep 24 04:48:53 PM UTC 24
Peak memory 211996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817569631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2817569631
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/17.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke.2488308047
Short name T361
Test name
Test status
Simulation time 43977402 ps
CPU time 2.3 seconds
Started Sep 24 04:48:28 PM UTC 24
Finished Sep 24 04:48:32 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488308047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2488308047
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/17.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_large_delays.2262481841
Short name T376
Test name
Test status
Simulation time 4122556396 ps
CPU time 16.31 seconds
Started Sep 24 04:48:36 PM UTC 24
Finished Sep 24 04:48:54 PM UTC 24
Peak memory 212132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262481841 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2262481841
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/17.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.2615528984
Short name T371
Test name
Test status
Simulation time 2148625951 ps
CPU time 10.61 seconds
Started Sep 24 04:48:36 PM UTC 24
Finished Sep 24 04:48:48 PM UTC 24
Peak memory 212052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615528984 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2615528984
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/17.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.1131955693
Short name T364
Test name
Test status
Simulation time 10578228 ps
CPU time 1.87 seconds
Started Sep 24 04:48:33 PM UTC 24
Finished Sep 24 04:48:36 PM UTC 24
Peak memory 210940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131955693 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.1131955693
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/17.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all.3602362553
Short name T218
Test name
Test status
Simulation time 3775744193 ps
CPU time 64.42 seconds
Started Sep 24 04:48:49 PM UTC 24
Finished Sep 24 04:49:56 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602362553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3602362553
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/17.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_error.638710764
Short name T377
Test name
Test status
Simulation time 5718855 ps
CPU time 1.21 seconds
Started Sep 24 04:48:54 PM UTC 24
Finished Sep 24 04:48:56 PM UTC 24
Peak memory 202212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638710764 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.638710764
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/17.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.1231639887
Short name T8
Test name
Test status
Simulation time 819095515 ps
CPU time 112.02 seconds
Started Sep 24 04:48:49 PM UTC 24
Finished Sep 24 04:50:44 PM UTC 24
Peak memory 216104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231639887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.1231639887
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/17.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.1454564853
Short name T406
Test name
Test status
Simulation time 912922169 ps
CPU time 68.62 seconds
Started Sep 24 04:48:54 PM UTC 24
Finished Sep 24 04:50:05 PM UTC 24
Peak memory 216236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454564853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.1454564853
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/17.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_unmapped_addr.3354485227
Short name T374
Test name
Test status
Simulation time 644966277 ps
CPU time 4.46 seconds
Started Sep 24 04:48:48 PM UTC 24
Finished Sep 24 04:48:53 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354485227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3354485227
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/17.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device.3314568010
Short name T214
Test name
Test status
Simulation time 1827118347 ps
CPU time 30.13 seconds
Started Sep 24 04:49:03 PM UTC 24
Finished Sep 24 04:49:34 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314568010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.3314568010
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/18.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.1914129215
Short name T207
Test name
Test status
Simulation time 35020930459 ps
CPU time 249.78 seconds
Started Sep 24 04:49:07 PM UTC 24
Finished Sep 24 04:53:20 PM UTC 24
Peak memory 214316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914129215 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.1914129215
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/18.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3360214742
Short name T393
Test name
Test status
Simulation time 3128302099 ps
CPU time 17.58 seconds
Started Sep 24 04:49:21 PM UTC 24
Finished Sep 24 04:49:40 PM UTC 24
Peak memory 212076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360214742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3360214742
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/18.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_error_random.1755574032
Short name T387
Test name
Test status
Simulation time 617156910 ps
CPU time 11.55 seconds
Started Sep 24 04:49:15 PM UTC 24
Finished Sep 24 04:49:28 PM UTC 24
Peak memory 212176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755574032 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1755574032
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/18.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random.4070271050
Short name T382
Test name
Test status
Simulation time 234260913 ps
CPU time 6.73 seconds
Started Sep 24 04:48:59 PM UTC 24
Finished Sep 24 04:49:06 PM UTC 24
Peak memory 212176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070271050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.4070271050
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/18.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_large_delays.398642074
Short name T504
Test name
Test status
Simulation time 142275560352 ps
CPU time 237.33 seconds
Started Sep 24 04:49:00 PM UTC 24
Finished Sep 24 04:53:01 PM UTC 24
Peak memory 211948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398642074 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.398642074
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/18.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_slow_rsp.1905718630
Short name T405
Test name
Test status
Simulation time 11438762066 ps
CPU time 61.62 seconds
Started Sep 24 04:49:00 PM UTC 24
Finished Sep 24 04:50:03 PM UTC 24
Peak memory 212060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905718630 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1905718630
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/18.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_zero_delays.1408287385
Short name T384
Test name
Test status
Simulation time 132947919 ps
CPU time 13.6 seconds
Started Sep 24 04:48:59 PM UTC 24
Finished Sep 24 04:49:13 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408287385 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.1408287385
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/18.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_same_source.1499722795
Short name T94
Test name
Test status
Simulation time 373346533 ps
CPU time 7.63 seconds
Started Sep 24 04:49:08 PM UTC 24
Finished Sep 24 04:49:17 PM UTC 24
Peak memory 211996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499722795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.1499722795
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/18.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke.2670935411
Short name T378
Test name
Test status
Simulation time 9829746 ps
CPU time 1.8 seconds
Started Sep 24 04:48:54 PM UTC 24
Finished Sep 24 04:48:57 PM UTC 24
Peak memory 210956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670935411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.2670935411
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/18.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_large_delays.3693213643
Short name T383
Test name
Test status
Simulation time 5263544590 ps
CPU time 9.88 seconds
Started Sep 24 04:48:55 PM UTC 24
Finished Sep 24 04:49:06 PM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693213643 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.3693213643
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/18.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.2814727870
Short name T386
Test name
Test status
Simulation time 1948471750 ps
CPU time 16.94 seconds
Started Sep 24 04:48:58 PM UTC 24
Finished Sep 24 04:49:17 PM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814727870 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2814727870
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/18.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.4267424951
Short name T379
Test name
Test status
Simulation time 9227013 ps
CPU time 1.73 seconds
Started Sep 24 04:48:54 PM UTC 24
Finished Sep 24 04:48:57 PM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267424951 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.4267424951
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/18.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all.3426560817
Short name T394
Test name
Test status
Simulation time 92456704 ps
CPU time 18.04 seconds
Started Sep 24 04:49:21 PM UTC 24
Finished Sep 24 04:49:40 PM UTC 24
Peak memory 212012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426560817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.3426560817
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/18.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_error.3987494180
Short name T401
Test name
Test status
Simulation time 1118934546 ps
CPU time 31.04 seconds
Started Sep 24 04:49:22 PM UTC 24
Finished Sep 24 04:49:55 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987494180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3987494180
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/18.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.1821698753
Short name T439
Test name
Test status
Simulation time 874327591 ps
CPU time 91.75 seconds
Started Sep 24 04:49:21 PM UTC 24
Finished Sep 24 04:50:55 PM UTC 24
Peak memory 216104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821698753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.1821698753
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/18.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.950394875
Short name T404
Test name
Test status
Simulation time 251016257 ps
CPU time 30.48 seconds
Started Sep 24 04:49:29 PM UTC 24
Finished Sep 24 04:50:01 PM UTC 24
Peak memory 214060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950394875 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.950394875
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/18.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_unmapped_addr.3726209904
Short name T389
Test name
Test status
Simulation time 867016318 ps
CPU time 18.4 seconds
Started Sep 24 04:49:16 PM UTC 24
Finished Sep 24 04:49:36 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726209904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3726209904
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/18.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device.498583648
Short name T412
Test name
Test status
Simulation time 1685118330 ps
CPU time 29.51 seconds
Started Sep 24 04:49:41 PM UTC 24
Finished Sep 24 04:50:12 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498583648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.498583648
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/19.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.930589102
Short name T411
Test name
Test status
Simulation time 1172469849 ps
CPU time 19.3 seconds
Started Sep 24 04:49:49 PM UTC 24
Finished Sep 24 04:50:11 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930589102 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.930589102
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/19.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_error_random.1355992814
Short name T400
Test name
Test status
Simulation time 151055826 ps
CPU time 9.01 seconds
Started Sep 24 04:49:43 PM UTC 24
Finished Sep 24 04:49:53 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355992814 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1355992814
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/19.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random.714456649
Short name T392
Test name
Test status
Simulation time 271182535 ps
CPU time 2.59 seconds
Started Sep 24 04:49:36 PM UTC 24
Finished Sep 24 04:49:39 PM UTC 24
Peak memory 211980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714456649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.714456649
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/19.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_large_delays.668204741
Short name T486
Test name
Test status
Simulation time 58482302949 ps
CPU time 164.29 seconds
Started Sep 24 04:49:38 PM UTC 24
Finished Sep 24 04:52:24 PM UTC 24
Peak memory 212264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668204741 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.668204741
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/19.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_slow_rsp.4174464974
Short name T431
Test name
Test status
Simulation time 8064273141 ps
CPU time 61.34 seconds
Started Sep 24 04:49:41 PM UTC 24
Finished Sep 24 04:50:44 PM UTC 24
Peak memory 212056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174464974 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.4174464974
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/19.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_zero_delays.57946783
Short name T396
Test name
Test status
Simulation time 63385747 ps
CPU time 8.74 seconds
Started Sep 24 04:49:38 PM UTC 24
Finished Sep 24 04:49:47 PM UTC 24
Peak memory 212260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57946783 -assert nopostproc +UVM_TESTNAME=xbar_
base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.57946783
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/19.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_same_source.3493063436
Short name T395
Test name
Test status
Simulation time 39604458 ps
CPU time 4.06 seconds
Started Sep 24 04:49:42 PM UTC 24
Finished Sep 24 04:49:47 PM UTC 24
Peak memory 214212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493063436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3493063436
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/19.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke.1856808903
Short name T388
Test name
Test status
Simulation time 69134138 ps
CPU time 2.87 seconds
Started Sep 24 04:49:30 PM UTC 24
Finished Sep 24 04:49:34 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856808903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.1856808903
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/19.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_large_delays.1595293501
Short name T96
Test name
Test status
Simulation time 3193038993 ps
CPU time 16.85 seconds
Started Sep 24 04:49:35 PM UTC 24
Finished Sep 24 04:49:54 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595293501 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.1595293501
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/19.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.1664082377
Short name T397
Test name
Test status
Simulation time 827017540 ps
CPU time 12.43 seconds
Started Sep 24 04:49:36 PM UTC 24
Finished Sep 24 04:49:49 PM UTC 24
Peak memory 211992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664082377 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1664082377
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/19.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.1376465684
Short name T390
Test name
Test status
Simulation time 8895321 ps
CPU time 1.83 seconds
Started Sep 24 04:49:34 PM UTC 24
Finished Sep 24 04:49:37 PM UTC 24
Peak memory 210940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376465684 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.1376465684
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/19.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all.1509116647
Short name T427
Test name
Test status
Simulation time 2271413764 ps
CPU time 42.25 seconds
Started Sep 24 04:49:51 PM UTC 24
Finished Sep 24 04:50:36 PM UTC 24
Peak memory 214316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509116647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1509116647
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/19.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_error.3614567727
Short name T425
Test name
Test status
Simulation time 296437381 ps
CPU time 38.3 seconds
Started Sep 24 04:49:54 PM UTC 24
Finished Sep 24 04:50:34 PM UTC 24
Peak memory 214052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614567727 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3614567727
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/19.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.3971761122
Short name T117
Test name
Test status
Simulation time 9907989296 ps
CPU time 212.29 seconds
Started Sep 24 04:49:51 PM UTC 24
Finished Sep 24 04:53:28 PM UTC 24
Peak memory 216172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971761122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.3971761122
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/19.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.1513451768
Short name T471
Test name
Test status
Simulation time 3107909589 ps
CPU time 126.86 seconds
Started Sep 24 04:49:54 PM UTC 24
Finished Sep 24 04:52:04 PM UTC 24
Peak memory 216344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513451768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.1513451768
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/19.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_unmapped_addr.886387380
Short name T408
Test name
Test status
Simulation time 790793807 ps
CPU time 15.14 seconds
Started Sep 24 04:49:49 PM UTC 24
Finished Sep 24 04:50:06 PM UTC 24
Peak memory 212012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886387380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.886387380
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/19.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device.3086982004
Short name T47
Test name
Test status
Simulation time 48397538 ps
CPU time 11.76 seconds
Started Sep 24 04:38:48 PM UTC 24
Finished Sep 24 04:39:01 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086982004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.3086982004
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/2.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.346434436
Short name T213
Test name
Test status
Simulation time 11428527924 ps
CPU time 90.7 seconds
Started Sep 24 04:38:52 PM UTC 24
Finished Sep 24 04:40:25 PM UTC 24
Peak memory 212260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346434436 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.346434436
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/2.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.3614534901
Short name T72
Test name
Test status
Simulation time 112460820 ps
CPU time 4.8 seconds
Started Sep 24 04:39:31 PM UTC 24
Finished Sep 24 04:39:37 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614534901 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.3614534901
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/2.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_error_random.3824052943
Short name T70
Test name
Test status
Simulation time 401758380 ps
CPU time 6.73 seconds
Started Sep 24 04:39:18 PM UTC 24
Finished Sep 24 04:39:26 PM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824052943 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3824052943
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/2.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random.61675346
Short name T59
Test name
Test status
Simulation time 728704857 ps
CPU time 10.72 seconds
Started Sep 24 04:38:35 PM UTC 24
Finished Sep 24 04:38:47 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61675346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.61675346
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/2.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_large_delays.416993396
Short name T67
Test name
Test status
Simulation time 30447921311 ps
CPU time 176.89 seconds
Started Sep 24 04:38:43 PM UTC 24
Finished Sep 24 04:41:42 PM UTC 24
Peak memory 212328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416993396 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.416993396
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/2.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_slow_rsp.3353979746
Short name T62
Test name
Test status
Simulation time 17263546669 ps
CPU time 94.27 seconds
Started Sep 24 04:38:44 PM UTC 24
Finished Sep 24 04:40:20 PM UTC 24
Peak memory 212052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353979746 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.3353979746
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/2.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_zero_delays.1597074894
Short name T42
Test name
Test status
Simulation time 50370201 ps
CPU time 6.5 seconds
Started Sep 24 04:38:35 PM UTC 24
Finished Sep 24 04:38:43 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597074894 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.1597074894
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/2.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_same_source.1383597434
Short name T60
Test name
Test status
Simulation time 1564032420 ps
CPU time 14.77 seconds
Started Sep 24 04:39:01 PM UTC 24
Finished Sep 24 04:39:17 PM UTC 24
Peak memory 212260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383597434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.1383597434
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/2.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke.4060613069
Short name T38
Test name
Test status
Simulation time 8416676 ps
CPU time 1.49 seconds
Started Sep 24 04:38:07 PM UTC 24
Finished Sep 24 04:38:10 PM UTC 24
Peak memory 210988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060613069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.4060613069
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/2.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_large_delays.182890220
Short name T57
Test name
Test status
Simulation time 4167425655 ps
CPU time 14.86 seconds
Started Sep 24 04:38:16 PM UTC 24
Finished Sep 24 04:38:32 PM UTC 24
Peak memory 212064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182890220 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.182890220
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/2.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.626950253
Short name T58
Test name
Test status
Simulation time 1070823251 ps
CPU time 13.03 seconds
Started Sep 24 04:38:27 PM UTC 24
Finished Sep 24 04:38:42 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626950253 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.626950253
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/2.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.2410568818
Short name T45
Test name
Test status
Simulation time 15671919 ps
CPU time 2.33 seconds
Started Sep 24 04:38:11 PM UTC 24
Finished Sep 24 04:38:15 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410568818 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.2410568818
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/2.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all.1114111544
Short name T133
Test name
Test status
Simulation time 3788606344 ps
CPU time 85.09 seconds
Started Sep 24 04:39:38 PM UTC 24
Finished Sep 24 04:41:05 PM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114111544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.1114111544
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/2.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3117148607
Short name T200
Test name
Test status
Simulation time 1864944000 ps
CPU time 43.88 seconds
Started Sep 24 04:39:59 PM UTC 24
Finished Sep 24 04:40:45 PM UTC 24
Peak memory 214056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117148607 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3117148607
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/2.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.1152073101
Short name T134
Test name
Test status
Simulation time 3419200970 ps
CPU time 100.34 seconds
Started Sep 24 04:40:10 PM UTC 24
Finished Sep 24 04:41:53 PM UTC 24
Peak memory 216168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152073101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.1152073101
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/2.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_unmapped_addr.3761719825
Short name T61
Test name
Test status
Simulation time 349196339 ps
CPU time 12.21 seconds
Started Sep 24 04:39:28 PM UTC 24
Finished Sep 24 04:39:41 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761719825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.3761719825
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/2.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device.3190266296
Short name T413
Test name
Test status
Simulation time 16934827 ps
CPU time 4.39 seconds
Started Sep 24 04:50:07 PM UTC 24
Finished Sep 24 04:50:13 PM UTC 24
Peak memory 212012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190266296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.3190266296
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/20.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1809946169
Short name T423
Test name
Test status
Simulation time 1062145182 ps
CPU time 14.95 seconds
Started Sep 24 04:50:14 PM UTC 24
Finished Sep 24 04:50:30 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809946169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.1809946169
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/20.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_error_random.3806098224
Short name T418
Test name
Test status
Simulation time 57863061 ps
CPU time 8.66 seconds
Started Sep 24 04:50:12 PM UTC 24
Finished Sep 24 04:50:22 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806098224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3806098224
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/20.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random.952401061
Short name T407
Test name
Test status
Simulation time 246458060 ps
CPU time 3.98 seconds
Started Sep 24 04:50:01 PM UTC 24
Finished Sep 24 04:50:06 PM UTC 24
Peak memory 211988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952401061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.952401061
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/20.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_large_delays.3266315505
Short name T451
Test name
Test status
Simulation time 14044535475 ps
CPU time 87.29 seconds
Started Sep 24 04:50:02 PM UTC 24
Finished Sep 24 04:51:32 PM UTC 24
Peak memory 212076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266315505 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.3266315505
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/20.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_slow_rsp.3814256701
Short name T434
Test name
Test status
Simulation time 5634702260 ps
CPU time 41.49 seconds
Started Sep 24 04:50:05 PM UTC 24
Finished Sep 24 04:50:48 PM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814256701 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3814256701
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/20.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_zero_delays.1889581967
Short name T410
Test name
Test status
Simulation time 33169699 ps
CPU time 7.67 seconds
Started Sep 24 04:50:01 PM UTC 24
Finished Sep 24 04:50:10 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889581967 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.1889581967
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/20.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_same_source.3192556116
Short name T415
Test name
Test status
Simulation time 178715608 ps
CPU time 7.34 seconds
Started Sep 24 04:50:09 PM UTC 24
Finished Sep 24 04:50:18 PM UTC 24
Peak memory 211996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192556116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3192556116
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/20.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke.109270827
Short name T403
Test name
Test status
Simulation time 107457590 ps
CPU time 2.68 seconds
Started Sep 24 04:49:56 PM UTC 24
Finished Sep 24 04:49:59 PM UTC 24
Peak memory 212196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109270827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.109270827
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/20.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_large_delays.2036088130
Short name T414
Test name
Test status
Simulation time 2800256231 ps
CPU time 16.58 seconds
Started Sep 24 04:49:59 PM UTC 24
Finished Sep 24 04:50:17 PM UTC 24
Peak memory 212040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036088130 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2036088130
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/20.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.2394652966
Short name T409
Test name
Test status
Simulation time 690867556 ps
CPU time 9.54 seconds
Started Sep 24 04:49:59 PM UTC 24
Finished Sep 24 04:50:10 PM UTC 24
Peak memory 211948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394652966 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2394652966
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/20.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.694819385
Short name T402
Test name
Test status
Simulation time 9388788 ps
CPU time 1.95 seconds
Started Sep 24 04:49:56 PM UTC 24
Finished Sep 24 04:49:59 PM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694819385 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.694819385
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/20.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all.2803802005
Short name T457
Test name
Test status
Simulation time 4381399289 ps
CPU time 84.6 seconds
Started Sep 24 04:50:14 PM UTC 24
Finished Sep 24 04:51:41 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803802005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2803802005
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/20.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_error.548310347
Short name T222
Test name
Test status
Simulation time 5903869390 ps
CPU time 35.77 seconds
Started Sep 24 04:50:18 PM UTC 24
Finished Sep 24 04:50:55 PM UTC 24
Peak memory 212132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548310347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.548310347
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/20.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.767968972
Short name T233
Test name
Test status
Simulation time 882290560 ps
CPU time 148.01 seconds
Started Sep 24 04:50:14 PM UTC 24
Finished Sep 24 04:52:45 PM UTC 24
Peak memory 216100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767968972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.767968972
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/20.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.3727758927
Short name T435
Test name
Test status
Simulation time 114158664 ps
CPU time 29.41 seconds
Started Sep 24 04:50:18 PM UTC 24
Finished Sep 24 04:50:49 PM UTC 24
Peak memory 214056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727758927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.3727758927
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/20.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_unmapped_addr.1673659089
Short name T416
Test name
Test status
Simulation time 1239977658 ps
CPU time 6.16 seconds
Started Sep 24 04:50:12 PM UTC 24
Finished Sep 24 04:50:19 PM UTC 24
Peak memory 212260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673659089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1673659089
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/20.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device.1651447944
Short name T215
Test name
Test status
Simulation time 1646058934 ps
CPU time 20.09 seconds
Started Sep 24 04:50:30 PM UTC 24
Finished Sep 24 04:50:51 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651447944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.1651447944
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/21.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.1087313096
Short name T227
Test name
Test status
Simulation time 14507554325 ps
CPU time 69.43 seconds
Started Sep 24 04:50:31 PM UTC 24
Finished Sep 24 04:51:43 PM UTC 24
Peak memory 212076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087313096 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.1087313096
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/21.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.338654685
Short name T430
Test name
Test status
Simulation time 12043455 ps
CPU time 2 seconds
Started Sep 24 04:50:37 PM UTC 24
Finished Sep 24 04:50:40 PM UTC 24
Peak memory 210940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338654685 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.338654685
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/21.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_error_random.2713417110
Short name T432
Test name
Test status
Simulation time 1626537599 ps
CPU time 11.07 seconds
Started Sep 24 04:50:35 PM UTC 24
Finished Sep 24 04:50:47 PM UTC 24
Peak memory 211992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713417110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2713417110
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/21.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random.730908734
Short name T422
Test name
Test status
Simulation time 28587911 ps
CPU time 3.04 seconds
Started Sep 24 04:50:24 PM UTC 24
Finished Sep 24 04:50:28 PM UTC 24
Peak memory 212052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730908734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.730908734
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/21.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_large_delays.3414479836
Short name T555
Test name
Test status
Simulation time 46332042751 ps
CPU time 232.6 seconds
Started Sep 24 04:50:26 PM UTC 24
Finished Sep 24 04:54:22 PM UTC 24
Peak memory 212268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414479836 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3414479836
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/21.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_slow_rsp.1815048496
Short name T456
Test name
Test status
Simulation time 22600469738 ps
CPU time 66.42 seconds
Started Sep 24 04:50:28 PM UTC 24
Finished Sep 24 04:51:36 PM UTC 24
Peak memory 212052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815048496 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1815048496
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/21.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_zero_delays.742126062
Short name T421
Test name
Test status
Simulation time 8697524 ps
CPU time 1.91 seconds
Started Sep 24 04:50:24 PM UTC 24
Finished Sep 24 04:50:27 PM UTC 24
Peak memory 210936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742126062 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.742126062
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/21.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_same_source.3451495689
Short name T437
Test name
Test status
Simulation time 1760101281 ps
CPU time 19.53 seconds
Started Sep 24 04:50:34 PM UTC 24
Finished Sep 24 04:50:54 PM UTC 24
Peak memory 211996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451495689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3451495689
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/21.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke.2986473558
Short name T417
Test name
Test status
Simulation time 10573898 ps
CPU time 1.91 seconds
Started Sep 24 04:50:18 PM UTC 24
Finished Sep 24 04:50:21 PM UTC 24
Peak memory 210968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986473558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2986473558
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/21.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_large_delays.2920622316
Short name T429
Test name
Test status
Simulation time 1903908778 ps
CPU time 15.22 seconds
Started Sep 24 04:50:22 PM UTC 24
Finished Sep 24 04:50:39 PM UTC 24
Peak memory 212200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920622316 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2920622316
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/21.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.4008315509
Short name T428
Test name
Test status
Simulation time 1334196826 ps
CPU time 14.35 seconds
Started Sep 24 04:50:22 PM UTC 24
Finished Sep 24 04:50:38 PM UTC 24
Peak memory 211988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008315509 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.4008315509
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/21.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.553923889
Short name T419
Test name
Test status
Simulation time 7723944 ps
CPU time 1.6 seconds
Started Sep 24 04:50:21 PM UTC 24
Finished Sep 24 04:50:23 PM UTC 24
Peak memory 210940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553923889 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.553923889
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/21.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all.1124335922
Short name T447
Test name
Test status
Simulation time 369311024 ps
CPU time 32.13 seconds
Started Sep 24 04:50:39 PM UTC 24
Finished Sep 24 04:51:13 PM UTC 24
Peak memory 212268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124335922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1124335922
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/21.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_error.188677904
Short name T180
Test name
Test status
Simulation time 1732675282 ps
CPU time 33.64 seconds
Started Sep 24 04:50:40 PM UTC 24
Finished Sep 24 04:51:15 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188677904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.188677904
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/21.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.1110118741
Short name T159
Test name
Test status
Simulation time 6107829394 ps
CPU time 77.78 seconds
Started Sep 24 04:50:40 PM UTC 24
Finished Sep 24 04:52:00 PM UTC 24
Peak memory 216172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110118741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.1110118741
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/21.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_unmapped_addr.2817130849
Short name T438
Test name
Test status
Simulation time 1944458129 ps
CPU time 16.5 seconds
Started Sep 24 04:50:37 PM UTC 24
Finished Sep 24 04:50:55 PM UTC 24
Peak memory 212260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817130849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.2817130849
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/21.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device.583759461
Short name T36
Test name
Test status
Simulation time 1671813589 ps
CPU time 15.07 seconds
Started Sep 24 04:50:54 PM UTC 24
Finished Sep 24 04:51:11 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583759461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.583759461
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/22.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.3692751994
Short name T226
Test name
Test status
Simulation time 25439042169 ps
CPU time 219.24 seconds
Started Sep 24 04:50:57 PM UTC 24
Finished Sep 24 04:54:40 PM UTC 24
Peak memory 214188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692751994 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.3692751994
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/22.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.236598756
Short name T445
Test name
Test status
Simulation time 46691808 ps
CPU time 3.26 seconds
Started Sep 24 04:51:03 PM UTC 24
Finished Sep 24 04:51:08 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236598756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.236598756
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/22.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_error_random.1142039453
Short name T444
Test name
Test status
Simulation time 415635876 ps
CPU time 9.41 seconds
Started Sep 24 04:50:57 PM UTC 24
Finished Sep 24 04:51:08 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142039453 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1142039453
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/22.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random.1812918045
Short name T440
Test name
Test status
Simulation time 1767716398 ps
CPU time 7.51 seconds
Started Sep 24 04:50:54 PM UTC 24
Finished Sep 24 04:51:03 PM UTC 24
Peak memory 211980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812918045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.1812918045
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/22.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_large_delays.2736450321
Short name T534
Test name
Test status
Simulation time 33569427223 ps
CPU time 170.09 seconds
Started Sep 24 04:50:54 PM UTC 24
Finished Sep 24 04:53:47 PM UTC 24
Peak memory 212076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736450321 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2736450321
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/22.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_slow_rsp.1028665900
Short name T478
Test name
Test status
Simulation time 40003553499 ps
CPU time 78.84 seconds
Started Sep 24 04:50:54 PM UTC 24
Finished Sep 24 04:52:15 PM UTC 24
Peak memory 212188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028665900 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1028665900
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/22.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_zero_delays.1114437183
Short name T441
Test name
Test status
Simulation time 105435648 ps
CPU time 7.88 seconds
Started Sep 24 04:50:54 PM UTC 24
Finished Sep 24 04:51:03 PM UTC 24
Peak memory 212196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114437183 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.1114437183
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/22.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_same_source.2883591744
Short name T443
Test name
Test status
Simulation time 345528216 ps
CPU time 8.97 seconds
Started Sep 24 04:50:57 PM UTC 24
Finished Sep 24 04:51:07 PM UTC 24
Peak memory 212256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883591744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.2883591744
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/22.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke.3614581826
Short name T433
Test name
Test status
Simulation time 34105519 ps
CPU time 1.89 seconds
Started Sep 24 04:50:45 PM UTC 24
Finished Sep 24 04:50:48 PM UTC 24
Peak memory 210924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614581826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.3614581826
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/22.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_large_delays.3101951352
Short name T183
Test name
Test status
Simulation time 5607185150 ps
CPU time 23.27 seconds
Started Sep 24 04:50:54 PM UTC 24
Finished Sep 24 04:51:19 PM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101951352 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.3101951352
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/22.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.1969902313
Short name T178
Test name
Test status
Simulation time 2498902239 ps
CPU time 19.89 seconds
Started Sep 24 04:50:54 PM UTC 24
Finished Sep 24 04:51:15 PM UTC 24
Peak memory 212244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969902313 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.1969902313
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/22.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.1188221397
Short name T436
Test name
Test status
Simulation time 8827824 ps
CPU time 1.98 seconds
Started Sep 24 04:50:49 PM UTC 24
Finished Sep 24 04:50:52 PM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188221397 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.1188221397
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/22.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all.3055565523
Short name T466
Test name
Test status
Simulation time 18863485452 ps
CPU time 47.06 seconds
Started Sep 24 04:51:08 PM UTC 24
Finished Sep 24 04:51:57 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055565523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.3055565523
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/22.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_error.556826166
Short name T480
Test name
Test status
Simulation time 5223204977 ps
CPU time 67.47 seconds
Started Sep 24 04:51:08 PM UTC 24
Finished Sep 24 04:52:17 PM UTC 24
Peak memory 214108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556826166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.556826166
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/22.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.4173318579
Short name T131
Test name
Test status
Simulation time 2421460978 ps
CPU time 38.7 seconds
Started Sep 24 04:51:08 PM UTC 24
Finished Sep 24 04:51:48 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173318579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.4173318579
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/22.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.3766309758
Short name T559
Test name
Test status
Simulation time 6624218420 ps
CPU time 192.31 seconds
Started Sep 24 04:51:08 PM UTC 24
Finished Sep 24 04:54:24 PM UTC 24
Peak memory 218476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766309758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.3766309758
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/22.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_unmapped_addr.2810480630
Short name T446
Test name
Test status
Simulation time 1005248316 ps
CPU time 9.71 seconds
Started Sep 24 04:50:57 PM UTC 24
Finished Sep 24 04:51:08 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810480630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.2810480630
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/22.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device.3231404619
Short name T115
Test name
Test status
Simulation time 1205899851 ps
CPU time 23.96 seconds
Started Sep 24 04:51:19 PM UTC 24
Finished Sep 24 04:51:44 PM UTC 24
Peak memory 212204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231404619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.3231404619
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/23.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.921995986
Short name T211
Test name
Test status
Simulation time 258633482264 ps
CPU time 283.88 seconds
Started Sep 24 04:51:19 PM UTC 24
Finished Sep 24 04:56:07 PM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921995986 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.921995986
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/23.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.3462311164
Short name T454
Test name
Test status
Simulation time 107587270 ps
CPU time 10.61 seconds
Started Sep 24 04:51:22 PM UTC 24
Finished Sep 24 04:51:34 PM UTC 24
Peak memory 212012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462311164 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.3462311164
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/23.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_error_random.1022474440
Short name T455
Test name
Test status
Simulation time 4407109809 ps
CPU time 15.42 seconds
Started Sep 24 04:51:19 PM UTC 24
Finished Sep 24 04:51:36 PM UTC 24
Peak memory 212044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022474440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1022474440
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/23.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random.3350662980
Short name T182
Test name
Test status
Simulation time 10235882 ps
CPU time 1.48 seconds
Started Sep 24 04:51:14 PM UTC 24
Finished Sep 24 04:51:17 PM UTC 24
Peak memory 210908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350662980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.3350662980
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/23.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_large_delays.2692657773
Short name T521
Test name
Test status
Simulation time 23059860478 ps
CPU time 124.32 seconds
Started Sep 24 04:51:14 PM UTC 24
Finished Sep 24 04:53:21 PM UTC 24
Peak memory 212268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692657773 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2692657773
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/23.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_slow_rsp.3364427403
Short name T450
Test name
Test status
Simulation time 2775116309 ps
CPU time 13.73 seconds
Started Sep 24 04:51:15 PM UTC 24
Finished Sep 24 04:51:29 PM UTC 24
Peak memory 212252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364427403 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3364427403
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/23.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_zero_delays.410416638
Short name T186
Test name
Test status
Simulation time 176192385 ps
CPU time 10.13 seconds
Started Sep 24 04:51:14 PM UTC 24
Finished Sep 24 04:51:26 PM UTC 24
Peak memory 212196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410416638 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.410416638
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/23.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_same_source.1396568757
Short name T449
Test name
Test status
Simulation time 389431337 ps
CPU time 9.03 seconds
Started Sep 24 04:51:19 PM UTC 24
Finished Sep 24 04:51:29 PM UTC 24
Peak memory 212064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396568757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.1396568757
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/23.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke.1345083231
Short name T181
Test name
Test status
Simulation time 11010366 ps
CPU time 1.91 seconds
Started Sep 24 04:51:13 PM UTC 24
Finished Sep 24 04:51:16 PM UTC 24
Peak memory 210920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345083231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.1345083231
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/23.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_large_delays.422642628
Short name T185
Test name
Test status
Simulation time 2142324420 ps
CPU time 8.93 seconds
Started Sep 24 04:51:13 PM UTC 24
Finished Sep 24 04:51:23 PM UTC 24
Peak memory 212264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422642628 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.422642628
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/23.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.2584870543
Short name T184
Test name
Test status
Simulation time 1283439020 ps
CPU time 8.83 seconds
Started Sep 24 04:51:13 PM UTC 24
Finished Sep 24 04:51:23 PM UTC 24
Peak memory 211988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584870543 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.2584870543
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/23.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.1565402759
Short name T179
Test name
Test status
Simulation time 10477023 ps
CPU time 1.81 seconds
Started Sep 24 04:51:13 PM UTC 24
Finished Sep 24 04:51:15 PM UTC 24
Peak memory 210936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565402759 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.1565402759
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/23.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all.2073675143
Short name T482
Test name
Test status
Simulation time 530283226 ps
CPU time 54.64 seconds
Started Sep 24 04:51:22 PM UTC 24
Finished Sep 24 04:52:19 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073675143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2073675143
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/23.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_error.1812829711
Short name T216
Test name
Test status
Simulation time 9151249826 ps
CPU time 92.08 seconds
Started Sep 24 04:51:25 PM UTC 24
Finished Sep 24 04:52:59 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812829711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1812829711
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/23.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.63176741
Short name T475
Test name
Test status
Simulation time 492808728 ps
CPU time 45.36 seconds
Started Sep 24 04:51:25 PM UTC 24
Finished Sep 24 04:52:12 PM UTC 24
Peak memory 214248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63176741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.63176741
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/23.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.3384911062
Short name T9
Test name
Test status
Simulation time 16135464619 ps
CPU time 169.87 seconds
Started Sep 24 04:51:27 PM UTC 24
Finished Sep 24 04:54:20 PM UTC 24
Peak memory 216168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384911062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.3384911062
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/23.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_unmapped_addr.1533921988
Short name T448
Test name
Test status
Simulation time 325941504 ps
CPU time 7.27 seconds
Started Sep 24 04:51:19 PM UTC 24
Finished Sep 24 04:51:28 PM UTC 24
Peak memory 212260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533921988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1533921988
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/23.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device.1836095764
Short name T463
Test name
Test status
Simulation time 295203773 ps
CPU time 6.96 seconds
Started Sep 24 04:51:39 PM UTC 24
Finished Sep 24 04:51:47 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836095764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.1836095764
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/24.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.1377917064
Short name T208
Test name
Test status
Simulation time 98688004052 ps
CPU time 205.08 seconds
Started Sep 24 04:51:43 PM UTC 24
Finished Sep 24 04:55:11 PM UTC 24
Peak memory 214316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377917064 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.1377917064
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/24.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.2912957637
Short name T468
Test name
Test status
Simulation time 590588047 ps
CPU time 10.54 seconds
Started Sep 24 04:51:47 PM UTC 24
Finished Sep 24 04:51:59 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912957637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.2912957637
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/24.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_error_random.1105286435
Short name T464
Test name
Test status
Simulation time 56282829 ps
CPU time 4.84 seconds
Started Sep 24 04:51:47 PM UTC 24
Finished Sep 24 04:51:53 PM UTC 24
Peak memory 211988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105286435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1105286435
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/24.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random.505569220
Short name T460
Test name
Test status
Simulation time 824115266 ps
CPU time 9.95 seconds
Started Sep 24 04:51:33 PM UTC 24
Finished Sep 24 04:51:45 PM UTC 24
Peak memory 212052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505569220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.505569220
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/24.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_large_delays.3949121918
Short name T539
Test name
Test status
Simulation time 111367858755 ps
CPU time 133.32 seconds
Started Sep 24 04:51:37 PM UTC 24
Finished Sep 24 04:53:52 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949121918 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3949121918
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/24.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_slow_rsp.2239984632
Short name T551
Test name
Test status
Simulation time 19368444563 ps
CPU time 155.89 seconds
Started Sep 24 04:51:37 PM UTC 24
Finished Sep 24 04:54:15 PM UTC 24
Peak memory 212056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239984632 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2239984632
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/24.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_zero_delays.326276084
Short name T458
Test name
Test status
Simulation time 34035244 ps
CPU time 4.99 seconds
Started Sep 24 04:51:35 PM UTC 24
Finished Sep 24 04:51:42 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326276084 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.326276084
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/24.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_same_source.2582529264
Short name T469
Test name
Test status
Simulation time 2925720126 ps
CPU time 15.2 seconds
Started Sep 24 04:51:43 PM UTC 24
Finished Sep 24 04:52:00 PM UTC 24
Peak memory 212256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582529264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.2582529264
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/24.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke.3843012201
Short name T452
Test name
Test status
Simulation time 10395133 ps
CPU time 1.99 seconds
Started Sep 24 04:51:29 PM UTC 24
Finished Sep 24 04:51:32 PM UTC 24
Peak memory 210924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843012201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3843012201
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/24.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_large_delays.2179200224
Short name T461
Test name
Test status
Simulation time 1276376913 ps
CPU time 13.08 seconds
Started Sep 24 04:51:31 PM UTC 24
Finished Sep 24 04:51:45 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179200224 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.2179200224
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/24.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.3369630399
Short name T459
Test name
Test status
Simulation time 3174276226 ps
CPU time 8.6 seconds
Started Sep 24 04:51:33 PM UTC 24
Finished Sep 24 04:51:43 PM UTC 24
Peak memory 212052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369630399 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.3369630399
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/24.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1486571010
Short name T453
Test name
Test status
Simulation time 11199174 ps
CPU time 1.92 seconds
Started Sep 24 04:51:31 PM UTC 24
Finished Sep 24 04:51:34 PM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486571010 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1486571010
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/24.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all.2162522555
Short name T527
Test name
Test status
Simulation time 26789946939 ps
CPU time 102.04 seconds
Started Sep 24 04:51:47 PM UTC 24
Finished Sep 24 04:53:31 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162522555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2162522555
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/24.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_error.3429328410
Short name T492
Test name
Test status
Simulation time 2801849744 ps
CPU time 47.39 seconds
Started Sep 24 04:51:47 PM UTC 24
Finished Sep 24 04:52:36 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429328410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3429328410
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/24.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.2530731333
Short name T543
Test name
Test status
Simulation time 966480279 ps
CPU time 137.51 seconds
Started Sep 24 04:51:47 PM UTC 24
Finished Sep 24 04:54:07 PM UTC 24
Peak memory 216080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530731333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.2530731333
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/24.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.1293016606
Short name T501
Test name
Test status
Simulation time 2627840598 ps
CPU time 62.48 seconds
Started Sep 24 04:51:50 PM UTC 24
Finished Sep 24 04:52:54 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293016606 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.1293016606
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/24.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_unmapped_addr.997908589
Short name T470
Test name
Test status
Simulation time 1061039735 ps
CPU time 14.57 seconds
Started Sep 24 04:51:47 PM UTC 24
Finished Sep 24 04:52:03 PM UTC 24
Peak memory 211988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997908589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.997908589
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/24.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device.3924899087
Short name T483
Test name
Test status
Simulation time 1806356205 ps
CPU time 13.91 seconds
Started Sep 24 04:52:04 PM UTC 24
Finished Sep 24 04:52:19 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924899087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3924899087
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/25.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.1714134410
Short name T209
Test name
Test status
Simulation time 297871181310 ps
CPU time 345.57 seconds
Started Sep 24 04:52:04 PM UTC 24
Finished Sep 24 04:57:54 PM UTC 24
Peak memory 214116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714134410 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.1714134410
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/25.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.794930490
Short name T481
Test name
Test status
Simulation time 326167204 ps
CPU time 4.9 seconds
Started Sep 24 04:52:12 PM UTC 24
Finished Sep 24 04:52:18 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794930490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.794930490
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/25.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_error_random.3000305922
Short name T474
Test name
Test status
Simulation time 32921106 ps
CPU time 3.51 seconds
Started Sep 24 04:52:06 PM UTC 24
Finished Sep 24 04:52:11 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000305922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.3000305922
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/25.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random.222970945
Short name T189
Test name
Test status
Simulation time 425801844 ps
CPU time 8.58 seconds
Started Sep 24 04:52:01 PM UTC 24
Finished Sep 24 04:52:11 PM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222970945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.222970945
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/25.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_large_delays.568611792
Short name T560
Test name
Test status
Simulation time 90089659475 ps
CPU time 139.98 seconds
Started Sep 24 04:52:04 PM UTC 24
Finished Sep 24 04:54:26 PM UTC 24
Peak memory 212048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568611792 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.568611792
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/25.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_slow_rsp.23284064
Short name T511
Test name
Test status
Simulation time 7756990778 ps
CPU time 66.43 seconds
Started Sep 24 04:52:04 PM UTC 24
Finished Sep 24 04:53:12 PM UTC 24
Peak memory 212020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23284064 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.23284064
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/25.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_zero_delays.2273489489
Short name T472
Test name
Test status
Simulation time 12931635 ps
CPU time 1.78 seconds
Started Sep 24 04:52:01 PM UTC 24
Finished Sep 24 04:52:04 PM UTC 24
Peak memory 210940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273489489 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.2273489489
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/25.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_same_source.613237162
Short name T477
Test name
Test status
Simulation time 47255584 ps
CPU time 5.79 seconds
Started Sep 24 04:52:06 PM UTC 24
Finished Sep 24 04:52:13 PM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613237162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.613237162
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/25.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke.2501576465
Short name T465
Test name
Test status
Simulation time 62007589 ps
CPU time 2.21 seconds
Started Sep 24 04:51:50 PM UTC 24
Finished Sep 24 04:51:53 PM UTC 24
Peak memory 211980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501576465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.2501576465
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/25.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_large_delays.4267512744
Short name T476
Test name
Test status
Simulation time 2285231887 ps
CPU time 15.56 seconds
Started Sep 24 04:51:55 PM UTC 24
Finished Sep 24 04:52:12 PM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267512744 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.4267512744
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/25.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.187474665
Short name T473
Test name
Test status
Simulation time 1175133279 ps
CPU time 8.54 seconds
Started Sep 24 04:51:58 PM UTC 24
Finished Sep 24 04:52:08 PM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187474665 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.187474665
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/25.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.1643447167
Short name T467
Test name
Test status
Simulation time 10504177 ps
CPU time 2.18 seconds
Started Sep 24 04:51:55 PM UTC 24
Finished Sep 24 04:51:59 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643447167 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.1643447167
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/25.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all.834600436
Short name T564
Test name
Test status
Simulation time 7396608652 ps
CPU time 134.72 seconds
Started Sep 24 04:52:12 PM UTC 24
Finished Sep 24 04:54:29 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834600436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.834600436
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/25.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_error.1106959871
Short name T502
Test name
Test status
Simulation time 679676793 ps
CPU time 39.54 seconds
Started Sep 24 04:52:15 PM UTC 24
Finished Sep 24 04:52:56 PM UTC 24
Peak memory 214056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106959871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1106959871
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/25.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.906580160
Short name T487
Test name
Test status
Simulation time 11366508 ps
CPU time 10.4 seconds
Started Sep 24 04:52:15 PM UTC 24
Finished Sep 24 04:52:26 PM UTC 24
Peak memory 211936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906580160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.906580160
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/25.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.830404136
Short name T541
Test name
Test status
Simulation time 5594673965 ps
CPU time 105.42 seconds
Started Sep 24 04:52:15 PM UTC 24
Finished Sep 24 04:54:03 PM UTC 24
Peak memory 216172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830404136 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.830404136
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/25.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_unmapped_addr.516744685
Short name T479
Test name
Test status
Simulation time 73835624 ps
CPU time 6.59 seconds
Started Sep 24 04:52:09 PM UTC 24
Finished Sep 24 04:52:17 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516744685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.516744685
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/25.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device.2613381906
Short name T490
Test name
Test status
Simulation time 23436624 ps
CPU time 6.16 seconds
Started Sep 24 04:52:27 PM UTC 24
Finished Sep 24 04:52:35 PM UTC 24
Peak memory 212012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613381906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.2613381906
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/26.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.2095456213
Short name T496
Test name
Test status
Simulation time 69917353 ps
CPU time 3.65 seconds
Started Sep 24 04:52:38 PM UTC 24
Finished Sep 24 04:52:42 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095456213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.2095456213
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/26.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_error_random.1163159426
Short name T493
Test name
Test status
Simulation time 58430029 ps
CPU time 4.88 seconds
Started Sep 24 04:52:32 PM UTC 24
Finished Sep 24 04:52:38 PM UTC 24
Peak memory 211988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163159426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.1163159426
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/26.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random.4269942873
Short name T491
Test name
Test status
Simulation time 3235278669 ps
CPU time 11.1 seconds
Started Sep 24 04:52:23 PM UTC 24
Finished Sep 24 04:52:35 PM UTC 24
Peak memory 212044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269942873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.4269942873
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/26.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_large_delays.719399732
Short name T586
Test name
Test status
Simulation time 38364370137 ps
CPU time 165.13 seconds
Started Sep 24 04:52:23 PM UTC 24
Finished Sep 24 04:55:11 PM UTC 24
Peak memory 212264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719399732 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.719399732
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/26.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_slow_rsp.608611615
Short name T549
Test name
Test status
Simulation time 15486528263 ps
CPU time 105.51 seconds
Started Sep 24 04:52:25 PM UTC 24
Finished Sep 24 04:54:13 PM UTC 24
Peak memory 212248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608611615 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.608611615
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/26.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_zero_delays.1488106519
Short name T489
Test name
Test status
Simulation time 32265865 ps
CPU time 5.76 seconds
Started Sep 24 04:52:23 PM UTC 24
Finished Sep 24 04:52:30 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488106519 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.1488106519
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/26.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_same_source.3830630942
Short name T500
Test name
Test status
Simulation time 1574157555 ps
CPU time 18.13 seconds
Started Sep 24 04:52:32 PM UTC 24
Finished Sep 24 04:52:51 PM UTC 24
Peak memory 211996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830630942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.3830630942
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/26.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke.4182764763
Short name T484
Test name
Test status
Simulation time 98458547 ps
CPU time 2.49 seconds
Started Sep 24 04:52:17 PM UTC 24
Finished Sep 24 04:52:20 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182764763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.4182764763
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/26.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_large_delays.3174285327
Short name T495
Test name
Test status
Simulation time 4462123539 ps
CPU time 17.38 seconds
Started Sep 24 04:52:21 PM UTC 24
Finished Sep 24 04:52:39 PM UTC 24
Peak memory 212052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174285327 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3174285327
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/26.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.3111260034
Short name T488
Test name
Test status
Simulation time 1164475110 ps
CPU time 7.55 seconds
Started Sep 24 04:52:21 PM UTC 24
Finished Sep 24 04:52:29 PM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111260034 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.3111260034
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/26.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.833044933
Short name T485
Test name
Test status
Simulation time 10803135 ps
CPU time 1.96 seconds
Started Sep 24 04:52:21 PM UTC 24
Finished Sep 24 04:52:24 PM UTC 24
Peak memory 210896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833044933 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.833044933
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/26.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all.4129656480
Short name T494
Test name
Test status
Simulation time 2600132445 ps
CPU time 39.1 seconds
Started Sep 24 04:52:42 PM UTC 24
Finished Sep 24 04:53:23 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129656480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.4129656480
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/26.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1831789046
Short name T518
Test name
Test status
Simulation time 9045883117 ps
CPU time 35.54 seconds
Started Sep 24 04:52:42 PM UTC 24
Finished Sep 24 04:53:19 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831789046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1831789046
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/26.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.2684663810
Short name T568
Test name
Test status
Simulation time 5045979201 ps
CPU time 115.53 seconds
Started Sep 24 04:52:42 PM UTC 24
Finished Sep 24 04:54:40 PM UTC 24
Peak memory 216172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684663810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.2684663810
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/26.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.4078133758
Short name T519
Test name
Test status
Simulation time 3283537783 ps
CPU time 37.36 seconds
Started Sep 24 04:52:42 PM UTC 24
Finished Sep 24 04:53:21 PM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078133758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.4078133758
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/26.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_unmapped_addr.1305351611
Short name T498
Test name
Test status
Simulation time 59222893 ps
CPU time 9.28 seconds
Started Sep 24 04:52:38 PM UTC 24
Finished Sep 24 04:52:48 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305351611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.1305351611
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/26.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device.554362340
Short name T513
Test name
Test status
Simulation time 54151534 ps
CPU time 13.83 seconds
Started Sep 24 04:52:59 PM UTC 24
Finished Sep 24 04:53:14 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554362340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.554362340
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/27.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.1155549673
Short name T223
Test name
Test status
Simulation time 25967987019 ps
CPU time 143.52 seconds
Started Sep 24 04:52:59 PM UTC 24
Finished Sep 24 04:55:25 PM UTC 24
Peak memory 212076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155549673 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.1155549673
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/27.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.1544472868
Short name T522
Test name
Test status
Simulation time 1475785440 ps
CPU time 15.58 seconds
Started Sep 24 04:53:05 PM UTC 24
Finished Sep 24 04:53:22 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544472868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.1544472868
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/27.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_error_random.3284466490
Short name T514
Test name
Test status
Simulation time 339782250 ps
CPU time 11.16 seconds
Started Sep 24 04:53:03 PM UTC 24
Finished Sep 24 04:53:15 PM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284466490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.3284466490
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/27.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random.1838586377
Short name T506
Test name
Test status
Simulation time 442668499 ps
CPU time 11.11 seconds
Started Sep 24 04:52:52 PM UTC 24
Finished Sep 24 04:53:04 PM UTC 24
Peak memory 211980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838586377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.1838586377
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/27.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_large_delays.2040740848
Short name T616
Test name
Test status
Simulation time 55681321500 ps
CPU time 174.23 seconds
Started Sep 24 04:52:55 PM UTC 24
Finished Sep 24 04:55:52 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040740848 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2040740848
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/27.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_slow_rsp.3430344835
Short name T510
Test name
Test status
Simulation time 2113218476 ps
CPU time 10.82 seconds
Started Sep 24 04:52:59 PM UTC 24
Finished Sep 24 04:53:11 PM UTC 24
Peak memory 212060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430344835 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3430344835
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/27.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_zero_delays.2519450333
Short name T505
Test name
Test status
Simulation time 59452290 ps
CPU time 6.38 seconds
Started Sep 24 04:52:54 PM UTC 24
Finished Sep 24 04:53:01 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519450333 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.2519450333
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/27.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_same_source.1530591982
Short name T509
Test name
Test status
Simulation time 406492735 ps
CPU time 5.69 seconds
Started Sep 24 04:53:01 PM UTC 24
Finished Sep 24 04:53:08 PM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530591982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1530591982
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/27.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke.1998858810
Short name T497
Test name
Test status
Simulation time 89753036 ps
CPU time 2.73 seconds
Started Sep 24 04:52:44 PM UTC 24
Finished Sep 24 04:52:48 PM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998858810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.1998858810
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/27.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_large_delays.2755785962
Short name T512
Test name
Test status
Simulation time 4048694371 ps
CPU time 20.34 seconds
Started Sep 24 04:52:52 PM UTC 24
Finished Sep 24 04:53:13 PM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755785962 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2755785962
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/27.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.2057545054
Short name T507
Test name
Test status
Simulation time 1475550864 ps
CPU time 11.95 seconds
Started Sep 24 04:52:52 PM UTC 24
Finished Sep 24 04:53:05 PM UTC 24
Peak memory 211992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057545054 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.2057545054
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/27.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.4228408405
Short name T499
Test name
Test status
Simulation time 10455517 ps
CPU time 1.78 seconds
Started Sep 24 04:52:47 PM UTC 24
Finished Sep 24 04:52:50 PM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228408405 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.4228408405
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/27.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all.2311605030
Short name T536
Test name
Test status
Simulation time 911267491 ps
CPU time 39.54 seconds
Started Sep 24 04:53:07 PM UTC 24
Finished Sep 24 04:53:49 PM UTC 24
Peak memory 214056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311605030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2311605030
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/27.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_error.2095721194
Short name T515
Test name
Test status
Simulation time 140366745 ps
CPU time 4.93 seconds
Started Sep 24 04:53:09 PM UTC 24
Finished Sep 24 04:53:15 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095721194 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2095721194
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/27.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.482911824
Short name T727
Test name
Test status
Simulation time 16158150514 ps
CPU time 283.14 seconds
Started Sep 24 04:53:07 PM UTC 24
Finished Sep 24 04:57:55 PM UTC 24
Peak memory 218208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482911824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.482911824
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/27.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.299743515
Short name T579
Test name
Test status
Simulation time 1025189077 ps
CPU time 102 seconds
Started Sep 24 04:53:14 PM UTC 24
Finished Sep 24 04:54:58 PM UTC 24
Peak memory 218412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299743515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.299743515
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/27.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_unmapped_addr.2711127268
Short name T508
Test name
Test status
Simulation time 72576828 ps
CPU time 2.79 seconds
Started Sep 24 04:53:03 PM UTC 24
Finished Sep 24 04:53:06 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711127268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2711127268
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/27.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.3197235514
Short name T219
Test name
Test status
Simulation time 18997680766 ps
CPU time 71.63 seconds
Started Sep 24 04:53:25 PM UTC 24
Finished Sep 24 04:54:39 PM UTC 24
Peak memory 212268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197235514 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.3197235514
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/28.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.882030557
Short name T526
Test name
Test status
Simulation time 18969135 ps
CPU time 1.75 seconds
Started Sep 24 04:53:26 PM UTC 24
Finished Sep 24 04:53:29 PM UTC 24
Peak memory 210944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882030557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.882030557
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/28.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_error_random.3482459919
Short name T520
Test name
Test status
Simulation time 8594929 ps
CPU time 1.63 seconds
Started Sep 24 04:53:25 PM UTC 24
Finished Sep 24 04:53:28 PM UTC 24
Peak memory 210944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482459919 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3482459919
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/28.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random.3922175408
Short name T530
Test name
Test status
Simulation time 1869605846 ps
CPU time 18.19 seconds
Started Sep 24 04:53:17 PM UTC 24
Finished Sep 24 04:53:37 PM UTC 24
Peak memory 212032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922175408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.3922175408
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/28.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_large_delays.2256929424
Short name T587
Test name
Test status
Simulation time 26859330364 ps
CPU time 112.04 seconds
Started Sep 24 04:53:20 PM UTC 24
Finished Sep 24 04:55:15 PM UTC 24
Peak memory 212076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256929424 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2256929424
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/28.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_slow_rsp.1379003307
Short name T603
Test name
Test status
Simulation time 20077235652 ps
CPU time 130.64 seconds
Started Sep 24 04:53:25 PM UTC 24
Finished Sep 24 04:55:38 PM UTC 24
Peak memory 212056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379003307 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.1379003307
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/28.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_zero_delays.1894315314
Short name T523
Test name
Test status
Simulation time 80568441 ps
CPU time 5.24 seconds
Started Sep 24 04:53:17 PM UTC 24
Finished Sep 24 04:53:24 PM UTC 24
Peak memory 211848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894315314 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.1894315314
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/28.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_same_source.1109963632
Short name T525
Test name
Test status
Simulation time 149733295 ps
CPU time 2.15 seconds
Started Sep 24 04:53:25 PM UTC 24
Finished Sep 24 04:53:28 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109963632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1109963632
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/28.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke.3631798566
Short name T516
Test name
Test status
Simulation time 15842885 ps
CPU time 1.77 seconds
Started Sep 24 04:53:14 PM UTC 24
Finished Sep 24 04:53:16 PM UTC 24
Peak memory 210924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631798566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.3631798566
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/28.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_large_delays.2837010602
Short name T524
Test name
Test status
Simulation time 2211284594 ps
CPU time 10.09 seconds
Started Sep 24 04:53:16 PM UTC 24
Finished Sep 24 04:53:27 PM UTC 24
Peak memory 212328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837010602 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2837010602
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/28.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.1355390890
Short name T531
Test name
Test status
Simulation time 13463188054 ps
CPU time 21.97 seconds
Started Sep 24 04:53:16 PM UTC 24
Finished Sep 24 04:53:39 PM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355390890 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.1355390890
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/28.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.4282628778
Short name T517
Test name
Test status
Simulation time 14812271 ps
CPU time 1.65 seconds
Started Sep 24 04:53:16 PM UTC 24
Finished Sep 24 04:53:18 PM UTC 24
Peak memory 210940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282628778 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.4282628778
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/28.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all.1180236948
Short name T532
Test name
Test status
Simulation time 229595192 ps
CPU time 12.17 seconds
Started Sep 24 04:53:28 PM UTC 24
Finished Sep 24 04:53:42 PM UTC 24
Peak memory 212016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180236948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.1180236948
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/28.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_error.329800584
Short name T569
Test name
Test status
Simulation time 460876266 ps
CPU time 73.44 seconds
Started Sep 24 04:53:32 PM UTC 24
Finished Sep 24 04:54:47 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329800584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.329800584
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/28.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.2184916007
Short name T599
Test name
Test status
Simulation time 668079666 ps
CPU time 119 seconds
Started Sep 24 04:53:32 PM UTC 24
Finished Sep 24 04:55:33 PM UTC 24
Peak memory 216172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184916007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.2184916007
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/28.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.1877796787
Short name T701
Test name
Test status
Simulation time 8328690512 ps
CPU time 234.23 seconds
Started Sep 24 04:53:32 PM UTC 24
Finished Sep 24 04:57:30 PM UTC 24
Peak memory 216172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877796787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.1877796787
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/28.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_unmapped_addr.2399034049
Short name T533
Test name
Test status
Simulation time 1074411253 ps
CPU time 15.35 seconds
Started Sep 24 04:53:25 PM UTC 24
Finished Sep 24 04:53:42 PM UTC 24
Peak memory 212044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399034049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.2399034049
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/28.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device.3127467615
Short name T544
Test name
Test status
Simulation time 989243841 ps
CPU time 17.86 seconds
Started Sep 24 04:53:49 PM UTC 24
Finished Sep 24 04:54:09 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127467615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.3127467615
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/29.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1451422481
Short name T202
Test name
Test status
Simulation time 68379815720 ps
CPU time 348.7 seconds
Started Sep 24 04:53:50 PM UTC 24
Finished Sep 24 04:59:43 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451422481 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.1451422481
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/29.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.1478372210
Short name T542
Test name
Test status
Simulation time 462040079 ps
CPU time 10.9 seconds
Started Sep 24 04:53:53 PM UTC 24
Finished Sep 24 04:54:05 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478372210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.1478372210
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/29.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_error_random.2407168769
Short name T540
Test name
Test status
Simulation time 34650423 ps
CPU time 4.1 seconds
Started Sep 24 04:53:52 PM UTC 24
Finished Sep 24 04:53:58 PM UTC 24
Peak memory 211988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407168769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.2407168769
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/29.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random.1126946052
Short name T190
Test name
Test status
Simulation time 536502248 ps
CPU time 7.75 seconds
Started Sep 24 04:53:39 PM UTC 24
Finished Sep 24 04:53:48 PM UTC 24
Peak memory 211980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126946052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.1126946052
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/29.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_large_delays.1638786727
Short name T581
Test name
Test status
Simulation time 21059182414 ps
CPU time 82.95 seconds
Started Sep 24 04:53:43 PM UTC 24
Finished Sep 24 04:55:08 PM UTC 24
Peak memory 212268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638786727 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.1638786727
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/29.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1452012730
Short name T151
Test name
Test status
Simulation time 66921615092 ps
CPU time 168.71 seconds
Started Sep 24 04:53:43 PM UTC 24
Finished Sep 24 04:56:35 PM UTC 24
Peak memory 212056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452012730 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1452012730
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/29.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_zero_delays.1069415494
Short name T538
Test name
Test status
Simulation time 57396900 ps
CPU time 8.27 seconds
Started Sep 24 04:53:41 PM UTC 24
Finished Sep 24 04:53:51 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069415494 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.1069415494
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/29.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_same_source.3512004360
Short name T547
Test name
Test status
Simulation time 857368563 ps
CPU time 20.29 seconds
Started Sep 24 04:53:50 PM UTC 24
Finished Sep 24 04:54:11 PM UTC 24
Peak memory 211996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512004360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.3512004360
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/29.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke.1696852868
Short name T528
Test name
Test status
Simulation time 68561605 ps
CPU time 2.71 seconds
Started Sep 24 04:53:32 PM UTC 24
Finished Sep 24 04:53:36 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696852868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.1696852868
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/29.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_large_delays.1975622090
Short name T537
Test name
Test status
Simulation time 1154459749 ps
CPU time 11.56 seconds
Started Sep 24 04:53:38 PM UTC 24
Finished Sep 24 04:53:50 PM UTC 24
Peak memory 211736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975622090 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1975622090
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/29.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.2141081971
Short name T535
Test name
Test status
Simulation time 5619798185 ps
CPU time 8.89 seconds
Started Sep 24 04:53:38 PM UTC 24
Finished Sep 24 04:53:48 PM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141081971 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.2141081971
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/29.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.656662636
Short name T529
Test name
Test status
Simulation time 11396025 ps
CPU time 1.79 seconds
Started Sep 24 04:53:33 PM UTC 24
Finished Sep 24 04:53:36 PM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656662636 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.656662636
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/29.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all.2041503856
Short name T618
Test name
Test status
Simulation time 28819310004 ps
CPU time 118.78 seconds
Started Sep 24 04:53:54 PM UTC 24
Finished Sep 24 04:55:55 PM UTC 24
Peak memory 214380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041503856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.2041503856
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/29.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_error.2819537744
Short name T545
Test name
Test status
Simulation time 202297357 ps
CPU time 9.76 seconds
Started Sep 24 04:53:59 PM UTC 24
Finished Sep 24 04:54:10 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819537744 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.2819537744
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/29.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.1844184951
Short name T656
Test name
Test status
Simulation time 2938684694 ps
CPU time 150.87 seconds
Started Sep 24 04:54:04 PM UTC 24
Finished Sep 24 04:56:37 PM UTC 24
Peak memory 216168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844184951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.1844184951
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/29.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_unmapped_addr.1173863094
Short name T548
Test name
Test status
Simulation time 4189900843 ps
CPU time 18.5 seconds
Started Sep 24 04:53:53 PM UTC 24
Finished Sep 24 04:54:13 PM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173863094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.1173863094
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/29.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.751240690
Short name T242
Test name
Test status
Simulation time 264319686 ps
CPU time 2.09 seconds
Started Sep 24 04:40:37 PM UTC 24
Finished Sep 24 04:40:41 PM UTC 24
Peak memory 212012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751240690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.751240690
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/3.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_error_random.1918511454
Short name T220
Test name
Test status
Simulation time 636221944 ps
CPU time 17.24 seconds
Started Sep 24 04:40:31 PM UTC 24
Finished Sep 24 04:40:50 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918511454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.1918511454
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/3.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random.2958634244
Short name T50
Test name
Test status
Simulation time 26306631 ps
CPU time 3.87 seconds
Started Sep 24 04:40:24 PM UTC 24
Finished Sep 24 04:40:29 PM UTC 24
Peak memory 211980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958634244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.2958634244
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/3.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_large_delays.411800030
Short name T83
Test name
Test status
Simulation time 51967147636 ps
CPU time 269.07 seconds
Started Sep 24 04:40:24 PM UTC 24
Finished Sep 24 04:44:57 PM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411800030 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.411800030
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/3.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_slow_rsp.2418992273
Short name T243
Test name
Test status
Simulation time 8065781566 ps
CPU time 25.4 seconds
Started Sep 24 04:40:29 PM UTC 24
Finished Sep 24 04:40:56 PM UTC 24
Peak memory 212052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418992273 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.2418992273
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/3.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_zero_delays.2937252013
Short name T51
Test name
Test status
Simulation time 82884773 ps
CPU time 4.6 seconds
Started Sep 24 04:40:24 PM UTC 24
Finished Sep 24 04:40:30 PM UTC 24
Peak memory 211996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937252013 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.2937252013
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/3.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_same_source.4144612568
Short name T241
Test name
Test status
Simulation time 15027126 ps
CPU time 2.89 seconds
Started Sep 24 04:40:30 PM UTC 24
Finished Sep 24 04:40:34 PM UTC 24
Peak memory 211996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144612568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.4144612568
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/3.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke.3469781379
Short name T48
Test name
Test status
Simulation time 146212321 ps
CPU time 2.61 seconds
Started Sep 24 04:40:10 PM UTC 24
Finished Sep 24 04:40:14 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469781379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3469781379
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/3.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_large_delays.3267381332
Short name T63
Test name
Test status
Simulation time 2969969345 ps
CPU time 16.81 seconds
Started Sep 24 04:40:19 PM UTC 24
Finished Sep 24 04:40:37 PM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267381332 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3267381332
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/3.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.3764284742
Short name T240
Test name
Test status
Simulation time 4375013492 ps
CPU time 9.03 seconds
Started Sep 24 04:40:20 PM UTC 24
Finished Sep 24 04:40:30 PM UTC 24
Peak memory 212048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764284742 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.3764284742
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/3.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.1734913655
Short name T49
Test name
Test status
Simulation time 24633672 ps
CPU time 2.06 seconds
Started Sep 24 04:40:16 PM UTC 24
Finished Sep 24 04:40:19 PM UTC 24
Peak memory 212252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734913655 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.1734913655
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/3.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all.3561729162
Short name T74
Test name
Test status
Simulation time 3325917492 ps
CPU time 74.41 seconds
Started Sep 24 04:40:42 PM UTC 24
Finished Sep 24 04:41:58 PM UTC 24
Peak memory 214380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561729162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.3561729162
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/3.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_error.3310347379
Short name T192
Test name
Test status
Simulation time 13925172207 ps
CPU time 126.74 seconds
Started Sep 24 04:40:49 PM UTC 24
Finished Sep 24 04:42:58 PM UTC 24
Peak memory 214312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310347379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3310347379
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/3.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.947981473
Short name T232
Test name
Test status
Simulation time 2909242705 ps
CPU time 163.01 seconds
Started Sep 24 04:40:51 PM UTC 24
Finished Sep 24 04:43:37 PM UTC 24
Peak memory 218220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947981473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.947981473
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/3.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_unmapped_addr.4176525288
Short name T64
Test name
Test status
Simulation time 510037887 ps
CPU time 11.2 seconds
Started Sep 24 04:40:35 PM UTC 24
Finished Sep 24 04:40:48 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176525288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.4176525288
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/3.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device.987930834
Short name T553
Test name
Test status
Simulation time 128534557 ps
CPU time 2.99 seconds
Started Sep 24 04:54:16 PM UTC 24
Finished Sep 24 04:54:20 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987930834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.987930834
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/30.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3136218536
Short name T562
Test name
Test status
Simulation time 24241242 ps
CPU time 3.54 seconds
Started Sep 24 04:54:22 PM UTC 24
Finished Sep 24 04:54:27 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136218536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3136218536
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/30.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_error_random.1367127725
Short name T557
Test name
Test status
Simulation time 114001779 ps
CPU time 2.9 seconds
Started Sep 24 04:54:19 PM UTC 24
Finished Sep 24 04:54:23 PM UTC 24
Peak memory 212244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367127725 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.1367127725
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/30.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random.1074572182
Short name T554
Test name
Test status
Simulation time 58481010 ps
CPU time 8.17 seconds
Started Sep 24 04:54:11 PM UTC 24
Finished Sep 24 04:54:21 PM UTC 24
Peak memory 212176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074572182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.1074572182
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/30.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.934577384
Short name T596
Test name
Test status
Simulation time 16114170193 ps
CPU time 74.07 seconds
Started Sep 24 04:54:13 PM UTC 24
Finished Sep 24 04:55:29 PM UTC 24
Peak memory 212328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934577384 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.934577384
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/30.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_slow_rsp.300277594
Short name T121
Test name
Test status
Simulation time 59504981293 ps
CPU time 156.14 seconds
Started Sep 24 04:54:16 PM UTC 24
Finished Sep 24 04:56:55 PM UTC 24
Peak memory 212056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300277594 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.300277594
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/30.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_zero_delays.3330419624
Short name T552
Test name
Test status
Simulation time 23100614 ps
CPU time 3.25 seconds
Started Sep 24 04:54:13 PM UTC 24
Finished Sep 24 04:54:17 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330419624 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.3330419624
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/30.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_same_source.1884942864
Short name T556
Test name
Test status
Simulation time 1698374720 ps
CPU time 4.14 seconds
Started Sep 24 04:54:17 PM UTC 24
Finished Sep 24 04:54:22 PM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884942864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.1884942864
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/30.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke.130786593
Short name T546
Test name
Test status
Simulation time 54304560 ps
CPU time 2.4 seconds
Started Sep 24 04:54:07 PM UTC 24
Finished Sep 24 04:54:10 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130786593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.130786593
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/30.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_large_delays.4122515897
Short name T558
Test name
Test status
Simulation time 1531458037 ps
CPU time 10.67 seconds
Started Sep 24 04:54:11 PM UTC 24
Finished Sep 24 04:54:23 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122515897 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.4122515897
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/30.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2966281897
Short name T561
Test name
Test status
Simulation time 1180495066 ps
CPU time 13.83 seconds
Started Sep 24 04:54:11 PM UTC 24
Finished Sep 24 04:54:26 PM UTC 24
Peak memory 211988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966281897 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2966281897
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/30.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.3284198818
Short name T550
Test name
Test status
Simulation time 11309428 ps
CPU time 1.68 seconds
Started Sep 24 04:54:11 PM UTC 24
Finished Sep 24 04:54:14 PM UTC 24
Peak memory 210940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284198818 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.3284198818
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/30.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all.753377192
Short name T607
Test name
Test status
Simulation time 3416531289 ps
CPU time 78.19 seconds
Started Sep 24 04:54:22 PM UTC 24
Finished Sep 24 04:55:42 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753377192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.753377192
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/30.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_error.1526878021
Short name T583
Test name
Test status
Simulation time 564708231 ps
CPU time 42.28 seconds
Started Sep 24 04:54:26 PM UTC 24
Finished Sep 24 04:55:09 PM UTC 24
Peak memory 212200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526878021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1526878021
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/30.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2836806797
Short name T650
Test name
Test status
Simulation time 1149460873 ps
CPU time 123.82 seconds
Started Sep 24 04:54:26 PM UTC 24
Finished Sep 24 04:56:32 PM UTC 24
Peak memory 216096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836806797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.2836806797
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/30.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.2337404986
Short name T680
Test name
Test status
Simulation time 1016505742 ps
CPU time 158.31 seconds
Started Sep 24 04:54:26 PM UTC 24
Finished Sep 24 04:57:07 PM UTC 24
Peak memory 216084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337404986 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.2337404986
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/30.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_unmapped_addr.1912438630
Short name T148
Test name
Test status
Simulation time 428240239 ps
CPU time 11.72 seconds
Started Sep 24 04:54:22 PM UTC 24
Finished Sep 24 04:54:35 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912438630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1912438630
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/30.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device.1016046786
Short name T118
Test name
Test status
Simulation time 571771290 ps
CPU time 21.69 seconds
Started Sep 24 04:54:35 PM UTC 24
Finished Sep 24 04:54:58 PM UTC 24
Peak memory 212268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016046786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.1016046786
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/31.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.1899191740
Short name T698
Test name
Test status
Simulation time 28041364604 ps
CPU time 169.44 seconds
Started Sep 24 04:54:35 PM UTC 24
Finished Sep 24 04:57:28 PM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899191740 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.1899191740
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/31.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.2713422325
Short name T571
Test name
Test status
Simulation time 129133176 ps
CPU time 7.39 seconds
Started Sep 24 04:54:41 PM UTC 24
Finished Sep 24 04:54:50 PM UTC 24
Peak memory 212204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713422325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.2713422325
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/31.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_error_random.2880617046
Short name T573
Test name
Test status
Simulation time 1339710053 ps
CPU time 12.84 seconds
Started Sep 24 04:54:39 PM UTC 24
Finished Sep 24 04:54:53 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880617046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.2880617046
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/31.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random.1827370646
Short name T566
Test name
Test status
Simulation time 293466427 ps
CPU time 3.69 seconds
Started Sep 24 04:54:29 PM UTC 24
Finished Sep 24 04:54:34 PM UTC 24
Peak memory 211980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827370646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.1827370646
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/31.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_large_delays.286213419
Short name T610
Test name
Test status
Simulation time 25918742726 ps
CPU time 72.66 seconds
Started Sep 24 04:54:31 PM UTC 24
Finished Sep 24 04:55:45 PM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286213419 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.286213419
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/31.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_slow_rsp.394358409
Short name T608
Test name
Test status
Simulation time 11349614494 ps
CPU time 68.63 seconds
Started Sep 24 04:54:33 PM UTC 24
Finished Sep 24 04:55:44 PM UTC 24
Peak memory 212048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394358409 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.394358409
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/31.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_zero_delays.3714593724
Short name T567
Test name
Test status
Simulation time 41866427 ps
CPU time 5.37 seconds
Started Sep 24 04:54:31 PM UTC 24
Finished Sep 24 04:54:37 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714593724 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.3714593724
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/31.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_same_source.1554877802
Short name T575
Test name
Test status
Simulation time 838057852 ps
CPU time 18.21 seconds
Started Sep 24 04:54:37 PM UTC 24
Finished Sep 24 04:54:56 PM UTC 24
Peak memory 211996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554877802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1554877802
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/31.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke.2316798443
Short name T563
Test name
Test status
Simulation time 12105270 ps
CPU time 1.99 seconds
Started Sep 24 04:54:26 PM UTC 24
Finished Sep 24 04:54:29 PM UTC 24
Peak memory 210968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316798443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2316798443
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/31.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_large_delays.18704449
Short name T572
Test name
Test status
Simulation time 8655326355 ps
CPU time 20.31 seconds
Started Sep 24 04:54:29 PM UTC 24
Finished Sep 24 04:54:51 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18704449 -assert nopostproc +UVM_TESTNAME=xbar_base_
test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.18704449
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/31.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.3654543885
Short name T570
Test name
Test status
Simulation time 2699367712 ps
CPU time 18.73 seconds
Started Sep 24 04:54:29 PM UTC 24
Finished Sep 24 04:54:49 PM UTC 24
Peak memory 212052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654543885 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3654543885
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/31.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.1612864518
Short name T565
Test name
Test status
Simulation time 10571054 ps
CPU time 1.65 seconds
Started Sep 24 04:54:29 PM UTC 24
Finished Sep 24 04:54:32 PM UTC 24
Peak memory 210936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612864518 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.1612864518
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/31.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all.1014294798
Short name T662
Test name
Test status
Simulation time 24383183801 ps
CPU time 120.19 seconds
Started Sep 24 04:54:41 PM UTC 24
Finished Sep 24 04:56:44 PM UTC 24
Peak memory 214316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014294798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.1014294798
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/31.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_error.695747199
Short name T582
Test name
Test status
Simulation time 3779633229 ps
CPU time 15.91 seconds
Started Sep 24 04:54:52 PM UTC 24
Finished Sep 24 04:55:09 PM UTC 24
Peak memory 212064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695747199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.695747199
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/31.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.2728321588
Short name T590
Test name
Test status
Simulation time 156884717 ps
CPU time 29.03 seconds
Started Sep 24 04:54:49 PM UTC 24
Finished Sep 24 04:55:19 PM UTC 24
Peak memory 214056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728321588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.2728321588
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/31.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.647010228
Short name T598
Test name
Test status
Simulation time 2027079801 ps
CPU time 39.43 seconds
Started Sep 24 04:54:52 PM UTC 24
Finished Sep 24 04:55:32 PM UTC 24
Peak memory 212204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647010228 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.647010228
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/31.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_unmapped_addr.1309154989
Short name T574
Test name
Test status
Simulation time 1440402652 ps
CPU time 12.05 seconds
Started Sep 24 04:54:41 PM UTC 24
Finished Sep 24 04:54:55 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309154989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1309154989
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/31.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device.1074940063
Short name T119
Test name
Test status
Simulation time 3464532686 ps
CPU time 32.82 seconds
Started Sep 24 04:55:06 PM UTC 24
Finished Sep 24 04:55:41 PM UTC 24
Peak memory 212076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074940063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.1074940063
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/32.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1153307634
Short name T228
Test name
Test status
Simulation time 10243617418 ps
CPU time 67.18 seconds
Started Sep 24 04:55:10 PM UTC 24
Finished Sep 24 04:56:19 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153307634 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.1153307634
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/32.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2887463952
Short name T594
Test name
Test status
Simulation time 948803441 ps
CPU time 10.36 seconds
Started Sep 24 04:55:13 PM UTC 24
Finished Sep 24 04:55:24 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887463952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.2887463952
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/32.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_error_random.123617176
Short name T591
Test name
Test status
Simulation time 540642650 ps
CPU time 8.38 seconds
Started Sep 24 04:55:12 PM UTC 24
Finished Sep 24 04:55:22 PM UTC 24
Peak memory 211836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123617176 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.123617176
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/32.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random.2987755737
Short name T584
Test name
Test status
Simulation time 73511331 ps
CPU time 9.74 seconds
Started Sep 24 04:54:59 PM UTC 24
Finished Sep 24 04:55:10 PM UTC 24
Peak memory 211980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987755737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.2987755737
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/32.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.3089957562
Short name T786
Test name
Test status
Simulation time 52494953878 ps
CPU time 238.15 seconds
Started Sep 24 04:55:01 PM UTC 24
Finished Sep 24 04:59:02 PM UTC 24
Peak memory 212064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089957562 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3089957562
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/32.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.1107774486
Short name T636
Test name
Test status
Simulation time 29965614218 ps
CPU time 77.66 seconds
Started Sep 24 04:55:01 PM UTC 24
Finished Sep 24 04:56:20 PM UTC 24
Peak memory 212032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107774486 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.1107774486
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/32.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_zero_delays.1479378674
Short name T580
Test name
Test status
Simulation time 70282455 ps
CPU time 4.99 seconds
Started Sep 24 04:54:59 PM UTC 24
Finished Sep 24 04:55:05 PM UTC 24
Peak memory 212196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479378674 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.1479378674
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/32.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_same_source.1291020495
Short name T601
Test name
Test status
Simulation time 2327467575 ps
CPU time 22.68 seconds
Started Sep 24 04:55:10 PM UTC 24
Finished Sep 24 04:55:34 PM UTC 24
Peak memory 212060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291020495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1291020495
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/32.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke.1529888375
Short name T576
Test name
Test status
Simulation time 63985135 ps
CPU time 2.52 seconds
Started Sep 24 04:54:53 PM UTC 24
Finished Sep 24 04:54:57 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529888375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.1529888375
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/32.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_large_delays.1918950553
Short name T585
Test name
Test status
Simulation time 2241455632 ps
CPU time 12.39 seconds
Started Sep 24 04:54:56 PM UTC 24
Finished Sep 24 04:55:10 PM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918950553 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.1918950553
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/32.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.146004539
Short name T588
Test name
Test status
Simulation time 3992542224 ps
CPU time 17.24 seconds
Started Sep 24 04:54:59 PM UTC 24
Finished Sep 24 04:55:17 PM UTC 24
Peak memory 212048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146004539 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.146004539
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/32.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.214415515
Short name T577
Test name
Test status
Simulation time 39551980 ps
CPU time 2.14 seconds
Started Sep 24 04:54:55 PM UTC 24
Finished Sep 24 04:54:58 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214415515 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.214415515
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/32.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all.1964096543
Short name T647
Test name
Test status
Simulation time 3725771514 ps
CPU time 68.81 seconds
Started Sep 24 04:55:16 PM UTC 24
Finished Sep 24 04:56:26 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964096543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1964096543
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/32.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_error.179597253
Short name T592
Test name
Test status
Simulation time 367898563 ps
CPU time 5.41 seconds
Started Sep 24 04:55:16 PM UTC 24
Finished Sep 24 04:55:22 PM UTC 24
Peak memory 214200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179597253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.179597253
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/32.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2293396824
Short name T602
Test name
Test status
Simulation time 122671535 ps
CPU time 17.98 seconds
Started Sep 24 04:55:16 PM UTC 24
Finished Sep 24 04:55:35 PM UTC 24
Peak memory 214060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293396824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.2293396824
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/32.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.2873515178
Short name T635
Test name
Test status
Simulation time 589710598 ps
CPU time 57.64 seconds
Started Sep 24 04:55:19 PM UTC 24
Finished Sep 24 04:56:19 PM UTC 24
Peak memory 216300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873515178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.2873515178
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/32.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_unmapped_addr.1412233042
Short name T589
Test name
Test status
Simulation time 180851966 ps
CPU time 5.05 seconds
Started Sep 24 04:55:12 PM UTC 24
Finished Sep 24 04:55:19 PM UTC 24
Peak memory 212076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412233042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1412233042
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/32.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device.1729872642
Short name T605
Test name
Test status
Simulation time 49277833 ps
CPU time 6.75 seconds
Started Sep 24 04:55:32 PM UTC 24
Finished Sep 24 04:55:40 PM UTC 24
Peak memory 212204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729872642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.1729872642
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/33.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.4229990899
Short name T615
Test name
Test status
Simulation time 4853444248 ps
CPU time 18.02 seconds
Started Sep 24 04:55:32 PM UTC 24
Finished Sep 24 04:55:52 PM UTC 24
Peak memory 212076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229990899 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.4229990899
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/33.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.1418918879
Short name T613
Test name
Test status
Simulation time 267536365 ps
CPU time 6.34 seconds
Started Sep 24 04:55:41 PM UTC 24
Finished Sep 24 04:55:48 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418918879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.1418918879
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/33.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_error_random.1773471902
Short name T611
Test name
Test status
Simulation time 241137667 ps
CPU time 7.6 seconds
Started Sep 24 04:55:37 PM UTC 24
Finished Sep 24 04:55:46 PM UTC 24
Peak memory 212052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773471902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.1773471902
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/33.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random.3953254679
Short name T597
Test name
Test status
Simulation time 10931995 ps
CPU time 1.79 seconds
Started Sep 24 04:55:27 PM UTC 24
Finished Sep 24 04:55:30 PM UTC 24
Peak memory 210920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953254679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.3953254679
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/33.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_large_delays.4006683399
Short name T619
Test name
Test status
Simulation time 8167691618 ps
CPU time 26.98 seconds
Started Sep 24 04:55:27 PM UTC 24
Finished Sep 24 04:55:55 PM UTC 24
Peak memory 212076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006683399 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.4006683399
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/33.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_slow_rsp.534412528
Short name T695
Test name
Test status
Simulation time 14362183203 ps
CPU time 110.95 seconds
Started Sep 24 04:55:32 PM UTC 24
Finished Sep 24 04:57:26 PM UTC 24
Peak memory 211840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534412528 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.534412528
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/33.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_zero_delays.4276816662
Short name T600
Test name
Test status
Simulation time 25708256 ps
CPU time 5.2 seconds
Started Sep 24 04:55:27 PM UTC 24
Finished Sep 24 04:55:33 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276816662 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.4276816662
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/33.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_same_source.2861284088
Short name T604
Test name
Test status
Simulation time 61199695 ps
CPU time 4.65 seconds
Started Sep 24 04:55:32 PM UTC 24
Finished Sep 24 04:55:38 PM UTC 24
Peak memory 211996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861284088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.2861284088
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/33.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke.2617280051
Short name T595
Test name
Test status
Simulation time 170375628 ps
CPU time 2.67 seconds
Started Sep 24 04:55:21 PM UTC 24
Finished Sep 24 04:55:25 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617280051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2617280051
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/33.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_large_delays.3579428386
Short name T37
Test name
Test status
Simulation time 1070926413 ps
CPU time 11.41 seconds
Started Sep 24 04:55:23 PM UTC 24
Finished Sep 24 04:55:36 PM UTC 24
Peak memory 212264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579428386 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.3579428386
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/33.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.265273843
Short name T606
Test name
Test status
Simulation time 2533301496 ps
CPU time 16.67 seconds
Started Sep 24 04:55:23 PM UTC 24
Finished Sep 24 04:55:41 PM UTC 24
Peak memory 212052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265273843 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.265273843
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/33.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.1701520149
Short name T593
Test name
Test status
Simulation time 9131196 ps
CPU time 1.63 seconds
Started Sep 24 04:55:21 PM UTC 24
Finished Sep 24 04:55:24 PM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701520149 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.1701520149
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/33.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all.2437564197
Short name T637
Test name
Test status
Simulation time 3239215230 ps
CPU time 37.68 seconds
Started Sep 24 04:55:41 PM UTC 24
Finished Sep 24 04:56:20 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437564197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.2437564197
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/33.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_error.3603803707
Short name T578
Test name
Test status
Simulation time 879666113 ps
CPU time 53.6 seconds
Started Sep 24 04:55:41 PM UTC 24
Finished Sep 24 04:56:37 PM UTC 24
Peak memory 214248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603803707 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3603803707
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/33.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.496312457
Short name T747
Test name
Test status
Simulation time 741022629 ps
CPU time 158.76 seconds
Started Sep 24 04:55:41 PM UTC 24
Finished Sep 24 04:58:23 PM UTC 24
Peak memory 216060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496312457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.496312457
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/33.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.3771866208
Short name T704
Test name
Test status
Simulation time 3498154482 ps
CPU time 109.61 seconds
Started Sep 24 04:55:41 PM UTC 24
Finished Sep 24 04:57:33 PM UTC 24
Peak memory 216172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771866208 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.3771866208
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/33.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_unmapped_addr.2506711537
Short name T621
Test name
Test status
Simulation time 763886071 ps
CPU time 17.93 seconds
Started Sep 24 04:55:37 PM UTC 24
Finished Sep 24 04:55:56 PM UTC 24
Peak memory 212196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506711537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.2506711537
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/33.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device.1078487306
Short name T617
Test name
Test status
Simulation time 30573490 ps
CPU time 5.62 seconds
Started Sep 24 04:55:48 PM UTC 24
Finished Sep 24 04:55:54 PM UTC 24
Peak memory 212204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078487306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.1078487306
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/34.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.747429307
Short name T888
Test name
Test status
Simulation time 74461694626 ps
CPU time 333.2 seconds
Started Sep 24 04:55:48 PM UTC 24
Finished Sep 24 05:01:25 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747429307 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.747429307
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/34.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.1478780488
Short name T632
Test name
Test status
Simulation time 5260397418 ps
CPU time 18.12 seconds
Started Sep 24 04:55:54 PM UTC 24
Finished Sep 24 04:56:13 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478780488 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.1478780488
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/34.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_error_random.4275699959
Short name T623
Test name
Test status
Simulation time 19069869 ps
CPU time 3.08 seconds
Started Sep 24 04:55:54 PM UTC 24
Finished Sep 24 04:55:58 PM UTC 24
Peak memory 211988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275699959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.4275699959
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/34.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random.3694325605
Short name T614
Test name
Test status
Simulation time 26860867 ps
CPU time 4.44 seconds
Started Sep 24 04:55:45 PM UTC 24
Finished Sep 24 04:55:51 PM UTC 24
Peak memory 211980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694325605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.3694325605
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/34.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.950968163
Short name T702
Test name
Test status
Simulation time 62883508860 ps
CPU time 100.79 seconds
Started Sep 24 04:55:47 PM UTC 24
Finished Sep 24 04:57:30 PM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950968163 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.950968163
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/34.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_slow_rsp.467411715
Short name T669
Test name
Test status
Simulation time 41114619835 ps
CPU time 65.55 seconds
Started Sep 24 04:55:47 PM UTC 24
Finished Sep 24 04:56:55 PM UTC 24
Peak memory 212052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467411715 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.467411715
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/34.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_zero_delays.2842811583
Short name T620
Test name
Test status
Simulation time 92080889 ps
CPU time 9.27 seconds
Started Sep 24 04:55:45 PM UTC 24
Finished Sep 24 04:55:56 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842811583 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.2842811583
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/34.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_same_source.1920343942
Short name T622
Test name
Test status
Simulation time 286972947 ps
CPU time 7.04 seconds
Started Sep 24 04:55:49 PM UTC 24
Finished Sep 24 04:55:57 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920343942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.1920343942
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/34.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke.44435219
Short name T609
Test name
Test status
Simulation time 108532017 ps
CPU time 2.75 seconds
Started Sep 24 04:55:41 PM UTC 24
Finished Sep 24 04:55:45 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44435219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs
/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.44435219
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/34.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_large_delays.97407133
Short name T624
Test name
Test status
Simulation time 2127861843 ps
CPU time 11.97 seconds
Started Sep 24 04:55:45 PM UTC 24
Finished Sep 24 04:55:58 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97407133 -assert nopostproc +UVM_TESTNAME=xbar_base_
test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.97407133
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/34.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.2467714207
Short name T628
Test name
Test status
Simulation time 2202734931 ps
CPU time 18.9 seconds
Started Sep 24 04:55:45 PM UTC 24
Finished Sep 24 04:56:05 PM UTC 24
Peak memory 212052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467714207 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.2467714207
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/34.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.2981591658
Short name T612
Test name
Test status
Simulation time 12851014 ps
CPU time 1.45 seconds
Started Sep 24 04:55:45 PM UTC 24
Finished Sep 24 04:55:47 PM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981591658 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.2981591658
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/34.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all.3472204832
Short name T646
Test name
Test status
Simulation time 5582361904 ps
CPU time 30.91 seconds
Started Sep 24 04:55:54 PM UTC 24
Finished Sep 24 04:56:26 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472204832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.3472204832
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/34.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_error.2007339155
Short name T645
Test name
Test status
Simulation time 729341400 ps
CPU time 27.95 seconds
Started Sep 24 04:55:57 PM UTC 24
Finished Sep 24 04:56:26 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007339155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.2007339155
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/34.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.4175848185
Short name T629
Test name
Test status
Simulation time 7515858 ps
CPU time 7.39 seconds
Started Sep 24 04:55:57 PM UTC 24
Finished Sep 24 04:56:06 PM UTC 24
Peak memory 212012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175848185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.4175848185
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/34.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.770743451
Short name T657
Test name
Test status
Simulation time 295679324 ps
CPU time 39.58 seconds
Started Sep 24 04:55:57 PM UTC 24
Finished Sep 24 04:56:38 PM UTC 24
Peak memory 214060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770743451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.770743451
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/34.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_unmapped_addr.2321245283
Short name T627
Test name
Test status
Simulation time 56664324 ps
CPU time 7.77 seconds
Started Sep 24 04:55:54 PM UTC 24
Finished Sep 24 04:56:03 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321245283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.2321245283
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/34.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device.4138717574
Short name T639
Test name
Test status
Simulation time 1006349153 ps
CPU time 12.13 seconds
Started Sep 24 04:56:08 PM UTC 24
Finished Sep 24 04:56:21 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138717574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.4138717574
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/35.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.3090433769
Short name T678
Test name
Test status
Simulation time 11834841027 ps
CPU time 52.56 seconds
Started Sep 24 04:56:08 PM UTC 24
Finished Sep 24 04:57:02 PM UTC 24
Peak memory 214116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090433769 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.3090433769
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/35.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1419877456
Short name T642
Test name
Test status
Simulation time 311751481 ps
CPU time 4.3 seconds
Started Sep 24 04:56:16 PM UTC 24
Finished Sep 24 04:56:22 PM UTC 24
Peak memory 212012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419877456 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.1419877456
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/35.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_error_random.1820256402
Short name T640
Test name
Test status
Simulation time 146845791 ps
CPU time 12.03 seconds
Started Sep 24 04:56:08 PM UTC 24
Finished Sep 24 04:56:21 PM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820256402 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.1820256402
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/35.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random.3244382827
Short name T634
Test name
Test status
Simulation time 596234672 ps
CPU time 13.13 seconds
Started Sep 24 04:56:04 PM UTC 24
Finished Sep 24 04:56:19 PM UTC 24
Peak memory 211980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244382827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.3244382827
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/35.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.1049168907
Short name T763
Test name
Test status
Simulation time 78147672098 ps
CPU time 154.65 seconds
Started Sep 24 04:56:04 PM UTC 24
Finished Sep 24 04:58:42 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049168907 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.1049168907
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/35.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.3233998953
Short name T692
Test name
Test status
Simulation time 47984964613 ps
CPU time 72.67 seconds
Started Sep 24 04:56:08 PM UTC 24
Finished Sep 24 04:57:22 PM UTC 24
Peak memory 212032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233998953 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3233998953
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/35.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_zero_delays.3622541057
Short name T630
Test name
Test status
Simulation time 55886016 ps
CPU time 5.83 seconds
Started Sep 24 04:56:04 PM UTC 24
Finished Sep 24 04:56:11 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622541057 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.3622541057
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/35.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_same_source.3464882500
Short name T641
Test name
Test status
Simulation time 3376517627 ps
CPU time 12.13 seconds
Started Sep 24 04:56:08 PM UTC 24
Finished Sep 24 04:56:21 PM UTC 24
Peak memory 212060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464882500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3464882500
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/35.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke.2611330486
Short name T625
Test name
Test status
Simulation time 57616237 ps
CPU time 2.31 seconds
Started Sep 24 04:55:57 PM UTC 24
Finished Sep 24 04:56:00 PM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611330486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.2611330486
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/35.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1332035089
Short name T633
Test name
Test status
Simulation time 1946195604 ps
CPU time 17.47 seconds
Started Sep 24 04:56:00 PM UTC 24
Finished Sep 24 04:56:18 PM UTC 24
Peak memory 212136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332035089 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1332035089
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/35.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.1991827650
Short name T631
Test name
Test status
Simulation time 5078162264 ps
CPU time 10.5 seconds
Started Sep 24 04:56:00 PM UTC 24
Finished Sep 24 04:56:12 PM UTC 24
Peak memory 212052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991827650 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1991827650
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/35.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.819335897
Short name T626
Test name
Test status
Simulation time 39493854 ps
CPU time 1.96 seconds
Started Sep 24 04:56:00 PM UTC 24
Finished Sep 24 04:56:03 PM UTC 24
Peak memory 210940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819335897 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.819335897
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/35.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all.86233697
Short name T648
Test name
Test status
Simulation time 201083004 ps
CPU time 11.13 seconds
Started Sep 24 04:56:16 PM UTC 24
Finished Sep 24 04:56:29 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86233697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-si
m-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.86233697
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/35.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_error.2073308668
Short name T710
Test name
Test status
Simulation time 6119965689 ps
CPU time 74.87 seconds
Started Sep 24 04:56:22 PM UTC 24
Finished Sep 24 04:57:39 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073308668 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.2073308668
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/35.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1220506007
Short name T697
Test name
Test status
Simulation time 226552282 ps
CPU time 68.38 seconds
Started Sep 24 04:56:16 PM UTC 24
Finished Sep 24 04:57:27 PM UTC 24
Peak memory 216104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220506007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.1220506007
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/35.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.2643924894
Short name T664
Test name
Test status
Simulation time 255404446 ps
CPU time 21.54 seconds
Started Sep 24 04:56:22 PM UTC 24
Finished Sep 24 04:56:45 PM UTC 24
Peak memory 214252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643924894 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.2643924894
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/35.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_unmapped_addr.3875755951
Short name T638
Test name
Test status
Simulation time 631333706 ps
CPU time 6.77 seconds
Started Sep 24 04:56:13 PM UTC 24
Finished Sep 24 04:56:20 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875755951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3875755951
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/35.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device.4163579290
Short name T652
Test name
Test status
Simulation time 54911011 ps
CPU time 3.18 seconds
Started Sep 24 04:56:28 PM UTC 24
Finished Sep 24 04:56:32 PM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163579290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.4163579290
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/36.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.938694784
Short name T212
Test name
Test status
Simulation time 28029088553 ps
CPU time 200.55 seconds
Started Sep 24 04:56:28 PM UTC 24
Finished Sep 24 04:59:51 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938694784 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.938694784
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/36.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.2030390107
Short name T651
Test name
Test status
Simulation time 56346617 ps
CPU time 5.02 seconds
Started Sep 24 04:56:30 PM UTC 24
Finished Sep 24 04:56:36 PM UTC 24
Peak memory 211996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030390107 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.2030390107
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/36.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_error_random.228381653
Short name T653
Test name
Test status
Simulation time 29484123 ps
CPU time 5.28 seconds
Started Sep 24 04:56:28 PM UTC 24
Finished Sep 24 04:56:34 PM UTC 24
Peak memory 212048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228381653 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.228381653
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/36.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random.2180381350
Short name T661
Test name
Test status
Simulation time 896313468 ps
CPU time 12.94 seconds
Started Sep 24 04:56:27 PM UTC 24
Finished Sep 24 04:56:42 PM UTC 24
Peak memory 211980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180381350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.2180381350
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/36.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.316850542
Short name T712
Test name
Test status
Simulation time 32127224841 ps
CPU time 73.23 seconds
Started Sep 24 04:56:28 PM UTC 24
Finished Sep 24 04:57:43 PM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316850542 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.316850542
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/36.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.2542365148
Short name T741
Test name
Test status
Simulation time 19695825792 ps
CPU time 102.96 seconds
Started Sep 24 04:56:28 PM UTC 24
Finished Sep 24 04:58:13 PM UTC 24
Peak memory 212156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542365148 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.2542365148
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/36.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_zero_delays.807780269
Short name T658
Test name
Test status
Simulation time 103690521 ps
CPU time 10.97 seconds
Started Sep 24 04:56:28 PM UTC 24
Finished Sep 24 04:56:40 PM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807780269 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.807780269
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/36.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_same_source.3602736520
Short name T665
Test name
Test status
Simulation time 912444152 ps
CPU time 17.18 seconds
Started Sep 24 04:56:28 PM UTC 24
Finished Sep 24 04:56:46 PM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602736520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3602736520
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/36.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke.4177984191
Short name T643
Test name
Test status
Simulation time 8728080 ps
CPU time 1.82 seconds
Started Sep 24 04:56:22 PM UTC 24
Finished Sep 24 04:56:25 PM UTC 24
Peak memory 210968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177984191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.4177984191
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/36.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_large_delays.2293294157
Short name T649
Test name
Test status
Simulation time 1542838235 ps
CPU time 7.29 seconds
Started Sep 24 04:56:22 PM UTC 24
Finished Sep 24 04:56:31 PM UTC 24
Peak memory 212200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293294157 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2293294157
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/36.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.2511431718
Short name T655
Test name
Test status
Simulation time 811409662 ps
CPU time 7.24 seconds
Started Sep 24 04:56:27 PM UTC 24
Finished Sep 24 04:56:36 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511431718 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.2511431718
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/36.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.2964801648
Short name T644
Test name
Test status
Simulation time 16494191 ps
CPU time 1.99 seconds
Started Sep 24 04:56:22 PM UTC 24
Finished Sep 24 04:56:25 PM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964801648 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.2964801648
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/36.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all.1321241506
Short name T122
Test name
Test status
Simulation time 3659965062 ps
CPU time 57.5 seconds
Started Sep 24 04:56:30 PM UTC 24
Finished Sep 24 04:57:30 PM UTC 24
Peak memory 214316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321241506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.1321241506
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/36.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_error.362907272
Short name T673
Test name
Test status
Simulation time 257061779 ps
CPU time 19.7 seconds
Started Sep 24 04:56:35 PM UTC 24
Finished Sep 24 04:56:56 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362907272 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.362907272
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/36.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.3155579414
Short name T714
Test name
Test status
Simulation time 768077862 ps
CPU time 72.77 seconds
Started Sep 24 04:56:32 PM UTC 24
Finished Sep 24 04:57:47 PM UTC 24
Peak memory 216108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155579414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.3155579414
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/36.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3608374180
Short name T762
Test name
Test status
Simulation time 732176209 ps
CPU time 123.61 seconds
Started Sep 24 04:56:35 PM UTC 24
Finished Sep 24 04:58:41 PM UTC 24
Peak memory 216236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608374180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.3608374180
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/36.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_unmapped_addr.700709303
Short name T654
Test name
Test status
Simulation time 20411710 ps
CPU time 3.06 seconds
Started Sep 24 04:56:30 PM UTC 24
Finished Sep 24 04:56:34 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700709303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.700709303
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/36.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device.4038486041
Short name T671
Test name
Test status
Simulation time 527759984 ps
CPU time 11.1 seconds
Started Sep 24 04:56:43 PM UTC 24
Finished Sep 24 04:56:55 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038486041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.4038486041
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/37.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.4051430029
Short name T822
Test name
Test status
Simulation time 23332624682 ps
CPU time 173.63 seconds
Started Sep 24 04:56:43 PM UTC 24
Finished Sep 24 04:59:39 PM UTC 24
Peak memory 212076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051430029 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.4051430029
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/37.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.4133815695
Short name T677
Test name
Test status
Simulation time 687286591 ps
CPU time 10.98 seconds
Started Sep 24 04:56:47 PM UTC 24
Finished Sep 24 04:56:59 PM UTC 24
Peak memory 212012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133815695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.4133815695
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/37.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_error_random.3739015764
Short name T672
Test name
Test status
Simulation time 127309518 ps
CPU time 7.28 seconds
Started Sep 24 04:56:47 PM UTC 24
Finished Sep 24 04:56:55 PM UTC 24
Peak memory 211964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739015764 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.3739015764
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/37.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random.3219913286
Short name T668
Test name
Test status
Simulation time 816111168 ps
CPU time 13.66 seconds
Started Sep 24 04:56:39 PM UTC 24
Finished Sep 24 04:56:54 PM UTC 24
Peak memory 211980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219913286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.3219913286
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/37.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.3261567344
Short name T724
Test name
Test status
Simulation time 19322909673 ps
CPU time 68.79 seconds
Started Sep 24 04:56:43 PM UTC 24
Finished Sep 24 04:57:53 PM UTC 24
Peak memory 212140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261567344 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.3261567344
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/37.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.2117567578
Short name T674
Test name
Test status
Simulation time 6484247017 ps
CPU time 14.18 seconds
Started Sep 24 04:56:43 PM UTC 24
Finished Sep 24 04:56:58 PM UTC 24
Peak memory 212060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117567578 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2117567578
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/37.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_zero_delays.953263406
Short name T663
Test name
Test status
Simulation time 27430104 ps
CPU time 4.59 seconds
Started Sep 24 04:56:39 PM UTC 24
Finished Sep 24 04:56:45 PM UTC 24
Peak memory 211996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953263406 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.953263406
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/37.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_same_source.4203295307
Short name T667
Test name
Test status
Simulation time 276024343 ps
CPU time 5.28 seconds
Started Sep 24 04:56:47 PM UTC 24
Finished Sep 24 04:56:53 PM UTC 24
Peak memory 212148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203295307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.4203295307
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/37.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke.2714598191
Short name T659
Test name
Test status
Simulation time 13416932 ps
CPU time 1.73 seconds
Started Sep 24 04:56:39 PM UTC 24
Finished Sep 24 04:56:41 PM UTC 24
Peak memory 210924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714598191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2714598191
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/37.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_large_delays.2548068252
Short name T666
Test name
Test status
Simulation time 1387787297 ps
CPU time 12.11 seconds
Started Sep 24 04:56:39 PM UTC 24
Finished Sep 24 04:56:52 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548068252 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.2548068252
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/37.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.3357850108
Short name T670
Test name
Test status
Simulation time 1955739478 ps
CPU time 15.06 seconds
Started Sep 24 04:56:39 PM UTC 24
Finished Sep 24 04:56:55 PM UTC 24
Peak memory 211988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357850108 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.3357850108
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/37.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3801380342
Short name T660
Test name
Test status
Simulation time 8873024 ps
CPU time 1.73 seconds
Started Sep 24 04:56:39 PM UTC 24
Finished Sep 24 04:56:41 PM UTC 24
Peak memory 210936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801380342 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.3801380342
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/37.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.31236237
Short name T783
Test name
Test status
Simulation time 23708245451 ps
CPU time 128.37 seconds
Started Sep 24 04:56:47 PM UTC 24
Finished Sep 24 04:58:58 PM UTC 24
Peak memory 214116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31236237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-si
m-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.31236237
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/37.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_error.2289702396
Short name T730
Test name
Test status
Simulation time 4507241615 ps
CPU time 72.08 seconds
Started Sep 24 04:56:49 PM UTC 24
Finished Sep 24 04:58:03 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289702396 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2289702396
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/37.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.2042754167
Short name T694
Test name
Test status
Simulation time 290966040 ps
CPU time 35 seconds
Started Sep 24 04:56:49 PM UTC 24
Finished Sep 24 04:57:25 PM UTC 24
Peak memory 214252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042754167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.2042754167
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/37.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.839455601
Short name T750
Test name
Test status
Simulation time 7349820432 ps
CPU time 88.68 seconds
Started Sep 24 04:56:55 PM UTC 24
Finished Sep 24 04:58:26 PM UTC 24
Peak memory 216172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839455601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.839455601
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/37.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_unmapped_addr.1869436776
Short name T679
Test name
Test status
Simulation time 997252134 ps
CPU time 14 seconds
Started Sep 24 04:56:47 PM UTC 24
Finished Sep 24 04:57:02 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869436776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1869436776
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/37.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device.1081254000
Short name T682
Test name
Test status
Simulation time 25335293 ps
CPU time 4.26 seconds
Started Sep 24 04:57:03 PM UTC 24
Finished Sep 24 04:57:09 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081254000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.1081254000
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/38.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.2150875729
Short name T125
Test name
Test status
Simulation time 279072860270 ps
CPU time 385.41 seconds
Started Sep 24 04:57:03 PM UTC 24
Finished Sep 24 05:03:34 PM UTC 24
Peak memory 214316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150875729 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.2150875729
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/38.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.2670710991
Short name T690
Test name
Test status
Simulation time 471857418 ps
CPU time 11.03 seconds
Started Sep 24 04:57:06 PM UTC 24
Finished Sep 24 04:57:18 PM UTC 24
Peak memory 212200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670710991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.2670710991
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/38.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_error_random.1491758559
Short name T684
Test name
Test status
Simulation time 390221309 ps
CPU time 7.78 seconds
Started Sep 24 04:57:03 PM UTC 24
Finished Sep 24 04:57:12 PM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491758559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.1491758559
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/38.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random.799691389
Short name T691
Test name
Test status
Simulation time 713956516 ps
CPU time 16.78 seconds
Started Sep 24 04:57:03 PM UTC 24
Finished Sep 24 04:57:21 PM UTC 24
Peak memory 212052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799691389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.799691389
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/38.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.2203798900
Short name T177
Test name
Test status
Simulation time 1815949056 ps
CPU time 11.79 seconds
Started Sep 24 04:57:03 PM UTC 24
Finished Sep 24 04:57:16 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203798900 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.2203798900
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/38.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.3848246448
Short name T772
Test name
Test status
Simulation time 20571810729 ps
CPU time 101.34 seconds
Started Sep 24 04:57:03 PM UTC 24
Finished Sep 24 04:58:47 PM UTC 24
Peak memory 212252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848246448 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.3848246448
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/38.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_zero_delays.395823706
Short name T687
Test name
Test status
Simulation time 340381996 ps
CPU time 9.76 seconds
Started Sep 24 04:57:03 PM UTC 24
Finished Sep 24 04:57:14 PM UTC 24
Peak memory 212196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395823706 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.395823706
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/38.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_same_source.516574775
Short name T688
Test name
Test status
Simulation time 751300907 ps
CPU time 12.37 seconds
Started Sep 24 04:57:03 PM UTC 24
Finished Sep 24 04:57:17 PM UTC 24
Peak memory 211992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516574775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.516574775
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/38.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke.2331327418
Short name T675
Test name
Test status
Simulation time 9026700 ps
CPU time 1.81 seconds
Started Sep 24 04:56:56 PM UTC 24
Finished Sep 24 04:56:58 PM UTC 24
Peak memory 210968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331327418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2331327418
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/38.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_large_delays.3171906649
Short name T681
Test name
Test status
Simulation time 3069060811 ps
CPU time 11.55 seconds
Started Sep 24 04:56:56 PM UTC 24
Finished Sep 24 04:57:08 PM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171906649 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.3171906649
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/38.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.1523742165
Short name T685
Test name
Test status
Simulation time 2468712301 ps
CPU time 9.19 seconds
Started Sep 24 04:57:03 PM UTC 24
Finished Sep 24 04:57:13 PM UTC 24
Peak memory 212056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523742165 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.1523742165
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/38.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.1793529602
Short name T676
Test name
Test status
Simulation time 10655372 ps
CPU time 1.94 seconds
Started Sep 24 04:56:56 PM UTC 24
Finished Sep 24 04:56:58 PM UTC 24
Peak memory 210940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793529602 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.1793529602
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/38.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.668560541
Short name T734
Test name
Test status
Simulation time 5118795548 ps
CPU time 61.8 seconds
Started Sep 24 04:57:06 PM UTC 24
Finished Sep 24 04:58:09 PM UTC 24
Peak memory 214116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668560541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.668560541
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/38.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.3360187773
Short name T744
Test name
Test status
Simulation time 728118428 ps
CPU time 62.74 seconds
Started Sep 24 04:57:11 PM UTC 24
Finished Sep 24 04:58:15 PM UTC 24
Peak memory 214056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360187773 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3360187773
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/38.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2499224622
Short name T752
Test name
Test status
Simulation time 3438079525 ps
CPU time 78.48 seconds
Started Sep 24 04:57:09 PM UTC 24
Finished Sep 24 04:58:29 PM UTC 24
Peak memory 216168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499224622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.2499224622
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/38.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.3852156374
Short name T716
Test name
Test status
Simulation time 209101263 ps
CPU time 35.44 seconds
Started Sep 24 04:57:11 PM UTC 24
Finished Sep 24 04:57:48 PM UTC 24
Peak memory 214056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852156374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.3852156374
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/38.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_unmapped_addr.3555290665
Short name T683
Test name
Test status
Simulation time 52189470 ps
CPU time 4.32 seconds
Started Sep 24 04:57:03 PM UTC 24
Finished Sep 24 04:57:09 PM UTC 24
Peak memory 212196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555290665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3555290665
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/38.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device.4026714106
Short name T693
Test name
Test status
Simulation time 124714596 ps
CPU time 4.39 seconds
Started Sep 24 04:57:20 PM UTC 24
Finished Sep 24 04:57:25 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026714106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.4026714106
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/39.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.837714465
Short name T794
Test name
Test status
Simulation time 17906757964 ps
CPU time 102.79 seconds
Started Sep 24 04:57:23 PM UTC 24
Finished Sep 24 04:59:07 PM UTC 24
Peak memory 212064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837714465 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.837714465
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/39.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.2404296418
Short name T713
Test name
Test status
Simulation time 2555232621 ps
CPU time 13.52 seconds
Started Sep 24 04:57:29 PM UTC 24
Finished Sep 24 04:57:44 PM UTC 24
Peak memory 212076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404296418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.2404296418
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/39.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_error_random.2050197541
Short name T705
Test name
Test status
Simulation time 38827409 ps
CPU time 3.64 seconds
Started Sep 24 04:57:29 PM UTC 24
Finished Sep 24 04:57:34 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050197541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.2050197541
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/39.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random.1092842023
Short name T699
Test name
Test status
Simulation time 244516967 ps
CPU time 10.99 seconds
Started Sep 24 04:57:17 PM UTC 24
Finished Sep 24 04:57:29 PM UTC 24
Peak memory 212172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092842023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.1092842023
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/39.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.3211869205
Short name T728
Test name
Test status
Simulation time 6197929474 ps
CPU time 33.81 seconds
Started Sep 24 04:57:20 PM UTC 24
Finished Sep 24 04:57:55 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211869205 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.3211869205
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/39.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.446096719
Short name T785
Test name
Test status
Simulation time 12210183224 ps
CPU time 100.55 seconds
Started Sep 24 04:57:20 PM UTC 24
Finished Sep 24 04:59:02 PM UTC 24
Peak memory 212056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446096719 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.446096719
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/39.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_zero_delays.512949496
Short name T700
Test name
Test status
Simulation time 238171906 ps
CPU time 8.58 seconds
Started Sep 24 04:57:20 PM UTC 24
Finished Sep 24 04:57:29 PM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512949496 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.512949496
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/39.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_same_source.581566414
Short name T706
Test name
Test status
Simulation time 450089323 ps
CPU time 9.15 seconds
Started Sep 24 04:57:24 PM UTC 24
Finished Sep 24 04:57:35 PM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581566414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.581566414
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/39.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke.2216431865
Short name T686
Test name
Test status
Simulation time 8993462 ps
CPU time 1.78 seconds
Started Sep 24 04:57:11 PM UTC 24
Finished Sep 24 04:57:14 PM UTC 24
Peak memory 210924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216431865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2216431865
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/39.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_large_delays.1525708268
Short name T696
Test name
Test status
Simulation time 2022186621 ps
CPU time 8.32 seconds
Started Sep 24 04:57:17 PM UTC 24
Finished Sep 24 04:57:26 PM UTC 24
Peak memory 212200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525708268 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.1525708268
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/39.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.3743223809
Short name T703
Test name
Test status
Simulation time 3792400572 ps
CPU time 13.53 seconds
Started Sep 24 04:57:17 PM UTC 24
Finished Sep 24 04:57:31 PM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743223809 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.3743223809
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/39.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2878167490
Short name T689
Test name
Test status
Simulation time 15022867 ps
CPU time 2.14 seconds
Started Sep 24 04:57:14 PM UTC 24
Finished Sep 24 04:57:17 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878167490 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.2878167490
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/39.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.456175417
Short name T711
Test name
Test status
Simulation time 338925496 ps
CPU time 8.25 seconds
Started Sep 24 04:57:29 PM UTC 24
Finished Sep 24 04:57:39 PM UTC 24
Peak memory 214052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456175417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.456175417
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/39.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.3902404014
Short name T738
Test name
Test status
Simulation time 308006205 ps
CPU time 37.97 seconds
Started Sep 24 04:57:33 PM UTC 24
Finished Sep 24 04:58:12 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902404014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3902404014
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/39.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.917201121
Short name T758
Test name
Test status
Simulation time 463282388 ps
CPU time 62.65 seconds
Started Sep 24 04:57:29 PM UTC 24
Finished Sep 24 04:58:34 PM UTC 24
Peak memory 214248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917201121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.917201121
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/39.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_unmapped_addr.425304549
Short name T707
Test name
Test status
Simulation time 155208326 ps
CPU time 4.83 seconds
Started Sep 24 04:57:29 PM UTC 24
Finished Sep 24 04:57:35 PM UTC 24
Peak memory 212112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425304549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.425304549
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/39.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device.4024338743
Short name T85
Test name
Test status
Simulation time 53309172 ps
CPU time 8.99 seconds
Started Sep 24 04:41:22 PM UTC 24
Finished Sep 24 04:41:32 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024338743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.4024338743
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/4.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.2928621105
Short name T199
Test name
Test status
Simulation time 31482972333 ps
CPU time 192.28 seconds
Started Sep 24 04:41:26 PM UTC 24
Finished Sep 24 04:44:42 PM UTC 24
Peak memory 214116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928621105 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.2928621105
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/4.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.1153022088
Short name T97
Test name
Test status
Simulation time 1571705124 ps
CPU time 18.51 seconds
Started Sep 24 04:41:39 PM UTC 24
Finished Sep 24 04:41:59 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153022088 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.1153022088
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/4.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_error_random.2305219062
Short name T86
Test name
Test status
Simulation time 24049909 ps
CPU time 4.78 seconds
Started Sep 24 04:41:33 PM UTC 24
Finished Sep 24 04:41:38 PM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305219062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.2305219062
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/4.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random.3003432366
Short name T53
Test name
Test status
Simulation time 839863027 ps
CPU time 13.41 seconds
Started Sep 24 04:41:06 PM UTC 24
Finished Sep 24 04:41:21 PM UTC 24
Peak memory 211980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003432366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.3003432366
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/4.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_large_delays.2306821629
Short name T77
Test name
Test status
Simulation time 56062558430 ps
CPU time 75 seconds
Started Sep 24 04:41:17 PM UTC 24
Finished Sep 24 04:42:33 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306821629 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.2306821629
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/4.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_slow_rsp.842842250
Short name T137
Test name
Test status
Simulation time 3019105047 ps
CPU time 39.14 seconds
Started Sep 24 04:41:17 PM UTC 24
Finished Sep 24 04:41:57 PM UTC 24
Peak memory 212048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842842250 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.842842250
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/4.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_zero_delays.2995759816
Short name T54
Test name
Test status
Simulation time 73972432 ps
CPU time 13.86 seconds
Started Sep 24 04:41:16 PM UTC 24
Finished Sep 24 04:41:32 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995759816 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.2995759816
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/4.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_same_source.1512967166
Short name T87
Test name
Test status
Simulation time 73832041 ps
CPU time 9.08 seconds
Started Sep 24 04:41:29 PM UTC 24
Finished Sep 24 04:41:40 PM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512967166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1512967166
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/4.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke.4164070029
Short name T244
Test name
Test status
Simulation time 324186503 ps
CPU time 2.73 seconds
Started Sep 24 04:40:56 PM UTC 24
Finished Sep 24 04:41:00 PM UTC 24
Peak memory 212200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164070029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.4164070029
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/4.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_large_delays.2442740699
Short name T245
Test name
Test status
Simulation time 4690207166 ps
CPU time 13.43 seconds
Started Sep 24 04:41:01 PM UTC 24
Finished Sep 24 04:41:15 PM UTC 24
Peak memory 212136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442740699 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2442740699
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/4.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.258705242
Short name T246
Test name
Test status
Simulation time 2971137514 ps
CPU time 9.53 seconds
Started Sep 24 04:41:05 PM UTC 24
Finished Sep 24 04:41:15 PM UTC 24
Peak memory 212264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258705242 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.258705242
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/4.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.2774966464
Short name T132
Test name
Test status
Simulation time 9599070 ps
CPU time 2.13 seconds
Started Sep 24 04:41:01 PM UTC 24
Finished Sep 24 04:41:04 PM UTC 24
Peak memory 212252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774966464 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.2774966464
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/4.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all.96540573
Short name T248
Test name
Test status
Simulation time 2508669691 ps
CPU time 33.92 seconds
Started Sep 24 04:41:41 PM UTC 24
Finished Sep 24 04:42:16 PM UTC 24
Peak memory 214364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96540573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-si
m-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.96540573
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/4.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_error.2188316072
Short name T88
Test name
Test status
Simulation time 45600586 ps
CPU time 7.9 seconds
Started Sep 24 04:41:43 PM UTC 24
Finished Sep 24 04:41:53 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188316072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2188316072
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/4.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.4117606525
Short name T249
Test name
Test status
Simulation time 335451930 ps
CPU time 33.84 seconds
Started Sep 24 04:41:43 PM UTC 24
Finished Sep 24 04:42:19 PM UTC 24
Peak memory 214060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117606525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.4117606525
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/4.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.2581821875
Short name T235
Test name
Test status
Simulation time 594130112 ps
CPU time 147.89 seconds
Started Sep 24 04:41:49 PM UTC 24
Finished Sep 24 04:44:20 PM UTC 24
Peak memory 218152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581821875 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.2581821875
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/4.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_unmapped_addr.2575685676
Short name T68
Test name
Test status
Simulation time 411744589 ps
CPU time 8.95 seconds
Started Sep 24 04:41:33 PM UTC 24
Finished Sep 24 04:41:43 PM UTC 24
Peak memory 212264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575685676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.2575685676
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/4.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device.3495164158
Short name T721
Test name
Test status
Simulation time 50585033 ps
CPU time 9.89 seconds
Started Sep 24 04:57:39 PM UTC 24
Finished Sep 24 04:57:50 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495164158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.3495164158
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/40.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.4122613100
Short name T755
Test name
Test status
Simulation time 6353364732 ps
CPU time 52.16 seconds
Started Sep 24 04:57:39 PM UTC 24
Finished Sep 24 04:58:33 PM UTC 24
Peak memory 212076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122613100 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.4122613100
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/40.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.959150560
Short name T722
Test name
Test status
Simulation time 31524022 ps
CPU time 4.2 seconds
Started Sep 24 04:57:47 PM UTC 24
Finished Sep 24 04:57:52 PM UTC 24
Peak memory 212268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959150560 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.959150560
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/40.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_error_random.3953619729
Short name T718
Test name
Test status
Simulation time 213051684 ps
CPU time 5.88 seconds
Started Sep 24 04:57:42 PM UTC 24
Finished Sep 24 04:57:48 PM UTC 24
Peak memory 211992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953619729 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3953619729
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/40.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random.3871115450
Short name T715
Test name
Test status
Simulation time 283616702 ps
CPU time 7.01 seconds
Started Sep 24 04:57:39 PM UTC 24
Finished Sep 24 04:57:47 PM UTC 24
Peak memory 212176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871115450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.3871115450
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/40.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.1378338219
Short name T889
Test name
Test status
Simulation time 48031926444 ps
CPU time 224.36 seconds
Started Sep 24 04:57:39 PM UTC 24
Finished Sep 24 05:01:27 PM UTC 24
Peak memory 212076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378338219 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.1378338219
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/40.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.3526944275
Short name T767
Test name
Test status
Simulation time 17409778388 ps
CPU time 63.74 seconds
Started Sep 24 04:57:39 PM UTC 24
Finished Sep 24 04:58:45 PM UTC 24
Peak memory 212056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526944275 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.3526944275
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/40.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_zero_delays.3454951944
Short name T720
Test name
Test status
Simulation time 60130255 ps
CPU time 9.56 seconds
Started Sep 24 04:57:39 PM UTC 24
Finished Sep 24 04:57:50 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454951944 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.3454951944
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/40.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_same_source.3535063909
Short name T717
Test name
Test status
Simulation time 110975969 ps
CPU time 7.67 seconds
Started Sep 24 04:57:39 PM UTC 24
Finished Sep 24 04:57:48 PM UTC 24
Peak memory 214220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535063909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3535063909
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/40.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke.521086261
Short name T708
Test name
Test status
Simulation time 14911326 ps
CPU time 1.68 seconds
Started Sep 24 04:57:33 PM UTC 24
Finished Sep 24 04:57:36 PM UTC 24
Peak memory 210812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521086261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.521086261
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/40.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_large_delays.3731549584
Short name T726
Test name
Test status
Simulation time 2479320670 ps
CPU time 19.72 seconds
Started Sep 24 04:57:33 PM UTC 24
Finished Sep 24 04:57:54 PM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731549584 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.3731549584
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/40.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.380034830
Short name T719
Test name
Test status
Simulation time 1414226112 ps
CPU time 14.62 seconds
Started Sep 24 04:57:33 PM UTC 24
Finished Sep 24 04:57:49 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380034830 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.380034830
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/40.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.610207199
Short name T709
Test name
Test status
Simulation time 9120275 ps
CPU time 2.04 seconds
Started Sep 24 04:57:33 PM UTC 24
Finished Sep 24 04:57:36 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610207199 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.610207199
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/40.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.3430087986
Short name T819
Test name
Test status
Simulation time 8373034756 ps
CPU time 106.17 seconds
Started Sep 24 04:57:47 PM UTC 24
Finished Sep 24 04:59:35 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430087986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3430087986
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/40.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.765571326
Short name T736
Test name
Test status
Simulation time 431734211 ps
CPU time 20.65 seconds
Started Sep 24 04:57:50 PM UTC 24
Finished Sep 24 04:58:12 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765571326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.765571326
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/40.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.2549175459
Short name T893
Test name
Test status
Simulation time 7693908259 ps
CPU time 234.85 seconds
Started Sep 24 04:57:50 PM UTC 24
Finished Sep 24 05:01:49 PM UTC 24
Peak memory 216172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549175459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.2549175459
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/40.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.1547282717
Short name T797
Test name
Test status
Simulation time 913275363 ps
CPU time 78.94 seconds
Started Sep 24 04:57:50 PM UTC 24
Finished Sep 24 04:59:11 PM UTC 24
Peak memory 216104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547282717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.1547282717
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/40.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_unmapped_addr.2759625857
Short name T729
Test name
Test status
Simulation time 543747299 ps
CPU time 13.49 seconds
Started Sep 24 04:57:42 PM UTC 24
Finished Sep 24 04:57:56 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759625857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2759625857
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/40.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device.2681047863
Short name T732
Test name
Test status
Simulation time 111427602 ps
CPU time 3.88 seconds
Started Sep 24 04:57:59 PM UTC 24
Finished Sep 24 04:58:04 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681047863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.2681047863
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/41.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3002094673
Short name T123
Test name
Test status
Simulation time 49905577943 ps
CPU time 80.51 seconds
Started Sep 24 04:57:59 PM UTC 24
Finished Sep 24 04:59:21 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002094673 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.3002094673
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/41.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.455811758
Short name T742
Test name
Test status
Simulation time 663682875 ps
CPU time 8.41 seconds
Started Sep 24 04:58:04 PM UTC 24
Finished Sep 24 04:58:13 PM UTC 24
Peak memory 212012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455811758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.455811758
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/41.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_error_random.2782713757
Short name T735
Test name
Test status
Simulation time 71716890 ps
CPU time 5.49 seconds
Started Sep 24 04:58:03 PM UTC 24
Finished Sep 24 04:58:10 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782713757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.2782713757
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/41.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random.852378510
Short name T731
Test name
Test status
Simulation time 366480753 ps
CPU time 3.81 seconds
Started Sep 24 04:57:59 PM UTC 24
Finished Sep 24 04:58:04 PM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852378510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.852378510
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/41.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.3703639886
Short name T831
Test name
Test status
Simulation time 67584476714 ps
CPU time 105.55 seconds
Started Sep 24 04:57:59 PM UTC 24
Finished Sep 24 04:59:46 PM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703639886 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.3703639886
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/41.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.2704718302
Short name T886
Test name
Test status
Simulation time 45567307911 ps
CPU time 200.45 seconds
Started Sep 24 04:57:59 PM UTC 24
Finished Sep 24 05:01:22 PM UTC 24
Peak memory 212056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704718302 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.2704718302
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/41.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_zero_delays.2475844905
Short name T733
Test name
Test status
Simulation time 100038914 ps
CPU time 5.97 seconds
Started Sep 24 04:57:59 PM UTC 24
Finished Sep 24 04:58:06 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475844905 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.2475844905
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/41.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_same_source.822854091
Short name T740
Test name
Test status
Simulation time 936028500 ps
CPU time 12.63 seconds
Started Sep 24 04:57:59 PM UTC 24
Finished Sep 24 04:58:13 PM UTC 24
Peak memory 211992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822854091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.822854091
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/41.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke.2127732355
Short name T725
Test name
Test status
Simulation time 60684791 ps
CPU time 1.93 seconds
Started Sep 24 04:57:50 PM UTC 24
Finished Sep 24 04:57:53 PM UTC 24
Peak memory 210924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127732355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.2127732355
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/41.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_large_delays.1656463078
Short name T746
Test name
Test status
Simulation time 13757909106 ps
CPU time 16.65 seconds
Started Sep 24 04:57:59 PM UTC 24
Finished Sep 24 04:58:16 PM UTC 24
Peak memory 212064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656463078 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.1656463078
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/41.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.2517841286
Short name T745
Test name
Test status
Simulation time 1471384743 ps
CPU time 16.39 seconds
Started Sep 24 04:57:59 PM UTC 24
Finished Sep 24 04:58:16 PM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517841286 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2517841286
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/41.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2179741620
Short name T723
Test name
Test status
Simulation time 9784707 ps
CPU time 1.45 seconds
Started Sep 24 04:57:50 PM UTC 24
Finished Sep 24 04:57:53 PM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179741620 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2179741620
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/41.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.2436645517
Short name T769
Test name
Test status
Simulation time 1773648416 ps
CPU time 40.56 seconds
Started Sep 24 04:58:04 PM UTC 24
Finished Sep 24 04:58:46 PM UTC 24
Peak memory 214060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436645517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.2436645517
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/41.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.4024953680
Short name T810
Test name
Test status
Simulation time 776288400 ps
CPU time 78.4 seconds
Started Sep 24 04:58:06 PM UTC 24
Finished Sep 24 04:59:27 PM UTC 24
Peak memory 216104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024953680 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.4024953680
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/41.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.485659754
Short name T811
Test name
Test status
Simulation time 3618369527 ps
CPU time 79.8 seconds
Started Sep 24 04:58:06 PM UTC 24
Finished Sep 24 04:59:28 PM UTC 24
Peak memory 214116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485659754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.485659754
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/41.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.4233709484
Short name T11
Test name
Test status
Simulation time 471934217 ps
CPU time 75.48 seconds
Started Sep 24 04:58:07 PM UTC 24
Finished Sep 24 04:59:24 PM UTC 24
Peak memory 216104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233709484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.4233709484
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/41.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_unmapped_addr.2756127886
Short name T739
Test name
Test status
Simulation time 291659654 ps
CPU time 8.01 seconds
Started Sep 24 04:58:04 PM UTC 24
Finished Sep 24 04:58:13 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756127886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2756127886
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/41.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device.335115107
Short name T765
Test name
Test status
Simulation time 1284980687 ps
CPU time 23.42 seconds
Started Sep 24 04:58:19 PM UTC 24
Finished Sep 24 04:58:44 PM UTC 24
Peak memory 212264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335115107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.335115107
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/42.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.174790079
Short name T203
Test name
Test status
Simulation time 39117810114 ps
CPU time 321.49 seconds
Started Sep 24 04:58:19 PM UTC 24
Finished Sep 24 05:03:45 PM UTC 24
Peak memory 214116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174790079 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.174790079
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/42.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.1280670556
Short name T751
Test name
Test status
Simulation time 16458246 ps
CPU time 1.98 seconds
Started Sep 24 04:58:25 PM UTC 24
Finished Sep 24 04:58:28 PM UTC 24
Peak memory 210988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280670556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.1280670556
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/42.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_error_random.3836462920
Short name T753
Test name
Test status
Simulation time 94743504 ps
CPU time 4.94 seconds
Started Sep 24 04:58:25 PM UTC 24
Finished Sep 24 04:58:31 PM UTC 24
Peak memory 211988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836462920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3836462920
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/42.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random.2641204956
Short name T129
Test name
Test status
Simulation time 763662202 ps
CPU time 14.25 seconds
Started Sep 24 04:58:19 PM UTC 24
Finished Sep 24 04:58:35 PM UTC 24
Peak memory 212176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641204956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2641204956
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/42.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.460119362
Short name T756
Test name
Test status
Simulation time 11820397425 ps
CPU time 12.91 seconds
Started Sep 24 04:58:19 PM UTC 24
Finished Sep 24 04:58:33 PM UTC 24
Peak memory 211964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460119362 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.460119362
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/42.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.3304897203
Short name T891
Test name
Test status
Simulation time 47949992240 ps
CPU time 187.01 seconds
Started Sep 24 04:58:19 PM UTC 24
Finished Sep 24 05:01:29 PM UTC 24
Peak memory 212052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304897203 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.3304897203
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/42.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_zero_delays.4007410992
Short name T749
Test name
Test status
Simulation time 18589699 ps
CPU time 3.3 seconds
Started Sep 24 04:58:19 PM UTC 24
Finished Sep 24 04:58:24 PM UTC 24
Peak memory 211860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007410992 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.4007410992
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/42.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_same_source.3898405220
Short name T759
Test name
Test status
Simulation time 528504908 ps
CPU time 9.13 seconds
Started Sep 24 04:58:25 PM UTC 24
Finished Sep 24 04:58:35 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898405220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.3898405220
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/42.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke.326853717
Short name T737
Test name
Test status
Simulation time 35025211 ps
CPU time 2.22 seconds
Started Sep 24 04:58:09 PM UTC 24
Finished Sep 24 04:58:12 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326853717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.326853717
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/42.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_large_delays.2995029911
Short name T748
Test name
Test status
Simulation time 7225925445 ps
CPU time 8.85 seconds
Started Sep 24 04:58:12 PM UTC 24
Finished Sep 24 04:58:23 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995029911 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.2995029911
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/42.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.968767465
Short name T754
Test name
Test status
Simulation time 822605185 ps
CPU time 11.18 seconds
Started Sep 24 04:58:19 PM UTC 24
Finished Sep 24 04:58:32 PM UTC 24
Peak memory 211988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968767465 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.968767465
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/42.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.4157729725
Short name T743
Test name
Test status
Simulation time 20565910 ps
CPU time 1.72 seconds
Started Sep 24 04:58:12 PM UTC 24
Finished Sep 24 04:58:15 PM UTC 24
Peak memory 210936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157729725 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.4157729725
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/42.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.3418576516
Short name T784
Test name
Test status
Simulation time 293184721 ps
CPU time 35.42 seconds
Started Sep 24 04:58:25 PM UTC 24
Finished Sep 24 04:59:02 PM UTC 24
Peak memory 216300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418576516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.3418576516
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/42.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3868304626
Short name T775
Test name
Test status
Simulation time 1706130848 ps
CPU time 19.12 seconds
Started Sep 24 04:58:30 PM UTC 24
Finished Sep 24 04:58:51 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868304626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3868304626
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/42.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.2508839508
Short name T895
Test name
Test status
Simulation time 3223347710 ps
CPU time 217.28 seconds
Started Sep 24 04:58:25 PM UTC 24
Finished Sep 24 05:02:06 PM UTC 24
Peak memory 218216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508839508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.2508839508
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/42.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.1945328527
Short name T853
Test name
Test status
Simulation time 673524143 ps
CPU time 99.75 seconds
Started Sep 24 04:58:30 PM UTC 24
Finished Sep 24 05:00:12 PM UTC 24
Peak memory 216300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945328527 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.1945328527
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/42.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_unmapped_addr.3312701888
Short name T761
Test name
Test status
Simulation time 673553097 ps
CPU time 12.92 seconds
Started Sep 24 04:58:25 PM UTC 24
Finished Sep 24 04:58:39 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312701888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3312701888
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/42.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.2804651714
Short name T778
Test name
Test status
Simulation time 627876491 ps
CPU time 13.25 seconds
Started Sep 24 04:58:37 PM UTC 24
Finished Sep 24 04:58:52 PM UTC 24
Peak memory 212204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804651714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.2804651714
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/43.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.2190344752
Short name T157
Test name
Test status
Simulation time 13136688729 ps
CPU time 41.81 seconds
Started Sep 24 04:58:37 PM UTC 24
Finished Sep 24 04:59:21 PM UTC 24
Peak memory 212076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190344752 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.2190344752
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/43.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.2392696073
Short name T779
Test name
Test status
Simulation time 64831064 ps
CPU time 5.1 seconds
Started Sep 24 04:58:48 PM UTC 24
Finished Sep 24 04:58:55 PM UTC 24
Peak memory 212012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392696073 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.2392696073
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/43.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.1418672618
Short name T766
Test name
Test status
Simulation time 38796132 ps
CPU time 2.86 seconds
Started Sep 24 04:58:39 PM UTC 24
Finished Sep 24 04:58:44 PM UTC 24
Peak memory 211988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418672618 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.1418672618
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/43.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random.27263682
Short name T764
Test name
Test status
Simulation time 315922474 ps
CPU time 4.51 seconds
Started Sep 24 04:58:37 PM UTC 24
Finished Sep 24 04:58:43 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27263682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.27263682
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/43.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.212307918
Short name T880
Test name
Test status
Simulation time 25228334563 ps
CPU time 132.24 seconds
Started Sep 24 04:58:37 PM UTC 24
Finished Sep 24 05:00:52 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212307918 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.212307918
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/43.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3812858456
Short name T896
Test name
Test status
Simulation time 97907413186 ps
CPU time 234.97 seconds
Started Sep 24 04:58:37 PM UTC 24
Finished Sep 24 05:02:36 PM UTC 24
Peak memory 212060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812858456 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3812858456
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/43.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.3453644218
Short name T771
Test name
Test status
Simulation time 209299919 ps
CPU time 7.76 seconds
Started Sep 24 04:58:37 PM UTC 24
Finished Sep 24 04:58:46 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453644218 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.3453644218
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/43.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.2041188040
Short name T773
Test name
Test status
Simulation time 65302436 ps
CPU time 9.47 seconds
Started Sep 24 04:58:37 PM UTC 24
Finished Sep 24 04:58:48 PM UTC 24
Peak memory 211992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041188040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.2041188040
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/43.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke.620902445
Short name T757
Test name
Test status
Simulation time 41061808 ps
CPU time 2.22 seconds
Started Sep 24 04:58:30 PM UTC 24
Finished Sep 24 04:58:34 PM UTC 24
Peak memory 212196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620902445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.620902445
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/43.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.3158346043
Short name T770
Test name
Test status
Simulation time 11565572929 ps
CPU time 10.57 seconds
Started Sep 24 04:58:34 PM UTC 24
Finished Sep 24 04:58:46 PM UTC 24
Peak memory 211804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158346043 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.3158346043
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/43.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.1537063724
Short name T774
Test name
Test status
Simulation time 1784676540 ps
CPU time 14.3 seconds
Started Sep 24 04:58:34 PM UTC 24
Finished Sep 24 04:58:50 PM UTC 24
Peak memory 211908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537063724 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1537063724
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/43.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.2894095749
Short name T760
Test name
Test status
Simulation time 10649333 ps
CPU time 1.85 seconds
Started Sep 24 04:58:34 PM UTC 24
Finished Sep 24 04:58:37 PM UTC 24
Peak memory 210940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894095749 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.2894095749
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/43.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.10203073
Short name T812
Test name
Test status
Simulation time 2645695046 ps
CPU time 39.44 seconds
Started Sep 24 04:58:48 PM UTC 24
Finished Sep 24 04:59:30 PM UTC 24
Peak memory 214116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10203073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-si
m-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.10203073
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/43.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.397875297
Short name T790
Test name
Test status
Simulation time 621957149 ps
CPU time 15.39 seconds
Started Sep 24 04:58:49 PM UTC 24
Finished Sep 24 04:59:06 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397875297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.397875297
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/43.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.321453492
Short name T821
Test name
Test status
Simulation time 505146399 ps
CPU time 47.98 seconds
Started Sep 24 04:58:49 PM UTC 24
Finished Sep 24 04:59:38 PM UTC 24
Peak memory 214052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321453492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.321453492
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/43.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.2395286494
Short name T817
Test name
Test status
Simulation time 935396944 ps
CPU time 44.57 seconds
Started Sep 24 04:58:49 PM UTC 24
Finished Sep 24 04:59:35 PM UTC 24
Peak memory 214252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395286494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.2395286494
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/43.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.46423293
Short name T768
Test name
Test status
Simulation time 101044017 ps
CPU time 2.8 seconds
Started Sep 24 04:58:41 PM UTC 24
Finished Sep 24 04:58:45 PM UTC 24
Peak memory 212200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46423293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.46423293
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/43.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.2755376247
Short name T782
Test name
Test status
Simulation time 26938999 ps
CPU time 3.51 seconds
Started Sep 24 04:58:52 PM UTC 24
Finished Sep 24 04:58:57 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755376247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.2755376247
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/44.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3186534426
Short name T824
Test name
Test status
Simulation time 25942291605 ps
CPU time 46.3 seconds
Started Sep 24 04:58:52 PM UTC 24
Finished Sep 24 04:59:40 PM UTC 24
Peak memory 212268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186534426 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.3186534426
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/44.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.4008257914
Short name T788
Test name
Test status
Simulation time 269283321 ps
CPU time 8 seconds
Started Sep 24 04:58:56 PM UTC 24
Finished Sep 24 04:59:05 PM UTC 24
Peak memory 212204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008257914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.4008257914
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/44.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.1800344953
Short name T789
Test name
Test status
Simulation time 813689123 ps
CPU time 8.1 seconds
Started Sep 24 04:58:56 PM UTC 24
Finished Sep 24 04:59:05 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800344953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1800344953
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/44.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random.2396838339
Short name T780
Test name
Test status
Simulation time 65952269 ps
CPU time 2.85 seconds
Started Sep 24 04:58:51 PM UTC 24
Finished Sep 24 04:58:56 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396838339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.2396838339
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/44.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.2488749567
Short name T168
Test name
Test status
Simulation time 28833642077 ps
CPU time 153.51 seconds
Started Sep 24 04:58:52 PM UTC 24
Finished Sep 24 05:01:28 PM UTC 24
Peak memory 212140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488749567 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2488749567
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/44.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.913820045
Short name T875
Test name
Test status
Simulation time 13952945879 ps
CPU time 105.09 seconds
Started Sep 24 04:58:52 PM UTC 24
Finished Sep 24 05:00:39 PM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913820045 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.913820045
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/44.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.2659800970
Short name T781
Test name
Test status
Simulation time 65709908 ps
CPU time 3.79 seconds
Started Sep 24 04:58:52 PM UTC 24
Finished Sep 24 04:58:56 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659800970 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.2659800970
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/44.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.3309865642
Short name T792
Test name
Test status
Simulation time 2589339421 ps
CPU time 9.39 seconds
Started Sep 24 04:58:56 PM UTC 24
Finished Sep 24 04:59:06 PM UTC 24
Peak memory 212256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309865642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3309865642
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/44.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.228244903
Short name T776
Test name
Test status
Simulation time 8758939 ps
CPU time 1.54 seconds
Started Sep 24 04:58:49 PM UTC 24
Finished Sep 24 04:58:52 PM UTC 24
Peak memory 210976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228244903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.228244903
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/44.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.226888411
Short name T796
Test name
Test status
Simulation time 13893436612 ps
CPU time 20.01 seconds
Started Sep 24 04:58:49 PM UTC 24
Finished Sep 24 04:59:10 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226888411 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.226888411
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/44.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.1554885543
Short name T791
Test name
Test status
Simulation time 1333146641 ps
CPU time 15.2 seconds
Started Sep 24 04:58:49 PM UTC 24
Finished Sep 24 04:59:06 PM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554885543 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.1554885543
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/44.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.2963068786
Short name T777
Test name
Test status
Simulation time 8350196 ps
CPU time 1.72 seconds
Started Sep 24 04:58:49 PM UTC 24
Finished Sep 24 04:58:52 PM UTC 24
Peak memory 210936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963068786 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.2963068786
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/44.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.3814052886
Short name T798
Test name
Test status
Simulation time 980960122 ps
CPU time 13.28 seconds
Started Sep 24 04:58:59 PM UTC 24
Finished Sep 24 04:59:13 PM UTC 24
Peak memory 212204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814052886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.3814052886
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/44.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2853503545
Short name T850
Test name
Test status
Simulation time 4208739946 ps
CPU time 68.12 seconds
Started Sep 24 04:58:59 PM UTC 24
Finished Sep 24 05:00:08 PM UTC 24
Peak memory 214312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853503545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2853503545
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/44.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.1449470007
Short name T856
Test name
Test status
Simulation time 3007799799 ps
CPU time 74.06 seconds
Started Sep 24 04:58:59 PM UTC 24
Finished Sep 24 05:00:14 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449470007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.1449470007
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/44.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.3883256763
Short name T849
Test name
Test status
Simulation time 714218525 ps
CPU time 66.46 seconds
Started Sep 24 04:58:59 PM UTC 24
Finished Sep 24 05:00:07 PM UTC 24
Peak memory 216364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883256763 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.3883256763
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/44.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.116043385
Short name T793
Test name
Test status
Simulation time 375393313 ps
CPU time 9.72 seconds
Started Sep 24 04:58:56 PM UTC 24
Finished Sep 24 04:59:07 PM UTC 24
Peak memory 212204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116043385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.116043385
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/44.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.2347198783
Short name T808
Test name
Test status
Simulation time 328532332 ps
CPU time 11.51 seconds
Started Sep 24 04:59:13 PM UTC 24
Finished Sep 24 04:59:26 PM UTC 24
Peak memory 211944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347198783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.2347198783
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/45.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2872322316
Short name T139
Test name
Test status
Simulation time 30270974363 ps
CPU time 178.36 seconds
Started Sep 24 04:59:13 PM UTC 24
Finished Sep 24 05:02:15 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872322316 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.2872322316
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/45.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.3877485073
Short name T805
Test name
Test status
Simulation time 655642661 ps
CPU time 5.54 seconds
Started Sep 24 04:59:19 PM UTC 24
Finished Sep 24 04:59:25 PM UTC 24
Peak memory 212204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877485073 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.3877485073
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/45.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.3200337540
Short name T802
Test name
Test status
Simulation time 812307917 ps
CPU time 7.95 seconds
Started Sep 24 04:59:14 PM UTC 24
Finished Sep 24 04:59:23 PM UTC 24
Peak memory 212244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200337540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3200337540
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/45.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random.3271526706
Short name T799
Test name
Test status
Simulation time 425822712 ps
CPU time 7.59 seconds
Started Sep 24 04:59:06 PM UTC 24
Finished Sep 24 04:59:14 PM UTC 24
Peak memory 211980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271526706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.3271526706
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/45.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.3432933230
Short name T154
Test name
Test status
Simulation time 34579490074 ps
CPU time 73.89 seconds
Started Sep 24 04:59:13 PM UTC 24
Finished Sep 24 05:00:29 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432933230 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3432933230
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/45.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.2495292508
Short name T815
Test name
Test status
Simulation time 2189397419 ps
CPU time 17.64 seconds
Started Sep 24 04:59:13 PM UTC 24
Finished Sep 24 04:59:32 PM UTC 24
Peak memory 211964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495292508 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2495292508
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/45.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.1966921238
Short name T800
Test name
Test status
Simulation time 8751072 ps
CPU time 1.78 seconds
Started Sep 24 04:59:13 PM UTC 24
Finished Sep 24 04:59:16 PM UTC 24
Peak memory 210940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966921238 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.1966921238
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/45.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.4195409667
Short name T807
Test name
Test status
Simulation time 693234517 ps
CPU time 11.37 seconds
Started Sep 24 04:59:13 PM UTC 24
Finished Sep 24 04:59:26 PM UTC 24
Peak memory 211996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195409667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.4195409667
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/45.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.1016429090
Short name T787
Test name
Test status
Simulation time 8269250 ps
CPU time 1.74 seconds
Started Sep 24 04:59:00 PM UTC 24
Finished Sep 24 04:59:03 PM UTC 24
Peak memory 210920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016429090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.1016429090
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/45.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.666985377
Short name T809
Test name
Test status
Simulation time 4661479585 ps
CPU time 19.8 seconds
Started Sep 24 04:59:06 PM UTC 24
Finished Sep 24 04:59:27 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666985377 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.666985377
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/45.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.2054436008
Short name T801
Test name
Test status
Simulation time 1145985304 ps
CPU time 11.75 seconds
Started Sep 24 04:59:06 PM UTC 24
Finished Sep 24 04:59:18 PM UTC 24
Peak memory 211992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054436008 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.2054436008
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/45.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.3402169888
Short name T795
Test name
Test status
Simulation time 20556344 ps
CPU time 1.47 seconds
Started Sep 24 04:59:05 PM UTC 24
Finished Sep 24 04:59:08 PM UTC 24
Peak memory 210940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402169888 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.3402169888
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/45.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.2642326975
Short name T847
Test name
Test status
Simulation time 385747446 ps
CPU time 43.78 seconds
Started Sep 24 04:59:19 PM UTC 24
Finished Sep 24 05:00:04 PM UTC 24
Peak memory 214248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642326975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.2642326975
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/45.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.1105948861
Short name T830
Test name
Test status
Simulation time 1758577742 ps
CPU time 24.44 seconds
Started Sep 24 04:59:19 PM UTC 24
Finished Sep 24 04:59:45 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105948861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1105948861
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/45.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1175313378
Short name T898
Test name
Test status
Simulation time 1781892261 ps
CPU time 222.77 seconds
Started Sep 24 04:59:19 PM UTC 24
Finished Sep 24 05:03:06 PM UTC 24
Peak memory 219284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175313378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.1175313378
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/45.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.2778430210
Short name T823
Test name
Test status
Simulation time 1316953126 ps
CPU time 19.35 seconds
Started Sep 24 04:59:19 PM UTC 24
Finished Sep 24 04:59:40 PM UTC 24
Peak memory 212012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778430210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.2778430210
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/45.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.3339821822
Short name T803
Test name
Test status
Simulation time 145502521 ps
CPU time 3.71 seconds
Started Sep 24 04:59:19 PM UTC 24
Finished Sep 24 04:59:24 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339821822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3339821822
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/45.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.3419773045
Short name T835
Test name
Test status
Simulation time 1720118223 ps
CPU time 18.11 seconds
Started Sep 24 04:59:30 PM UTC 24
Finished Sep 24 04:59:49 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419773045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.3419773045
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/46.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1112598007
Short name T900
Test name
Test status
Simulation time 61150037947 ps
CPU time 295.53 seconds
Started Sep 24 04:59:30 PM UTC 24
Finished Sep 24 05:04:30 PM UTC 24
Peak memory 216168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112598007 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.1112598007
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/46.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.217967869
Short name T825
Test name
Test status
Simulation time 64909093 ps
CPU time 4.44 seconds
Started Sep 24 04:59:35 PM UTC 24
Finished Sep 24 04:59:40 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217967869 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.217967869
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/46.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.4144565753
Short name T818
Test name
Test status
Simulation time 81553990 ps
CPU time 4.02 seconds
Started Sep 24 04:59:30 PM UTC 24
Finished Sep 24 04:59:35 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144565753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.4144565753
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/46.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random.1756963332
Short name T814
Test name
Test status
Simulation time 37640634 ps
CPU time 3.65 seconds
Started Sep 24 04:59:26 PM UTC 24
Finished Sep 24 04:59:31 PM UTC 24
Peak memory 211980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756963332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.1756963332
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/46.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.3211829755
Short name T130
Test name
Test status
Simulation time 98623986998 ps
CPU time 200.24 seconds
Started Sep 24 04:59:30 PM UTC 24
Finished Sep 24 05:02:53 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211829755 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3211829755
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/46.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.2156857510
Short name T834
Test name
Test status
Simulation time 3341915081 ps
CPU time 17.99 seconds
Started Sep 24 04:59:30 PM UTC 24
Finished Sep 24 04:59:49 PM UTC 24
Peak memory 212056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156857510 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2156857510
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/46.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.2691122825
Short name T813
Test name
Test status
Simulation time 15849371 ps
CPU time 3.06 seconds
Started Sep 24 04:59:26 PM UTC 24
Finished Sep 24 04:59:30 PM UTC 24
Peak memory 212196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691122825 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.2691122825
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/46.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.4075580118
Short name T826
Test name
Test status
Simulation time 1441214818 ps
CPU time 9.61 seconds
Started Sep 24 04:59:30 PM UTC 24
Finished Sep 24 04:59:41 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075580118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.4075580118
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/46.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.3973924599
Short name T804
Test name
Test status
Simulation time 203199670 ps
CPU time 1.84 seconds
Started Sep 24 04:59:21 PM UTC 24
Finished Sep 24 04:59:24 PM UTC 24
Peak memory 211028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973924599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3973924599
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/46.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1800083833
Short name T820
Test name
Test status
Simulation time 2414644449 ps
CPU time 12.34 seconds
Started Sep 24 04:59:23 PM UTC 24
Finished Sep 24 04:59:36 PM UTC 24
Peak memory 212264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800083833 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1800083833
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/46.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.728662892
Short name T816
Test name
Test status
Simulation time 5018131411 ps
CPU time 6.76 seconds
Started Sep 24 04:59:26 PM UTC 24
Finished Sep 24 04:59:34 PM UTC 24
Peak memory 212048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728662892 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.728662892
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/46.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1706229320
Short name T806
Test name
Test status
Simulation time 9400464 ps
CPU time 1.84 seconds
Started Sep 24 04:59:23 PM UTC 24
Finished Sep 24 04:59:26 PM UTC 24
Peak memory 210936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706229320 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.1706229320
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/46.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.1674608057
Short name T877
Test name
Test status
Simulation time 6266349158 ps
CPU time 64.28 seconds
Started Sep 24 04:59:35 PM UTC 24
Finished Sep 24 05:00:41 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674608057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1674608057
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/46.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.3233948407
Short name T829
Test name
Test status
Simulation time 113808923 ps
CPU time 8.02 seconds
Started Sep 24 04:59:35 PM UTC 24
Finished Sep 24 04:59:44 PM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233948407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.3233948407
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/46.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.540889135
Short name T873
Test name
Test status
Simulation time 1283350554 ps
CPU time 58.62 seconds
Started Sep 24 04:59:35 PM UTC 24
Finished Sep 24 05:00:35 PM UTC 24
Peak memory 216100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540889135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.540889135
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/46.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.4102675880
Short name T859
Test name
Test status
Simulation time 259890475 ps
CPU time 38.74 seconds
Started Sep 24 04:59:35 PM UTC 24
Finished Sep 24 05:00:15 PM UTC 24
Peak memory 214060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102675880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.4102675880
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/46.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.880839798
Short name T837
Test name
Test status
Simulation time 1240523868 ps
CPU time 13.95 seconds
Started Sep 24 04:59:35 PM UTC 24
Finished Sep 24 04:59:50 PM UTC 24
Peak memory 212204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880839798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.880839798
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/46.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.4116787153
Short name T138
Test name
Test status
Simulation time 1516983335 ps
CPU time 23.95 seconds
Started Sep 24 04:59:45 PM UTC 24
Finished Sep 24 05:00:10 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116787153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.4116787153
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/47.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.2559359015
Short name T894
Test name
Test status
Simulation time 95543049010 ps
CPU time 131.75 seconds
Started Sep 24 04:59:45 PM UTC 24
Finished Sep 24 05:01:59 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559359015 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.2559359015
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/47.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3424470026
Short name T845
Test name
Test status
Simulation time 345783454 ps
CPU time 8.04 seconds
Started Sep 24 04:59:49 PM UTC 24
Finished Sep 24 04:59:59 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424470026 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.3424470026
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/47.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.2000993647
Short name T839
Test name
Test status
Simulation time 539489138 ps
CPU time 5.95 seconds
Started Sep 24 04:59:45 PM UTC 24
Finished Sep 24 04:59:52 PM UTC 24
Peak memory 211988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000993647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.2000993647
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/47.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random.2557217373
Short name T840
Test name
Test status
Simulation time 741229473 ps
CPU time 14.49 seconds
Started Sep 24 04:59:39 PM UTC 24
Finished Sep 24 04:59:54 PM UTC 24
Peak memory 212176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557217373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.2557217373
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/47.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.2191412580
Short name T881
Test name
Test status
Simulation time 13264546128 ps
CPU time 69.88 seconds
Started Sep 24 04:59:45 PM UTC 24
Finished Sep 24 05:00:57 PM UTC 24
Peak memory 212268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191412580 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.2191412580
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/47.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.809245088
Short name T882
Test name
Test status
Simulation time 10343853229 ps
CPU time 71.09 seconds
Started Sep 24 04:59:45 PM UTC 24
Finished Sep 24 05:00:58 PM UTC 24
Peak memory 212056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809245088 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.809245088
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/47.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.3759728530
Short name T836
Test name
Test status
Simulation time 31065332 ps
CPU time 3.69 seconds
Started Sep 24 04:59:45 PM UTC 24
Finished Sep 24 04:59:50 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759728530 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.3759728530
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/47.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.1169841660
Short name T842
Test name
Test status
Simulation time 931979710 ps
CPU time 11.39 seconds
Started Sep 24 04:59:45 PM UTC 24
Finished Sep 24 04:59:58 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169841660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.1169841660
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/47.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.2897468732
Short name T827
Test name
Test status
Simulation time 18154227 ps
CPU time 1.62 seconds
Started Sep 24 04:59:38 PM UTC 24
Finished Sep 24 04:59:41 PM UTC 24
Peak memory 210920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897468732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.2897468732
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/47.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.3236893972
Short name T833
Test name
Test status
Simulation time 1925556749 ps
CPU time 8.89 seconds
Started Sep 24 04:59:38 PM UTC 24
Finished Sep 24 04:59:48 PM UTC 24
Peak memory 212200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236893972 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.3236893972
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/47.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3765750257
Short name T832
Test name
Test status
Simulation time 1582807675 ps
CPU time 8.71 seconds
Started Sep 24 04:59:38 PM UTC 24
Finished Sep 24 04:59:48 PM UTC 24
Peak memory 212184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765750257 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3765750257
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/47.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.2806320740
Short name T828
Test name
Test status
Simulation time 9097728 ps
CPU time 1.67 seconds
Started Sep 24 04:59:38 PM UTC 24
Finished Sep 24 04:59:41 PM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806320740 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.2806320740
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/47.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.3611727877
Short name T852
Test name
Test status
Simulation time 204568104 ps
CPU time 20.46 seconds
Started Sep 24 04:59:49 PM UTC 24
Finished Sep 24 05:00:11 PM UTC 24
Peak memory 214252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611727877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.3611727877
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/47.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.1393547657
Short name T879
Test name
Test status
Simulation time 3805174699 ps
CPU time 57.07 seconds
Started Sep 24 04:59:49 PM UTC 24
Finished Sep 24 05:00:48 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393547657 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.1393547657
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/47.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.3050742106
Short name T13
Test name
Test status
Simulation time 5132675078 ps
CPU time 91.29 seconds
Started Sep 24 04:59:49 PM UTC 24
Finished Sep 24 05:01:23 PM UTC 24
Peak memory 216352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050742106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.3050742106
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/47.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.361551791
Short name T851
Test name
Test status
Simulation time 192969324 ps
CPU time 20.37 seconds
Started Sep 24 04:59:49 PM UTC 24
Finished Sep 24 05:00:11 PM UTC 24
Peak memory 214060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361551791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.361551791
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/47.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.189681037
Short name T838
Test name
Test status
Simulation time 41499099 ps
CPU time 5.55 seconds
Started Sep 24 04:59:45 PM UTC 24
Finished Sep 24 04:59:52 PM UTC 24
Peak memory 212012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189681037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.189681037
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/47.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.2407340064
Short name T862
Test name
Test status
Simulation time 2311345980 ps
CPU time 21.07 seconds
Started Sep 24 04:59:58 PM UTC 24
Finished Sep 24 05:00:20 PM UTC 24
Peak memory 212268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407340064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.2407340064
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/48.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.117791528
Short name T874
Test name
Test status
Simulation time 2819136164 ps
CPU time 29.83 seconds
Started Sep 24 05:00:04 PM UTC 24
Finished Sep 24 05:00:38 PM UTC 24
Peak memory 214268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117791528 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.117791528
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/48.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.1964851285
Short name T861
Test name
Test status
Simulation time 86866523 ps
CPU time 8.53 seconds
Started Sep 24 05:00:04 PM UTC 24
Finished Sep 24 05:00:17 PM UTC 24
Peak memory 212076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964851285 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.1964851285
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/48.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.2754475415
Short name T855
Test name
Test status
Simulation time 76377069 ps
CPU time 6.07 seconds
Started Sep 24 05:00:04 PM UTC 24
Finished Sep 24 05:00:14 PM UTC 24
Peak memory 211940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754475415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2754475415
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/48.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random.1419638312
Short name T848
Test name
Test status
Simulation time 445706747 ps
CPU time 8.49 seconds
Started Sep 24 04:59:55 PM UTC 24
Finished Sep 24 05:00:05 PM UTC 24
Peak memory 211980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419638312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.1419638312
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/48.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.1467921537
Short name T887
Test name
Test status
Simulation time 21526578942 ps
CPU time 87.85 seconds
Started Sep 24 04:59:55 PM UTC 24
Finished Sep 24 05:01:25 PM UTC 24
Peak memory 212268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467921537 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1467921537
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/48.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.516378577
Short name T892
Test name
Test status
Simulation time 78466066295 ps
CPU time 107.84 seconds
Started Sep 24 04:59:58 PM UTC 24
Finished Sep 24 05:01:48 PM UTC 24
Peak memory 212248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516378577 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.516378577
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/48.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.1485508826
Short name T844
Test name
Test status
Simulation time 36047936 ps
CPU time 2.31 seconds
Started Sep 24 04:59:55 PM UTC 24
Finished Sep 24 04:59:58 PM UTC 24
Peak memory 212200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485508826 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.1485508826
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/48.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.535900075
Short name T866
Test name
Test status
Simulation time 1492377139 ps
CPU time 15.7 seconds
Started Sep 24 05:00:04 PM UTC 24
Finished Sep 24 05:00:24 PM UTC 24
Peak memory 214204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535900075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.535900075
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/48.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.1260489761
Short name T843
Test name
Test status
Simulation time 43433293 ps
CPU time 2.28 seconds
Started Sep 24 04:59:55 PM UTC 24
Finished Sep 24 04:59:58 PM UTC 24
Peak memory 211988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260489761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.1260489761
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/48.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.3718721167
Short name T857
Test name
Test status
Simulation time 4384696595 ps
CPU time 18.52 seconds
Started Sep 24 04:59:55 PM UTC 24
Finished Sep 24 05:00:15 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718721167 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.3718721167
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/48.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.637079990
Short name T846
Test name
Test status
Simulation time 2578504482 ps
CPU time 6.13 seconds
Started Sep 24 04:59:55 PM UTC 24
Finished Sep 24 05:00:02 PM UTC 24
Peak memory 212052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637079990 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.637079990
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/48.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.1591194174
Short name T841
Test name
Test status
Simulation time 10093779 ps
CPU time 1.8 seconds
Started Sep 24 04:59:55 PM UTC 24
Finished Sep 24 04:59:58 PM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591194174 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.1591194174
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/48.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.1502625604
Short name T870
Test name
Test status
Simulation time 963581251 ps
CPU time 19.95 seconds
Started Sep 24 05:00:07 PM UTC 24
Finished Sep 24 05:00:29 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502625604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.1502625604
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/48.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.538052575
Short name T885
Test name
Test status
Simulation time 3574591349 ps
CPU time 63.44 seconds
Started Sep 24 05:00:10 PM UTC 24
Finished Sep 24 05:01:16 PM UTC 24
Peak memory 212064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538052575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.538052575
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/48.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3994456903
Short name T899
Test name
Test status
Simulation time 1029075323 ps
CPU time 175.39 seconds
Started Sep 24 05:00:10 PM UTC 24
Finished Sep 24 05:03:09 PM UTC 24
Peak memory 216108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994456903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.3994456903
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/48.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.2765986483
Short name T884
Test name
Test status
Simulation time 353221603 ps
CPU time 56.84 seconds
Started Sep 24 05:00:10 PM UTC 24
Finished Sep 24 05:01:10 PM UTC 24
Peak memory 214056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765986483 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.2765986483
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/48.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.72919919
Short name T858
Test name
Test status
Simulation time 1432767177 ps
CPU time 6.54 seconds
Started Sep 24 05:00:04 PM UTC 24
Finished Sep 24 05:00:15 PM UTC 24
Peak memory 212200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72919919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.72919919
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/48.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.3826682804
Short name T124
Test name
Test status
Simulation time 1344398962 ps
CPU time 20.99 seconds
Started Sep 24 05:00:17 PM UTC 24
Finished Sep 24 05:00:40 PM UTC 24
Peak memory 212204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826682804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.3826682804
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/49.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3502107673
Short name T126
Test name
Test status
Simulation time 138886995678 ps
CPU time 322.45 seconds
Started Sep 24 05:00:17 PM UTC 24
Finished Sep 24 05:05:45 PM UTC 24
Peak memory 216172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502107673 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.3502107673
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/49.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1147957500
Short name T872
Test name
Test status
Simulation time 754384407 ps
CPU time 11.05 seconds
Started Sep 24 05:00:20 PM UTC 24
Finished Sep 24 05:00:32 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147957500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.1147957500
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/49.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.1143740755
Short name T868
Test name
Test status
Simulation time 189295947 ps
CPU time 8.99 seconds
Started Sep 24 05:00:18 PM UTC 24
Finished Sep 24 05:00:28 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143740755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.1143740755
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/49.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random.1250086125
Short name T867
Test name
Test status
Simulation time 68047620 ps
CPU time 11.6 seconds
Started Sep 24 05:00:13 PM UTC 24
Finished Sep 24 05:00:27 PM UTC 24
Peak memory 211980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250086125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.1250086125
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/49.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.340848839
Short name T897
Test name
Test status
Simulation time 44211325646 ps
CPU time 144.93 seconds
Started Sep 24 05:00:17 PM UTC 24
Finished Sep 24 05:02:45 PM UTC 24
Peak memory 212264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340848839 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.340848839
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/49.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.957898324
Short name T878
Test name
Test status
Simulation time 3935514702 ps
CPU time 28.43 seconds
Started Sep 24 05:00:17 PM UTC 24
Finished Sep 24 05:00:48 PM UTC 24
Peak memory 212056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957898324 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.957898324
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/49.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.2183017576
Short name T864
Test name
Test status
Simulation time 25300231 ps
CPU time 4.18 seconds
Started Sep 24 05:00:17 PM UTC 24
Finished Sep 24 05:00:23 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183017576 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.2183017576
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/49.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.3077027763
Short name T869
Test name
Test status
Simulation time 714620076 ps
CPU time 9.12 seconds
Started Sep 24 05:00:18 PM UTC 24
Finished Sep 24 05:00:28 PM UTC 24
Peak memory 211996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077027763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.3077027763
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/49.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.1305381949
Short name T854
Test name
Test status
Simulation time 19590788 ps
CPU time 1.83 seconds
Started Sep 24 05:00:10 PM UTC 24
Finished Sep 24 05:00:14 PM UTC 24
Peak memory 210968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305381949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1305381949
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/49.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.969820705
Short name T871
Test name
Test status
Simulation time 13761285699 ps
CPU time 16.25 seconds
Started Sep 24 05:00:13 PM UTC 24
Finished Sep 24 05:00:31 PM UTC 24
Peak memory 212200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969820705 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.969820705
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/49.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.555814289
Short name T863
Test name
Test status
Simulation time 1623772528 ps
CPU time 7.78 seconds
Started Sep 24 05:00:13 PM UTC 24
Finished Sep 24 05:00:23 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555814289 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.555814289
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/49.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.985706952
Short name T860
Test name
Test status
Simulation time 15606330 ps
CPU time 1.8 seconds
Started Sep 24 05:00:13 PM UTC 24
Finished Sep 24 05:00:16 PM UTC 24
Peak memory 210940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985706952 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.985706952
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/49.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.2608510641
Short name T890
Test name
Test status
Simulation time 3556829499 ps
CPU time 64.75 seconds
Started Sep 24 05:00:23 PM UTC 24
Finished Sep 24 05:01:29 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608510641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.2608510641
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/49.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2526762412
Short name T876
Test name
Test status
Simulation time 156155059 ps
CPU time 10.91 seconds
Started Sep 24 05:00:28 PM UTC 24
Finished Sep 24 05:00:40 PM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526762412 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2526762412
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/49.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1623596639
Short name T14
Test name
Test status
Simulation time 2388015551 ps
CPU time 144.53 seconds
Started Sep 24 05:00:28 PM UTC 24
Finished Sep 24 05:02:56 PM UTC 24
Peak memory 216152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623596639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.1623596639
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/49.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.528438788
Short name T883
Test name
Test status
Simulation time 349649966 ps
CPU time 32.82 seconds
Started Sep 24 05:00:28 PM UTC 24
Finished Sep 24 05:01:03 PM UTC 24
Peak memory 214060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528438788 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.528438788
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/49.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.3570994260
Short name T865
Test name
Test status
Simulation time 12684866 ps
CPU time 2.1 seconds
Started Sep 24 05:00:20 PM UTC 24
Finished Sep 24 05:00:23 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570994260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3570994260
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/49.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device.1242116940
Short name T101
Test name
Test status
Simulation time 39210367 ps
CPU time 8.37 seconds
Started Sep 24 04:42:02 PM UTC 24
Finished Sep 24 04:42:11 PM UTC 24
Peak memory 212200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242116940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1242116940
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/5.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.3828602915
Short name T198
Test name
Test status
Simulation time 65104890598 ps
CPU time 128.14 seconds
Started Sep 24 04:42:02 PM UTC 24
Finished Sep 24 04:44:12 PM UTC 24
Peak memory 214116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828602915 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.3828602915
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/5.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.1727902490
Short name T247
Test name
Test status
Simulation time 1257817218 ps
CPU time 3.5 seconds
Started Sep 24 04:42:11 PM UTC 24
Finished Sep 24 04:42:15 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727902490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1727902490
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/5.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_error_random.839975848
Short name T251
Test name
Test status
Simulation time 1794394107 ps
CPU time 16.42 seconds
Started Sep 24 04:42:05 PM UTC 24
Finished Sep 24 04:42:23 PM UTC 24
Peak memory 212176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839975848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.839975848
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/5.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random.2118862090
Short name T75
Test name
Test status
Simulation time 228412820 ps
CPU time 3.79 seconds
Started Sep 24 04:42:00 PM UTC 24
Finished Sep 24 04:42:05 PM UTC 24
Peak memory 212176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118862090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.2118862090
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/5.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_large_delays.976229210
Short name T278
Test name
Test status
Simulation time 145860029018 ps
CPU time 154.76 seconds
Started Sep 24 04:42:00 PM UTC 24
Finished Sep 24 04:44:38 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976229210 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.976229210
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/5.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_slow_rsp.2079482747
Short name T111
Test name
Test status
Simulation time 27732762186 ps
CPU time 82.22 seconds
Started Sep 24 04:42:02 PM UTC 24
Finished Sep 24 04:43:26 PM UTC 24
Peak memory 212052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079482747 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2079482747
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/5.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_zero_delays.3595706740
Short name T98
Test name
Test status
Simulation time 20769928 ps
CPU time 3.16 seconds
Started Sep 24 04:42:00 PM UTC 24
Finished Sep 24 04:42:04 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595706740 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.3595706740
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/5.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_same_source.185207989
Short name T102
Test name
Test status
Simulation time 66001447 ps
CPU time 5.9 seconds
Started Sep 24 04:42:05 PM UTC 24
Finished Sep 24 04:42:12 PM UTC 24
Peak memory 214012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185207989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.185207989
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/5.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke.1160986958
Short name T135
Test name
Test status
Simulation time 10435400 ps
CPU time 2.28 seconds
Started Sep 24 04:41:52 PM UTC 24
Finished Sep 24 04:41:55 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160986958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.1160986958
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/5.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_large_delays.1406125244
Short name T100
Test name
Test status
Simulation time 4241669437 ps
CPU time 9.96 seconds
Started Sep 24 04:42:00 PM UTC 24
Finished Sep 24 04:42:11 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406125244 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.1406125244
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/5.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.1896190413
Short name T99
Test name
Test status
Simulation time 730773516 ps
CPU time 8.82 seconds
Started Sep 24 04:42:00 PM UTC 24
Finished Sep 24 04:42:10 PM UTC 24
Peak memory 211980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896190413 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1896190413
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/5.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.4196389106
Short name T136
Test name
Test status
Simulation time 8988507 ps
CPU time 1.34 seconds
Started Sep 24 04:41:53 PM UTC 24
Finished Sep 24 04:41:56 PM UTC 24
Peak memory 210980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196389106 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.4196389106
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/5.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all.3336416159
Short name T257
Test name
Test status
Simulation time 330958715 ps
CPU time 41.74 seconds
Started Sep 24 04:42:12 PM UTC 24
Finished Sep 24 04:42:55 PM UTC 24
Peak memory 212012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336416159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3336416159
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/5.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_error.2632953404
Short name T104
Test name
Test status
Simulation time 7169423924 ps
CPU time 52.99 seconds
Started Sep 24 04:42:13 PM UTC 24
Finished Sep 24 04:43:08 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632953404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2632953404
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/5.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.92494909
Short name T230
Test name
Test status
Simulation time 1112140088 ps
CPU time 263.04 seconds
Started Sep 24 04:42:12 PM UTC 24
Finished Sep 24 04:46:39 PM UTC 24
Peak memory 218136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92494909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.92494909
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/5.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.3362135574
Short name T193
Test name
Test status
Simulation time 841921791 ps
CPU time 87.68 seconds
Started Sep 24 04:42:16 PM UTC 24
Finished Sep 24 04:43:45 PM UTC 24
Peak memory 218156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362135574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.3362135574
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/5.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_unmapped_addr.660221850
Short name T103
Test name
Test status
Simulation time 374778190 ps
CPU time 7.24 seconds
Started Sep 24 04:42:06 PM UTC 24
Finished Sep 24 04:42:15 PM UTC 24
Peak memory 212012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660221850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.660221850
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/5.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device.2131503482
Short name T35
Test name
Test status
Simulation time 3277372206 ps
CPU time 24.09 seconds
Started Sep 24 04:42:35 PM UTC 24
Finished Sep 24 04:43:01 PM UTC 24
Peak memory 212264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131503482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2131503482
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/6.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.3738281214
Short name T108
Test name
Test status
Simulation time 490130311 ps
CPU time 16.35 seconds
Started Sep 24 04:43:00 PM UTC 24
Finished Sep 24 04:43:18 PM UTC 24
Peak memory 211948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738281214 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.3738281214
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/6.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_error_random.2559582605
Short name T259
Test name
Test status
Simulation time 1159276594 ps
CPU time 13.29 seconds
Started Sep 24 04:42:45 PM UTC 24
Finished Sep 24 04:42:59 PM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559582605 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2559582605
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/6.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random.863767668
Short name T252
Test name
Test status
Simulation time 216281470 ps
CPU time 7.74 seconds
Started Sep 24 04:42:22 PM UTC 24
Finished Sep 24 04:42:31 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863767668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.863767668
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/6.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_large_delays.2217006094
Short name T274
Test name
Test status
Simulation time 56020288599 ps
CPU time 114.59 seconds
Started Sep 24 04:42:31 PM UTC 24
Finished Sep 24 04:44:28 PM UTC 24
Peak memory 212264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217006094 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2217006094
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/6.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_slow_rsp.807729995
Short name T79
Test name
Test status
Simulation time 16382510190 ps
CPU time 83.78 seconds
Started Sep 24 04:42:34 PM UTC 24
Finished Sep 24 04:43:59 PM UTC 24
Peak memory 212048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807729995 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.807729995
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/6.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_zero_delays.3445014608
Short name T255
Test name
Test status
Simulation time 71937284 ps
CPU time 12.27 seconds
Started Sep 24 04:42:24 PM UTC 24
Finished Sep 24 04:42:38 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445014608 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.3445014608
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/6.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_same_source.2137965309
Short name T256
Test name
Test status
Simulation time 392334207 ps
CPU time 4.35 seconds
Started Sep 24 04:42:38 PM UTC 24
Finished Sep 24 04:42:44 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137965309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2137965309
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/6.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke.2970704333
Short name T76
Test name
Test status
Simulation time 38596364 ps
CPU time 1.89 seconds
Started Sep 24 04:42:16 PM UTC 24
Finished Sep 24 04:42:18 PM UTC 24
Peak memory 210988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970704333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2970704333
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/6.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_large_delays.3760109433
Short name T254
Test name
Test status
Simulation time 4871673955 ps
CPU time 16.12 seconds
Started Sep 24 04:42:19 PM UTC 24
Finished Sep 24 04:42:37 PM UTC 24
Peak memory 212136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760109433 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3760109433
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/6.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.1350260312
Short name T253
Test name
Test status
Simulation time 1993563947 ps
CPU time 11.06 seconds
Started Sep 24 04:42:21 PM UTC 24
Finished Sep 24 04:42:33 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350260312 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1350260312
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/6.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.2362019484
Short name T250
Test name
Test status
Simulation time 20584410 ps
CPU time 2.05 seconds
Started Sep 24 04:42:18 PM UTC 24
Finished Sep 24 04:42:21 PM UTC 24
Peak memory 211996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362019484 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.2362019484
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/6.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all.698983818
Short name T262
Test name
Test status
Simulation time 2724413949 ps
CPU time 37.62 seconds
Started Sep 24 04:43:00 PM UTC 24
Finished Sep 24 04:43:39 PM UTC 24
Peak memory 214280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698983818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.698983818
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/6.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_error.1121104496
Short name T107
Test name
Test status
Simulation time 350735670 ps
CPU time 11.44 seconds
Started Sep 24 04:43:02 PM UTC 24
Finished Sep 24 04:43:15 PM UTC 24
Peak memory 211976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121104496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.1121104496
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/6.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.111275422
Short name T81
Test name
Test status
Simulation time 1656557771 ps
CPU time 89.25 seconds
Started Sep 24 04:43:02 PM UTC 24
Finished Sep 24 04:44:34 PM UTC 24
Peak memory 216084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111275422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.111275422
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/6.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1753713993
Short name T217
Test name
Test status
Simulation time 9620928457 ps
CPU time 219.2 seconds
Started Sep 24 04:43:03 PM UTC 24
Finished Sep 24 04:46:46 PM UTC 24
Peak memory 218372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753713993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.1753713993
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/6.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_unmapped_addr.3320551914
Short name T258
Test name
Test status
Simulation time 9349452 ps
CPU time 1.88 seconds
Started Sep 24 04:42:56 PM UTC 24
Finished Sep 24 04:42:59 PM UTC 24
Peak memory 210928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320551914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3320551914
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/6.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device.3743794111
Short name T260
Test name
Test status
Simulation time 15922539 ps
CPU time 4.03 seconds
Started Sep 24 04:43:27 PM UTC 24
Finished Sep 24 04:43:32 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743794111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.3743794111
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/7.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.987275224
Short name T197
Test name
Test status
Simulation time 55307473040 ps
CPU time 455.88 seconds
Started Sep 24 04:43:27 PM UTC 24
Finished Sep 24 04:51:09 PM UTC 24
Peak memory 214096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987275224 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.987275224
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/7.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.399910078
Short name T265
Test name
Test status
Simulation time 70191462 ps
CPU time 1.96 seconds
Started Sep 24 04:43:42 PM UTC 24
Finished Sep 24 04:43:45 PM UTC 24
Peak memory 210944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399910078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.399910078
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/7.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_error_random.519324933
Short name T264
Test name
Test status
Simulation time 400958112 ps
CPU time 8.48 seconds
Started Sep 24 04:43:34 PM UTC 24
Finished Sep 24 04:43:44 PM UTC 24
Peak memory 211988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519324933 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.519324933
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/7.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random.3986736765
Short name T109
Test name
Test status
Simulation time 45776066 ps
CPU time 3.24 seconds
Started Sep 24 04:43:16 PM UTC 24
Finished Sep 24 04:43:21 PM UTC 24
Peak memory 211980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986736765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.3986736765
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/7.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_large_delays.3161732487
Short name T301
Test name
Test status
Simulation time 38861013061 ps
CPU time 152.6 seconds
Started Sep 24 04:43:22 PM UTC 24
Finished Sep 24 04:45:58 PM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161732487 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3161732487
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/7.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_slow_rsp.1786804296
Short name T127
Test name
Test status
Simulation time 24454450058 ps
CPU time 131.03 seconds
Started Sep 24 04:43:24 PM UTC 24
Finished Sep 24 04:45:38 PM UTC 24
Peak memory 212052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786804296 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_per
i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.1786804296
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/7.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_zero_delays.591674522
Short name T261
Test name
Test status
Simulation time 74728528 ps
CPU time 13.5 seconds
Started Sep 24 04:43:19 PM UTC 24
Finished Sep 24 04:43:34 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591674522 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.591674522
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/7.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_same_source.3524856140
Short name T263
Test name
Test status
Simulation time 115561622 ps
CPU time 6.99 seconds
Started Sep 24 04:43:33 PM UTC 24
Finished Sep 24 04:43:41 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524856140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3524856140
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/7.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke.1350468339
Short name T105
Test name
Test status
Simulation time 9479973 ps
CPU time 1.83 seconds
Started Sep 24 04:43:08 PM UTC 24
Finished Sep 24 04:43:11 PM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350468339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.1350468339
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/7.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_large_delays.157308862
Short name T78
Test name
Test status
Simulation time 2430832714 ps
CPU time 12.03 seconds
Started Sep 24 04:43:13 PM UTC 24
Finished Sep 24 04:43:26 PM UTC 24
Peak memory 212264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157308862 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.157308862
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/7.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.378345100
Short name T110
Test name
Test status
Simulation time 1461115852 ps
CPU time 7.8 seconds
Started Sep 24 04:43:14 PM UTC 24
Finished Sep 24 04:43:23 PM UTC 24
Peak memory 212196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378345100 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.378345100
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/7.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.138420738
Short name T106
Test name
Test status
Simulation time 12905692 ps
CPU time 1.89 seconds
Started Sep 24 04:43:10 PM UTC 24
Finished Sep 24 04:43:13 PM UTC 24
Peak memory 210980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138420738 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.138420738
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/7.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all.1168635039
Short name T175
Test name
Test status
Simulation time 603114291 ps
CPU time 84.56 seconds
Started Sep 24 04:43:42 PM UTC 24
Finished Sep 24 04:45:09 PM UTC 24
Peak memory 216108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168635039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1168635039
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/7.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_error.2468820785
Short name T194
Test name
Test status
Simulation time 4775121455 ps
CPU time 56.71 seconds
Started Sep 24 04:43:46 PM UTC 24
Finished Sep 24 04:44:44 PM UTC 24
Peak memory 212264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468820785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2468820785
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/7.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.4149830847
Short name T239
Test name
Test status
Simulation time 484324169 ps
CPU time 29.23 seconds
Started Sep 24 04:43:46 PM UTC 24
Finished Sep 24 04:44:16 PM UTC 24
Peak memory 214060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149830847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.4149830847
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/7.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_unmapped_addr.60438664
Short name T266
Test name
Test status
Simulation time 43344090 ps
CPU time 5.64 seconds
Started Sep 24 04:43:42 PM UTC 24
Finished Sep 24 04:43:49 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60438664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.60438664
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/7.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device.840559423
Short name T224
Test name
Test status
Simulation time 1399372534 ps
CPU time 26.23 seconds
Started Sep 24 04:44:06 PM UTC 24
Finished Sep 24 04:44:33 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840559423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xba
r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.840559423
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/8.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.1333094574
Short name T225
Test name
Test status
Simulation time 26006466681 ps
CPU time 26.41 seconds
Started Sep 24 04:44:07 PM UTC 24
Finished Sep 24 04:44:35 PM UTC 24
Peak memory 212264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333094574 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.1333094574
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/8.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.2606619893
Short name T277
Test name
Test status
Simulation time 1484811764 ps
CPU time 18.23 seconds
Started Sep 24 04:44:17 PM UTC 24
Finished Sep 24 04:44:37 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606619893 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.2606619893
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/8.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_error_random.1059009504
Short name T273
Test name
Test status
Simulation time 57904488 ps
CPU time 5.71 seconds
Started Sep 24 04:44:12 PM UTC 24
Finished Sep 24 04:44:19 PM UTC 24
Peak memory 211988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059009504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.1059009504
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/8.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random.4138400482
Short name T269
Test name
Test status
Simulation time 67498279 ps
CPU time 6.45 seconds
Started Sep 24 04:43:51 PM UTC 24
Finished Sep 24 04:43:58 PM UTC 24
Peak memory 211980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138400482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.4138400482
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/8.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_large_delays.87129770
Short name T82
Test name
Test status
Simulation time 15307714026 ps
CPU time 52.74 seconds
Started Sep 24 04:44:00 PM UTC 24
Finished Sep 24 04:44:55 PM UTC 24
Peak memory 212264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87129770 -assert nopostproc +UVM_TESTNAME=xbar_base_
test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_p
eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.87129770
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/8.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_slow_rsp.948261190
Short name T276
Test name
Test status
Simulation time 6352084750 ps
CPU time 26.97 seconds
Started Sep 24 04:44:06 PM UTC 24
Finished Sep 24 04:44:34 PM UTC 24
Peak memory 212244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948261190 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.948261190
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/8.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_zero_delays.3533305506
Short name T271
Test name
Test status
Simulation time 92763534 ps
CPU time 5.93 seconds
Started Sep 24 04:43:59 PM UTC 24
Finished Sep 24 04:44:06 PM UTC 24
Peak memory 212260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533305506 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.3533305506
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/8.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_same_source.3427369047
Short name T272
Test name
Test status
Simulation time 124460340 ps
CPU time 3.23 seconds
Started Sep 24 04:44:07 PM UTC 24
Finished Sep 24 04:44:12 PM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427369047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.3427369047
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/8.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke.3175521888
Short name T267
Test name
Test status
Simulation time 62142657 ps
CPU time 2.42 seconds
Started Sep 24 04:43:46 PM UTC 24
Finished Sep 24 04:43:49 PM UTC 24
Peak memory 212008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175521888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3175521888
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/8.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_large_delays.3766600782
Short name T270
Test name
Test status
Simulation time 1835498314 ps
CPU time 13.27 seconds
Started Sep 24 04:43:51 PM UTC 24
Finished Sep 24 04:44:05 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766600782 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3766600782
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/8.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.1856352229
Short name T153
Test name
Test status
Simulation time 2155395027 ps
CPU time 13.73 seconds
Started Sep 24 04:43:51 PM UTC 24
Finished Sep 24 04:44:05 PM UTC 24
Peak memory 212308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856352229 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.1856352229
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/8.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.1145165462
Short name T268
Test name
Test status
Simulation time 10167715 ps
CPU time 1.85 seconds
Started Sep 24 04:43:47 PM UTC 24
Finished Sep 24 04:43:50 PM UTC 24
Peak memory 211040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145165462 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.1145165462
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/8.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all.1059587054
Short name T166
Test name
Test status
Simulation time 11378614310 ps
CPU time 83.14 seconds
Started Sep 24 04:44:21 PM UTC 24
Finished Sep 24 04:45:46 PM UTC 24
Peak memory 216172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059587054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1059587054
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/8.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_error.1056511046
Short name T281
Test name
Test status
Simulation time 265210393 ps
CPU time 15.48 seconds
Started Sep 24 04:44:26 PM UTC 24
Finished Sep 24 04:44:43 PM UTC 24
Peak memory 212200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056511046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.1056511046
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/8.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.1467097945
Short name T90
Test name
Test status
Simulation time 2860236915 ps
CPU time 63.26 seconds
Started Sep 24 04:44:21 PM UTC 24
Finished Sep 24 04:45:26 PM UTC 24
Peak memory 216168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467097945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.1467097945
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/8.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.563593293
Short name T237
Test name
Test status
Simulation time 462218268 ps
CPU time 51.38 seconds
Started Sep 24 04:44:31 PM UTC 24
Finished Sep 24 04:45:24 PM UTC 24
Peak memory 214056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563593293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.563593293
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/8.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_unmapped_addr.2100493776
Short name T80
Test name
Test status
Simulation time 447248152 ps
CPU time 9.96 seconds
Started Sep 24 04:44:14 PM UTC 24
Finished Sep 24 04:44:25 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100493776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2100493776
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/8.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device.4133534582
Short name T89
Test name
Test status
Simulation time 829332304 ps
CPU time 17.44 seconds
Started Sep 24 04:44:41 PM UTC 24
Finished Sep 24 04:45:00 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133534582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb
ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.4133534582
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/9.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.3117728980
Short name T149
Test name
Test status
Simulation time 14443542847 ps
CPU time 38.96 seconds
Started Sep 24 04:44:41 PM UTC 24
Finished Sep 24 04:45:22 PM UTC 24
Peak memory 214312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117728980 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.3117728980
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/9.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.482992441
Short name T285
Test name
Test status
Simulation time 312457082 ps
CPU time 6.2 seconds
Started Sep 24 04:44:46 PM UTC 24
Finished Sep 24 04:44:53 PM UTC 24
Peak memory 212012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482992441 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.482992441
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/9.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_error_random.2797266308
Short name T169
Test name
Test status
Simulation time 3030396768 ps
CPU time 12.08 seconds
Started Sep 24 04:44:44 PM UTC 24
Finished Sep 24 04:44:58 PM UTC 24
Peak memory 212052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797266308 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2797266308
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/9.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random.3592055934
Short name T171
Test name
Test status
Simulation time 934507746 ps
CPU time 22.05 seconds
Started Sep 24 04:44:35 PM UTC 24
Finished Sep 24 04:44:59 PM UTC 24
Peak memory 211980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592055934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.3592055934
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/9.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_large_delays.2886532923
Short name T84
Test name
Test status
Simulation time 5466730735 ps
CPU time 35.06 seconds
Started Sep 24 04:44:41 PM UTC 24
Finished Sep 24 04:45:18 PM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886532923 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar
_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.2886532923
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/9.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_slow_rsp.267080350
Short name T336
Test name
Test status
Simulation time 25009684006 ps
CPU time 182.2 seconds
Started Sep 24 04:44:41 PM UTC 24
Finished Sep 24 04:47:47 PM UTC 24
Peak memory 212052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267080350 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.267080350
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/9.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_zero_delays.1879076040
Short name T280
Test name
Test status
Simulation time 110150500 ps
CPU time 5.16 seconds
Started Sep 24 04:44:36 PM UTC 24
Finished Sep 24 04:44:43 PM UTC 24
Peak memory 212000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879076040 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.1879076040
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/9.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_same_source.3749051045
Short name T283
Test name
Test status
Simulation time 1311595141 ps
CPU time 4.78 seconds
Started Sep 24 04:44:43 PM UTC 24
Finished Sep 24 04:44:49 PM UTC 24
Peak memory 211996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749051045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3749051045
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/9.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke.3262157437
Short name T275
Test name
Test status
Simulation time 8715306 ps
CPU time 1.96 seconds
Started Sep 24 04:44:31 PM UTC 24
Finished Sep 24 04:44:34 PM UTC 24
Peak memory 210988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262157437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3262157437
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/9.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_large_delays.1038027910
Short name T284
Test name
Test status
Simulation time 3862138221 ps
CPU time 15.07 seconds
Started Sep 24 04:44:35 PM UTC 24
Finished Sep 24 04:44:52 PM UTC 24
Peak memory 212068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038027910 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_
peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.1038027910
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/9.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.2992029229
Short name T282
Test name
Test status
Simulation time 855331344 ps
CPU time 9.76 seconds
Started Sep 24 04:44:35 PM UTC 24
Finished Sep 24 04:44:46 PM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992029229 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2992029229
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/9.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.848311818
Short name T279
Test name
Test status
Simulation time 15052166 ps
CPU time 1.94 seconds
Started Sep 24 04:44:35 PM UTC 24
Finished Sep 24 04:44:38 PM UTC 24
Peak memory 210932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848311818 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/x
bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.848311818
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/9.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all.1718825164
Short name T173
Test name
Test status
Simulation time 135519374 ps
CPU time 12.95 seconds
Started Sep 24 04:44:47 PM UTC 24
Finished Sep 24 04:45:01 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718825164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1718825164
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/9.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_error.341095789
Short name T287
Test name
Test status
Simulation time 248403483 ps
CPU time 2.7 seconds
Started Sep 24 04:44:52 PM UTC 24
Finished Sep 24 04:44:56 PM UTC 24
Peak memory 212004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341095789 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.341095789
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/9.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.1648028362
Short name T92
Test name
Test status
Simulation time 9145416221 ps
CPU time 148.72 seconds
Started Sep 24 04:44:50 PM UTC 24
Finished Sep 24 04:47:22 PM UTC 24
Peak memory 216168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648028362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.1648028362
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/9.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.3798188836
Short name T339
Test name
Test status
Simulation time 6328632129 ps
CPU time 174.81 seconds
Started Sep 24 04:44:54 PM UTC 24
Finished Sep 24 04:47:52 PM UTC 24
Peak memory 216172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798188836 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.3798188836
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/9.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_unmapped_addr.3564786317
Short name T286
Test name
Test status
Simulation time 71495871 ps
CPU time 8.52 seconds
Started Sep 24 04:44:44 PM UTC 24
Finished Sep 24 04:44:54 PM UTC 24
Peak memory 212072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564786317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_pe
ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3564786317
Directory /workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/9.xbar_unmapped_addr/latest
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