Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	446	1			T16	1		T56	1		T27	1
all_values[1]	449	1			T16	2		T56	1		T42	1
all_values[2]	412	1			T16	3		T27	1		T47	1
all_values[3]	491	1			T56	1		T53	1		T305	1
all_values[4]	425	1			T56	1		T42	1		T299	1
all_values[5]	434	1			T56	1		T42	2		T299	2
all_values[6]	449	1			T27	1		T53	1		T358	1
all_values[7]	436	1			T56	1		T47	3		T296	1
all_values[8]	464	1			T56	2		T42	1		T47	2
all_values[9]	450	1			T42	1		T299	1		T53	1
all_values[10]	466	1			T27	1		T299	1		T71	3
all_values[11]	470	1			T16	1		T47	1		T71	1
all_values[12]	439	1			T16	1		T27	1		T47	1
all_values[13]	417	1			T56	1		T47	3		T299	1
all_values[14]	458	1			T56	3		T42	1		T47	1
all_values[15]	461	1			T47	1		T296	1		T50	2
all_values[16]	463	1			T42	3		T50	1		T149	1
all_values[17]	424	1			T16	1		T42	2		T47	1
all_values[18]	444	1			T56	1		T27	1		T299	2
all_values[19]	451	1			T56	1		T27	1		T47	1
all_values[20]	482	1			T47	1		T149	1		T305	5
all_values[21]	431	1			T16	1		T50	1		T358	1
all_values[22]	448	1			T47	1		T53	1		T358	1
all_values[23]	448	1			T16	2		T42	1		T299	1
all_values[24]	428	1			T27	1		T42	2		T71	1
all_values[25]	444	1			T16	1		T296	2		T149	3
all_values[26]	440	1			T16	1		T47	1		T71	1