| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.30 | 100.00 | 95.80 | 100.00 | 100.00 | 100.00 | 100.00 |
| T775 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.2332822461 | Oct 02 07:03:32 PM UTC 24 | Oct 02 07:03:37 PM UTC 24 | 53534441 ps | ||
| T776 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.2956571394 | Oct 02 07:03:30 PM UTC 24 | Oct 02 07:03:38 PM UTC 24 | 52642431 ps | ||
| T777 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.54997619 | Oct 02 07:02:35 PM UTC 24 | Oct 02 07:03:38 PM UTC 24 | 6350869070 ps | ||
| T778 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.695124793 | Oct 02 07:03:35 PM UTC 24 | Oct 02 07:03:39 PM UTC 24 | 47124058 ps | ||
| T779 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.3472078770 | Oct 02 07:03:32 PM UTC 24 | Oct 02 07:03:39 PM UTC 24 | 82374500 ps | ||
| T780 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.617535342 | Oct 02 07:02:20 PM UTC 24 | Oct 02 07:03:41 PM UTC 24 | 15824858821 ps | ||
| T781 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1101969312 | Oct 02 07:03:39 PM UTC 24 | Oct 02 07:03:41 PM UTC 24 | 9355218 ps | ||
| T782 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1471091559 | Oct 02 07:03:26 PM UTC 24 | Oct 02 07:03:42 PM UTC 24 | 4608308847 ps | ||
| T783 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.2264355213 | Oct 02 07:02:54 PM UTC 24 | Oct 02 07:03:42 PM UTC 24 | 422068904 ps | ||
| T784 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.23621749 | Oct 02 07:03:26 PM UTC 24 | Oct 02 07:03:42 PM UTC 24 | 2440212322 ps | ||
| T785 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.657164009 | Oct 02 07:03:40 PM UTC 24 | Oct 02 07:03:44 PM UTC 24 | 21210712 ps | ||
| T786 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_slow_rsp.2527584350 | Oct 02 07:01:30 PM UTC 24 | Oct 02 07:03:45 PM UTC 24 | 16753743178 ps | ||
| T787 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.2327285352 | Oct 02 07:03:52 PM UTC 24 | Oct 02 07:04:05 PM UTC 24 | 3942525618 ps | ||
| T788 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.1093978135 | Oct 02 07:03:28 PM UTC 24 | Oct 02 07:03:46 PM UTC 24 | 3034436218 ps | ||
| T789 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.254635254 | Oct 02 07:03:39 PM UTC 24 | Oct 02 07:03:46 PM UTC 24 | 3565347533 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_large_delays.2794324580 | Oct 02 07:00:17 PM UTC 24 | Oct 02 07:03:48 PM UTC 24 | 235840941783 ps | ||
| T790 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.3749324694 | Oct 02 07:03:45 PM UTC 24 | Oct 02 07:03:48 PM UTC 24 | 133645418 ps | ||
| T791 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2687243707 | Oct 02 07:03:32 PM UTC 24 | Oct 02 07:03:49 PM UTC 24 | 721069970 ps | ||
| T792 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.783740344 | Oct 02 07:03:20 PM UTC 24 | Oct 02 07:03:49 PM UTC 24 | 4057259728 ps | ||
| T793 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1319238105 | Oct 02 07:03:39 PM UTC 24 | Oct 02 07:03:50 PM UTC 24 | 3462410805 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.2015978430 | Oct 02 07:03:44 PM UTC 24 | Oct 02 07:03:51 PM UTC 24 | 38890266 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.2379281986 | Oct 02 07:02:40 PM UTC 24 | Oct 02 07:03:51 PM UTC 24 | 10023346645 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random.1494794314 | Oct 02 07:03:40 PM UTC 24 | Oct 02 07:03:52 PM UTC 24 | 599662685 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.2794015408 | Oct 02 07:03:44 PM UTC 24 | Oct 02 07:03:53 PM UTC 24 | 81105746 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1846757206 | Oct 02 07:03:08 PM UTC 24 | Oct 02 07:03:53 PM UTC 24 | 438648950 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.324574889 | Oct 02 07:03:47 PM UTC 24 | Oct 02 07:03:55 PM UTC 24 | 329539607 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.4059166219 | Oct 02 07:03:52 PM UTC 24 | Oct 02 07:03:55 PM UTC 24 | 9694390 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.2760178155 | Oct 02 07:03:52 PM UTC 24 | Oct 02 07:03:55 PM UTC 24 | 9655960 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.3894186716 | Oct 02 07:03:54 PM UTC 24 | Oct 02 07:04:01 PM UTC 24 | 79334159 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.3029726404 | Oct 02 07:03:56 PM UTC 24 | Oct 02 07:04:01 PM UTC 24 | 17056243 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1176364326 | Oct 02 07:03:34 PM UTC 24 | Oct 02 07:04:02 PM UTC 24 | 289879557 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.925528639 | Oct 02 07:03:56 PM UTC 24 | Oct 02 07:04:02 PM UTC 24 | 80225443 ps | ||
| T336 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.2798588654 | Oct 02 06:58:59 PM UTC 24 | Oct 02 07:04:02 PM UTC 24 | 49572628498 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.3714867270 | Oct 02 07:02:50 PM UTC 24 | Oct 02 07:04:03 PM UTC 24 | 39106327271 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.2331460959 | Oct 02 07:03:44 PM UTC 24 | Oct 02 07:04:04 PM UTC 24 | 2497094312 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.1443265470 | Oct 02 07:03:47 PM UTC 24 | Oct 02 07:04:04 PM UTC 24 | 246112176 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random.2159646093 | Oct 02 07:03:54 PM UTC 24 | Oct 02 07:04:06 PM UTC 24 | 659207136 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.1153782639 | Oct 02 07:02:29 PM UTC 24 | Oct 02 07:04:07 PM UTC 24 | 16109167158 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.3901186549 | Oct 02 07:03:20 PM UTC 24 | Oct 02 07:04:07 PM UTC 24 | 391909690 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.644006492 | Oct 02 07:04:06 PM UTC 24 | Oct 02 07:04:09 PM UTC 24 | 12020580 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1350778742 | Oct 02 07:04:08 PM UTC 24 | Oct 02 07:04:10 PM UTC 24 | 15251430 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.948191311 | Oct 02 07:03:52 PM UTC 24 | Oct 02 07:04:12 PM UTC 24 | 8754689369 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.1958513797 | Oct 02 07:04:05 PM UTC 24 | Oct 02 07:04:13 PM UTC 24 | 170390926 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.624674441 | Oct 02 07:02:53 PM UTC 24 | Oct 02 07:04:13 PM UTC 24 | 15794674396 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.1193562857 | Oct 02 07:03:32 PM UTC 24 | Oct 02 07:04:14 PM UTC 24 | 249235276 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.3032059755 | Oct 02 07:04:06 PM UTC 24 | Oct 02 07:04:15 PM UTC 24 | 88986676 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.3320323788 | Oct 02 07:04:10 PM UTC 24 | Oct 02 07:04:15 PM UTC 24 | 64025175 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.4103606996 | Oct 02 07:04:03 PM UTC 24 | Oct 02 07:04:15 PM UTC 24 | 534566815 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random.2697511324 | Oct 02 07:04:10 PM UTC 24 | Oct 02 07:04:19 PM UTC 24 | 588802300 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.1513818321 | Oct 02 07:04:16 PM UTC 24 | Oct 02 07:04:20 PM UTC 24 | 19068303 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.1731107812 | Oct 02 07:04:09 PM UTC 24 | Oct 02 07:04:20 PM UTC 24 | 984492372 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.429783355 | Oct 02 07:04:03 PM UTC 24 | Oct 02 07:04:20 PM UTC 24 | 1030999148 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.199219595 | Oct 02 07:04:16 PM UTC 24 | Oct 02 07:04:21 PM UTC 24 | 41779442 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.1557113520 | Oct 02 07:04:14 PM UTC 24 | Oct 02 07:04:22 PM UTC 24 | 56057043 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.2733828653 | Oct 02 07:04:16 PM UTC 24 | Oct 02 07:04:23 PM UTC 24 | 189067696 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1492371315 | Oct 02 07:03:21 PM UTC 24 | Oct 02 07:04:23 PM UTC 24 | 4231082059 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.3773576692 | Oct 02 07:03:48 PM UTC 24 | Oct 02 07:04:24 PM UTC 24 | 3874415246 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.3622606336 | Oct 02 07:04:06 PM UTC 24 | Oct 02 07:04:24 PM UTC 24 | 3236857794 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1417928630 | Oct 02 07:04:08 PM UTC 24 | Oct 02 07:04:24 PM UTC 24 | 6587305980 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.179990818 | Oct 02 07:04:23 PM UTC 24 | Oct 02 07:04:26 PM UTC 24 | 9736639 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.286578510 | Oct 02 07:04:23 PM UTC 24 | Oct 02 07:04:26 PM UTC 24 | 17956106 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.4062838347 | Oct 02 07:04:17 PM UTC 24 | Oct 02 07:04:29 PM UTC 24 | 539625603 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.4073713948 | Oct 02 07:03:34 PM UTC 24 | Oct 02 07:04:29 PM UTC 24 | 522969689 ps | ||
| T319 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.323571625 | Oct 02 06:57:35 PM UTC 24 | Oct 02 07:04:29 PM UTC 24 | 111229191968 ps | ||
| T832 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.3313138175 | Oct 02 07:04:06 PM UTC 24 | Oct 02 07:04:30 PM UTC 24 | 205702540 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.3000776781 | Oct 02 07:02:45 PM UTC 24 | Oct 02 07:04:31 PM UTC 24 | 650120186 ps | ||
| T833 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random.2829503001 | Oct 02 07:04:25 PM UTC 24 | Oct 02 07:04:31 PM UTC 24 | 125745195 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.806980441 | Oct 02 07:01:41 PM UTC 24 | Oct 02 07:04:32 PM UTC 24 | 39857123142 ps | ||
| T834 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.1534152062 | Oct 02 07:04:27 PM UTC 24 | Oct 02 07:04:32 PM UTC 24 | 23137316 ps | ||
| T835 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.2647706718 | Oct 02 07:04:25 PM UTC 24 | Oct 02 07:04:32 PM UTC 24 | 1041105618 ps | ||
| T836 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.2947099653 | Oct 02 07:03:24 PM UTC 24 | Oct 02 07:04:33 PM UTC 24 | 1228718093 ps | ||
| T837 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.279851876 | Oct 02 07:04:30 PM UTC 24 | Oct 02 07:04:34 PM UTC 24 | 28180340 ps | ||
| T838 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.1499668262 | Oct 02 07:04:25 PM UTC 24 | Oct 02 07:04:35 PM UTC 24 | 174623885 ps | ||
| T839 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.863563644 | Oct 02 07:04:32 PM UTC 24 | Oct 02 07:04:35 PM UTC 24 | 14892090 ps | ||
| T840 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.3741331955 | Oct 02 07:02:04 PM UTC 24 | Oct 02 07:04:35 PM UTC 24 | 783049950 ps | ||
| T841 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.3316332069 | Oct 02 07:02:56 PM UTC 24 | Oct 02 07:04:36 PM UTC 24 | 756374841 ps | ||
| T842 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.2365094969 | Oct 02 07:04:19 PM UTC 24 | Oct 02 07:04:36 PM UTC 24 | 1030995696 ps | ||
| T843 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.1392624315 | Oct 02 07:04:06 PM UTC 24 | Oct 02 07:04:37 PM UTC 24 | 1614418725 ps | ||
| T844 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.2581964797 | Oct 02 07:04:35 PM UTC 24 | Oct 02 07:04:37 PM UTC 24 | 17726005 ps | ||
| T845 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.4217334226 | Oct 02 07:02:29 PM UTC 24 | Oct 02 07:04:37 PM UTC 24 | 3759040813 ps | ||
| T846 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.1693599583 | Oct 02 07:04:35 PM UTC 24 | Oct 02 07:04:38 PM UTC 24 | 448403947 ps | ||
| T326 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.3046911941 | Oct 02 06:57:05 PM UTC 24 | Oct 02 07:04:40 PM UTC 24 | 76725762818 ps | ||
| T847 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.1477806347 | Oct 02 07:04:32 PM UTC 24 | Oct 02 07:04:41 PM UTC 24 | 603224924 ps | ||
| T848 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.3492456531 | Oct 02 07:03:08 PM UTC 24 | Oct 02 07:04:43 PM UTC 24 | 4402341782 ps | ||
| T849 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random.2732639064 | Oct 02 07:04:37 PM UTC 24 | Oct 02 07:04:43 PM UTC 24 | 58028915 ps | ||
| T850 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.4029694518 | Oct 02 07:04:32 PM UTC 24 | Oct 02 07:04:44 PM UTC 24 | 1504659706 ps | ||
| T851 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.668207031 | Oct 02 07:04:25 PM UTC 24 | Oct 02 07:04:45 PM UTC 24 | 3496407761 ps | ||
| T852 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.662451597 | Oct 02 07:04:34 PM UTC 24 | Oct 02 07:04:45 PM UTC 24 | 4668564717 ps | ||
| T853 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.1444501916 | Oct 02 07:04:37 PM UTC 24 | Oct 02 07:04:47 PM UTC 24 | 77824094 ps | ||
| T854 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.4011639378 | Oct 02 07:04:41 PM UTC 24 | Oct 02 07:04:47 PM UTC 24 | 1595996680 ps | ||
| T855 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.3455218236 | Oct 02 07:02:56 PM UTC 24 | Oct 02 07:04:47 PM UTC 24 | 8396296491 ps | ||
| T856 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2562215734 | Oct 02 07:02:14 PM UTC 24 | Oct 02 07:04:49 PM UTC 24 | 1523435834 ps | ||
| T857 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.352141390 | Oct 02 07:04:32 PM UTC 24 | Oct 02 07:04:49 PM UTC 24 | 427843243 ps | ||
| T858 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.308940768 | Oct 02 07:04:39 PM UTC 24 | Oct 02 07:04:50 PM UTC 24 | 577432482 ps | ||
| T859 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.2979200293 | Oct 02 07:04:39 PM UTC 24 | Oct 02 07:04:50 PM UTC 24 | 69918057 ps | ||
| T860 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.3093484633 | Oct 02 07:02:10 PM UTC 24 | Oct 02 07:04:50 PM UTC 24 | 40794502415 ps | ||
| T861 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.947434647 | Oct 02 07:01:50 PM UTC 24 | Oct 02 07:04:51 PM UTC 24 | 30038736368 ps | ||
| T862 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3806622 | Oct 02 07:04:37 PM UTC 24 | Oct 02 07:04:51 PM UTC 24 | 2487387624 ps | ||
| T863 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.3531439582 | Oct 02 07:04:37 PM UTC 24 | Oct 02 07:04:51 PM UTC 24 | 1654102476 ps | ||
| T864 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.2076210476 | Oct 02 07:04:44 PM UTC 24 | Oct 02 07:04:51 PM UTC 24 | 224579692 ps | ||
| T865 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.3099599561 | Oct 02 07:04:44 PM UTC 24 | Oct 02 07:04:52 PM UTC 24 | 525287515 ps | ||
| T866 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.4168874143 | Oct 02 07:02:42 PM UTC 24 | Oct 02 07:04:56 PM UTC 24 | 1643514615 ps | ||
| T867 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.3046522821 | Oct 02 07:04:48 PM UTC 24 | Oct 02 07:04:57 PM UTC 24 | 16016662 ps | ||
| T868 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.759499934 | Oct 02 07:03:02 PM UTC 24 | Oct 02 07:04:58 PM UTC 24 | 23801836320 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.2551638092 | Oct 02 07:04:14 PM UTC 24 | Oct 02 07:04:58 PM UTC 24 | 5883485353 ps | ||
| T869 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.45155089 | Oct 02 07:04:23 PM UTC 24 | Oct 02 07:04:59 PM UTC 24 | 315140640 ps | ||
| T870 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.839155720 | Oct 02 07:03:50 PM UTC 24 | Oct 02 07:05:04 PM UTC 24 | 1760218893 ps | ||
| T347 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.1923767925 | Oct 02 07:00:53 PM UTC 24 | Oct 02 07:05:14 PM UTC 24 | 96412522123 ps | ||
| T871 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1653181034 | Oct 02 07:02:21 PM UTC 24 | Oct 02 07:05:15 PM UTC 24 | 15274994829 ps | ||
| T872 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.4175065471 | Oct 02 07:03:40 PM UTC 24 | Oct 02 07:05:17 PM UTC 24 | 143295761480 ps | ||
| T873 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.655056022 | Oct 02 07:03:34 PM UTC 24 | Oct 02 07:05:22 PM UTC 24 | 1958513556 ps | ||
| T331 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.2313638585 | Oct 02 07:01:05 PM UTC 24 | Oct 02 07:05:23 PM UTC 24 | 33873367468 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.3581557649 | Oct 02 07:03:02 PM UTC 24 | Oct 02 07:05:26 PM UTC 24 | 58883025828 ps | ||
| T874 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.2356024514 | Oct 02 07:02:36 PM UTC 24 | Oct 02 07:05:27 PM UTC 24 | 22087333695 ps | ||
| T875 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.4048230991 | Oct 02 07:04:48 PM UTC 24 | Oct 02 07:05:31 PM UTC 24 | 597674715 ps | ||
| T876 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.190161191 | Oct 02 07:04:21 PM UTC 24 | Oct 02 07:05:35 PM UTC 24 | 25251746908 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.2432431656 | Oct 02 07:02:50 PM UTC 24 | Oct 02 07:05:36 PM UTC 24 | 25261950338 ps | ||
| T877 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.1652937559 | Oct 02 07:03:44 PM UTC 24 | Oct 02 07:05:40 PM UTC 24 | 14282872313 ps | ||
| T878 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.2682117132 | Oct 02 07:01:52 PM UTC 24 | Oct 02 07:05:40 PM UTC 24 | 55144493339 ps | ||
| T879 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.3108742638 | Oct 02 07:04:48 PM UTC 24 | Oct 02 07:05:42 PM UTC 24 | 658088111 ps | ||
| T880 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.985190888 | Oct 02 07:03:47 PM UTC 24 | Oct 02 07:05:42 PM UTC 24 | 1316601349 ps | ||
| T881 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1344198835 | Oct 02 07:04:35 PM UTC 24 | Oct 02 07:05:42 PM UTC 24 | 501543808 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.297894272 | Oct 02 07:01:32 PM UTC 24 | Oct 02 07:05:42 PM UTC 24 | 31694894728 ps | ||
| T882 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.1033444280 | Oct 02 07:03:54 PM UTC 24 | Oct 02 07:05:44 PM UTC 24 | 17685542380 ps | ||
| T883 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.1090070391 | Oct 02 07:04:11 PM UTC 24 | Oct 02 07:05:48 PM UTC 24 | 22640653144 ps | ||
| T884 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.2080389685 | Oct 02 07:03:15 PM UTC 24 | Oct 02 07:05:52 PM UTC 24 | 30614720824 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.1547736529 | Oct 02 07:04:21 PM UTC 24 | Oct 02 07:06:04 PM UTC 24 | 3979106971 ps | ||
| T885 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.727551349 | Oct 02 07:03:28 PM UTC 24 | Oct 02 07:06:09 PM UTC 24 | 60779995325 ps | ||
| T886 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.2886508132 | Oct 02 07:03:56 PM UTC 24 | Oct 02 07:06:14 PM UTC 24 | 23659218780 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.3873492839 | Oct 02 07:03:44 PM UTC 24 | Oct 02 07:06:14 PM UTC 24 | 25225705651 ps | ||
| T887 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.1185706539 | Oct 02 07:04:48 PM UTC 24 | Oct 02 07:06:15 PM UTC 24 | 2437766140 ps | ||
| T888 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.1593996070 | Oct 02 07:04:25 PM UTC 24 | Oct 02 07:06:15 PM UTC 24 | 112363247586 ps | ||
| T889 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.3906201122 | Oct 02 07:03:02 PM UTC 24 | Oct 02 07:06:17 PM UTC 24 | 36612922055 ps | ||
| T339 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1943633595 | Oct 02 07:00:28 PM UTC 24 | Oct 02 07:06:22 PM UTC 24 | 38954202573 ps | ||
| T890 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3523589952 | Oct 02 07:03:18 PM UTC 24 | Oct 02 07:06:22 PM UTC 24 | 40017106913 ps | ||
| T891 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2680105031 | Oct 02 07:01:19 PM UTC 24 | Oct 02 07:06:25 PM UTC 24 | 112962079981 ps | ||
| T892 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.1402209714 | Oct 02 07:03:15 PM UTC 24 | Oct 02 07:06:28 PM UTC 24 | 26821541197 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.737412925 | Oct 02 07:03:30 PM UTC 24 | Oct 02 07:06:30 PM UTC 24 | 22316577422 ps | ||
| T893 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1056007988 | Oct 02 07:03:28 PM UTC 24 | Oct 02 07:06:31 PM UTC 24 | 44150441822 ps | ||
| T894 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.2220475029 | Oct 02 07:04:37 PM UTC 24 | Oct 02 07:06:32 PM UTC 24 | 31881280794 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.1183430008 | Oct 02 07:03:54 PM UTC 24 | Oct 02 07:06:33 PM UTC 24 | 38951666257 ps | ||
| T895 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3208763360 | Oct 02 07:04:34 PM UTC 24 | Oct 02 07:06:38 PM UTC 24 | 1326855969 ps | ||
| T343 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3924215669 | Oct 02 07:02:00 PM UTC 24 | Oct 02 07:06:52 PM UTC 24 | 190981754731 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.2740672042 | Oct 02 07:04:39 PM UTC 24 | Oct 02 07:07:11 PM UTC 24 | 25206189424 ps | ||
| T896 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.1403053172 | Oct 02 07:04:27 PM UTC 24 | Oct 02 07:07:32 PM UTC 24 | 33164748411 ps | ||
| T897 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.3490658382 | Oct 02 07:01:41 PM UTC 24 | Oct 02 07:07:47 PM UTC 24 | 48603707893 ps | ||
| T898 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.898444084 | Oct 02 07:04:39 PM UTC 24 | Oct 02 07:08:08 PM UTC 24 | 27558109700 ps | ||
| T899 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.720216884 | Oct 02 07:02:12 PM UTC 24 | Oct 02 07:09:08 PM UTC 24 | 102192583087 ps | ||
| T344 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.597997037 | Oct 02 07:04:16 PM UTC 24 | Oct 02 07:11:13 PM UTC 24 | 119843524106 ps | ||
| T900 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2432308311 | Oct 02 07:04:30 PM UTC 24 | Oct 02 07:11:21 PM UTC 24 | 67038938220 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_error_random.326597378 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 430607114 ps |
| CPU time | 2.99 seconds |
| Started | Oct 02 06:53:08 PM UTC 24 |
| Finished | Oct 02 06:53:12 PM UTC 24 |
| Peak memory | 211980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326597378 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.326597378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/0.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.3278534609 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 94552761243 ps |
| CPU time | 351.53 seconds |
| Started | Oct 02 06:56:26 PM UTC 24 |
| Finished | Oct 02 07:02:23 PM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278534609 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.3278534609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.4142772528 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 68746527040 ps |
| CPU time | 308.04 seconds |
| Started | Oct 02 06:53:27 PM UTC 24 |
| Finished | Oct 02 06:58:39 PM UTC 24 |
| Peak memory | 214108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142772528 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.4142772528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.477416162 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 3818811039 ps |
| CPU time | 20.26 seconds |
| Started | Oct 02 06:52:58 PM UTC 24 |
| Finished | Oct 02 06:53:19 PM UTC 24 |
| Peak memory | 212064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477416162 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.477416162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.3421528590 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 39884008287 ps |
| CPU time | 351.61 seconds |
| Started | Oct 02 06:53:42 PM UTC 24 |
| Finished | Oct 02 06:59:39 PM UTC 24 |
| Peak memory | 214376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421528590 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.3421528590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.4121435410 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 113616503 ps |
| CPU time | 13.87 seconds |
| Started | Oct 02 06:53:12 PM UTC 24 |
| Finished | Oct 02 06:53:27 PM UTC 24 |
| Peak memory | 214060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121435410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.4121435410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.1923767925 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 96412522123 ps |
| CPU time | 257.25 seconds |
| Started | Oct 02 07:00:53 PM UTC 24 |
| Finished | Oct 02 07:05:14 PM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923767925 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.1923767925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.1511128428 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 1108935880 ps |
| CPU time | 93.78 seconds |
| Started | Oct 02 06:53:49 PM UTC 24 |
| Finished | Oct 02 06:55:25 PM UTC 24 |
| Peak memory | 216104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511128428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.1511128428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random.3675004823 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 801173941 ps |
| CPU time | 12.96 seconds |
| Started | Oct 02 06:53:17 PM UTC 24 |
| Finished | Oct 02 06:53:31 PM UTC 24 |
| Peak memory | 211980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675004823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.3675004823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/1.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device.3981695762 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1968835122 ps |
| CPU time | 30.79 seconds |
| Started | Oct 02 06:55:00 PM UTC 24 |
| Finished | Oct 02 06:55:32 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981695762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.3981695762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/6.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.3038171804 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 50802941620 ps |
| CPU time | 372.54 seconds |
| Started | Oct 02 06:54:39 PM UTC 24 |
| Finished | Oct 02 07:00:57 PM UTC 24 |
| Peak memory | 216360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038171804 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.3038171804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.297894272 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 31694894728 ps |
| CPU time | 246.68 seconds |
| Started | Oct 02 07:01:32 PM UTC 24 |
| Finished | Oct 02 07:05:42 PM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297894272 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.297894272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.1089472812 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 5269120519 ps |
| CPU time | 50.26 seconds |
| Started | Oct 02 06:54:27 PM UTC 24 |
| Finished | Oct 02 06:55:19 PM UTC 24 |
| Peak memory | 214124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089472812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.1089472812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_large_delays.594723034 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 39967657180 ps |
| CPU time | 92.81 seconds |
| Started | Oct 02 06:53:20 PM UTC 24 |
| Finished | Oct 02 06:54:55 PM UTC 24 |
| Peak memory | 212264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594723034 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.594723034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/1.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_zero_delays.607854474 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 59163362 ps |
| CPU time | 7.86 seconds |
| Started | Oct 02 06:52:58 PM UTC 24 |
| Finished | Oct 02 06:53:07 PM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607854474 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.607854474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/0.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.3000776781 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 650120186 ps |
| CPU time | 103.94 seconds |
| Started | Oct 02 07:02:45 PM UTC 24 |
| Finished | Oct 02 07:04:31 PM UTC 24 |
| Peak memory | 216104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000776781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.3000776781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.3822995452 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 522613474 ps |
| CPU time | 50.09 seconds |
| Started | Oct 02 06:59:04 PM UTC 24 |
| Finished | Oct 02 06:59:55 PM UTC 24 |
| Peak memory | 214228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822995452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.3822995452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.2865885196 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 2929421037 ps |
| CPU time | 167.08 seconds |
| Started | Oct 02 06:56:19 PM UTC 24 |
| Finished | Oct 02 06:59:09 PM UTC 24 |
| Peak memory | 216172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865885196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.2865885196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.597997037 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 119843524106 ps |
| CPU time | 412.16 seconds |
| Started | Oct 02 07:04:16 PM UTC 24 |
| Finished | Oct 02 07:11:13 PM UTC 24 |
| Peak memory | 220048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597997037 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.597997037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.4085025478 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 313433925 ps |
| CPU time | 53.65 seconds |
| Started | Oct 02 06:55:48 PM UTC 24 |
| Finished | Oct 02 06:56:43 PM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085025478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.4085025478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all.3584815769 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 3020055900 ps |
| CPU time | 47.22 seconds |
| Started | Oct 02 06:54:09 PM UTC 24 |
| Finished | Oct 02 06:54:58 PM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584815769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.3584815769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/3.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.2407803261 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 71823530415 ps |
| CPU time | 254.21 seconds |
| Started | Oct 02 06:58:49 PM UTC 24 |
| Finished | Oct 02 07:03:07 PM UTC 24 |
| Peak memory | 214308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407803261 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.2407803261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all.509163735 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 9906552804 ps |
| CPU time | 125.78 seconds |
| Started | Oct 02 06:53:29 PM UTC 24 |
| Finished | Oct 02 06:55:37 PM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509163735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.509163735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/1.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.1427195795 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 47038089860 ps |
| CPU time | 298.82 seconds |
| Started | Oct 02 06:57:50 PM UTC 24 |
| Finished | Oct 02 07:02:52 PM UTC 24 |
| Peak memory | 214188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427195795 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.1427195795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device.2409098517 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1423891155 ps |
| CPU time | 14.37 seconds |
| Started | Oct 02 06:54:04 PM UTC 24 |
| Finished | Oct 02 06:54:20 PM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409098517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.2409098517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/3.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.878129269 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 639303869 ps |
| CPU time | 100.48 seconds |
| Started | Oct 02 06:59:41 PM UTC 24 |
| Finished | Oct 02 07:01:23 PM UTC 24 |
| Peak memory | 216100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878129269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.878129269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.1218949691 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 802542135 ps |
| CPU time | 132.47 seconds |
| Started | Oct 02 06:56:34 PM UTC 24 |
| Finished | Oct 02 06:58:49 PM UTC 24 |
| Peak memory | 216172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218949691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.1218949691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.2265636226 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1609853149 ps |
| CPU time | 113.78 seconds |
| Started | Oct 02 07:01:35 PM UTC 24 |
| Finished | Oct 02 07:03:31 PM UTC 24 |
| Peak memory | 216104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265636226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.2265636226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_slow_rsp.474299804 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 13295496970 ps |
| CPU time | 82.84 seconds |
| Started | Oct 02 06:53:21 PM UTC 24 |
| Finished | Oct 02 06:54:47 PM UTC 24 |
| Peak memory | 212048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474299804 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.474299804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/1.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_large_delays.2405446548 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 26631377879 ps |
| CPU time | 116.88 seconds |
| Started | Oct 02 06:59:48 PM UTC 24 |
| Finished | Oct 02 07:01:47 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405446548 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.2405446548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/26.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device.1910955760 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4814088698 ps |
| CPU time | 21.26 seconds |
| Started | Oct 02 06:53:01 PM UTC 24 |
| Finished | Oct 02 06:53:24 PM UTC 24 |
| Peak memory | 212208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910955760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.1910955760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/0.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.1366685885 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 25815799791 ps |
| CPU time | 156.26 seconds |
| Started | Oct 02 06:53:04 PM UTC 24 |
| Finished | Oct 02 06:55:43 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366685885 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.1366685885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.602959750 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 41140201 ps |
| CPU time | 3.07 seconds |
| Started | Oct 02 06:53:09 PM UTC 24 |
| Finished | Oct 02 06:53:13 PM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602959750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.602959750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random.3774686094 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 1509931831 ps |
| CPU time | 21.15 seconds |
| Started | Oct 02 06:52:58 PM UTC 24 |
| Finished | Oct 02 06:53:20 PM UTC 24 |
| Peak memory | 211980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774686094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3774686094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/0.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_large_delays.1202575700 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 71507978154 ps |
| CPU time | 176.9 seconds |
| Started | Oct 02 06:53:00 PM UTC 24 |
| Finished | Oct 02 06:55:59 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202575700 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1202575700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/0.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_slow_rsp.363382016 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 7741565040 ps |
| CPU time | 61.39 seconds |
| Started | Oct 02 06:53:00 PM UTC 24 |
| Finished | Oct 02 06:54:03 PM UTC 24 |
| Peak memory | 212244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363382016 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.363382016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/0.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_same_source.3834433135 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 45216436 ps |
| CPU time | 1.81 seconds |
| Started | Oct 02 06:53:04 PM UTC 24 |
| Finished | Oct 02 06:53:07 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834433135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.3834433135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/0.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke.2517529838 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 53994674 ps |
| CPU time | 2.59 seconds |
| Started | Oct 02 06:52:50 PM UTC 24 |
| Finished | Oct 02 06:52:53 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517529838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2517529838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/0.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_large_delays.1846257031 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5576399939 ps |
| CPU time | 14.58 seconds |
| Started | Oct 02 06:52:54 PM UTC 24 |
| Finished | Oct 02 06:53:10 PM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846257031 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.1846257031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/0.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.3971630720 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11491151 ps |
| CPU time | 2.09 seconds |
| Started | Oct 02 06:52:53 PM UTC 24 |
| Finished | Oct 02 06:52:56 PM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971630720 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.3971630720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/0.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all.3702046363 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 502297826 ps |
| CPU time | 35.35 seconds |
| Started | Oct 02 06:53:09 PM UTC 24 |
| Finished | Oct 02 06:53:46 PM UTC 24 |
| Peak memory | 214252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702046363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3702046363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/0.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_error.3103014545 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 90350262 ps |
| CPU time | 10.85 seconds |
| Started | Oct 02 06:53:11 PM UTC 24 |
| Finished | Oct 02 06:53:23 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103014545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3103014545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/0.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.3711380555 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 3726603950 ps |
| CPU time | 217.06 seconds |
| Started | Oct 02 06:53:10 PM UTC 24 |
| Finished | Oct 02 06:56:50 PM UTC 24 |
| Peak memory | 216172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711380555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.3711380555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_unmapped_addr.4251245149 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 49452781 ps |
| CPU time | 2.15 seconds |
| Started | Oct 02 06:53:08 PM UTC 24 |
| Finished | Oct 02 06:53:11 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251245149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.4251245149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/0.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device.2072450768 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 113109619 ps |
| CPU time | 7.31 seconds |
| Started | Oct 02 06:53:24 PM UTC 24 |
| Finished | Oct 02 06:53:33 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072450768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.2072450768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/1.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.3203419599 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 100676784 ps |
| CPU time | 5.34 seconds |
| Started | Oct 02 06:53:27 PM UTC 24 |
| Finished | Oct 02 06:53:34 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203419599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.3203419599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_error_random.3326624573 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 61587399 ps |
| CPU time | 9.91 seconds |
| Started | Oct 02 06:53:27 PM UTC 24 |
| Finished | Oct 02 06:53:38 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326624573 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.3326624573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/1.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_zero_delays.676892002 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 26264854 ps |
| CPU time | 2.84 seconds |
| Started | Oct 02 06:53:20 PM UTC 24 |
| Finished | Oct 02 06:53:24 PM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676892002 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.676892002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/1.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_same_source.696390796 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3956266972 ps |
| CPU time | 12.12 seconds |
| Started | Oct 02 06:53:27 PM UTC 24 |
| Finished | Oct 02 06:53:40 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696390796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.696390796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/1.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke.4110472865 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 70280096 ps |
| CPU time | 1.57 seconds |
| Started | Oct 02 06:53:12 PM UTC 24 |
| Finished | Oct 02 06:53:15 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110472865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.4110472865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/1.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_large_delays.651276843 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3048016503 ps |
| CPU time | 11.42 seconds |
| Started | Oct 02 06:53:15 PM UTC 24 |
| Finished | Oct 02 06:53:27 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651276843 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.651276843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/1.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.4191190185 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1690770597 ps |
| CPU time | 21.5 seconds |
| Started | Oct 02 06:53:16 PM UTC 24 |
| Finished | Oct 02 06:53:38 PM UTC 24 |
| Peak memory | 212180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191190185 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.4191190185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1881423776 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 7806939 ps |
| CPU time | 1.42 seconds |
| Started | Oct 02 06:53:13 PM UTC 24 |
| Finished | Oct 02 06:53:16 PM UTC 24 |
| Peak memory | 210932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881423776 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.1881423776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/1.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_error.71164743 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 2245588076 ps |
| CPU time | 35.93 seconds |
| Started | Oct 02 06:53:29 PM UTC 24 |
| Finished | Oct 02 06:54:06 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71164743 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.71164743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/1.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.3394124911 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 6111271579 ps |
| CPU time | 145.1 seconds |
| Started | Oct 02 06:53:29 PM UTC 24 |
| Finished | Oct 02 06:55:57 PM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394124911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.3394124911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.1235113914 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 197177232 ps |
| CPU time | 10.26 seconds |
| Started | Oct 02 06:53:31 PM UTC 24 |
| Finished | Oct 02 06:53:42 PM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235113914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.1235113914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_unmapped_addr.1721733864 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 225611603 ps |
| CPU time | 5.5 seconds |
| Started | Oct 02 06:53:27 PM UTC 24 |
| Finished | Oct 02 06:53:34 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721733864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1721733864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/1.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device.3221989320 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 89438018 ps |
| CPU time | 4.45 seconds |
| Started | Oct 02 06:56:12 PM UTC 24 |
| Finished | Oct 02 06:56:17 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221989320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.3221989320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/10.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.283291055 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 21553357972 ps |
| CPU time | 146.73 seconds |
| Started | Oct 02 06:56:14 PM UTC 24 |
| Finished | Oct 02 06:58:43 PM UTC 24 |
| Peak memory | 214312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283291055 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.283291055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.1059463945 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 628498656 ps |
| CPU time | 10.46 seconds |
| Started | Oct 02 06:56:17 PM UTC 24 |
| Finished | Oct 02 06:56:29 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059463945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.1059463945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_error_random.1934306011 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 376338622 ps |
| CPU time | 9.09 seconds |
| Started | Oct 02 06:56:15 PM UTC 24 |
| Finished | Oct 02 06:56:25 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934306011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.1934306011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/10.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random.1450800719 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 61547313 ps |
| CPU time | 10.95 seconds |
| Started | Oct 02 06:56:09 PM UTC 24 |
| Finished | Oct 02 06:56:22 PM UTC 24 |
| Peak memory | 211980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450800719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.1450800719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/10.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_large_delays.814264823 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 5721025243 ps |
| CPU time | 31.13 seconds |
| Started | Oct 02 06:56:11 PM UTC 24 |
| Finished | Oct 02 06:56:43 PM UTC 24 |
| Peak memory | 212076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814264823 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.814264823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/10.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_slow_rsp.2910164775 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 16870901238 ps |
| CPU time | 163.8 seconds |
| Started | Oct 02 06:56:12 PM UTC 24 |
| Finished | Oct 02 06:58:59 PM UTC 24 |
| Peak memory | 212060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910164775 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.2910164775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/10.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_zero_delays.3649984651 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 78643068 ps |
| CPU time | 7.66 seconds |
| Started | Oct 02 06:56:11 PM UTC 24 |
| Finished | Oct 02 06:56:19 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649984651 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3649984651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/10.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_same_source.2067179283 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 212153047 ps |
| CPU time | 2.66 seconds |
| Started | Oct 02 06:56:15 PM UTC 24 |
| Finished | Oct 02 06:56:18 PM UTC 24 |
| Peak memory | 211996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067179283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2067179283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/10.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke.2121954516 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 227170341 ps |
| CPU time | 2.04 seconds |
| Started | Oct 02 06:56:07 PM UTC 24 |
| Finished | Oct 02 06:56:10 PM UTC 24 |
| Peak memory | 212180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121954516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2121954516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/10.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3473627889 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 2281338428 ps |
| CPU time | 12.1 seconds |
| Started | Oct 02 06:56:08 PM UTC 24 |
| Finished | Oct 02 06:56:21 PM UTC 24 |
| Peak memory | 212264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473627889 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3473627889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/10.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3065483594 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 1658134169 ps |
| CPU time | 5.28 seconds |
| Started | Oct 02 06:56:08 PM UTC 24 |
| Finished | Oct 02 06:56:15 PM UTC 24 |
| Peak memory | 212184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065483594 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3065483594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.2380695679 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 9397966 ps |
| CPU time | 1.49 seconds |
| Started | Oct 02 06:56:08 PM UTC 24 |
| Finished | Oct 02 06:56:11 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380695679 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.2380695679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/10.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all.2665888086 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 8746912164 ps |
| CPU time | 102.29 seconds |
| Started | Oct 02 06:56:19 PM UTC 24 |
| Finished | Oct 02 06:58:03 PM UTC 24 |
| Peak memory | 214124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665888086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.2665888086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/10.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_error.1760647560 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 186837949 ps |
| CPU time | 17.33 seconds |
| Started | Oct 02 06:56:20 PM UTC 24 |
| Finished | Oct 02 06:56:39 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760647560 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.1760647560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/10.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.1626497940 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 9855074497 ps |
| CPU time | 134.87 seconds |
| Started | Oct 02 06:56:20 PM UTC 24 |
| Finished | Oct 02 06:58:38 PM UTC 24 |
| Peak memory | 216348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626497940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.1626497940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_unmapped_addr.2739724300 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 427367268 ps |
| CPU time | 8.32 seconds |
| Started | Oct 02 06:56:16 PM UTC 24 |
| Finished | Oct 02 06:56:25 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739724300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.2739724300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/10.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device.3378161658 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 2227584963 ps |
| CPU time | 17.48 seconds |
| Started | Oct 02 06:56:26 PM UTC 24 |
| Finished | Oct 02 06:56:46 PM UTC 24 |
| Peak memory | 212204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378161658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.3378161658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/11.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.312754260 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 209595365 ps |
| CPU time | 4.39 seconds |
| Started | Oct 02 06:56:33 PM UTC 24 |
| Finished | Oct 02 06:56:39 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312754260 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.312754260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_error_random.9707176 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 490553566 ps |
| CPU time | 12.39 seconds |
| Started | Oct 02 06:56:30 PM UTC 24 |
| Finished | Oct 02 06:56:44 PM UTC 24 |
| Peak memory | 212244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9707176 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.9707176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/11.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random.2033529194 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 6807296288 ps |
| CPU time | 17.87 seconds |
| Started | Oct 02 06:56:24 PM UTC 24 |
| Finished | Oct 02 06:56:43 PM UTC 24 |
| Peak memory | 212044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033529194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.2033529194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/11.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_large_delays.2480427643 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 51428843704 ps |
| CPU time | 160.5 seconds |
| Started | Oct 02 06:56:26 PM UTC 24 |
| Finished | Oct 02 06:59:10 PM UTC 24 |
| Peak memory | 212268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480427643 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.2480427643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/11.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_slow_rsp.303328160 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 16891109817 ps |
| CPU time | 143.85 seconds |
| Started | Oct 02 06:56:26 PM UTC 24 |
| Finished | Oct 02 06:58:53 PM UTC 24 |
| Peak memory | 212048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303328160 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.303328160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/11.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_zero_delays.2302275699 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 70417310 ps |
| CPU time | 7.98 seconds |
| Started | Oct 02 06:56:24 PM UTC 24 |
| Finished | Oct 02 06:56:33 PM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302275699 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.2302275699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/11.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_same_source.707953419 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 8842760 ps |
| CPU time | 1.73 seconds |
| Started | Oct 02 06:56:30 PM UTC 24 |
| Finished | Oct 02 06:56:33 PM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707953419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.707953419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/11.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke.1415709226 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 12001979 ps |
| CPU time | 1.54 seconds |
| Started | Oct 02 06:56:20 PM UTC 24 |
| Finished | Oct 02 06:56:23 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415709226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.1415709226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/11.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_large_delays.3779031788 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 4457290529 ps |
| CPU time | 16.75 seconds |
| Started | Oct 02 06:56:22 PM UTC 24 |
| Finished | Oct 02 06:56:40 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779031788 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.3779031788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/11.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.935503435 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1005982981 ps |
| CPU time | 11.29 seconds |
| Started | Oct 02 06:56:24 PM UTC 24 |
| Finished | Oct 02 06:56:36 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935503435 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.935503435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.1454235886 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 13475886 ps |
| CPU time | 1.7 seconds |
| Started | Oct 02 06:56:22 PM UTC 24 |
| Finished | Oct 02 06:56:25 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454235886 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.1454235886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/11.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all.1125867953 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 187681981 ps |
| CPU time | 7.95 seconds |
| Started | Oct 02 06:56:34 PM UTC 24 |
| Finished | Oct 02 06:56:44 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125867953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1125867953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/11.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_error.3943097700 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 257424555 ps |
| CPU time | 27.06 seconds |
| Started | Oct 02 06:56:34 PM UTC 24 |
| Finished | Oct 02 06:57:03 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943097700 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.3943097700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/11.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.1672611948 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 201405693 ps |
| CPU time | 24.79 seconds |
| Started | Oct 02 06:56:36 PM UTC 24 |
| Finished | Oct 02 06:57:02 PM UTC 24 |
| Peak memory | 214056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672611948 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.1672611948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_unmapped_addr.1452783489 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 10964129 ps |
| CPU time | 1.77 seconds |
| Started | Oct 02 06:56:30 PM UTC 24 |
| Finished | Oct 02 06:56:33 PM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452783489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1452783489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/11.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device.3861636776 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 364208146 ps |
| CPU time | 11.51 seconds |
| Started | Oct 02 06:56:44 PM UTC 24 |
| Finished | Oct 02 06:56:57 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861636776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.3861636776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/12.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.1505226062 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 10947052098 ps |
| CPU time | 73.89 seconds |
| Started | Oct 02 06:56:44 PM UTC 24 |
| Finished | Oct 02 06:58:00 PM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505226062 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.1505226062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.3863781015 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 102298355 ps |
| CPU time | 3.44 seconds |
| Started | Oct 02 06:56:46 PM UTC 24 |
| Finished | Oct 02 06:56:50 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863781015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.3863781015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_error_random.1188985331 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 232488308 ps |
| CPU time | 6.9 seconds |
| Started | Oct 02 06:56:45 PM UTC 24 |
| Finished | Oct 02 06:56:53 PM UTC 24 |
| Peak memory | 212184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188985331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1188985331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/12.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random.3251575016 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 184402813 ps |
| CPU time | 2.17 seconds |
| Started | Oct 02 06:56:41 PM UTC 24 |
| Finished | Oct 02 06:56:44 PM UTC 24 |
| Peak memory | 212048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251575016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.3251575016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/12.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_large_delays.983097528 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 96401573205 ps |
| CPU time | 197.5 seconds |
| Started | Oct 02 06:56:42 PM UTC 24 |
| Finished | Oct 02 07:00:03 PM UTC 24 |
| Peak memory | 212264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983097528 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.983097528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/12.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_slow_rsp.1556646653 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 42790091064 ps |
| CPU time | 95.32 seconds |
| Started | Oct 02 06:56:42 PM UTC 24 |
| Finished | Oct 02 06:58:20 PM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556646653 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.1556646653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/12.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_zero_delays.29862129 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 35271503 ps |
| CPU time | 4.39 seconds |
| Started | Oct 02 06:56:42 PM UTC 24 |
| Finished | Oct 02 06:56:47 PM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29862129 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.29862129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/12.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_same_source.1441015807 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 64013132 ps |
| CPU time | 4.5 seconds |
| Started | Oct 02 06:56:44 PM UTC 24 |
| Finished | Oct 02 06:56:50 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441015807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1441015807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/12.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke.1123694774 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 38572308 ps |
| CPU time | 2.09 seconds |
| Started | Oct 02 06:56:36 PM UTC 24 |
| Finished | Oct 02 06:56:39 PM UTC 24 |
| Peak memory | 212180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123694774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.1123694774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/12.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_large_delays.4104934244 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 3133002941 ps |
| CPU time | 15.4 seconds |
| Started | Oct 02 06:56:39 PM UTC 24 |
| Finished | Oct 02 06:56:56 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104934244 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.4104934244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/12.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.1913876922 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 1203903040 ps |
| CPU time | 11.66 seconds |
| Started | Oct 02 06:56:40 PM UTC 24 |
| Finished | Oct 02 06:56:52 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913876922 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1913876922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.1763811438 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 12454680 ps |
| CPU time | 1.95 seconds |
| Started | Oct 02 06:56:37 PM UTC 24 |
| Finished | Oct 02 06:56:40 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763811438 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.1763811438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/12.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all.613669580 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 2394697711 ps |
| CPU time | 45.3 seconds |
| Started | Oct 02 06:56:47 PM UTC 24 |
| Finished | Oct 02 06:57:34 PM UTC 24 |
| Peak memory | 214312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613669580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.613669580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/12.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_error.1232553911 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1822767560 ps |
| CPU time | 9.26 seconds |
| Started | Oct 02 06:56:48 PM UTC 24 |
| Finished | Oct 02 06:56:59 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232553911 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1232553911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/12.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.1524562029 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 5883889 ps |
| CPU time | 1.15 seconds |
| Started | Oct 02 06:56:48 PM UTC 24 |
| Finished | Oct 02 06:56:50 PM UTC 24 |
| Peak memory | 202224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524562029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.1524562029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.1310137862 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 86519337 ps |
| CPU time | 5.46 seconds |
| Started | Oct 02 06:56:48 PM UTC 24 |
| Finished | Oct 02 06:56:55 PM UTC 24 |
| Peak memory | 212268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310137862 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.1310137862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_unmapped_addr.1982536757 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 233441475 ps |
| CPU time | 3.95 seconds |
| Started | Oct 02 06:56:46 PM UTC 24 |
| Finished | Oct 02 06:56:51 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982536757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1982536757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/12.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device.2249308859 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 2190459935 ps |
| CPU time | 22.16 seconds |
| Started | Oct 02 06:56:54 PM UTC 24 |
| Finished | Oct 02 06:57:17 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249308859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.2249308859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/13.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.429741775 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 22861293006 ps |
| CPU time | 112.91 seconds |
| Started | Oct 02 06:56:56 PM UTC 24 |
| Finished | Oct 02 06:58:51 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429741775 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.429741775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.3888667185 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 49632961 ps |
| CPU time | 4.72 seconds |
| Started | Oct 02 06:56:57 PM UTC 24 |
| Finished | Oct 02 06:57:03 PM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888667185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.3888667185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_error_random.2888154520 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 65792479 ps |
| CPU time | 5.28 seconds |
| Started | Oct 02 06:56:56 PM UTC 24 |
| Finished | Oct 02 06:57:02 PM UTC 24 |
| Peak memory | 212184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888154520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.2888154520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/13.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random.3886421293 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 47396085 ps |
| CPU time | 2.42 seconds |
| Started | Oct 02 06:56:52 PM UTC 24 |
| Finished | Oct 02 06:56:56 PM UTC 24 |
| Peak memory | 211976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886421293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.3886421293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/13.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_large_delays.1255783510 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 29809409152 ps |
| CPU time | 159.72 seconds |
| Started | Oct 02 06:56:54 PM UTC 24 |
| Finished | Oct 02 06:59:36 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255783510 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.1255783510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/13.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_slow_rsp.2475326049 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 20357694700 ps |
| CPU time | 91.91 seconds |
| Started | Oct 02 06:56:54 PM UTC 24 |
| Finished | Oct 02 06:58:28 PM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475326049 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2475326049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/13.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_zero_delays.1155439090 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 160398858 ps |
| CPU time | 8.22 seconds |
| Started | Oct 02 06:56:52 PM UTC 24 |
| Finished | Oct 02 06:57:02 PM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155439090 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.1155439090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/13.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_same_source.2127363737 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 70284939 ps |
| CPU time | 3.39 seconds |
| Started | Oct 02 06:56:56 PM UTC 24 |
| Finished | Oct 02 06:57:00 PM UTC 24 |
| Peak memory | 211996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127363737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2127363737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/13.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke.3336506130 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 39097382 ps |
| CPU time | 1.82 seconds |
| Started | Oct 02 06:56:52 PM UTC 24 |
| Finished | Oct 02 06:56:55 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336506130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.3336506130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/13.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_large_delays.472781492 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 6912965722 ps |
| CPU time | 9.76 seconds |
| Started | Oct 02 06:56:52 PM UTC 24 |
| Finished | Oct 02 06:57:03 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472781492 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.472781492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/13.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.231614350 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 4310625488 ps |
| CPU time | 15.62 seconds |
| Started | Oct 02 06:56:52 PM UTC 24 |
| Finished | Oct 02 06:57:09 PM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231614350 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.231614350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.3727263955 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 12076307 ps |
| CPU time | 1.64 seconds |
| Started | Oct 02 06:56:52 PM UTC 24 |
| Finished | Oct 02 06:56:55 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727263955 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.3727263955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/13.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all.207883481 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 2442320039 ps |
| CPU time | 14.37 seconds |
| Started | Oct 02 06:56:57 PM UTC 24 |
| Finished | Oct 02 06:57:13 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207883481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.207883481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/13.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_error.476408461 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 3411301264 ps |
| CPU time | 54.97 seconds |
| Started | Oct 02 06:56:59 PM UTC 24 |
| Finished | Oct 02 06:57:56 PM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476408461 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.476408461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/13.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.1375464808 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 307584969 ps |
| CPU time | 34.51 seconds |
| Started | Oct 02 06:56:59 PM UTC 24 |
| Finished | Oct 02 06:57:35 PM UTC 24 |
| Peak memory | 214256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375464808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.1375464808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.58762933 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 1226526325 ps |
| CPU time | 78.97 seconds |
| Started | Oct 02 06:57:00 PM UTC 24 |
| Finished | Oct 02 06:58:21 PM UTC 24 |
| Peak memory | 216108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58762933 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.58762933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_unmapped_addr.454480751 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 100273413 ps |
| CPU time | 2.23 seconds |
| Started | Oct 02 06:56:57 PM UTC 24 |
| Finished | Oct 02 06:57:00 PM UTC 24 |
| Peak memory | 212204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454480751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.454480751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/13.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device.3968867327 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 175655561 ps |
| CPU time | 3.72 seconds |
| Started | Oct 02 06:57:05 PM UTC 24 |
| Finished | Oct 02 06:57:09 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968867327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.3968867327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/14.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.3046911941 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 76725762818 ps |
| CPU time | 448.7 seconds |
| Started | Oct 02 06:57:05 PM UTC 24 |
| Finished | Oct 02 07:04:40 PM UTC 24 |
| Peak memory | 218068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046911941 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.3046911941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.1331923960 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 57709651 ps |
| CPU time | 1.7 seconds |
| Started | Oct 02 06:57:10 PM UTC 24 |
| Finished | Oct 02 06:57:13 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331923960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.1331923960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_error_random.606129369 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 955423376 ps |
| CPU time | 17.18 seconds |
| Started | Oct 02 06:57:05 PM UTC 24 |
| Finished | Oct 02 06:57:23 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606129369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.606129369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/14.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random.4269629523 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 780435155 ps |
| CPU time | 17.63 seconds |
| Started | Oct 02 06:57:03 PM UTC 24 |
| Finished | Oct 02 06:57:22 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269629523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.4269629523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/14.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_large_delays.966551549 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 29827207259 ps |
| CPU time | 82.92 seconds |
| Started | Oct 02 06:57:05 PM UTC 24 |
| Finished | Oct 02 06:58:30 PM UTC 24 |
| Peak memory | 212264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966551549 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.966551549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/14.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_slow_rsp.2806429694 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 16624933370 ps |
| CPU time | 78.38 seconds |
| Started | Oct 02 06:57:05 PM UTC 24 |
| Finished | Oct 02 06:58:25 PM UTC 24 |
| Peak memory | 212060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806429694 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.2806429694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/14.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_zero_delays.2076862141 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 61854404 ps |
| CPU time | 9.39 seconds |
| Started | Oct 02 06:57:03 PM UTC 24 |
| Finished | Oct 02 06:57:14 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076862141 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2076862141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/14.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_same_source.2810258146 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 338538664 ps |
| CPU time | 3.66 seconds |
| Started | Oct 02 06:57:05 PM UTC 24 |
| Finished | Oct 02 06:57:10 PM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810258146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.2810258146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/14.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke.1929905344 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 15005185 ps |
| CPU time | 1.38 seconds |
| Started | Oct 02 06:57:02 PM UTC 24 |
| Finished | Oct 02 06:57:04 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929905344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.1929905344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/14.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_large_delays.1369566225 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 4421587962 ps |
| CPU time | 12.29 seconds |
| Started | Oct 02 06:57:03 PM UTC 24 |
| Finished | Oct 02 06:57:17 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369566225 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.1369566225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/14.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2371348444 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 4335857778 ps |
| CPU time | 12.42 seconds |
| Started | Oct 02 06:57:03 PM UTC 24 |
| Finished | Oct 02 06:57:17 PM UTC 24 |
| Peak memory | 212052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371348444 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2371348444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.1953109999 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 10897339 ps |
| CPU time | 1.66 seconds |
| Started | Oct 02 06:57:02 PM UTC 24 |
| Finished | Oct 02 06:57:04 PM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953109999 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.1953109999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/14.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all.1858184756 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 3729992588 ps |
| CPU time | 59.19 seconds |
| Started | Oct 02 06:57:10 PM UTC 24 |
| Finished | Oct 02 06:58:11 PM UTC 24 |
| Peak memory | 214380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858184756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.1858184756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/14.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_error.247270307 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 1375664785 ps |
| CPU time | 21.56 seconds |
| Started | Oct 02 06:57:12 PM UTC 24 |
| Finished | Oct 02 06:57:34 PM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247270307 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.247270307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/14.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.3483160327 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 878716335 ps |
| CPU time | 71.64 seconds |
| Started | Oct 02 06:57:10 PM UTC 24 |
| Finished | Oct 02 06:58:24 PM UTC 24 |
| Peak memory | 214060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483160327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.3483160327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.3300743332 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 368558140 ps |
| CPU time | 39.47 seconds |
| Started | Oct 02 06:57:14 PM UTC 24 |
| Finished | Oct 02 06:57:55 PM UTC 24 |
| Peak memory | 214252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300743332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.3300743332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_unmapped_addr.1002978486 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 371202091 ps |
| CPU time | 8.7 seconds |
| Started | Oct 02 06:57:06 PM UTC 24 |
| Finished | Oct 02 06:57:16 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002978486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1002978486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/14.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device.253336713 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 339067965 ps |
| CPU time | 11.73 seconds |
| Started | Oct 02 06:57:18 PM UTC 24 |
| Finished | Oct 02 06:57:31 PM UTC 24 |
| Peak memory | 211972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253336713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.253336713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/15.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.496988918 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 19717569560 ps |
| CPU time | 70.75 seconds |
| Started | Oct 02 06:57:18 PM UTC 24 |
| Finished | Oct 02 06:58:31 PM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496988918 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.496988918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.228333963 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 33080632 ps |
| CPU time | 3.15 seconds |
| Started | Oct 02 06:57:24 PM UTC 24 |
| Finished | Oct 02 06:57:28 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228333963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.228333963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_error_random.3235106948 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 181144371 ps |
| CPU time | 6.51 seconds |
| Started | Oct 02 06:57:22 PM UTC 24 |
| Finished | Oct 02 06:57:29 PM UTC 24 |
| Peak memory | 211988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235106948 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3235106948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/15.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random.3432985639 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 162545498 ps |
| CPU time | 10.72 seconds |
| Started | Oct 02 06:57:16 PM UTC 24 |
| Finished | Oct 02 06:57:28 PM UTC 24 |
| Peak memory | 211976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432985639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.3432985639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/15.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_large_delays.3324255860 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 32277532885 ps |
| CPU time | 139.07 seconds |
| Started | Oct 02 06:57:18 PM UTC 24 |
| Finished | Oct 02 06:59:40 PM UTC 24 |
| Peak memory | 212268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324255860 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.3324255860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/15.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_slow_rsp.4036548046 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 13118384208 ps |
| CPU time | 22.41 seconds |
| Started | Oct 02 06:57:18 PM UTC 24 |
| Finished | Oct 02 06:57:42 PM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036548046 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.4036548046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/15.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_zero_delays.1007174579 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 20546660 ps |
| CPU time | 2.59 seconds |
| Started | Oct 02 06:57:17 PM UTC 24 |
| Finished | Oct 02 06:57:21 PM UTC 24 |
| Peak memory | 212260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007174579 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.1007174579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/15.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_same_source.3770610841 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 31562075 ps |
| CPU time | 4.47 seconds |
| Started | Oct 02 06:57:18 PM UTC 24 |
| Finished | Oct 02 06:57:24 PM UTC 24 |
| Peak memory | 211996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770610841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.3770610841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/15.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke.2992819696 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 59164606 ps |
| CPU time | 1.96 seconds |
| Started | Oct 02 06:57:14 PM UTC 24 |
| Finished | Oct 02 06:57:17 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992819696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.2992819696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/15.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_large_delays.3646846889 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1882161521 ps |
| CPU time | 12.16 seconds |
| Started | Oct 02 06:57:14 PM UTC 24 |
| Finished | Oct 02 06:57:28 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646846889 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3646846889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/15.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.681094977 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 11112142486 ps |
| CPU time | 11.01 seconds |
| Started | Oct 02 06:57:16 PM UTC 24 |
| Finished | Oct 02 06:57:28 PM UTC 24 |
| Peak memory | 212044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681094977 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.681094977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.2814108195 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 11276393 ps |
| CPU time | 1.59 seconds |
| Started | Oct 02 06:57:14 PM UTC 24 |
| Finished | Oct 02 06:57:17 PM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814108195 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.2814108195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/15.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all.3257115797 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 2599530743 ps |
| CPU time | 48.29 seconds |
| Started | Oct 02 06:57:25 PM UTC 24 |
| Finished | Oct 02 06:58:15 PM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257115797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3257115797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/15.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_error.2865935389 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 142463191 ps |
| CPU time | 10.76 seconds |
| Started | Oct 02 06:57:28 PM UTC 24 |
| Finished | Oct 02 06:57:40 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865935389 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2865935389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/15.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3790645241 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 141772052 ps |
| CPU time | 34.9 seconds |
| Started | Oct 02 06:57:25 PM UTC 24 |
| Finished | Oct 02 06:58:01 PM UTC 24 |
| Peak memory | 214056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790645241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.3790645241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.2510707709 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 6974435385 ps |
| CPU time | 160.59 seconds |
| Started | Oct 02 06:57:29 PM UTC 24 |
| Finished | Oct 02 07:00:13 PM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510707709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.2510707709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_unmapped_addr.1329542045 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 836363265 ps |
| CPU time | 12.5 seconds |
| Started | Oct 02 06:57:23 PM UTC 24 |
| Finished | Oct 02 06:57:36 PM UTC 24 |
| Peak memory | 212268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329542045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1329542045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/15.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device.860497381 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 49723134 ps |
| CPU time | 9.5 seconds |
| Started | Oct 02 06:57:35 PM UTC 24 |
| Finished | Oct 02 06:57:46 PM UTC 24 |
| Peak memory | 212204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860497381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.860497381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/16.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.323571625 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 111229191968 ps |
| CPU time | 408.25 seconds |
| Started | Oct 02 06:57:35 PM UTC 24 |
| Finished | Oct 02 07:04:29 PM UTC 24 |
| Peak memory | 217992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323571625 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.323571625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.2560774186 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 301506046 ps |
| CPU time | 6.34 seconds |
| Started | Oct 02 06:57:40 PM UTC 24 |
| Finished | Oct 02 06:57:48 PM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560774186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.2560774186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_error_random.1898728084 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 232797241 ps |
| CPU time | 5.92 seconds |
| Started | Oct 02 06:57:37 PM UTC 24 |
| Finished | Oct 02 06:57:44 PM UTC 24 |
| Peak memory | 212180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898728084 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1898728084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/16.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random.769140247 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 302770090 ps |
| CPU time | 10.26 seconds |
| Started | Oct 02 06:57:32 PM UTC 24 |
| Finished | Oct 02 06:57:43 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769140247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.769140247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/16.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_large_delays.4234934454 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 41474232753 ps |
| CPU time | 93.14 seconds |
| Started | Oct 02 06:57:33 PM UTC 24 |
| Finished | Oct 02 06:59:08 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234934454 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.4234934454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/16.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_slow_rsp.1060692832 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 20269957898 ps |
| CPU time | 76.5 seconds |
| Started | Oct 02 06:57:34 PM UTC 24 |
| Finished | Oct 02 06:58:53 PM UTC 24 |
| Peak memory | 212060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060692832 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1060692832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/16.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_zero_delays.3959796396 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 40485358 ps |
| CPU time | 2.41 seconds |
| Started | Oct 02 06:57:33 PM UTC 24 |
| Finished | Oct 02 06:57:37 PM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959796396 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.3959796396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/16.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_same_source.17032368 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 4289795112 ps |
| CPU time | 9.8 seconds |
| Started | Oct 02 06:57:37 PM UTC 24 |
| Finished | Oct 02 06:57:48 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17032368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.17032368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/16.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke.465740275 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 8190172 ps |
| CPU time | 1.64 seconds |
| Started | Oct 02 06:57:30 PM UTC 24 |
| Finished | Oct 02 06:57:32 PM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465740275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.465740275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/16.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_large_delays.3372289979 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 6907523988 ps |
| CPU time | 11.2 seconds |
| Started | Oct 02 06:57:30 PM UTC 24 |
| Finished | Oct 02 06:57:42 PM UTC 24 |
| Peak memory | 212264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372289979 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3372289979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/16.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.426096957 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 1384703709 ps |
| CPU time | 17.06 seconds |
| Started | Oct 02 06:57:31 PM UTC 24 |
| Finished | Oct 02 06:57:49 PM UTC 24 |
| Peak memory | 212180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426096957 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.426096957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.2885125474 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 27145437 ps |
| CPU time | 1.9 seconds |
| Started | Oct 02 06:57:30 PM UTC 24 |
| Finished | Oct 02 06:57:33 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885125474 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.2885125474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/16.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all.479460953 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 339864969 ps |
| CPU time | 19.01 seconds |
| Started | Oct 02 06:57:41 PM UTC 24 |
| Finished | Oct 02 06:58:02 PM UTC 24 |
| Peak memory | 214216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479460953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.479460953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/16.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_error.3180646512 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 90133756 ps |
| CPU time | 12.43 seconds |
| Started | Oct 02 06:57:42 PM UTC 24 |
| Finished | Oct 02 06:57:56 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180646512 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.3180646512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/16.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3802699492 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 6846911 ps |
| CPU time | 1.21 seconds |
| Started | Oct 02 06:57:42 PM UTC 24 |
| Finished | Oct 02 06:57:45 PM UTC 24 |
| Peak memory | 202228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802699492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.3802699492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.3414513065 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 576324495 ps |
| CPU time | 70.31 seconds |
| Started | Oct 02 06:57:45 PM UTC 24 |
| Finished | Oct 02 06:58:57 PM UTC 24 |
| Peak memory | 216052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414513065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.3414513065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_unmapped_addr.473664132 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 54444931 ps |
| CPU time | 9.51 seconds |
| Started | Oct 02 06:57:38 PM UTC 24 |
| Finished | Oct 02 06:57:49 PM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473664132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.473664132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/16.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device.3429774763 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 91792784 ps |
| CPU time | 10.52 seconds |
| Started | Oct 02 06:57:50 PM UTC 24 |
| Finished | Oct 02 06:58:01 PM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429774763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.3429774763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/17.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.2921112859 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 564715782 ps |
| CPU time | 6.57 seconds |
| Started | Oct 02 06:57:56 PM UTC 24 |
| Finished | Oct 02 06:58:03 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921112859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.2921112859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_error_random.2854789540 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 1012732218 ps |
| CPU time | 13.26 seconds |
| Started | Oct 02 06:57:53 PM UTC 24 |
| Finished | Oct 02 06:58:08 PM UTC 24 |
| Peak memory | 212244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854789540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2854789540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/17.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random.2082708210 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 845637884 ps |
| CPU time | 18.75 seconds |
| Started | Oct 02 06:57:48 PM UTC 24 |
| Finished | Oct 02 06:58:08 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082708210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.2082708210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/17.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_large_delays.884943077 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 36545831595 ps |
| CPU time | 166.01 seconds |
| Started | Oct 02 06:57:48 PM UTC 24 |
| Finished | Oct 02 07:00:37 PM UTC 24 |
| Peak memory | 212264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884943077 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.884943077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/17.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_slow_rsp.741924896 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 10155337511 ps |
| CPU time | 38.9 seconds |
| Started | Oct 02 06:57:50 PM UTC 24 |
| Finished | Oct 02 06:58:30 PM UTC 24 |
| Peak memory | 212052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741924896 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.741924896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/17.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_zero_delays.3793827010 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 46068147 ps |
| CPU time | 2.1 seconds |
| Started | Oct 02 06:57:48 PM UTC 24 |
| Finished | Oct 02 06:57:51 PM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793827010 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.3793827010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/17.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_same_source.154789338 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 37757851 ps |
| CPU time | 4.74 seconds |
| Started | Oct 02 06:57:51 PM UTC 24 |
| Finished | Oct 02 06:57:57 PM UTC 24 |
| Peak memory | 211996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154789338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.154789338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/17.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke.1992193758 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 9068554 ps |
| CPU time | 1.48 seconds |
| Started | Oct 02 06:57:45 PM UTC 24 |
| Finished | Oct 02 06:57:47 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992193758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.1992193758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/17.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_large_delays.4079417217 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 15012061406 ps |
| CPU time | 17.08 seconds |
| Started | Oct 02 06:57:46 PM UTC 24 |
| Finished | Oct 02 06:58:04 PM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079417217 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.4079417217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/17.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.3736808892 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8165117199 ps |
| CPU time | 16.74 seconds |
| Started | Oct 02 06:57:47 PM UTC 24 |
| Finished | Oct 02 06:58:05 PM UTC 24 |
| Peak memory | 212052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736808892 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.3736808892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.765631128 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 8696208 ps |
| CPU time | 1.4 seconds |
| Started | Oct 02 06:57:46 PM UTC 24 |
| Finished | Oct 02 06:57:48 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765631128 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.765631128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/17.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all.1436845456 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 2049085478 ps |
| CPU time | 44.34 seconds |
| Started | Oct 02 06:57:58 PM UTC 24 |
| Finished | Oct 02 06:58:44 PM UTC 24 |
| Peak memory | 214060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436845456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.1436845456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/17.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_error.3942130867 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 191581607 ps |
| CPU time | 20.91 seconds |
| Started | Oct 02 06:57:58 PM UTC 24 |
| Finished | Oct 02 06:58:21 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942130867 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3942130867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/17.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.802753711 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 625812200 ps |
| CPU time | 85.74 seconds |
| Started | Oct 02 06:57:58 PM UTC 24 |
| Finished | Oct 02 06:59:26 PM UTC 24 |
| Peak memory | 216092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802753711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.802753711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.1038750627 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 118826113 ps |
| CPU time | 10.03 seconds |
| Started | Oct 02 06:57:58 PM UTC 24 |
| Finished | Oct 02 06:58:10 PM UTC 24 |
| Peak memory | 212076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038750627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.1038750627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_unmapped_addr.4274402125 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 35765751 ps |
| CPU time | 3.01 seconds |
| Started | Oct 02 06:57:53 PM UTC 24 |
| Finished | Oct 02 06:57:57 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274402125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.4274402125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/17.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device.3520813512 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 985121811 ps |
| CPU time | 17.66 seconds |
| Started | Oct 02 06:58:05 PM UTC 24 |
| Finished | Oct 02 06:58:24 PM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520813512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.3520813512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/18.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.1500086284 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 76059923161 ps |
| CPU time | 214.58 seconds |
| Started | Oct 02 06:58:05 PM UTC 24 |
| Finished | Oct 02 07:01:43 PM UTC 24 |
| Peak memory | 214124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500086284 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.1500086284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.333792469 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 968879498 ps |
| CPU time | 9.33 seconds |
| Started | Oct 02 06:58:10 PM UTC 24 |
| Finished | Oct 02 06:58:21 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333792469 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.333792469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_error_random.40418865 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 92362129 ps |
| CPU time | 9.48 seconds |
| Started | Oct 02 06:58:08 PM UTC 24 |
| Finished | Oct 02 06:58:19 PM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40418865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.40418865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/18.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random.1714880352 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 306112960 ps |
| CPU time | 8.17 seconds |
| Started | Oct 02 06:58:02 PM UTC 24 |
| Finished | Oct 02 06:58:12 PM UTC 24 |
| Peak memory | 212240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714880352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.1714880352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/18.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_large_delays.1912760234 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 13724142859 ps |
| CPU time | 66.93 seconds |
| Started | Oct 02 06:58:05 PM UTC 24 |
| Finished | Oct 02 06:59:14 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912760234 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.1912760234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/18.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_slow_rsp.954189967 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 7987038044 ps |
| CPU time | 45.53 seconds |
| Started | Oct 02 06:58:05 PM UTC 24 |
| Finished | Oct 02 06:58:52 PM UTC 24 |
| Peak memory | 212048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954189967 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.954189967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/18.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_zero_delays.1915474313 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 86737318 ps |
| CPU time | 9.57 seconds |
| Started | Oct 02 06:58:04 PM UTC 24 |
| Finished | Oct 02 06:58:14 PM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915474313 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.1915474313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/18.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_same_source.2001963673 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 869816108 ps |
| CPU time | 7.29 seconds |
| Started | Oct 02 06:58:06 PM UTC 24 |
| Finished | Oct 02 06:58:14 PM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001963673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2001963673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/18.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke.1079697413 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 52220885 ps |
| CPU time | 2.43 seconds |
| Started | Oct 02 06:57:59 PM UTC 24 |
| Finished | Oct 02 06:58:03 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079697413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.1079697413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/18.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_large_delays.3785987139 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 4673417650 ps |
| CPU time | 14.07 seconds |
| Started | Oct 02 06:58:02 PM UTC 24 |
| Finished | Oct 02 06:58:18 PM UTC 24 |
| Peak memory | 212264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785987139 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.3785987139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/18.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.3554804372 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 2758744441 ps |
| CPU time | 20.14 seconds |
| Started | Oct 02 06:58:02 PM UTC 24 |
| Finished | Oct 02 06:58:24 PM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554804372 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.3554804372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.2215099536 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 8949728 ps |
| CPU time | 1.77 seconds |
| Started | Oct 02 06:58:01 PM UTC 24 |
| Finished | Oct 02 06:58:04 PM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215099536 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.2215099536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/18.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all.3463248594 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 3966439538 ps |
| CPU time | 71.57 seconds |
| Started | Oct 02 06:58:13 PM UTC 24 |
| Finished | Oct 02 06:59:26 PM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463248594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.3463248594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/18.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1556704828 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 547279013 ps |
| CPU time | 33.63 seconds |
| Started | Oct 02 06:58:16 PM UTC 24 |
| Finished | Oct 02 06:58:51 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556704828 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1556704828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/18.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.2095888225 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1485057936 ps |
| CPU time | 214.23 seconds |
| Started | Oct 02 06:58:13 PM UTC 24 |
| Finished | Oct 02 07:01:50 PM UTC 24 |
| Peak memory | 216108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095888225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.2095888225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.3629884501 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 1412530880 ps |
| CPU time | 145.39 seconds |
| Started | Oct 02 06:58:16 PM UTC 24 |
| Finished | Oct 02 07:00:44 PM UTC 24 |
| Peak memory | 218632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629884501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.3629884501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_unmapped_addr.1634230206 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 129000079 ps |
| CPU time | 6.82 seconds |
| Started | Oct 02 06:58:09 PM UTC 24 |
| Finished | Oct 02 06:58:17 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634230206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1634230206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/18.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device.278538561 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 808888607 ps |
| CPU time | 8.76 seconds |
| Started | Oct 02 06:58:22 PM UTC 24 |
| Finished | Oct 02 06:58:32 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278538561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.278538561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/19.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.641359289 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 20557084827 ps |
| CPU time | 142.38 seconds |
| Started | Oct 02 06:58:22 PM UTC 24 |
| Finished | Oct 02 07:00:47 PM UTC 24 |
| Peak memory | 214116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641359289 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.641359289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.1314406822 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 431894151 ps |
| CPU time | 7.85 seconds |
| Started | Oct 02 06:58:25 PM UTC 24 |
| Finished | Oct 02 06:58:34 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314406822 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.1314406822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_error_random.1320744395 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 530225957 ps |
| CPU time | 11.74 seconds |
| Started | Oct 02 06:58:24 PM UTC 24 |
| Finished | Oct 02 06:58:37 PM UTC 24 |
| Peak memory | 212244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320744395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1320744395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/19.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random.3352217520 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 231480485 ps |
| CPU time | 5.66 seconds |
| Started | Oct 02 06:58:21 PM UTC 24 |
| Finished | Oct 02 06:58:27 PM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352217520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.3352217520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/19.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_large_delays.3287131568 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 14050780609 ps |
| CPU time | 73.64 seconds |
| Started | Oct 02 06:58:22 PM UTC 24 |
| Finished | Oct 02 06:59:37 PM UTC 24 |
| Peak memory | 212024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287131568 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.3287131568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/19.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_slow_rsp.3191435874 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 19039794967 ps |
| CPU time | 61.2 seconds |
| Started | Oct 02 06:58:22 PM UTC 24 |
| Finished | Oct 02 06:59:25 PM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191435874 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.3191435874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/19.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_zero_delays.1434242431 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 103242213 ps |
| CPU time | 3.57 seconds |
| Started | Oct 02 06:58:21 PM UTC 24 |
| Finished | Oct 02 06:58:25 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434242431 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.1434242431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/19.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_same_source.1644065715 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 2313943154 ps |
| CPU time | 17.02 seconds |
| Started | Oct 02 06:58:24 PM UTC 24 |
| Finished | Oct 02 06:58:43 PM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644065715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.1644065715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/19.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke.2110331163 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 39850875 ps |
| CPU time | 1.92 seconds |
| Started | Oct 02 06:58:16 PM UTC 24 |
| Finished | Oct 02 06:58:19 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110331163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2110331163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/19.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3946663325 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1960166877 ps |
| CPU time | 13.91 seconds |
| Started | Oct 02 06:58:18 PM UTC 24 |
| Finished | Oct 02 06:58:33 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946663325 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3946663325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/19.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.3104254648 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 3162066825 ps |
| CPU time | 14.77 seconds |
| Started | Oct 02 06:58:20 PM UTC 24 |
| Finished | Oct 02 06:58:36 PM UTC 24 |
| Peak memory | 212052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104254648 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3104254648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.2715917791 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 10158228 ps |
| CPU time | 1.91 seconds |
| Started | Oct 02 06:58:18 PM UTC 24 |
| Finished | Oct 02 06:58:21 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715917791 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.2715917791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/19.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all.2997832938 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 784987457 ps |
| CPU time | 14.24 seconds |
| Started | Oct 02 06:58:27 PM UTC 24 |
| Finished | Oct 02 06:58:43 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997832938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2997832938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/19.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_error.972662976 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 20317645063 ps |
| CPU time | 64.75 seconds |
| Started | Oct 02 06:58:28 PM UTC 24 |
| Finished | Oct 02 06:59:35 PM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972662976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.972662976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/19.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.2705221126 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 269745066 ps |
| CPU time | 39.65 seconds |
| Started | Oct 02 06:58:27 PM UTC 24 |
| Finished | Oct 02 06:59:09 PM UTC 24 |
| Peak memory | 216104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705221126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.2705221126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.463300697 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 394410779 ps |
| CPU time | 23.47 seconds |
| Started | Oct 02 06:58:28 PM UTC 24 |
| Finished | Oct 02 06:58:53 PM UTC 24 |
| Peak memory | 214060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463300697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.463300697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_unmapped_addr.1601831327 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 38431351 ps |
| CPU time | 2.94 seconds |
| Started | Oct 02 06:58:25 PM UTC 24 |
| Finished | Oct 02 06:58:29 PM UTC 24 |
| Peak memory | 212264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601831327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.1601831327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/19.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device.746105609 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 167960217 ps |
| CPU time | 14.01 seconds |
| Started | Oct 02 06:53:42 PM UTC 24 |
| Finished | Oct 02 06:53:58 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746105609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.746105609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/2.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.4179007055 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 49977579 ps |
| CPU time | 2.95 seconds |
| Started | Oct 02 06:53:47 PM UTC 24 |
| Finished | Oct 02 06:53:51 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179007055 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.4179007055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_error_random.2403784128 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 1158242546 ps |
| CPU time | 18.09 seconds |
| Started | Oct 02 06:53:44 PM UTC 24 |
| Finished | Oct 02 06:54:03 PM UTC 24 |
| Peak memory | 212184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403784128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2403784128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/2.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random.2390362767 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 87446953 ps |
| CPU time | 8.19 seconds |
| Started | Oct 02 06:53:36 PM UTC 24 |
| Finished | Oct 02 06:53:46 PM UTC 24 |
| Peak memory | 211976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390362767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.2390362767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/2.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_large_delays.1870758307 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 21277128731 ps |
| CPU time | 122.42 seconds |
| Started | Oct 02 06:53:39 PM UTC 24 |
| Finished | Oct 02 06:55:45 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870758307 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.1870758307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/2.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_slow_rsp.3198411867 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 32621763026 ps |
| CPU time | 131.06 seconds |
| Started | Oct 02 06:53:40 PM UTC 24 |
| Finished | Oct 02 06:55:53 PM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198411867 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.3198411867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/2.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_zero_delays.1086815131 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 19977833 ps |
| CPU time | 3.05 seconds |
| Started | Oct 02 06:53:37 PM UTC 24 |
| Finished | Oct 02 06:53:42 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086815131 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.1086815131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/2.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_same_source.1462992668 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 104657798 ps |
| CPU time | 4.13 seconds |
| Started | Oct 02 06:53:43 PM UTC 24 |
| Finished | Oct 02 06:53:49 PM UTC 24 |
| Peak memory | 214016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462992668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.1462992668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/2.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke.1701259264 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 200055882 ps |
| CPU time | 2.4 seconds |
| Started | Oct 02 06:53:32 PM UTC 24 |
| Finished | Oct 02 06:53:35 PM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701259264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.1701259264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/2.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_large_delays.532678735 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 2433966255 ps |
| CPU time | 11.91 seconds |
| Started | Oct 02 06:53:34 PM UTC 24 |
| Finished | Oct 02 06:53:47 PM UTC 24 |
| Peak memory | 212264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532678735 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.532678735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/2.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.1183365081 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1978365164 ps |
| CPU time | 12.17 seconds |
| Started | Oct 02 06:53:35 PM UTC 24 |
| Finished | Oct 02 06:53:49 PM UTC 24 |
| Peak memory | 211988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183365081 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.1183365081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.3622151570 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 9129243 ps |
| CPU time | 1.96 seconds |
| Started | Oct 02 06:53:33 PM UTC 24 |
| Finished | Oct 02 06:53:36 PM UTC 24 |
| Peak memory | 210932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622151570 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.3622151570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/2.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all.3279747929 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 2628389804 ps |
| CPU time | 28.82 seconds |
| Started | Oct 02 06:53:49 PM UTC 24 |
| Finished | Oct 02 06:54:19 PM UTC 24 |
| Peak memory | 214316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279747929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3279747929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/2.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_error.209997879 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 2267726440 ps |
| CPU time | 18.51 seconds |
| Started | Oct 02 06:53:50 PM UTC 24 |
| Finished | Oct 02 06:54:10 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209997879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.209997879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/2.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.191233002 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 1984971847 ps |
| CPU time | 91.66 seconds |
| Started | Oct 02 06:53:50 PM UTC 24 |
| Finished | Oct 02 06:55:24 PM UTC 24 |
| Peak memory | 214060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191233002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.191233002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_unmapped_addr.18854706 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 46951450 ps |
| CPU time | 3.99 seconds |
| Started | Oct 02 06:53:47 PM UTC 24 |
| Finished | Oct 02 06:53:52 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18854706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.18854706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/2.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device.3472290170 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 933571289 ps |
| CPU time | 20.01 seconds |
| Started | Oct 02 06:58:35 PM UTC 24 |
| Finished | Oct 02 06:58:57 PM UTC 24 |
| Peak memory | 212204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472290170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.3472290170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/20.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.3869060323 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 30420170815 ps |
| CPU time | 205.82 seconds |
| Started | Oct 02 06:58:35 PM UTC 24 |
| Finished | Oct 02 07:02:05 PM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869060323 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.3869060323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.764356166 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 56628131 ps |
| CPU time | 5.78 seconds |
| Started | Oct 02 06:58:40 PM UTC 24 |
| Finished | Oct 02 06:58:47 PM UTC 24 |
| Peak memory | 212204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764356166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.764356166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_error_random.942528622 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 1905068719 ps |
| CPU time | 14.32 seconds |
| Started | Oct 02 06:58:39 PM UTC 24 |
| Finished | Oct 02 06:58:54 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942528622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.942528622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/20.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random.1458490187 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 710109127 ps |
| CPU time | 6.42 seconds |
| Started | Oct 02 06:58:33 PM UTC 24 |
| Finished | Oct 02 06:58:40 PM UTC 24 |
| Peak memory | 211980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458490187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.1458490187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/20.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_large_delays.1163577822 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 36176459614 ps |
| CPU time | 82.07 seconds |
| Started | Oct 02 06:58:34 PM UTC 24 |
| Finished | Oct 02 06:59:58 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163577822 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1163577822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/20.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_slow_rsp.750441293 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 57488093007 ps |
| CPU time | 125.22 seconds |
| Started | Oct 02 06:58:34 PM UTC 24 |
| Finished | Oct 02 07:00:42 PM UTC 24 |
| Peak memory | 212048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750441293 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.750441293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/20.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_zero_delays.1263168369 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 73464521 ps |
| CPU time | 6.47 seconds |
| Started | Oct 02 06:58:34 PM UTC 24 |
| Finished | Oct 02 06:58:42 PM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263168369 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.1263168369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/20.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_same_source.281070515 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 225206575 ps |
| CPU time | 3.44 seconds |
| Started | Oct 02 06:58:38 PM UTC 24 |
| Finished | Oct 02 06:58:42 PM UTC 24 |
| Peak memory | 214020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281070515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.281070515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/20.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke.378516669 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 46698928 ps |
| CPU time | 2.45 seconds |
| Started | Oct 02 06:58:31 PM UTC 24 |
| Finished | Oct 02 06:58:34 PM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378516669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.378516669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/20.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_large_delays.356080332 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 1164007568 ps |
| CPU time | 6.79 seconds |
| Started | Oct 02 06:58:31 PM UTC 24 |
| Finished | Oct 02 06:58:39 PM UTC 24 |
| Peak memory | 211816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356080332 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.356080332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/20.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.304042620 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 1417459521 ps |
| CPU time | 11.43 seconds |
| Started | Oct 02 06:58:33 PM UTC 24 |
| Finished | Oct 02 06:58:45 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304042620 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.304042620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.18846677 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 11163143 ps |
| CPU time | 1.57 seconds |
| Started | Oct 02 06:58:31 PM UTC 24 |
| Finished | Oct 02 06:58:33 PM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18846677 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.18846677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/20.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all.1931240034 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 2042348326 ps |
| CPU time | 39.25 seconds |
| Started | Oct 02 06:58:40 PM UTC 24 |
| Finished | Oct 02 06:59:21 PM UTC 24 |
| Peak memory | 214060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931240034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.1931240034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/20.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_error.3817421749 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 122721012 ps |
| CPU time | 11.01 seconds |
| Started | Oct 02 06:58:43 PM UTC 24 |
| Finished | Oct 02 06:58:55 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817421749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.3817421749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/20.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.4270006260 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 1496080117 ps |
| CPU time | 81.41 seconds |
| Started | Oct 02 06:58:41 PM UTC 24 |
| Finished | Oct 02 07:00:05 PM UTC 24 |
| Peak memory | 216100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270006260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.4270006260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.1435901945 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 71691893 ps |
| CPU time | 8.64 seconds |
| Started | Oct 02 06:58:43 PM UTC 24 |
| Finished | Oct 02 06:58:52 PM UTC 24 |
| Peak memory | 212204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435901945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.1435901945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_unmapped_addr.1911722398 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 43855845 ps |
| CPU time | 2.75 seconds |
| Started | Oct 02 06:58:39 PM UTC 24 |
| Finished | Oct 02 06:58:43 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911722398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1911722398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/20.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device.2746502141 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 225130561 ps |
| CPU time | 6.18 seconds |
| Started | Oct 02 06:58:48 PM UTC 24 |
| Finished | Oct 02 06:58:55 PM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746502141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.2746502141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/21.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.3200213536 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 657663684 ps |
| CPU time | 9.77 seconds |
| Started | Oct 02 06:58:52 PM UTC 24 |
| Finished | Oct 02 06:59:03 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200213536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.3200213536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_error_random.3101213649 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 47801278 ps |
| CPU time | 3.83 seconds |
| Started | Oct 02 06:58:52 PM UTC 24 |
| Finished | Oct 02 06:58:57 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101213649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3101213649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/21.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random.453372129 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 37090539 ps |
| CPU time | 1.98 seconds |
| Started | Oct 02 06:58:45 PM UTC 24 |
| Finished | Oct 02 06:58:48 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453372129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.453372129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/21.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_large_delays.4069098649 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 4591369095 ps |
| CPU time | 19.1 seconds |
| Started | Oct 02 06:58:48 PM UTC 24 |
| Finished | Oct 02 06:59:08 PM UTC 24 |
| Peak memory | 212076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069098649 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.4069098649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/21.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_slow_rsp.1387121813 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 18202896262 ps |
| CPU time | 55.84 seconds |
| Started | Oct 02 06:58:48 PM UTC 24 |
| Finished | Oct 02 06:59:45 PM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387121813 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1387121813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/21.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_zero_delays.3607970744 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 117948167 ps |
| CPU time | 5.46 seconds |
| Started | Oct 02 06:58:46 PM UTC 24 |
| Finished | Oct 02 06:58:53 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607970744 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.3607970744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/21.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_same_source.2886001520 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 209674104 ps |
| CPU time | 4.78 seconds |
| Started | Oct 02 06:58:50 PM UTC 24 |
| Finished | Oct 02 06:58:56 PM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886001520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2886001520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/21.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke.3980921004 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 26158727 ps |
| CPU time | 1.25 seconds |
| Started | Oct 02 06:58:44 PM UTC 24 |
| Finished | Oct 02 06:58:46 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980921004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.3980921004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/21.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_large_delays.1957334498 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 1864187816 ps |
| CPU time | 18.47 seconds |
| Started | Oct 02 06:58:44 PM UTC 24 |
| Finished | Oct 02 06:59:04 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957334498 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.1957334498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/21.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.3827728256 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 1478788344 ps |
| CPU time | 12.86 seconds |
| Started | Oct 02 06:58:44 PM UTC 24 |
| Finished | Oct 02 06:58:58 PM UTC 24 |
| Peak memory | 211988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827728256 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.3827728256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.249633436 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 8795707 ps |
| CPU time | 1.71 seconds |
| Started | Oct 02 06:58:44 PM UTC 24 |
| Finished | Oct 02 06:58:47 PM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249633436 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.249633436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/21.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all.1183220478 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 101672813 ps |
| CPU time | 6.16 seconds |
| Started | Oct 02 06:58:54 PM UTC 24 |
| Finished | Oct 02 06:59:01 PM UTC 24 |
| Peak memory | 212076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183220478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1183220478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/21.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_error.2872307440 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 252250685 ps |
| CPU time | 21.94 seconds |
| Started | Oct 02 06:58:54 PM UTC 24 |
| Finished | Oct 02 06:59:17 PM UTC 24 |
| Peak memory | 214056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872307440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.2872307440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/21.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.4150198439 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 1153059128 ps |
| CPU time | 152.46 seconds |
| Started | Oct 02 06:58:54 PM UTC 24 |
| Finished | Oct 02 07:01:29 PM UTC 24 |
| Peak memory | 216108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150198439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.4150198439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.3451024744 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 5070854395 ps |
| CPU time | 66.07 seconds |
| Started | Oct 02 06:58:54 PM UTC 24 |
| Finished | Oct 02 07:00:02 PM UTC 24 |
| Peak memory | 213976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451024744 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.3451024744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_unmapped_addr.214304573 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 249409398 ps |
| CPU time | 4.7 seconds |
| Started | Oct 02 06:58:52 PM UTC 24 |
| Finished | Oct 02 06:58:58 PM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214304573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.214304573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/21.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device.1878064564 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 24197332 ps |
| CPU time | 3.86 seconds |
| Started | Oct 02 06:58:58 PM UTC 24 |
| Finished | Oct 02 06:59:03 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878064564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.1878064564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/22.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.2798588654 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 49572628498 ps |
| CPU time | 299.11 seconds |
| Started | Oct 02 06:58:59 PM UTC 24 |
| Finished | Oct 02 07:04:02 PM UTC 24 |
| Peak memory | 216364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798588654 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.2798588654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.2033787068 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 37606771 ps |
| CPU time | 1.78 seconds |
| Started | Oct 02 06:58:59 PM UTC 24 |
| Finished | Oct 02 06:59:02 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033787068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.2033787068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_error_random.887939001 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 681419000 ps |
| CPU time | 12.74 seconds |
| Started | Oct 02 06:58:59 PM UTC 24 |
| Finished | Oct 02 06:59:13 PM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887939001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.887939001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/22.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random.2034022348 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 408855284 ps |
| CPU time | 4.35 seconds |
| Started | Oct 02 06:58:58 PM UTC 24 |
| Finished | Oct 02 06:59:03 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034022348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.2034022348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/22.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_large_delays.3313507067 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 10837719475 ps |
| CPU time | 48.99 seconds |
| Started | Oct 02 06:58:58 PM UTC 24 |
| Finished | Oct 02 06:59:48 PM UTC 24 |
| Peak memory | 212332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313507067 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3313507067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/22.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_slow_rsp.2571468247 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 100650810675 ps |
| CPU time | 102.61 seconds |
| Started | Oct 02 06:58:58 PM UTC 24 |
| Finished | Oct 02 07:00:42 PM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571468247 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.2571468247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/22.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_zero_delays.964309304 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 357501910 ps |
| CPU time | 8.15 seconds |
| Started | Oct 02 06:58:58 PM UTC 24 |
| Finished | Oct 02 06:59:07 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964309304 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.964309304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/22.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_same_source.1454727345 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 1168089496 ps |
| CPU time | 14.68 seconds |
| Started | Oct 02 06:58:59 PM UTC 24 |
| Finished | Oct 02 06:59:15 PM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454727345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1454727345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/22.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke.1799119157 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 10473621 ps |
| CPU time | 1.71 seconds |
| Started | Oct 02 06:58:54 PM UTC 24 |
| Finished | Oct 02 06:58:57 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799119157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.1799119157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/22.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1188784088 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 2587060163 ps |
| CPU time | 11.89 seconds |
| Started | Oct 02 06:58:56 PM UTC 24 |
| Finished | Oct 02 06:59:09 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188784088 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1188784088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/22.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.1808279597 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 6754824500 ps |
| CPU time | 8.83 seconds |
| Started | Oct 02 06:58:56 PM UTC 24 |
| Finished | Oct 02 06:59:06 PM UTC 24 |
| Peak memory | 212248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808279597 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.1808279597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.2621217078 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 15230605 ps |
| CPU time | 1.32 seconds |
| Started | Oct 02 06:58:55 PM UTC 24 |
| Finished | Oct 02 06:58:57 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621217078 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.2621217078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/22.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all.1232461117 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 455030080 ps |
| CPU time | 52.01 seconds |
| Started | Oct 02 06:59:01 PM UTC 24 |
| Finished | Oct 02 06:59:55 PM UTC 24 |
| Peak memory | 214124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232461117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.1232461117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/22.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_error.784913 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 5394807292 ps |
| CPU time | 60.55 seconds |
| Started | Oct 02 06:59:04 PM UTC 24 |
| Finished | Oct 02 07:00:06 PM UTC 24 |
| Peak memory | 212140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_T EST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.784913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/22.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.2063605660 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 124006191 ps |
| CPU time | 16.88 seconds |
| Started | Oct 02 06:59:03 PM UTC 24 |
| Finished | Oct 02 06:59:21 PM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063605660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.2063605660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_unmapped_addr.1134842312 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 110452067 ps |
| CPU time | 9.77 seconds |
| Started | Oct 02 06:58:59 PM UTC 24 |
| Finished | Oct 02 06:59:10 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134842312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.1134842312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/22.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device.2720551970 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 157236539 ps |
| CPU time | 6.48 seconds |
| Started | Oct 02 06:59:09 PM UTC 24 |
| Finished | Oct 02 06:59:16 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720551970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.2720551970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/23.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.3215511100 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 40672116323 ps |
| CPU time | 121.03 seconds |
| Started | Oct 02 06:59:10 PM UTC 24 |
| Finished | Oct 02 07:01:14 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215511100 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.3215511100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.3234901585 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 797061847 ps |
| CPU time | 18.39 seconds |
| Started | Oct 02 06:59:12 PM UTC 24 |
| Finished | Oct 02 06:59:31 PM UTC 24 |
| Peak memory | 211612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234901585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.3234901585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_error_random.4028467921 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 3015481459 ps |
| CPU time | 13.15 seconds |
| Started | Oct 02 06:59:10 PM UTC 24 |
| Finished | Oct 02 06:59:25 PM UTC 24 |
| Peak memory | 212048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028467921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.4028467921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/23.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random.916180221 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 41230061 ps |
| CPU time | 2.43 seconds |
| Started | Oct 02 06:59:07 PM UTC 24 |
| Finished | Oct 02 06:59:11 PM UTC 24 |
| Peak memory | 211988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916180221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.916180221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/23.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_large_delays.431932302 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 51292975078 ps |
| CPU time | 165.13 seconds |
| Started | Oct 02 06:59:09 PM UTC 24 |
| Finished | Oct 02 07:01:57 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431932302 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.431932302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/23.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_slow_rsp.2176724640 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 2661423006 ps |
| CPU time | 12.99 seconds |
| Started | Oct 02 06:59:09 PM UTC 24 |
| Finished | Oct 02 06:59:23 PM UTC 24 |
| Peak memory | 212060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176724640 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.2176724640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/23.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_zero_delays.2486957358 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 34853369 ps |
| CPU time | 6.16 seconds |
| Started | Oct 02 06:59:08 PM UTC 24 |
| Finished | Oct 02 06:59:15 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486957358 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.2486957358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/23.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_same_source.166057864 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 3833255762 ps |
| CPU time | 10.28 seconds |
| Started | Oct 02 06:59:10 PM UTC 24 |
| Finished | Oct 02 06:59:22 PM UTC 24 |
| Peak memory | 212312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166057864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.166057864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/23.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke.3431221558 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 276775206 ps |
| CPU time | 2.02 seconds |
| Started | Oct 02 06:59:04 PM UTC 24 |
| Finished | Oct 02 06:59:07 PM UTC 24 |
| Peak memory | 212180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431221558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.3431221558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/23.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_large_delays.2334724385 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 2126872273 ps |
| CPU time | 7.66 seconds |
| Started | Oct 02 06:59:06 PM UTC 24 |
| Finished | Oct 02 06:59:15 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334724385 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2334724385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/23.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.4142133579 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 827157850 ps |
| CPU time | 6.18 seconds |
| Started | Oct 02 06:59:07 PM UTC 24 |
| Finished | Oct 02 06:59:15 PM UTC 24 |
| Peak memory | 212184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142133579 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.4142133579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.1682273048 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 15405409 ps |
| CPU time | 1.78 seconds |
| Started | Oct 02 06:59:05 PM UTC 24 |
| Finished | Oct 02 06:59:08 PM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682273048 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.1682273048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/23.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all.2188173198 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1586707149 ps |
| CPU time | 33 seconds |
| Started | Oct 02 06:59:12 PM UTC 24 |
| Finished | Oct 02 06:59:46 PM UTC 24 |
| Peak memory | 213636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188173198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2188173198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/23.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_error.433604892 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 32099517052 ps |
| CPU time | 92.23 seconds |
| Started | Oct 02 06:59:15 PM UTC 24 |
| Finished | Oct 02 07:00:49 PM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433604892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.433604892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/23.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.323389482 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 231441440 ps |
| CPU time | 31 seconds |
| Started | Oct 02 06:59:14 PM UTC 24 |
| Finished | Oct 02 06:59:46 PM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323389482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.323389482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.3140955318 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 52868418 ps |
| CPU time | 11.94 seconds |
| Started | Oct 02 06:59:15 PM UTC 24 |
| Finished | Oct 02 06:59:28 PM UTC 24 |
| Peak memory | 212204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140955318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.3140955318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_unmapped_addr.2264516853 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 409724004 ps |
| CPU time | 3.61 seconds |
| Started | Oct 02 06:59:10 PM UTC 24 |
| Finished | Oct 02 06:59:15 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264516853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2264516853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/23.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device.3680304599 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 58696545 ps |
| CPU time | 15.11 seconds |
| Started | Oct 02 06:59:21 PM UTC 24 |
| Finished | Oct 02 06:59:38 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680304599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.3680304599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/24.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.2915562887 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 6315561530 ps |
| CPU time | 48.82 seconds |
| Started | Oct 02 06:59:22 PM UTC 24 |
| Finished | Oct 02 07:00:13 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915562887 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.2915562887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.3809038151 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 255033166 ps |
| CPU time | 7.08 seconds |
| Started | Oct 02 06:59:26 PM UTC 24 |
| Finished | Oct 02 06:59:34 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809038151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.3809038151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_error_random.2328894969 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 31127924 ps |
| CPU time | 4.83 seconds |
| Started | Oct 02 06:59:24 PM UTC 24 |
| Finished | Oct 02 06:59:29 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328894969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.2328894969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/24.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random.299466925 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 569436709 ps |
| CPU time | 7.61 seconds |
| Started | Oct 02 06:59:18 PM UTC 24 |
| Finished | Oct 02 06:59:26 PM UTC 24 |
| Peak memory | 212180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299466925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.299466925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/24.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_large_delays.4255087412 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 28082063114 ps |
| CPU time | 132.04 seconds |
| Started | Oct 02 06:59:20 PM UTC 24 |
| Finished | Oct 02 07:01:34 PM UTC 24 |
| Peak memory | 212076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255087412 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.4255087412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/24.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_slow_rsp.1251811115 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 24747221592 ps |
| CPU time | 92.52 seconds |
| Started | Oct 02 06:59:20 PM UTC 24 |
| Finished | Oct 02 07:00:55 PM UTC 24 |
| Peak memory | 212252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251811115 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.1251811115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/24.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_zero_delays.16992502 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 81137375 ps |
| CPU time | 9.01 seconds |
| Started | Oct 02 06:59:18 PM UTC 24 |
| Finished | Oct 02 06:59:28 PM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16992502 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.16992502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/24.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_same_source.1655167080 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1019237789 ps |
| CPU time | 19.71 seconds |
| Started | Oct 02 06:59:22 PM UTC 24 |
| Finished | Oct 02 06:59:44 PM UTC 24 |
| Peak memory | 211996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655167080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.1655167080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/24.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke.1373799 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 403417101 ps |
| CPU time | 1.65 seconds |
| Started | Oct 02 06:59:16 PM UTC 24 |
| Finished | Oct 02 06:59:19 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_T EST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1373799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/24.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_large_delays.3063442305 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 3909518853 ps |
| CPU time | 17.04 seconds |
| Started | Oct 02 06:59:16 PM UTC 24 |
| Finished | Oct 02 06:59:35 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063442305 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3063442305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/24.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.546403148 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 1459487422 ps |
| CPU time | 17.05 seconds |
| Started | Oct 02 06:59:17 PM UTC 24 |
| Finished | Oct 02 06:59:35 PM UTC 24 |
| Peak memory | 211980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546403148 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.546403148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.3624784039 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 10190492 ps |
| CPU time | 1.87 seconds |
| Started | Oct 02 06:59:16 PM UTC 24 |
| Finished | Oct 02 06:59:19 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624784039 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.3624784039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/24.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all.2365654464 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 2781151630 ps |
| CPU time | 21.59 seconds |
| Started | Oct 02 06:59:27 PM UTC 24 |
| Finished | Oct 02 06:59:51 PM UTC 24 |
| Peak memory | 212076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365654464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2365654464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/24.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_error.174298743 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 310717880 ps |
| CPU time | 34.13 seconds |
| Started | Oct 02 06:59:27 PM UTC 24 |
| Finished | Oct 02 07:00:04 PM UTC 24 |
| Peak memory | 214124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174298743 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.174298743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/24.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.1114029952 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 242421881 ps |
| CPU time | 26.66 seconds |
| Started | Oct 02 06:59:27 PM UTC 24 |
| Finished | Oct 02 06:59:56 PM UTC 24 |
| Peak memory | 214316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114029952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.1114029952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.1325358782 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 282107850 ps |
| CPU time | 29.71 seconds |
| Started | Oct 02 06:59:28 PM UTC 24 |
| Finished | Oct 02 07:00:00 PM UTC 24 |
| Peak memory | 214056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325358782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.1325358782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_unmapped_addr.1453984349 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 185677873 ps |
| CPU time | 3.52 seconds |
| Started | Oct 02 06:59:26 PM UTC 24 |
| Finished | Oct 02 06:59:30 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453984349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1453984349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/24.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device.916816351 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 808078156 ps |
| CPU time | 13.69 seconds |
| Started | Oct 02 06:59:36 PM UTC 24 |
| Finished | Oct 02 06:59:51 PM UTC 24 |
| Peak memory | 212076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916816351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.916816351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/25.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.1311849548 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 7688375388 ps |
| CPU time | 60.02 seconds |
| Started | Oct 02 06:59:36 PM UTC 24 |
| Finished | Oct 02 07:00:38 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311849548 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.1311849548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.3589835504 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 985708780 ps |
| CPU time | 14.14 seconds |
| Started | Oct 02 06:59:39 PM UTC 24 |
| Finished | Oct 02 06:59:54 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589835504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.3589835504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_error_random.1383915679 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 58714258 ps |
| CPU time | 5.09 seconds |
| Started | Oct 02 06:59:37 PM UTC 24 |
| Finished | Oct 02 06:59:43 PM UTC 24 |
| Peak memory | 212180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383915679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.1383915679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/25.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random.1974201308 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1301476612 ps |
| CPU time | 19.44 seconds |
| Started | Oct 02 06:59:33 PM UTC 24 |
| Finished | Oct 02 06:59:54 PM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974201308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.1974201308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/25.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_large_delays.1947261513 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 1200662368 ps |
| CPU time | 11.68 seconds |
| Started | Oct 02 06:59:34 PM UTC 24 |
| Finished | Oct 02 06:59:47 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947261513 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.1947261513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/25.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_slow_rsp.2742217763 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 175706706735 ps |
| CPU time | 214.46 seconds |
| Started | Oct 02 06:59:36 PM UTC 24 |
| Finished | Oct 02 07:03:14 PM UTC 24 |
| Peak memory | 212052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742217763 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.2742217763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/25.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_zero_delays.279452568 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 39834065 ps |
| CPU time | 4.85 seconds |
| Started | Oct 02 06:59:34 PM UTC 24 |
| Finished | Oct 02 06:59:40 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279452568 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.279452568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/25.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_same_source.2022546787 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 93139067 ps |
| CPU time | 7.51 seconds |
| Started | Oct 02 06:59:37 PM UTC 24 |
| Finished | Oct 02 06:59:45 PM UTC 24 |
| Peak memory | 214264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022546787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2022546787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/25.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke.462817128 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 12540382 ps |
| CPU time | 1.66 seconds |
| Started | Oct 02 06:59:30 PM UTC 24 |
| Finished | Oct 02 06:59:32 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462817128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.462817128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/25.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_large_delays.3010922114 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 2504349227 ps |
| CPU time | 16.86 seconds |
| Started | Oct 02 06:59:32 PM UTC 24 |
| Finished | Oct 02 06:59:50 PM UTC 24 |
| Peak memory | 212264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010922114 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3010922114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/25.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.2318654425 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 3186672583 ps |
| CPU time | 6.07 seconds |
| Started | Oct 02 06:59:33 PM UTC 24 |
| Finished | Oct 02 06:59:40 PM UTC 24 |
| Peak memory | 211660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318654425 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.2318654425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.557099380 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 7580624 ps |
| CPU time | 1.6 seconds |
| Started | Oct 02 06:59:31 PM UTC 24 |
| Finished | Oct 02 06:59:33 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557099380 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.557099380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/25.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all.2692345675 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 2153260378 ps |
| CPU time | 35 seconds |
| Started | Oct 02 06:59:39 PM UTC 24 |
| Finished | Oct 02 07:00:16 PM UTC 24 |
| Peak memory | 214252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692345675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.2692345675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/25.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_error.1127176193 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 319102492 ps |
| CPU time | 17.6 seconds |
| Started | Oct 02 06:59:41 PM UTC 24 |
| Finished | Oct 02 07:00:00 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127176193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1127176193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/25.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.3196350327 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 4201366077 ps |
| CPU time | 52.01 seconds |
| Started | Oct 02 06:59:41 PM UTC 24 |
| Finished | Oct 02 07:00:35 PM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196350327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.3196350327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_unmapped_addr.816914972 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 337729050 ps |
| CPU time | 7.7 seconds |
| Started | Oct 02 06:59:38 PM UTC 24 |
| Finished | Oct 02 06:59:47 PM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816914972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.816914972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/25.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device.2408189821 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 17872228 ps |
| CPU time | 4.65 seconds |
| Started | Oct 02 06:59:48 PM UTC 24 |
| Finished | Oct 02 06:59:54 PM UTC 24 |
| Peak memory | 212268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408189821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.2408189821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/26.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.2523451303 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 49099585295 ps |
| CPU time | 84.82 seconds |
| Started | Oct 02 06:59:48 PM UTC 24 |
| Finished | Oct 02 07:01:15 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523451303 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.2523451303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.3530777118 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 426576027 ps |
| CPU time | 9.54 seconds |
| Started | Oct 02 06:59:51 PM UTC 24 |
| Finished | Oct 02 07:00:01 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530777118 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.3530777118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_error_random.350609566 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 1521918028 ps |
| CPU time | 16.49 seconds |
| Started | Oct 02 06:59:50 PM UTC 24 |
| Finished | Oct 02 07:00:07 PM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350609566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.350609566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/26.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random.721427703 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 129627022 ps |
| CPU time | 9.45 seconds |
| Started | Oct 02 06:59:45 PM UTC 24 |
| Finished | Oct 02 06:59:56 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721427703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.721427703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/26.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_slow_rsp.3640254682 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 26677542771 ps |
| CPU time | 204.37 seconds |
| Started | Oct 02 06:59:48 PM UTC 24 |
| Finished | Oct 02 07:03:16 PM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640254682 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.3640254682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/26.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_zero_delays.1702618358 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 87890866 ps |
| CPU time | 11.24 seconds |
| Started | Oct 02 06:59:45 PM UTC 24 |
| Finished | Oct 02 06:59:58 PM UTC 24 |
| Peak memory | 212264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702618358 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.1702618358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/26.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_same_source.1662263694 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 1054048208 ps |
| CPU time | 9.13 seconds |
| Started | Oct 02 06:59:48 PM UTC 24 |
| Finished | Oct 02 06:59:59 PM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662263694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.1662263694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/26.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke.3549837742 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 10750235 ps |
| CPU time | 1.85 seconds |
| Started | Oct 02 06:59:41 PM UTC 24 |
| Finished | Oct 02 06:59:44 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549837742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.3549837742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/26.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_large_delays.3173954938 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 4469309963 ps |
| CPU time | 9.3 seconds |
| Started | Oct 02 06:59:44 PM UTC 24 |
| Finished | Oct 02 06:59:55 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173954938 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3173954938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/26.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.1428364828 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 1474104963 ps |
| CPU time | 5.86 seconds |
| Started | Oct 02 06:59:45 PM UTC 24 |
| Finished | Oct 02 06:59:52 PM UTC 24 |
| Peak memory | 211988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428364828 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1428364828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.4149430901 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 22335524 ps |
| CPU time | 1.74 seconds |
| Started | Oct 02 06:59:42 PM UTC 24 |
| Finished | Oct 02 06:59:45 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149430901 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.4149430901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/26.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all.2764870640 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 9099160426 ps |
| CPU time | 97.67 seconds |
| Started | Oct 02 06:59:52 PM UTC 24 |
| Finished | Oct 02 07:01:32 PM UTC 24 |
| Peak memory | 216240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764870640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2764870640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/26.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1249668654 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 5444180227 ps |
| CPU time | 33.71 seconds |
| Started | Oct 02 06:59:53 PM UTC 24 |
| Finished | Oct 02 07:00:28 PM UTC 24 |
| Peak memory | 212264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249668654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1249668654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/26.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.3662647008 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 722367048 ps |
| CPU time | 118 seconds |
| Started | Oct 02 06:59:52 PM UTC 24 |
| Finished | Oct 02 07:01:52 PM UTC 24 |
| Peak memory | 214060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662647008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.3662647008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.3410460770 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 1553780292 ps |
| CPU time | 34.33 seconds |
| Started | Oct 02 06:59:55 PM UTC 24 |
| Finished | Oct 02 07:00:30 PM UTC 24 |
| Peak memory | 214056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410460770 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.3410460770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_unmapped_addr.3816757270 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 622078914 ps |
| CPU time | 9.82 seconds |
| Started | Oct 02 06:59:50 PM UTC 24 |
| Finished | Oct 02 07:00:00 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816757270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.3816757270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/26.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device.1576289521 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 1761199790 ps |
| CPU time | 8.5 seconds |
| Started | Oct 02 06:59:59 PM UTC 24 |
| Finished | Oct 02 07:00:09 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576289521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.1576289521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/27.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.1497093072 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 106146646598 ps |
| CPU time | 177.79 seconds |
| Started | Oct 02 06:59:59 PM UTC 24 |
| Finished | Oct 02 07:03:00 PM UTC 24 |
| Peak memory | 214124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497093072 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.1497093072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.2511296183 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 40156293 ps |
| CPU time | 2.76 seconds |
| Started | Oct 02 07:00:01 PM UTC 24 |
| Finished | Oct 02 07:00:18 PM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511296183 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.2511296183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_error_random.1848170231 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 232106728 ps |
| CPU time | 1.72 seconds |
| Started | Oct 02 07:00:01 PM UTC 24 |
| Finished | Oct 02 07:00:17 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848170231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.1848170231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/27.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random.3906995404 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 270961840 ps |
| CPU time | 7.37 seconds |
| Started | Oct 02 06:59:56 PM UTC 24 |
| Finished | Oct 02 07:00:05 PM UTC 24 |
| Peak memory | 211980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906995404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.3906995404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/27.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_large_delays.1698234880 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 111620530464 ps |
| CPU time | 178.99 seconds |
| Started | Oct 02 06:59:58 PM UTC 24 |
| Finished | Oct 02 07:03:00 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698234880 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1698234880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/27.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_slow_rsp.1653117188 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 7033489194 ps |
| CPU time | 70.05 seconds |
| Started | Oct 02 06:59:58 PM UTC 24 |
| Finished | Oct 02 07:01:10 PM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653117188 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.1653117188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/27.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_zero_delays.4138121090 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 131669297 ps |
| CPU time | 5.35 seconds |
| Started | Oct 02 06:59:58 PM UTC 24 |
| Finished | Oct 02 07:00:04 PM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138121090 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.4138121090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/27.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_same_source.1663929484 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 790812274 ps |
| CPU time | 11.21 seconds |
| Started | Oct 02 06:59:59 PM UTC 24 |
| Finished | Oct 02 07:00:12 PM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663929484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1663929484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/27.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke.358629218 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 33776363 ps |
| CPU time | 1.51 seconds |
| Started | Oct 02 06:59:55 PM UTC 24 |
| Finished | Oct 02 06:59:57 PM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358629218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.358629218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/27.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_large_delays.2425470632 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 1970328468 ps |
| CPU time | 8.03 seconds |
| Started | Oct 02 06:59:56 PM UTC 24 |
| Finished | Oct 02 07:00:05 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425470632 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2425470632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/27.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.2055493400 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 1469099130 ps |
| CPU time | 11.3 seconds |
| Started | Oct 02 06:59:56 PM UTC 24 |
| Finished | Oct 02 07:00:09 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055493400 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.2055493400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.199430947 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 17222770 ps |
| CPU time | 2 seconds |
| Started | Oct 02 06:59:56 PM UTC 24 |
| Finished | Oct 02 06:59:59 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199430947 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.199430947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/27.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all.1675515512 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 30788303 ps |
| CPU time | 1.38 seconds |
| Started | Oct 02 07:00:02 PM UTC 24 |
| Finished | Oct 02 07:00:17 PM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675515512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.1675515512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/27.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_error.96637414 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 92533285 ps |
| CPU time | 9.91 seconds |
| Started | Oct 02 07:00:17 PM UTC 24 |
| Finished | Oct 02 07:00:28 PM UTC 24 |
| Peak memory | 212016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96637414 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.96637414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/27.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.3291942932 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 455104854 ps |
| CPU time | 75.75 seconds |
| Started | Oct 02 07:00:17 PM UTC 24 |
| Finished | Oct 02 07:01:35 PM UTC 24 |
| Peak memory | 216104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291942932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.3291942932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.1171186424 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 2579172903 ps |
| CPU time | 87.21 seconds |
| Started | Oct 02 07:00:17 PM UTC 24 |
| Finished | Oct 02 07:01:46 PM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171186424 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.1171186424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_unmapped_addr.484651538 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 63343695 ps |
| CPU time | 3.75 seconds |
| Started | Oct 02 07:00:01 PM UTC 24 |
| Finished | Oct 02 07:00:19 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484651538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.484651538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/27.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device.2570594003 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 315316621 ps |
| CPU time | 8.2 seconds |
| Started | Oct 02 07:00:17 PM UTC 24 |
| Finished | Oct 02 07:00:27 PM UTC 24 |
| Peak memory | 212204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570594003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.2570594003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/28.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2168160981 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 13727819048 ps |
| CPU time | 61.5 seconds |
| Started | Oct 02 07:00:17 PM UTC 24 |
| Finished | Oct 02 07:01:21 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168160981 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.2168160981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.3904536342 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 84966480 ps |
| CPU time | 4.22 seconds |
| Started | Oct 02 07:00:19 PM UTC 24 |
| Finished | Oct 02 07:00:24 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904536342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.3904536342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_error_random.958502718 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 40487741 ps |
| CPU time | 5.79 seconds |
| Started | Oct 02 07:00:17 PM UTC 24 |
| Finished | Oct 02 07:00:24 PM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958502718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.958502718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/28.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random.3529367533 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 113300301 ps |
| CPU time | 6.29 seconds |
| Started | Oct 02 07:00:17 PM UTC 24 |
| Finished | Oct 02 07:00:25 PM UTC 24 |
| Peak memory | 211904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529367533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.3529367533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/28.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_large_delays.2794324580 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 235840941783 ps |
| CPU time | 207.03 seconds |
| Started | Oct 02 07:00:17 PM UTC 24 |
| Finished | Oct 02 07:03:48 PM UTC 24 |
| Peak memory | 212140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794324580 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2794324580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/28.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_slow_rsp.614772 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 20323040010 ps |
| CPU time | 69.63 seconds |
| Started | Oct 02 07:00:17 PM UTC 24 |
| Finished | Oct 02 07:01:29 PM UTC 24 |
| Peak memory | 212260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614772 -assert nopostproc +UVM_TESTNAME=xbar_base_test + UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-si m-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.614772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/28.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_zero_delays.1686537049 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 100987272 ps |
| CPU time | 2.73 seconds |
| Started | Oct 02 07:00:17 PM UTC 24 |
| Finished | Oct 02 07:00:21 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686537049 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.1686537049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/28.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_same_source.3908367314 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 28899450 ps |
| CPU time | 3.37 seconds |
| Started | Oct 02 07:00:17 PM UTC 24 |
| Finished | Oct 02 07:00:22 PM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908367314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3908367314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/28.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke.3251133238 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 45537005 ps |
| CPU time | 1.62 seconds |
| Started | Oct 02 07:00:17 PM UTC 24 |
| Finished | Oct 02 07:00:20 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251133238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.3251133238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/28.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_large_delays.2760010019 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3944752489 ps |
| CPU time | 20.29 seconds |
| Started | Oct 02 07:00:17 PM UTC 24 |
| Finished | Oct 02 07:00:39 PM UTC 24 |
| Peak memory | 212064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760010019 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2760010019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/28.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.1763112330 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 873140397 ps |
| CPU time | 9.46 seconds |
| Started | Oct 02 07:00:17 PM UTC 24 |
| Finished | Oct 02 07:00:28 PM UTC 24 |
| Peak memory | 211988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763112330 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.1763112330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.3802994661 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 32021665 ps |
| CPU time | 1.71 seconds |
| Started | Oct 02 07:00:17 PM UTC 24 |
| Finished | Oct 02 07:00:20 PM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802994661 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.3802994661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/28.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all.3853016893 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 270064909 ps |
| CPU time | 34.33 seconds |
| Started | Oct 02 07:00:19 PM UTC 24 |
| Finished | Oct 02 07:00:55 PM UTC 24 |
| Peak memory | 214056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853016893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.3853016893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/28.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_error.3099451003 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 3181475246 ps |
| CPU time | 25.38 seconds |
| Started | Oct 02 07:00:19 PM UTC 24 |
| Finished | Oct 02 07:00:46 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099451003 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.3099451003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/28.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.1701164428 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 437445111 ps |
| CPU time | 65.19 seconds |
| Started | Oct 02 07:00:19 PM UTC 24 |
| Finished | Oct 02 07:01:26 PM UTC 24 |
| Peak memory | 214252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701164428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.1701164428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.412359647 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 803609466 ps |
| CPU time | 80.66 seconds |
| Started | Oct 02 07:00:21 PM UTC 24 |
| Finished | Oct 02 07:01:43 PM UTC 24 |
| Peak memory | 216108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412359647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.412359647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_unmapped_addr.3547291180 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 483108324 ps |
| CPU time | 7.93 seconds |
| Started | Oct 02 07:00:18 PM UTC 24 |
| Finished | Oct 02 07:00:27 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547291180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3547291180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/28.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device.3046129082 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 104615853 ps |
| CPU time | 12.13 seconds |
| Started | Oct 02 07:00:26 PM UTC 24 |
| Finished | Oct 02 07:00:39 PM UTC 24 |
| Peak memory | 212204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046129082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.3046129082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/29.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1943633595 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 38954202573 ps |
| CPU time | 349.4 seconds |
| Started | Oct 02 07:00:28 PM UTC 24 |
| Finished | Oct 02 07:06:22 PM UTC 24 |
| Peak memory | 218004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943633595 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.1943633595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.1647379858 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 400638798 ps |
| CPU time | 8.85 seconds |
| Started | Oct 02 07:00:29 PM UTC 24 |
| Finished | Oct 02 07:00:39 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647379858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.1647379858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_error_random.138280942 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 20385407 ps |
| CPU time | 2.09 seconds |
| Started | Oct 02 07:00:28 PM UTC 24 |
| Finished | Oct 02 07:00:31 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138280942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.138280942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/29.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random.1189061757 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 784231392 ps |
| CPU time | 13.34 seconds |
| Started | Oct 02 07:00:24 PM UTC 24 |
| Finished | Oct 02 07:00:39 PM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189061757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.1189061757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/29.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_large_delays.3057446381 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 52308632371 ps |
| CPU time | 149.64 seconds |
| Started | Oct 02 07:00:26 PM UTC 24 |
| Finished | Oct 02 07:02:58 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057446381 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.3057446381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/29.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1816141907 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 14010820952 ps |
| CPU time | 103.46 seconds |
| Started | Oct 02 07:00:26 PM UTC 24 |
| Finished | Oct 02 07:02:11 PM UTC 24 |
| Peak memory | 212060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816141907 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1816141907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/29.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_zero_delays.2602993392 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 214532198 ps |
| CPU time | 5.33 seconds |
| Started | Oct 02 07:00:24 PM UTC 24 |
| Finished | Oct 02 07:00:31 PM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602993392 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.2602993392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/29.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_same_source.1767232069 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 38582396 ps |
| CPU time | 5 seconds |
| Started | Oct 02 07:00:28 PM UTC 24 |
| Finished | Oct 02 07:00:34 PM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767232069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1767232069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/29.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke.2638679902 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 66062734 ps |
| CPU time | 1.88 seconds |
| Started | Oct 02 07:00:21 PM UTC 24 |
| Finished | Oct 02 07:00:24 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638679902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2638679902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/29.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_large_delays.1411552230 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 9569929770 ps |
| CPU time | 26 seconds |
| Started | Oct 02 07:00:22 PM UTC 24 |
| Finished | Oct 02 07:00:49 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411552230 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1411552230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/29.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.4234302128 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 3114332812 ps |
| CPU time | 9.66 seconds |
| Started | Oct 02 07:00:23 PM UTC 24 |
| Finished | Oct 02 07:00:34 PM UTC 24 |
| Peak memory | 212248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234302128 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.4234302128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.670771989 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 9266308 ps |
| CPU time | 1.37 seconds |
| Started | Oct 02 07:00:21 PM UTC 24 |
| Finished | Oct 02 07:00:23 PM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670771989 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.670771989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/29.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all.175844870 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 693125196 ps |
| CPU time | 24.57 seconds |
| Started | Oct 02 07:00:29 PM UTC 24 |
| Finished | Oct 02 07:00:55 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175844870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.175844870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/29.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_error.3237271812 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 4358573274 ps |
| CPU time | 88.22 seconds |
| Started | Oct 02 07:00:32 PM UTC 24 |
| Finished | Oct 02 07:02:02 PM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237271812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3237271812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/29.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.1186254618 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 1293999926 ps |
| CPU time | 179.41 seconds |
| Started | Oct 02 07:00:32 PM UTC 24 |
| Finished | Oct 02 07:03:34 PM UTC 24 |
| Peak memory | 216004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186254618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.1186254618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.1480592915 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 9629977177 ps |
| CPU time | 45.83 seconds |
| Started | Oct 02 07:00:32 PM UTC 24 |
| Finished | Oct 02 07:01:19 PM UTC 24 |
| Peak memory | 214012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480592915 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.1480592915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_unmapped_addr.645610833 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 46649608 ps |
| CPU time | 6.18 seconds |
| Started | Oct 02 07:00:29 PM UTC 24 |
| Finished | Oct 02 07:00:36 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645610833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.645610833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/29.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.474263782 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 26634101943 ps |
| CPU time | 216.11 seconds |
| Started | Oct 02 06:54:05 PM UTC 24 |
| Finished | Oct 02 06:57:45 PM UTC 24 |
| Peak memory | 214116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474263782 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.474263782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.3976896421 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 199439807 ps |
| CPU time | 3.71 seconds |
| Started | Oct 02 06:54:08 PM UTC 24 |
| Finished | Oct 02 06:54:13 PM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976896421 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.3976896421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_error_random.1061103662 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 71171081 ps |
| CPU time | 6.27 seconds |
| Started | Oct 02 06:54:05 PM UTC 24 |
| Finished | Oct 02 06:54:13 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061103662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.1061103662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/3.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random.548384691 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1135001175 ps |
| CPU time | 17.57 seconds |
| Started | Oct 02 06:53:58 PM UTC 24 |
| Finished | Oct 02 06:54:17 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548384691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.548384691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/3.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_large_delays.1693646086 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 10007422743 ps |
| CPU time | 17.78 seconds |
| Started | Oct 02 06:54:00 PM UTC 24 |
| Finished | Oct 02 06:54:19 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693646086 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1693646086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/3.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_slow_rsp.573382423 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 21702327404 ps |
| CPU time | 114.5 seconds |
| Started | Oct 02 06:54:04 PM UTC 24 |
| Finished | Oct 02 06:56:01 PM UTC 24 |
| Peak memory | 212048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573382423 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.573382423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/3.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_zero_delays.2076960035 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 30068459 ps |
| CPU time | 3.91 seconds |
| Started | Oct 02 06:54:00 PM UTC 24 |
| Finished | Oct 02 06:54:05 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076960035 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.2076960035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/3.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_same_source.1043716124 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 236650287 ps |
| CPU time | 2.32 seconds |
| Started | Oct 02 06:54:05 PM UTC 24 |
| Finished | Oct 02 06:54:09 PM UTC 24 |
| Peak memory | 212036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043716124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1043716124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/3.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke.2678547695 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 40842741 ps |
| CPU time | 2.1 seconds |
| Started | Oct 02 06:53:52 PM UTC 24 |
| Finished | Oct 02 06:53:55 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678547695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2678547695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/3.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_large_delays.3636259840 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 1402235617 ps |
| CPU time | 10.46 seconds |
| Started | Oct 02 06:53:56 PM UTC 24 |
| Finished | Oct 02 06:54:08 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636259840 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3636259840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/3.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1171342903 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 2182017127 ps |
| CPU time | 13.85 seconds |
| Started | Oct 02 06:53:56 PM UTC 24 |
| Finished | Oct 02 06:54:11 PM UTC 24 |
| Peak memory | 212044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171342903 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1171342903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.3882795535 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10560471 ps |
| CPU time | 1.76 seconds |
| Started | Oct 02 06:53:53 PM UTC 24 |
| Finished | Oct 02 06:53:56 PM UTC 24 |
| Peak memory | 210932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882795535 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.3882795535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/3.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_error.1184631189 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 13835438295 ps |
| CPU time | 119.79 seconds |
| Started | Oct 02 06:54:11 PM UTC 24 |
| Finished | Oct 02 06:56:13 PM UTC 24 |
| Peak memory | 214312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184631189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.1184631189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/3.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.2971084283 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 3512174154 ps |
| CPU time | 111.91 seconds |
| Started | Oct 02 06:54:10 PM UTC 24 |
| Finished | Oct 02 06:56:04 PM UTC 24 |
| Peak memory | 214124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971084283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.2971084283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.2486788474 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 524153104 ps |
| CPU time | 112.04 seconds |
| Started | Oct 02 06:54:12 PM UTC 24 |
| Finished | Oct 02 06:56:06 PM UTC 24 |
| Peak memory | 216300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486788474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.2486788474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_unmapped_addr.924172463 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 428135904 ps |
| CPU time | 11.08 seconds |
| Started | Oct 02 06:54:08 PM UTC 24 |
| Finished | Oct 02 06:54:21 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924172463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.924172463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/3.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device.3413490334 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 1027067095 ps |
| CPU time | 12.2 seconds |
| Started | Oct 02 07:00:40 PM UTC 24 |
| Finished | Oct 02 07:00:53 PM UTC 24 |
| Peak memory | 212204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413490334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.3413490334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/30.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.2535073427 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 20300589646 ps |
| CPU time | 159.29 seconds |
| Started | Oct 02 07:00:40 PM UTC 24 |
| Finished | Oct 02 07:03:22 PM UTC 24 |
| Peak memory | 214076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535073427 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.2535073427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.4283157179 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 9673298 ps |
| CPU time | 1.47 seconds |
| Started | Oct 02 07:00:43 PM UTC 24 |
| Finished | Oct 02 07:00:45 PM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283157179 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.4283157179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_error_random.526459636 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 1096911317 ps |
| CPU time | 13.44 seconds |
| Started | Oct 02 07:00:41 PM UTC 24 |
| Finished | Oct 02 07:00:56 PM UTC 24 |
| Peak memory | 211980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526459636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.526459636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/30.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random.595654466 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 68106817 ps |
| CPU time | 10.38 seconds |
| Started | Oct 02 07:00:40 PM UTC 24 |
| Finished | Oct 02 07:00:51 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595654466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.595654466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/30.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.669356913 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 5586487500 ps |
| CPU time | 21.58 seconds |
| Started | Oct 02 07:00:40 PM UTC 24 |
| Finished | Oct 02 07:01:03 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669356913 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.669356913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/30.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1277960608 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 2459691502 ps |
| CPU time | 25.51 seconds |
| Started | Oct 02 07:00:40 PM UTC 24 |
| Finished | Oct 02 07:01:07 PM UTC 24 |
| Peak memory | 212248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277960608 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1277960608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/30.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_zero_delays.391148217 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 100867130 ps |
| CPU time | 5.87 seconds |
| Started | Oct 02 07:00:40 PM UTC 24 |
| Finished | Oct 02 07:00:47 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391148217 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.391148217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/30.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_same_source.4056415045 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 10873195 ps |
| CPU time | 2.12 seconds |
| Started | Oct 02 07:00:40 PM UTC 24 |
| Finished | Oct 02 07:00:43 PM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056415045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.4056415045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/30.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke.2526968438 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 95060111 ps |
| CPU time | 2.5 seconds |
| Started | Oct 02 07:00:35 PM UTC 24 |
| Finished | Oct 02 07:00:39 PM UTC 24 |
| Peak memory | 212180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526968438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2526968438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/30.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_large_delays.1693193026 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 5347408706 ps |
| CPU time | 12.78 seconds |
| Started | Oct 02 07:00:36 PM UTC 24 |
| Finished | Oct 02 07:00:50 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693193026 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1693193026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/30.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2265626288 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 6280118807 ps |
| CPU time | 22.79 seconds |
| Started | Oct 02 07:00:37 PM UTC 24 |
| Finished | Oct 02 07:01:02 PM UTC 24 |
| Peak memory | 212248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265626288 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2265626288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.4191898497 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 16590485 ps |
| CPU time | 1.72 seconds |
| Started | Oct 02 07:00:35 PM UTC 24 |
| Finished | Oct 02 07:00:38 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191898497 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.4191898497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/30.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all.970526759 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 636277822 ps |
| CPU time | 25.11 seconds |
| Started | Oct 02 07:00:44 PM UTC 24 |
| Finished | Oct 02 07:01:11 PM UTC 24 |
| Peak memory | 214184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970526759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.970526759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/30.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_error.3118234200 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 1230674820 ps |
| CPU time | 14.87 seconds |
| Started | Oct 02 07:00:46 PM UTC 24 |
| Finished | Oct 02 07:01:02 PM UTC 24 |
| Peak memory | 214056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118234200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3118234200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/30.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2534240296 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 680679057 ps |
| CPU time | 46.37 seconds |
| Started | Oct 02 07:00:46 PM UTC 24 |
| Finished | Oct 02 07:01:34 PM UTC 24 |
| Peak memory | 214056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534240296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.2534240296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.1044167790 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 15301024 ps |
| CPU time | 6.88 seconds |
| Started | Oct 02 07:00:48 PM UTC 24 |
| Finished | Oct 02 07:00:56 PM UTC 24 |
| Peak memory | 214056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044167790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.1044167790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_unmapped_addr.3962373349 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 476321956 ps |
| CPU time | 8.27 seconds |
| Started | Oct 02 07:00:43 PM UTC 24 |
| Finished | Oct 02 07:00:52 PM UTC 24 |
| Peak memory | 212264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962373349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.3962373349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/30.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device.1937389461 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 1233894449 ps |
| CPU time | 7.8 seconds |
| Started | Oct 02 07:00:53 PM UTC 24 |
| Finished | Oct 02 07:01:02 PM UTC 24 |
| Peak memory | 212204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937389461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.1937389461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/31.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.3178014443 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 106532747 ps |
| CPU time | 2.24 seconds |
| Started | Oct 02 07:00:56 PM UTC 24 |
| Finished | Oct 02 07:00:59 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178014443 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.3178014443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_error_random.3803088366 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 1196958792 ps |
| CPU time | 7.13 seconds |
| Started | Oct 02 07:00:54 PM UTC 24 |
| Finished | Oct 02 07:01:02 PM UTC 24 |
| Peak memory | 212244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803088366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3803088366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/31.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random.1528356040 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 90995155 ps |
| CPU time | 2.77 seconds |
| Started | Oct 02 07:00:51 PM UTC 24 |
| Finished | Oct 02 07:00:55 PM UTC 24 |
| Peak memory | 211980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528356040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.1528356040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/31.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_large_delays.2604450821 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 46305103037 ps |
| CPU time | 76.42 seconds |
| Started | Oct 02 07:00:52 PM UTC 24 |
| Finished | Oct 02 07:02:10 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604450821 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.2604450821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/31.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_slow_rsp.2454203124 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 13795278586 ps |
| CPU time | 94.02 seconds |
| Started | Oct 02 07:00:52 PM UTC 24 |
| Finished | Oct 02 07:02:28 PM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454203124 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.2454203124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/31.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_zero_delays.2230749261 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 16703528 ps |
| CPU time | 3.02 seconds |
| Started | Oct 02 07:00:52 PM UTC 24 |
| Finished | Oct 02 07:00:56 PM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230749261 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.2230749261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/31.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_same_source.1159171651 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 62283587 ps |
| CPU time | 5.1 seconds |
| Started | Oct 02 07:00:53 PM UTC 24 |
| Finished | Oct 02 07:00:59 PM UTC 24 |
| Peak memory | 214024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159171651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1159171651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/31.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke.2371010322 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 53172036 ps |
| CPU time | 2.18 seconds |
| Started | Oct 02 07:00:48 PM UTC 24 |
| Finished | Oct 02 07:00:51 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371010322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2371010322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/31.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_large_delays.869024179 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 1767357074 ps |
| CPU time | 11.89 seconds |
| Started | Oct 02 07:00:50 PM UTC 24 |
| Finished | Oct 02 07:01:03 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869024179 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.869024179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/31.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.2019078592 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 4191347823 ps |
| CPU time | 10.49 seconds |
| Started | Oct 02 07:00:50 PM UTC 24 |
| Finished | Oct 02 07:01:02 PM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019078592 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2019078592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.4199841545 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 16652309 ps |
| CPU time | 1.76 seconds |
| Started | Oct 02 07:00:48 PM UTC 24 |
| Finished | Oct 02 07:00:51 PM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199841545 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.4199841545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/31.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all.3638624328 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 4123756509 ps |
| CPU time | 61.27 seconds |
| Started | Oct 02 07:00:56 PM UTC 24 |
| Finished | Oct 02 07:01:59 PM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638624328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3638624328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/31.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_error.759448522 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 9639782782 ps |
| CPU time | 106.3 seconds |
| Started | Oct 02 07:00:57 PM UTC 24 |
| Finished | Oct 02 07:02:46 PM UTC 24 |
| Peak memory | 213972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759448522 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.759448522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/31.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.3906505365 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 9093092780 ps |
| CPU time | 143.32 seconds |
| Started | Oct 02 07:00:56 PM UTC 24 |
| Finished | Oct 02 07:03:22 PM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906505365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.3906505365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.2915053407 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 69775361 ps |
| CPU time | 9.1 seconds |
| Started | Oct 02 07:00:57 PM UTC 24 |
| Finished | Oct 02 07:01:07 PM UTC 24 |
| Peak memory | 213836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915053407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.2915053407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_unmapped_addr.1466041864 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 1325896872 ps |
| CPU time | 9.33 seconds |
| Started | Oct 02 07:00:56 PM UTC 24 |
| Finished | Oct 02 07:01:06 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466041864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1466041864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/31.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device.977959361 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 1032716592 ps |
| CPU time | 18.55 seconds |
| Started | Oct 02 07:01:03 PM UTC 24 |
| Finished | Oct 02 07:01:22 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977959361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.977959361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/32.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.2313638585 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 33873367468 ps |
| CPU time | 253.96 seconds |
| Started | Oct 02 07:01:05 PM UTC 24 |
| Finished | Oct 02 07:05:23 PM UTC 24 |
| Peak memory | 214312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313638585 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.2313638585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.903382330 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 41524959 ps |
| CPU time | 5.77 seconds |
| Started | Oct 02 07:01:07 PM UTC 24 |
| Finished | Oct 02 07:01:14 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903382330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.903382330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_error_random.2308613090 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 1793414342 ps |
| CPU time | 9.43 seconds |
| Started | Oct 02 07:01:05 PM UTC 24 |
| Finished | Oct 02 07:01:15 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308613090 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2308613090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/32.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random.4209289333 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 890695384 ps |
| CPU time | 14.19 seconds |
| Started | Oct 02 07:01:02 PM UTC 24 |
| Finished | Oct 02 07:01:18 PM UTC 24 |
| Peak memory | 211980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209289333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.4209289333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/32.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.2534808 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 3557954032 ps |
| CPU time | 13.21 seconds |
| Started | Oct 02 07:01:02 PM UTC 24 |
| Finished | Oct 02 07:01:17 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534808 -assert nopostproc +UVM_TESTNAME=xbar_base_t est +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.2534808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/32.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.461497743 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 1717637929 ps |
| CPU time | 18.48 seconds |
| Started | Oct 02 07:01:03 PM UTC 24 |
| Finished | Oct 02 07:01:22 PM UTC 24 |
| Peak memory | 211988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461497743 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.461497743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/32.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_zero_delays.2693851952 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 121987795 ps |
| CPU time | 9.41 seconds |
| Started | Oct 02 07:01:02 PM UTC 24 |
| Finished | Oct 02 07:01:13 PM UTC 24 |
| Peak memory | 211824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693851952 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.2693851952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/32.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_same_source.3573669194 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 122836124 ps |
| CPU time | 7.33 seconds |
| Started | Oct 02 07:01:05 PM UTC 24 |
| Finished | Oct 02 07:01:13 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573669194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3573669194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/32.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke.430846259 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 238063851 ps |
| CPU time | 2.72 seconds |
| Started | Oct 02 07:00:57 PM UTC 24 |
| Finished | Oct 02 07:01:01 PM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430846259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.430846259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/32.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_large_delays.2795597959 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 8032650939 ps |
| CPU time | 17.7 seconds |
| Started | Oct 02 07:01:00 PM UTC 24 |
| Finished | Oct 02 07:01:20 PM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795597959 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2795597959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/32.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.1913015156 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 8747606554 ps |
| CPU time | 17.71 seconds |
| Started | Oct 02 07:01:00 PM UTC 24 |
| Finished | Oct 02 07:01:20 PM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913015156 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.1913015156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.2339834689 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 12035139 ps |
| CPU time | 1.59 seconds |
| Started | Oct 02 07:00:59 PM UTC 24 |
| Finished | Oct 02 07:01:01 PM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339834689 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.2339834689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/32.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all.2946161252 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 1497359071 ps |
| CPU time | 34.09 seconds |
| Started | Oct 02 07:01:08 PM UTC 24 |
| Finished | Oct 02 07:01:44 PM UTC 24 |
| Peak memory | 214252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946161252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2946161252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/32.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_error.260813540 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 72218483 ps |
| CPU time | 9.06 seconds |
| Started | Oct 02 07:01:11 PM UTC 24 |
| Finished | Oct 02 07:01:21 PM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260813540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.260813540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/32.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2919211948 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 227477709 ps |
| CPU time | 50.81 seconds |
| Started | Oct 02 07:01:08 PM UTC 24 |
| Finished | Oct 02 07:02:01 PM UTC 24 |
| Peak memory | 214112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919211948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.2919211948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.210857646 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 13969985803 ps |
| CPU time | 106.59 seconds |
| Started | Oct 02 07:01:12 PM UTC 24 |
| Finished | Oct 02 07:03:01 PM UTC 24 |
| Peak memory | 216144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210857646 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.210857646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_unmapped_addr.1627949724 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 713173990 ps |
| CPU time | 11.59 seconds |
| Started | Oct 02 07:01:05 PM UTC 24 |
| Finished | Oct 02 07:01:18 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627949724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1627949724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/32.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device.3284690373 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 380632524 ps |
| CPU time | 9.52 seconds |
| Started | Oct 02 07:01:19 PM UTC 24 |
| Finished | Oct 02 07:01:29 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284690373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.3284690373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/33.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2680105031 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 112962079981 ps |
| CPU time | 302.28 seconds |
| Started | Oct 02 07:01:19 PM UTC 24 |
| Finished | Oct 02 07:06:25 PM UTC 24 |
| Peak memory | 219792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680105031 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.2680105031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.2694550913 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 71695433 ps |
| CPU time | 4.6 seconds |
| Started | Oct 02 07:01:22 PM UTC 24 |
| Finished | Oct 02 07:01:27 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694550913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.2694550913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_error_random.3038942 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 841847876 ps |
| CPU time | 15.59 seconds |
| Started | Oct 02 07:01:20 PM UTC 24 |
| Finished | Oct 02 07:01:37 PM UTC 24 |
| Peak memory | 211988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3038942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/33.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random.3575792579 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 439782661 ps |
| CPU time | 9.85 seconds |
| Started | Oct 02 07:01:16 PM UTC 24 |
| Finished | Oct 02 07:01:27 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575792579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.3575792579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/33.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_large_delays.4079814277 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 7881578599 ps |
| CPU time | 32.71 seconds |
| Started | Oct 02 07:01:18 PM UTC 24 |
| Finished | Oct 02 07:01:53 PM UTC 24 |
| Peak memory | 212076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079814277 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.4079814277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/33.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_slow_rsp.137074896 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 3836234467 ps |
| CPU time | 10.23 seconds |
| Started | Oct 02 07:01:19 PM UTC 24 |
| Finished | Oct 02 07:01:30 PM UTC 24 |
| Peak memory | 212244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137074896 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.137074896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/33.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_zero_delays.3792478697 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 60163304 ps |
| CPU time | 9.89 seconds |
| Started | Oct 02 07:01:17 PM UTC 24 |
| Finished | Oct 02 07:01:28 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792478697 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.3792478697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/33.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_same_source.1807276675 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 3691155002 ps |
| CPU time | 16.83 seconds |
| Started | Oct 02 07:01:20 PM UTC 24 |
| Finished | Oct 02 07:01:38 PM UTC 24 |
| Peak memory | 214084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807276675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.1807276675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/33.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke.1501551168 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 46823566 ps |
| CPU time | 1.95 seconds |
| Started | Oct 02 07:01:14 PM UTC 24 |
| Finished | Oct 02 07:01:17 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501551168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1501551168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/33.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_large_delays.2220179105 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 3431871838 ps |
| CPU time | 18.97 seconds |
| Started | Oct 02 07:01:16 PM UTC 24 |
| Finished | Oct 02 07:01:36 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220179105 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2220179105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/33.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.3685344421 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 827803179 ps |
| CPU time | 6.3 seconds |
| Started | Oct 02 07:01:16 PM UTC 24 |
| Finished | Oct 02 07:01:23 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685344421 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.3685344421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.466733729 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 16967844 ps |
| CPU time | 1.93 seconds |
| Started | Oct 02 07:01:14 PM UTC 24 |
| Finished | Oct 02 07:01:17 PM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466733729 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.466733729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/33.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all.3415463959 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 220976009 ps |
| CPU time | 32.69 seconds |
| Started | Oct 02 07:01:22 PM UTC 24 |
| Finished | Oct 02 07:01:56 PM UTC 24 |
| Peak memory | 214056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415463959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3415463959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/33.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_error.2988163885 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 29473820129 ps |
| CPU time | 72.4 seconds |
| Started | Oct 02 07:01:23 PM UTC 24 |
| Finished | Oct 02 07:02:38 PM UTC 24 |
| Peak memory | 214312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988163885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.2988163885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/33.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.2887041077 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 295054445 ps |
| CPU time | 54.55 seconds |
| Started | Oct 02 07:01:22 PM UTC 24 |
| Finished | Oct 02 07:02:18 PM UTC 24 |
| Peak memory | 216104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887041077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.2887041077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.207448329 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 108799334 ps |
| CPU time | 19.13 seconds |
| Started | Oct 02 07:01:23 PM UTC 24 |
| Finished | Oct 02 07:01:44 PM UTC 24 |
| Peak memory | 212204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207448329 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.207448329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_unmapped_addr.1249169253 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 158264705 ps |
| CPU time | 7.26 seconds |
| Started | Oct 02 07:01:22 PM UTC 24 |
| Finished | Oct 02 07:01:30 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249169253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.1249169253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/33.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device.2167837530 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 334988496 ps |
| CPU time | 7.9 seconds |
| Started | Oct 02 07:01:30 PM UTC 24 |
| Finished | Oct 02 07:01:39 PM UTC 24 |
| Peak memory | 212204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167837530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.2167837530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/34.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.286787811 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 806160854 ps |
| CPU time | 13.63 seconds |
| Started | Oct 02 07:01:32 PM UTC 24 |
| Finished | Oct 02 07:01:47 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286787811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.286787811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_error_random.1184715340 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 936444191 ps |
| CPU time | 18.1 seconds |
| Started | Oct 02 07:01:32 PM UTC 24 |
| Finished | Oct 02 07:01:51 PM UTC 24 |
| Peak memory | 212180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184715340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1184715340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/34.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random.3496860190 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 194990092 ps |
| CPU time | 6.03 seconds |
| Started | Oct 02 07:01:28 PM UTC 24 |
| Finished | Oct 02 07:01:35 PM UTC 24 |
| Peak memory | 212240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496860190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.3496860190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/34.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.2647783657 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 6195756119 ps |
| CPU time | 22.74 seconds |
| Started | Oct 02 07:01:30 PM UTC 24 |
| Finished | Oct 02 07:01:54 PM UTC 24 |
| Peak memory | 212268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647783657 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.2647783657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/34.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_slow_rsp.2527584350 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 16753743178 ps |
| CPU time | 132.72 seconds |
| Started | Oct 02 07:01:30 PM UTC 24 |
| Finished | Oct 02 07:03:45 PM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527584350 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2527584350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/34.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_zero_delays.4064601593 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 56329436 ps |
| CPU time | 7.43 seconds |
| Started | Oct 02 07:01:30 PM UTC 24 |
| Finished | Oct 02 07:01:38 PM UTC 24 |
| Peak memory | 212260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064601593 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.4064601593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/34.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_same_source.2870214424 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2131398268 ps |
| CPU time | 11.14 seconds |
| Started | Oct 02 07:01:32 PM UTC 24 |
| Finished | Oct 02 07:01:44 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870214424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.2870214424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/34.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke.722534105 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 142675513 ps |
| CPU time | 2.07 seconds |
| Started | Oct 02 07:01:25 PM UTC 24 |
| Finished | Oct 02 07:01:28 PM UTC 24 |
| Peak memory | 212260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722534105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.722534105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/34.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_large_delays.3144160522 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3891924098 ps |
| CPU time | 11 seconds |
| Started | Oct 02 07:01:26 PM UTC 24 |
| Finished | Oct 02 07:01:39 PM UTC 24 |
| Peak memory | 212328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144160522 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.3144160522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/34.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.4136512421 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 5318349047 ps |
| CPU time | 8.53 seconds |
| Started | Oct 02 07:01:27 PM UTC 24 |
| Finished | Oct 02 07:01:37 PM UTC 24 |
| Peak memory | 212052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136512421 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.4136512421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.3180491093 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 39856631 ps |
| CPU time | 1.53 seconds |
| Started | Oct 02 07:01:25 PM UTC 24 |
| Finished | Oct 02 07:01:27 PM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180491093 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.3180491093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/34.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all.1404858627 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 59746619 ps |
| CPU time | 10.21 seconds |
| Started | Oct 02 07:01:33 PM UTC 24 |
| Finished | Oct 02 07:01:45 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404858627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1404858627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/34.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_error.1602194128 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 496641221 ps |
| CPU time | 10.62 seconds |
| Started | Oct 02 07:01:37 PM UTC 24 |
| Finished | Oct 02 07:01:49 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602194128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1602194128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/34.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.1941175933 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 504608647 ps |
| CPU time | 20.06 seconds |
| Started | Oct 02 07:01:37 PM UTC 24 |
| Finished | Oct 02 07:01:58 PM UTC 24 |
| Peak memory | 214056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941175933 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.1941175933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_unmapped_addr.318656612 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 43047782 ps |
| CPU time | 3.95 seconds |
| Started | Oct 02 07:01:32 PM UTC 24 |
| Finished | Oct 02 07:01:37 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318656612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.318656612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/34.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device.1026682011 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 10270860 ps |
| CPU time | 2.03 seconds |
| Started | Oct 02 07:01:41 PM UTC 24 |
| Finished | Oct 02 07:01:44 PM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026682011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.1026682011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/35.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.3490658382 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 48603707893 ps |
| CPU time | 361.26 seconds |
| Started | Oct 02 07:01:41 PM UTC 24 |
| Finished | Oct 02 07:07:47 PM UTC 24 |
| Peak memory | 217788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490658382 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.3490658382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.588753247 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 325068365 ps |
| CPU time | 9.29 seconds |
| Started | Oct 02 07:01:45 PM UTC 24 |
| Finished | Oct 02 07:01:56 PM UTC 24 |
| Peak memory | 212204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588753247 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.588753247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_error_random.3473382754 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 1036478534 ps |
| CPU time | 14.27 seconds |
| Started | Oct 02 07:01:45 PM UTC 24 |
| Finished | Oct 02 07:02:01 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473382754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3473382754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/35.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random.3024011894 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 176618239 ps |
| CPU time | 3.34 seconds |
| Started | Oct 02 07:01:38 PM UTC 24 |
| Finished | Oct 02 07:01:43 PM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024011894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.3024011894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/35.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.806980441 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 39857123142 ps |
| CPU time | 168.46 seconds |
| Started | Oct 02 07:01:41 PM UTC 24 |
| Finished | Oct 02 07:04:32 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806980441 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.806980441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/35.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.4210926327 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 13833698128 ps |
| CPU time | 88.71 seconds |
| Started | Oct 02 07:01:41 PM UTC 24 |
| Finished | Oct 02 07:03:11 PM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210926327 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.4210926327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/35.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_zero_delays.3357993691 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 81236369 ps |
| CPU time | 6.78 seconds |
| Started | Oct 02 07:01:41 PM UTC 24 |
| Finished | Oct 02 07:01:49 PM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357993691 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.3357993691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/35.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_same_source.3086836112 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 24971486 ps |
| CPU time | 3.74 seconds |
| Started | Oct 02 07:01:41 PM UTC 24 |
| Finished | Oct 02 07:01:46 PM UTC 24 |
| Peak memory | 211960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086836112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3086836112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/35.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke.1235096078 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 14223271 ps |
| CPU time | 1.56 seconds |
| Started | Oct 02 07:01:37 PM UTC 24 |
| Finished | Oct 02 07:01:39 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235096078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1235096078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/35.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_large_delays.134808983 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 2417942152 ps |
| CPU time | 12.12 seconds |
| Started | Oct 02 07:01:38 PM UTC 24 |
| Finished | Oct 02 07:01:52 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134808983 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.134808983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/35.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.3949618027 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 1882402454 ps |
| CPU time | 13.88 seconds |
| Started | Oct 02 07:01:38 PM UTC 24 |
| Finished | Oct 02 07:01:53 PM UTC 24 |
| Peak memory | 211988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949618027 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.3949618027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.2081035880 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 11740426 ps |
| CPU time | 1.32 seconds |
| Started | Oct 02 07:01:37 PM UTC 24 |
| Finished | Oct 02 07:01:39 PM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081035880 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.2081035880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/35.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all.4054209046 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 207211520 ps |
| CPU time | 17.75 seconds |
| Started | Oct 02 07:01:46 PM UTC 24 |
| Finished | Oct 02 07:02:04 PM UTC 24 |
| Peak memory | 214056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054209046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.4054209046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/35.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_error.2892230425 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 475575259 ps |
| CPU time | 27.78 seconds |
| Started | Oct 02 07:01:46 PM UTC 24 |
| Finished | Oct 02 07:02:15 PM UTC 24 |
| Peak memory | 214056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892230425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.2892230425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/35.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.3366492829 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 1393428256 ps |
| CPU time | 97.54 seconds |
| Started | Oct 02 07:01:46 PM UTC 24 |
| Finished | Oct 02 07:03:25 PM UTC 24 |
| Peak memory | 216108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366492829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.3366492829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.1032942345 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 120672551 ps |
| CPU time | 49.8 seconds |
| Started | Oct 02 07:01:46 PM UTC 24 |
| Finished | Oct 02 07:02:37 PM UTC 24 |
| Peak memory | 214044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032942345 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.1032942345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_unmapped_addr.2420451838 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 1024894776 ps |
| CPU time | 11.33 seconds |
| Started | Oct 02 07:01:45 PM UTC 24 |
| Finished | Oct 02 07:01:58 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420451838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.2420451838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/35.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device.1212773827 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 863831770 ps |
| CPU time | 15.61 seconds |
| Started | Oct 02 07:01:52 PM UTC 24 |
| Finished | Oct 02 07:02:09 PM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212773827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.1212773827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/36.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.2682117132 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 55144493339 ps |
| CPU time | 225.06 seconds |
| Started | Oct 02 07:01:52 PM UTC 24 |
| Finished | Oct 02 07:05:40 PM UTC 24 |
| Peak memory | 214112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682117132 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.2682117132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.1188767953 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 41018501 ps |
| CPU time | 3.2 seconds |
| Started | Oct 02 07:01:54 PM UTC 24 |
| Finished | Oct 02 07:01:58 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188767953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.1188767953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_error_random.2779524109 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 1120999844 ps |
| CPU time | 12.51 seconds |
| Started | Oct 02 07:01:54 PM UTC 24 |
| Finished | Oct 02 07:02:08 PM UTC 24 |
| Peak memory | 211988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779524109 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2779524109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/36.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random.100256301 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 505095640 ps |
| CPU time | 5.6 seconds |
| Started | Oct 02 07:01:50 PM UTC 24 |
| Finished | Oct 02 07:01:57 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100256301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.100256301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/36.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.3549204104 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 80041773894 ps |
| CPU time | 79.02 seconds |
| Started | Oct 02 07:01:50 PM UTC 24 |
| Finished | Oct 02 07:03:11 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549204104 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3549204104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/36.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.947434647 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 30038736368 ps |
| CPU time | 177.52 seconds |
| Started | Oct 02 07:01:50 PM UTC 24 |
| Finished | Oct 02 07:04:51 PM UTC 24 |
| Peak memory | 212048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947434647 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.947434647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/36.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_zero_delays.3161517200 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 30407122 ps |
| CPU time | 2.24 seconds |
| Started | Oct 02 07:01:50 PM UTC 24 |
| Finished | Oct 02 07:01:54 PM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161517200 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.3161517200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/36.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_same_source.3973247101 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 362041264 ps |
| CPU time | 7.81 seconds |
| Started | Oct 02 07:01:52 PM UTC 24 |
| Finished | Oct 02 07:02:01 PM UTC 24 |
| Peak memory | 211996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973247101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3973247101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/36.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke.2364628238 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 10811182 ps |
| CPU time | 1.8 seconds |
| Started | Oct 02 07:01:48 PM UTC 24 |
| Finished | Oct 02 07:01:50 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364628238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.2364628238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/36.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_large_delays.2536220345 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 3085607751 ps |
| CPU time | 6.44 seconds |
| Started | Oct 02 07:01:48 PM UTC 24 |
| Finished | Oct 02 07:01:55 PM UTC 24 |
| Peak memory | 212264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536220345 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2536220345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/36.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.1156526167 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 1189344727 ps |
| CPU time | 8.02 seconds |
| Started | Oct 02 07:01:50 PM UTC 24 |
| Finished | Oct 02 07:01:59 PM UTC 24 |
| Peak memory | 211992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156526167 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.1156526167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.2616589307 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 15982953 ps |
| CPU time | 1.83 seconds |
| Started | Oct 02 07:01:48 PM UTC 24 |
| Finished | Oct 02 07:01:50 PM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616589307 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.2616589307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/36.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all.193998287 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 90151831 ps |
| CPU time | 9.7 seconds |
| Started | Oct 02 07:01:54 PM UTC 24 |
| Finished | Oct 02 07:02:05 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193998287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.193998287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/36.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_error.1812693135 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 3138230565 ps |
| CPU time | 54.09 seconds |
| Started | Oct 02 07:01:54 PM UTC 24 |
| Finished | Oct 02 07:02:50 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812693135 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1812693135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/36.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2356647099 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 486234857 ps |
| CPU time | 49.74 seconds |
| Started | Oct 02 07:01:54 PM UTC 24 |
| Finished | Oct 02 07:02:46 PM UTC 24 |
| Peak memory | 216104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356647099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.2356647099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.1089627007 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 417360237 ps |
| CPU time | 34.71 seconds |
| Started | Oct 02 07:01:56 PM UTC 24 |
| Finished | Oct 02 07:02:32 PM UTC 24 |
| Peak memory | 214060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089627007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.1089627007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_unmapped_addr.2143236236 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 473876831 ps |
| CPU time | 12.35 seconds |
| Started | Oct 02 07:01:54 PM UTC 24 |
| Finished | Oct 02 07:02:08 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143236236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2143236236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/36.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device.1297588141 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 31114919 ps |
| CPU time | 6.29 seconds |
| Started | Oct 02 07:02:00 PM UTC 24 |
| Finished | Oct 02 07:02:07 PM UTC 24 |
| Peak memory | 211960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297588141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.1297588141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/37.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3924215669 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 190981754731 ps |
| CPU time | 288.4 seconds |
| Started | Oct 02 07:02:00 PM UTC 24 |
| Finished | Oct 02 07:06:52 PM UTC 24 |
| Peak memory | 214264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924215669 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.3924215669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.1137166734 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 665082496 ps |
| CPU time | 7.69 seconds |
| Started | Oct 02 07:02:02 PM UTC 24 |
| Finished | Oct 02 07:02:11 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137166734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.1137166734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_error_random.909633369 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 417184080 ps |
| CPU time | 8.01 seconds |
| Started | Oct 02 07:02:02 PM UTC 24 |
| Finished | Oct 02 07:02:11 PM UTC 24 |
| Peak memory | 211980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909633369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.909633369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/37.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random.3930478169 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 32169255 ps |
| CPU time | 4.11 seconds |
| Started | Oct 02 07:01:58 PM UTC 24 |
| Finished | Oct 02 07:02:03 PM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930478169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.3930478169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/37.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.1131589033 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 15984432044 ps |
| CPU time | 82.35 seconds |
| Started | Oct 02 07:02:00 PM UTC 24 |
| Finished | Oct 02 07:03:24 PM UTC 24 |
| Peak memory | 212140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131589033 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.1131589033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/37.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.1438542745 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 643836604 ps |
| CPU time | 6.95 seconds |
| Started | Oct 02 07:02:00 PM UTC 24 |
| Finished | Oct 02 07:02:08 PM UTC 24 |
| Peak memory | 211992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438542745 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1438542745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/37.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_zero_delays.1431075523 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 209501578 ps |
| CPU time | 8.88 seconds |
| Started | Oct 02 07:02:00 PM UTC 24 |
| Finished | Oct 02 07:02:10 PM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431075523 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.1431075523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/37.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_same_source.2318237241 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 58509595 ps |
| CPU time | 5.59 seconds |
| Started | Oct 02 07:02:00 PM UTC 24 |
| Finished | Oct 02 07:02:07 PM UTC 24 |
| Peak memory | 211996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318237241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2318237241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/37.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke.2168463556 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 51104359 ps |
| CPU time | 2.34 seconds |
| Started | Oct 02 07:01:56 PM UTC 24 |
| Finished | Oct 02 07:01:59 PM UTC 24 |
| Peak memory | 211988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168463556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2168463556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/37.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_large_delays.156858988 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 15496191679 ps |
| CPU time | 13.41 seconds |
| Started | Oct 02 07:01:58 PM UTC 24 |
| Finished | Oct 02 07:02:12 PM UTC 24 |
| Peak memory | 212264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156858988 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.156858988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/37.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.445160599 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 698056014 ps |
| CPU time | 9.75 seconds |
| Started | Oct 02 07:01:58 PM UTC 24 |
| Finished | Oct 02 07:02:09 PM UTC 24 |
| Peak memory | 212180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445160599 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.445160599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3324771769 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 13276122 ps |
| CPU time | 1.86 seconds |
| Started | Oct 02 07:01:58 PM UTC 24 |
| Finished | Oct 02 07:02:01 PM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324771769 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.3324771769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/37.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.3980516471 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 1951192211 ps |
| CPU time | 42.19 seconds |
| Started | Oct 02 07:02:02 PM UTC 24 |
| Finished | Oct 02 07:02:46 PM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980516471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3980516471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/37.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_error.1989163861 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 2890748584 ps |
| CPU time | 46.75 seconds |
| Started | Oct 02 07:02:05 PM UTC 24 |
| Finished | Oct 02 07:02:53 PM UTC 24 |
| Peak memory | 213912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989163861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1989163861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/37.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.3741331955 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 783049950 ps |
| CPU time | 147.95 seconds |
| Started | Oct 02 07:02:04 PM UTC 24 |
| Finished | Oct 02 07:04:35 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741331955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.3741331955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3036071763 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 46007433 ps |
| CPU time | 2.82 seconds |
| Started | Oct 02 07:02:06 PM UTC 24 |
| Finished | Oct 02 07:02:10 PM UTC 24 |
| Peak memory | 214252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036071763 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.3036071763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_unmapped_addr.3311339714 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 418245890 ps |
| CPU time | 10.05 seconds |
| Started | Oct 02 07:02:02 PM UTC 24 |
| Finished | Oct 02 07:02:13 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311339714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.3311339714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/37.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device.3972049018 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 55936629 ps |
| CPU time | 14.31 seconds |
| Started | Oct 02 07:02:12 PM UTC 24 |
| Finished | Oct 02 07:02:27 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972049018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.3972049018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/38.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.720216884 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 102192583087 ps |
| CPU time | 410.61 seconds |
| Started | Oct 02 07:02:12 PM UTC 24 |
| Finished | Oct 02 07:09:08 PM UTC 24 |
| Peak memory | 217804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720216884 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.720216884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.1418313598 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 523497589 ps |
| CPU time | 15.67 seconds |
| Started | Oct 02 07:02:12 PM UTC 24 |
| Finished | Oct 02 07:02:29 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418313598 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.1418313598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_error_random.3656280577 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 1917398069 ps |
| CPU time | 13.55 seconds |
| Started | Oct 02 07:02:12 PM UTC 24 |
| Finished | Oct 02 07:02:27 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656280577 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.3656280577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/38.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random.3200308539 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 397804220 ps |
| CPU time | 6.41 seconds |
| Started | Oct 02 07:02:09 PM UTC 24 |
| Finished | Oct 02 07:02:17 PM UTC 24 |
| Peak memory | 211980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200308539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.3200308539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/38.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.3093484633 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 40794502415 ps |
| CPU time | 158.38 seconds |
| Started | Oct 02 07:02:10 PM UTC 24 |
| Finished | Oct 02 07:04:50 PM UTC 24 |
| Peak memory | 212268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093484633 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.3093484633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/38.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.1439017143 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 7540286617 ps |
| CPU time | 69.12 seconds |
| Started | Oct 02 07:02:10 PM UTC 24 |
| Finished | Oct 02 07:03:20 PM UTC 24 |
| Peak memory | 212052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439017143 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.1439017143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/38.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_zero_delays.1668314144 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 35209890 ps |
| CPU time | 6.72 seconds |
| Started | Oct 02 07:02:10 PM UTC 24 |
| Finished | Oct 02 07:02:17 PM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668314144 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.1668314144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/38.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_same_source.1435259960 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 1389099303 ps |
| CPU time | 18.1 seconds |
| Started | Oct 02 07:02:12 PM UTC 24 |
| Finished | Oct 02 07:02:31 PM UTC 24 |
| Peak memory | 211996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435259960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1435259960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/38.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke.2072888462 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 75625962 ps |
| CPU time | 2.46 seconds |
| Started | Oct 02 07:02:06 PM UTC 24 |
| Finished | Oct 02 07:02:10 PM UTC 24 |
| Peak memory | 212244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072888462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2072888462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/38.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_large_delays.3528324006 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 2087338202 ps |
| CPU time | 11.08 seconds |
| Started | Oct 02 07:02:08 PM UTC 24 |
| Finished | Oct 02 07:02:20 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528324006 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.3528324006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/38.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.2267411738 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 1943492773 ps |
| CPU time | 23.73 seconds |
| Started | Oct 02 07:02:09 PM UTC 24 |
| Finished | Oct 02 07:02:34 PM UTC 24 |
| Peak memory | 211992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267411738 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2267411738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.2216362411 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 9915088 ps |
| CPU time | 1.52 seconds |
| Started | Oct 02 07:02:06 PM UTC 24 |
| Finished | Oct 02 07:02:09 PM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216362411 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.2216362411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/38.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.4184011696 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 521517637 ps |
| CPU time | 7.46 seconds |
| Started | Oct 02 07:02:12 PM UTC 24 |
| Finished | Oct 02 07:02:21 PM UTC 24 |
| Peak memory | 211996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184011696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.4184011696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/38.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.1770453013 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 6995709 ps |
| CPU time | 1.21 seconds |
| Started | Oct 02 07:02:14 PM UTC 24 |
| Finished | Oct 02 07:02:16 PM UTC 24 |
| Peak memory | 202224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770453013 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1770453013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/38.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2562215734 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 1523435834 ps |
| CPU time | 152.15 seconds |
| Started | Oct 02 07:02:14 PM UTC 24 |
| Finished | Oct 02 07:04:49 PM UTC 24 |
| Peak memory | 216104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562215734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.2562215734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.2820544932 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 547988346 ps |
| CPU time | 51.02 seconds |
| Started | Oct 02 07:02:14 PM UTC 24 |
| Finished | Oct 02 07:03:07 PM UTC 24 |
| Peak memory | 216300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820544932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.2820544932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_unmapped_addr.1787199279 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 38113624 ps |
| CPU time | 5.25 seconds |
| Started | Oct 02 07:02:12 PM UTC 24 |
| Finished | Oct 02 07:02:18 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787199279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1787199279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/38.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device.3186479581 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 1410517962 ps |
| CPU time | 18.83 seconds |
| Started | Oct 02 07:02:20 PM UTC 24 |
| Finished | Oct 02 07:02:40 PM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186479581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.3186479581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/39.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1653181034 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 15274994829 ps |
| CPU time | 171.78 seconds |
| Started | Oct 02 07:02:21 PM UTC 24 |
| Finished | Oct 02 07:05:15 PM UTC 24 |
| Peak memory | 214124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653181034 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.1653181034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.183988706 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 533249318 ps |
| CPU time | 10.51 seconds |
| Started | Oct 02 07:02:26 PM UTC 24 |
| Finished | Oct 02 07:02:38 PM UTC 24 |
| Peak memory | 212204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183988706 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.183988706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_error_random.93376845 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 1631639682 ps |
| CPU time | 14.43 seconds |
| Started | Oct 02 07:02:22 PM UTC 24 |
| Finished | Oct 02 07:02:38 PM UTC 24 |
| Peak memory | 211992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93376845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.93376845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/39.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random.1304981987 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 115832302 ps |
| CPU time | 9.74 seconds |
| Started | Oct 02 07:02:18 PM UTC 24 |
| Finished | Oct 02 07:02:29 PM UTC 24 |
| Peak memory | 211988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304981987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.1304981987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/39.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.3819409227 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 8456355905 ps |
| CPU time | 29.15 seconds |
| Started | Oct 02 07:02:20 PM UTC 24 |
| Finished | Oct 02 07:02:51 PM UTC 24 |
| Peak memory | 212076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819409227 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.3819409227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/39.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.617535342 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 15824858821 ps |
| CPU time | 78.93 seconds |
| Started | Oct 02 07:02:20 PM UTC 24 |
| Finished | Oct 02 07:03:41 PM UTC 24 |
| Peak memory | 212052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617535342 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.617535342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/39.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_zero_delays.1628330498 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 67934105 ps |
| CPU time | 3.74 seconds |
| Started | Oct 02 07:02:20 PM UTC 24 |
| Finished | Oct 02 07:02:25 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628330498 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.1628330498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/39.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_same_source.2766996139 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 26400025 ps |
| CPU time | 4.15 seconds |
| Started | Oct 02 07:02:22 PM UTC 24 |
| Finished | Oct 02 07:02:27 PM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766996139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.2766996139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/39.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke.269213571 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 205779015 ps |
| CPU time | 2.68 seconds |
| Started | Oct 02 07:02:14 PM UTC 24 |
| Finished | Oct 02 07:02:18 PM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269213571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.269213571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/39.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_large_delays.628099718 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 3214767426 ps |
| CPU time | 14.64 seconds |
| Started | Oct 02 07:02:16 PM UTC 24 |
| Finished | Oct 02 07:02:32 PM UTC 24 |
| Peak memory | 212264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628099718 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.628099718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/39.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.532726500 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 935351655 ps |
| CPU time | 5.82 seconds |
| Started | Oct 02 07:02:18 PM UTC 24 |
| Finished | Oct 02 07:02:25 PM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532726500 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.532726500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2922671618 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 10257374 ps |
| CPU time | 1.25 seconds |
| Started | Oct 02 07:02:16 PM UTC 24 |
| Finished | Oct 02 07:02:18 PM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922671618 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.2922671618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/39.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.2081404417 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 414281326 ps |
| CPU time | 27.33 seconds |
| Started | Oct 02 07:02:26 PM UTC 24 |
| Finished | Oct 02 07:02:55 PM UTC 24 |
| Peak memory | 214316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081404417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.2081404417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/39.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.21207629 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 1542157788 ps |
| CPU time | 39.53 seconds |
| Started | Oct 02 07:02:29 PM UTC 24 |
| Finished | Oct 02 07:03:10 PM UTC 24 |
| Peak memory | 213928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21207629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.21207629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/39.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.1153782639 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 16109167158 ps |
| CPU time | 95.56 seconds |
| Started | Oct 02 07:02:29 PM UTC 24 |
| Finished | Oct 02 07:04:07 PM UTC 24 |
| Peak memory | 216364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153782639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.1153782639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.4217334226 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 3759040813 ps |
| CPU time | 125.69 seconds |
| Started | Oct 02 07:02:29 PM UTC 24 |
| Finished | Oct 02 07:04:37 PM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217334226 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.4217334226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_unmapped_addr.2966036331 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 24324849 ps |
| CPU time | 3.96 seconds |
| Started | Oct 02 07:02:24 PM UTC 24 |
| Finished | Oct 02 07:02:29 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966036331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.2966036331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/39.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device.3839410402 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 53827017 ps |
| CPU time | 10.38 seconds |
| Started | Oct 02 06:54:20 PM UTC 24 |
| Finished | Oct 02 06:54:31 PM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839410402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.3839410402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/4.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.1227793270 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 34855693468 ps |
| CPU time | 280.96 seconds |
| Started | Oct 02 06:54:20 PM UTC 24 |
| Finished | Oct 02 06:59:05 PM UTC 24 |
| Peak memory | 214116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227793270 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.1227793270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.155817623 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 146174992 ps |
| CPU time | 10.07 seconds |
| Started | Oct 02 06:54:22 PM UTC 24 |
| Finished | Oct 02 06:54:34 PM UTC 24 |
| Peak memory | 212272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155817623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.155817623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_error_random.3312661533 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 29497539 ps |
| CPU time | 4.44 seconds |
| Started | Oct 02 06:54:21 PM UTC 24 |
| Finished | Oct 02 06:54:27 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312661533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3312661533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/4.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random.3307972770 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 8721503 ps |
| CPU time | 1.86 seconds |
| Started | Oct 02 06:54:18 PM UTC 24 |
| Finished | Oct 02 06:54:20 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307972770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.3307972770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/4.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_large_delays.3625785534 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 27440963764 ps |
| CPU time | 115.57 seconds |
| Started | Oct 02 06:54:19 PM UTC 24 |
| Finished | Oct 02 06:56:16 PM UTC 24 |
| Peak memory | 212264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625785534 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.3625785534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/4.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_slow_rsp.3198382418 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 10296356567 ps |
| CPU time | 77.08 seconds |
| Started | Oct 02 06:54:19 PM UTC 24 |
| Finished | Oct 02 06:55:38 PM UTC 24 |
| Peak memory | 212060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198382418 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3198382418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/4.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_zero_delays.2045156005 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 68478737 ps |
| CPU time | 3.41 seconds |
| Started | Oct 02 06:54:18 PM UTC 24 |
| Finished | Oct 02 06:54:22 PM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045156005 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.2045156005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/4.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_same_source.1471430324 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 66168908 ps |
| CPU time | 5.27 seconds |
| Started | Oct 02 06:54:20 PM UTC 24 |
| Finished | Oct 02 06:54:26 PM UTC 24 |
| Peak memory | 211996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471430324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1471430324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/4.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke.891563423 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 57469110 ps |
| CPU time | 2.33 seconds |
| Started | Oct 02 06:54:14 PM UTC 24 |
| Finished | Oct 02 06:54:17 PM UTC 24 |
| Peak memory | 211608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891563423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.891563423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/4.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_large_delays.1560908273 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 3829631196 ps |
| CPU time | 16.58 seconds |
| Started | Oct 02 06:54:16 PM UTC 24 |
| Finished | Oct 02 06:54:34 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560908273 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1560908273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/4.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.2886618621 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 3257149303 ps |
| CPU time | 10.51 seconds |
| Started | Oct 02 06:54:16 PM UTC 24 |
| Finished | Oct 02 06:54:28 PM UTC 24 |
| Peak memory | 212048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886618621 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2886618621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.4162306664 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 11278814 ps |
| CPU time | 1.6 seconds |
| Started | Oct 02 06:54:14 PM UTC 24 |
| Finished | Oct 02 06:54:17 PM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162306664 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.4162306664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/4.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all.3358208913 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 20710602745 ps |
| CPU time | 111.79 seconds |
| Started | Oct 02 06:54:25 PM UTC 24 |
| Finished | Oct 02 06:56:19 PM UTC 24 |
| Peak memory | 216152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358208913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.3358208913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/4.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_error.34378074 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 10326999500 ps |
| CPU time | 57.44 seconds |
| Started | Oct 02 06:54:27 PM UTC 24 |
| Finished | Oct 02 06:55:26 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34378074 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.34378074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/4.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.3434109376 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 6870133319 ps |
| CPU time | 162.7 seconds |
| Started | Oct 02 06:54:28 PM UTC 24 |
| Finished | Oct 02 06:57:14 PM UTC 24 |
| Peak memory | 216148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434109376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.3434109376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_unmapped_addr.3164655739 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 135286763 ps |
| CPU time | 11.71 seconds |
| Started | Oct 02 06:54:21 PM UTC 24 |
| Finished | Oct 02 06:54:34 PM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164655739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3164655739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/4.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device.649585699 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 464334624 ps |
| CPU time | 12.44 seconds |
| Started | Oct 02 07:02:35 PM UTC 24 |
| Finished | Oct 02 07:02:48 PM UTC 24 |
| Peak memory | 212204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649585699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.649585699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/40.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.2356024514 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 22087333695 ps |
| CPU time | 168.52 seconds |
| Started | Oct 02 07:02:36 PM UTC 24 |
| Finished | Oct 02 07:05:27 PM UTC 24 |
| Peak memory | 214124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356024514 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.2356024514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.3040422879 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 351846870 ps |
| CPU time | 6.93 seconds |
| Started | Oct 02 07:02:39 PM UTC 24 |
| Finished | Oct 02 07:02:47 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040422879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.3040422879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_error_random.456153536 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 467267385 ps |
| CPU time | 7.21 seconds |
| Started | Oct 02 07:02:39 PM UTC 24 |
| Finished | Oct 02 07:02:47 PM UTC 24 |
| Peak memory | 211980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456153536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.456153536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/40.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random.3590871151 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 794132248 ps |
| CPU time | 5.4 seconds |
| Started | Oct 02 07:02:33 PM UTC 24 |
| Finished | Oct 02 07:02:39 PM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590871151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.3590871151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/40.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.2080901614 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 35637993651 ps |
| CPU time | 36.27 seconds |
| Started | Oct 02 07:02:33 PM UTC 24 |
| Finished | Oct 02 07:03:10 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080901614 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.2080901614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/40.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.54997619 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 6350869070 ps |
| CPU time | 61.84 seconds |
| Started | Oct 02 07:02:35 PM UTC 24 |
| Finished | Oct 02 07:03:38 PM UTC 24 |
| Peak memory | 212048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54997619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.54997619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/40.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_zero_delays.3440332199 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 184820942 ps |
| CPU time | 9.66 seconds |
| Started | Oct 02 07:02:33 PM UTC 24 |
| Finished | Oct 02 07:02:44 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440332199 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.3440332199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/40.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_same_source.846725607 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 908213636 ps |
| CPU time | 14.84 seconds |
| Started | Oct 02 07:02:39 PM UTC 24 |
| Finished | Oct 02 07:02:55 PM UTC 24 |
| Peak memory | 211992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846725607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.846725607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/40.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke.1631697084 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 8911347 ps |
| CPU time | 1.65 seconds |
| Started | Oct 02 07:02:29 PM UTC 24 |
| Finished | Oct 02 07:02:32 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631697084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.1631697084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/40.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_large_delays.942296222 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 2126230285 ps |
| CPU time | 9.97 seconds |
| Started | Oct 02 07:02:31 PM UTC 24 |
| Finished | Oct 02 07:02:42 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942296222 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.942296222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/40.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.3353073134 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 1353461203 ps |
| CPU time | 12.93 seconds |
| Started | Oct 02 07:02:31 PM UTC 24 |
| Finished | Oct 02 07:02:45 PM UTC 24 |
| Peak memory | 212184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353073134 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.3353073134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.3859133722 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 11110793 ps |
| CPU time | 1.93 seconds |
| Started | Oct 02 07:02:31 PM UTC 24 |
| Finished | Oct 02 07:02:34 PM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859133722 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.3859133722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/40.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.2379281986 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 10023346645 ps |
| CPU time | 69.18 seconds |
| Started | Oct 02 07:02:40 PM UTC 24 |
| Finished | Oct 02 07:03:51 PM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379281986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.2379281986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/40.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.3616073180 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 231650166 ps |
| CPU time | 29.45 seconds |
| Started | Oct 02 07:02:43 PM UTC 24 |
| Finished | Oct 02 07:03:14 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616073180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3616073180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/40.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.4168874143 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 1643514615 ps |
| CPU time | 131.66 seconds |
| Started | Oct 02 07:02:42 PM UTC 24 |
| Finished | Oct 02 07:04:56 PM UTC 24 |
| Peak memory | 216232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168874143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.4168874143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_unmapped_addr.4066310566 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 361561786 ps |
| CPU time | 9.22 seconds |
| Started | Oct 02 07:02:39 PM UTC 24 |
| Finished | Oct 02 07:02:49 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066310566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.4066310566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/40.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device.3804882018 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 14584906 ps |
| CPU time | 2.86 seconds |
| Started | Oct 02 07:02:50 PM UTC 24 |
| Finished | Oct 02 07:02:54 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804882018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.3804882018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/41.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.624674441 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 15794674396 ps |
| CPU time | 78.75 seconds |
| Started | Oct 02 07:02:53 PM UTC 24 |
| Finished | Oct 02 07:04:13 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624674441 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.624674441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.343423600 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 575508732 ps |
| CPU time | 3.09 seconds |
| Started | Oct 02 07:02:53 PM UTC 24 |
| Finished | Oct 02 07:02:57 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343423600 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.343423600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_error_random.335348986 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 235116651 ps |
| CPU time | 6.28 seconds |
| Started | Oct 02 07:02:53 PM UTC 24 |
| Finished | Oct 02 07:03:00 PM UTC 24 |
| Peak memory | 211980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335348986 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.335348986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/41.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random.136879020 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 13856246 ps |
| CPU time | 2.05 seconds |
| Started | Oct 02 07:02:48 PM UTC 24 |
| Finished | Oct 02 07:02:51 PM UTC 24 |
| Peak memory | 212244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136879020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.136879020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/41.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.3714867270 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 39106327271 ps |
| CPU time | 70.7 seconds |
| Started | Oct 02 07:02:50 PM UTC 24 |
| Finished | Oct 02 07:04:03 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714867270 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.3714867270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/41.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.2432431656 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 25261950338 ps |
| CPU time | 163.07 seconds |
| Started | Oct 02 07:02:50 PM UTC 24 |
| Finished | Oct 02 07:05:36 PM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432431656 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.2432431656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/41.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_zero_delays.309823268 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 21908880 ps |
| CPU time | 2.43 seconds |
| Started | Oct 02 07:02:48 PM UTC 24 |
| Finished | Oct 02 07:02:52 PM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309823268 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.309823268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/41.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_same_source.3192050000 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 13705066 ps |
| CPU time | 1.36 seconds |
| Started | Oct 02 07:02:53 PM UTC 24 |
| Finished | Oct 02 07:02:55 PM UTC 24 |
| Peak memory | 210932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192050000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.3192050000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/41.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke.3037297416 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 47959473 ps |
| CPU time | 1.98 seconds |
| Started | Oct 02 07:02:46 PM UTC 24 |
| Finished | Oct 02 07:02:49 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037297416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3037297416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/41.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_large_delays.2287368880 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 2428825477 ps |
| CPU time | 13.09 seconds |
| Started | Oct 02 07:02:48 PM UTC 24 |
| Finished | Oct 02 07:03:02 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287368880 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2287368880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/41.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.1819665907 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 2199075983 ps |
| CPU time | 9.85 seconds |
| Started | Oct 02 07:02:48 PM UTC 24 |
| Finished | Oct 02 07:02:59 PM UTC 24 |
| Peak memory | 212052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819665907 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.1819665907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.406208618 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 9334952 ps |
| CPU time | 1.86 seconds |
| Started | Oct 02 07:02:48 PM UTC 24 |
| Finished | Oct 02 07:02:51 PM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406208618 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.406208618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/41.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.1185978099 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 790891122 ps |
| CPU time | 18.65 seconds |
| Started | Oct 02 07:02:54 PM UTC 24 |
| Finished | Oct 02 07:03:14 PM UTC 24 |
| Peak memory | 212188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185978099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1185978099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/41.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.3455218236 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 8396296491 ps |
| CPU time | 108.81 seconds |
| Started | Oct 02 07:02:56 PM UTC 24 |
| Finished | Oct 02 07:04:47 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455218236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3455218236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/41.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.2264355213 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 422068904 ps |
| CPU time | 45.8 seconds |
| Started | Oct 02 07:02:54 PM UTC 24 |
| Finished | Oct 02 07:03:42 PM UTC 24 |
| Peak memory | 214056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264355213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.2264355213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.3316332069 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 756374841 ps |
| CPU time | 97.02 seconds |
| Started | Oct 02 07:02:56 PM UTC 24 |
| Finished | Oct 02 07:04:36 PM UTC 24 |
| Peak memory | 216108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316332069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.3316332069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_unmapped_addr.3811144972 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 66760582 ps |
| CPU time | 5.47 seconds |
| Started | Oct 02 07:02:53 PM UTC 24 |
| Finished | Oct 02 07:02:59 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811144972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3811144972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/41.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device.2724556193 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 970096783 ps |
| CPU time | 25.94 seconds |
| Started | Oct 02 07:03:02 PM UTC 24 |
| Finished | Oct 02 07:03:29 PM UTC 24 |
| Peak memory | 212080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724556193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.2724556193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/42.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.759499934 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 23801836320 ps |
| CPU time | 113.42 seconds |
| Started | Oct 02 07:03:02 PM UTC 24 |
| Finished | Oct 02 07:04:58 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759499934 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.759499934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.4247099854 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 621359416 ps |
| CPU time | 18.17 seconds |
| Started | Oct 02 07:03:04 PM UTC 24 |
| Finished | Oct 02 07:03:23 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247099854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.4247099854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_error_random.2405469918 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 277738718 ps |
| CPU time | 6.65 seconds |
| Started | Oct 02 07:03:04 PM UTC 24 |
| Finished | Oct 02 07:03:12 PM UTC 24 |
| Peak memory | 212180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405469918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.2405469918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/42.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random.541964103 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 21191168 ps |
| CPU time | 1.83 seconds |
| Started | Oct 02 07:02:59 PM UTC 24 |
| Finished | Oct 02 07:03:02 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541964103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.541964103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/42.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.3906201122 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 36612922055 ps |
| CPU time | 192.69 seconds |
| Started | Oct 02 07:03:02 PM UTC 24 |
| Finished | Oct 02 07:06:17 PM UTC 24 |
| Peak memory | 212268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906201122 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3906201122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/42.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.3581557649 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 58883025828 ps |
| CPU time | 141.94 seconds |
| Started | Oct 02 07:03:02 PM UTC 24 |
| Finished | Oct 02 07:05:26 PM UTC 24 |
| Peak memory | 212060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581557649 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.3581557649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/42.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_zero_delays.2744622878 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 78235190 ps |
| CPU time | 7.87 seconds |
| Started | Oct 02 07:03:02 PM UTC 24 |
| Finished | Oct 02 07:03:11 PM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744622878 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.2744622878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/42.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_same_source.1816184063 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 87882363 ps |
| CPU time | 3.05 seconds |
| Started | Oct 02 07:03:02 PM UTC 24 |
| Finished | Oct 02 07:03:06 PM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816184063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.1816184063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/42.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke.1389871887 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 28332884 ps |
| CPU time | 1.54 seconds |
| Started | Oct 02 07:02:56 PM UTC 24 |
| Finished | Oct 02 07:02:59 PM UTC 24 |
| Peak memory | 210616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389871887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.1389871887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/42.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_large_delays.3044883549 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 6026440158 ps |
| CPU time | 16.63 seconds |
| Started | Oct 02 07:02:58 PM UTC 24 |
| Finished | Oct 02 07:03:16 PM UTC 24 |
| Peak memory | 212264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044883549 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.3044883549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/42.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.1070001290 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 1733396653 ps |
| CPU time | 10.47 seconds |
| Started | Oct 02 07:02:59 PM UTC 24 |
| Finished | Oct 02 07:03:11 PM UTC 24 |
| Peak memory | 211988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070001290 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1070001290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.3786323551 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 10505845 ps |
| CPU time | 1.24 seconds |
| Started | Oct 02 07:02:56 PM UTC 24 |
| Finished | Oct 02 07:02:59 PM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786323551 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.3786323551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/42.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.3492456531 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 4402341782 ps |
| CPU time | 92.04 seconds |
| Started | Oct 02 07:03:08 PM UTC 24 |
| Finished | Oct 02 07:04:43 PM UTC 24 |
| Peak memory | 214108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492456531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.3492456531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/42.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.1459014022 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 3516162012 ps |
| CPU time | 20.8 seconds |
| Started | Oct 02 07:03:08 PM UTC 24 |
| Finished | Oct 02 07:03:31 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459014022 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.1459014022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/42.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1846757206 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 438648950 ps |
| CPU time | 42.91 seconds |
| Started | Oct 02 07:03:08 PM UTC 24 |
| Finished | Oct 02 07:03:53 PM UTC 24 |
| Peak memory | 214056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846757206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.1846757206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.2708272698 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 427478296 ps |
| CPU time | 24.73 seconds |
| Started | Oct 02 07:03:11 PM UTC 24 |
| Finished | Oct 02 07:03:37 PM UTC 24 |
| Peak memory | 214060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708272698 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.2708272698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_unmapped_addr.3075262674 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 506470156 ps |
| CPU time | 4.99 seconds |
| Started | Oct 02 07:03:04 PM UTC 24 |
| Finished | Oct 02 07:03:10 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075262674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3075262674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/42.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.1747267275 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 234538996 ps |
| CPU time | 5.39 seconds |
| Started | Oct 02 07:03:17 PM UTC 24 |
| Finished | Oct 02 07:03:24 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747267275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.1747267275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/43.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3523589952 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 40017106913 ps |
| CPU time | 181.18 seconds |
| Started | Oct 02 07:03:18 PM UTC 24 |
| Finished | Oct 02 07:06:22 PM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523589952 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.3523589952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.2933290940 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 488706409 ps |
| CPU time | 8.25 seconds |
| Started | Oct 02 07:03:20 PM UTC 24 |
| Finished | Oct 02 07:03:29 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933290940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.2933290940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.2106760646 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 782070574 ps |
| CPU time | 6.22 seconds |
| Started | Oct 02 07:03:18 PM UTC 24 |
| Finished | Oct 02 07:03:25 PM UTC 24 |
| Peak memory | 211988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106760646 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.2106760646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/43.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random.1067124356 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 200028280 ps |
| CPU time | 2.76 seconds |
| Started | Oct 02 07:03:14 PM UTC 24 |
| Finished | Oct 02 07:03:18 PM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067124356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.1067124356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/43.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.2080389685 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 30614720824 ps |
| CPU time | 154.47 seconds |
| Started | Oct 02 07:03:15 PM UTC 24 |
| Finished | Oct 02 07:05:52 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080389685 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2080389685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/43.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.1402209714 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 26821541197 ps |
| CPU time | 190.09 seconds |
| Started | Oct 02 07:03:15 PM UTC 24 |
| Finished | Oct 02 07:06:28 PM UTC 24 |
| Peak memory | 212252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402209714 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1402209714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/43.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.1210977189 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 27639833 ps |
| CPU time | 2.56 seconds |
| Started | Oct 02 07:03:15 PM UTC 24 |
| Finished | Oct 02 07:03:18 PM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210977189 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.1210977189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/43.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.2375657160 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 149107273 ps |
| CPU time | 6.34 seconds |
| Started | Oct 02 07:03:18 PM UTC 24 |
| Finished | Oct 02 07:03:25 PM UTC 24 |
| Peak memory | 214012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375657160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.2375657160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/43.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke.1075582727 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 22856546 ps |
| CPU time | 1.74 seconds |
| Started | Oct 02 07:03:11 PM UTC 24 |
| Finished | Oct 02 07:03:14 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075582727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1075582727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/43.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.3433299963 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 2020391046 ps |
| CPU time | 13.99 seconds |
| Started | Oct 02 07:03:14 PM UTC 24 |
| Finished | Oct 02 07:03:30 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433299963 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.3433299963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/43.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.314020216 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 2414707381 ps |
| CPU time | 13.01 seconds |
| Started | Oct 02 07:03:14 PM UTC 24 |
| Finished | Oct 02 07:03:29 PM UTC 24 |
| Peak memory | 212048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314020216 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.314020216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.3706906544 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 9452804 ps |
| CPU time | 1.69 seconds |
| Started | Oct 02 07:03:14 PM UTC 24 |
| Finished | Oct 02 07:03:17 PM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706906544 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.3706906544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/43.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.783740344 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 4057259728 ps |
| CPU time | 28.28 seconds |
| Started | Oct 02 07:03:20 PM UTC 24 |
| Finished | Oct 02 07:03:49 PM UTC 24 |
| Peak memory | 214312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783740344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.783740344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/43.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1492371315 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 4231082059 ps |
| CPU time | 60.27 seconds |
| Started | Oct 02 07:03:21 PM UTC 24 |
| Finished | Oct 02 07:04:23 PM UTC 24 |
| Peak memory | 214312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492371315 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1492371315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/43.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.3901186549 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 391909690 ps |
| CPU time | 45.55 seconds |
| Started | Oct 02 07:03:20 PM UTC 24 |
| Finished | Oct 02 07:04:07 PM UTC 24 |
| Peak memory | 214056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901186549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.3901186549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.2947099653 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 1228718093 ps |
| CPU time | 67.14 seconds |
| Started | Oct 02 07:03:24 PM UTC 24 |
| Finished | Oct 02 07:04:33 PM UTC 24 |
| Peak memory | 216108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947099653 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.2947099653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.542060405 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 1537616042 ps |
| CPU time | 12.86 seconds |
| Started | Oct 02 07:03:18 PM UTC 24 |
| Finished | Oct 02 07:03:32 PM UTC 24 |
| Peak memory | 212140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542060405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.542060405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/43.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.1093978135 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 3034436218 ps |
| CPU time | 16.27 seconds |
| Started | Oct 02 07:03:28 PM UTC 24 |
| Finished | Oct 02 07:03:46 PM UTC 24 |
| Peak memory | 212020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093978135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.1093978135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/44.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.737412925 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 22316577422 ps |
| CPU time | 177.08 seconds |
| Started | Oct 02 07:03:30 PM UTC 24 |
| Finished | Oct 02 07:06:30 PM UTC 24 |
| Peak memory | 214184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737412925 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.737412925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2687243707 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 721069970 ps |
| CPU time | 16.02 seconds |
| Started | Oct 02 07:03:32 PM UTC 24 |
| Finished | Oct 02 07:03:49 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687243707 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.2687243707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.3472078770 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 82374500 ps |
| CPU time | 5.6 seconds |
| Started | Oct 02 07:03:32 PM UTC 24 |
| Finished | Oct 02 07:03:39 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472078770 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.3472078770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/44.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random.1962806688 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 21553440 ps |
| CPU time | 2.26 seconds |
| Started | Oct 02 07:03:26 PM UTC 24 |
| Finished | Oct 02 07:03:30 PM UTC 24 |
| Peak memory | 211980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962806688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.1962806688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/44.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.727551349 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 60779995325 ps |
| CPU time | 158.05 seconds |
| Started | Oct 02 07:03:28 PM UTC 24 |
| Finished | Oct 02 07:06:09 PM UTC 24 |
| Peak memory | 212220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727551349 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.727551349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/44.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1056007988 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 44150441822 ps |
| CPU time | 180.35 seconds |
| Started | Oct 02 07:03:28 PM UTC 24 |
| Finished | Oct 02 07:06:31 PM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056007988 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.1056007988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/44.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.3253638272 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 76353287 ps |
| CPU time | 4.51 seconds |
| Started | Oct 02 07:03:26 PM UTC 24 |
| Finished | Oct 02 07:03:32 PM UTC 24 |
| Peak memory | 212260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253638272 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.3253638272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/44.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.2956571394 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 52642431 ps |
| CPU time | 6.83 seconds |
| Started | Oct 02 07:03:30 PM UTC 24 |
| Finished | Oct 02 07:03:38 PM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956571394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.2956571394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/44.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.4291276911 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 89555435 ps |
| CPU time | 2.1 seconds |
| Started | Oct 02 07:03:24 PM UTC 24 |
| Finished | Oct 02 07:03:27 PM UTC 24 |
| Peak memory | 212244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291276911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.4291276911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/44.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1471091559 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 4608308847 ps |
| CPU time | 14.12 seconds |
| Started | Oct 02 07:03:26 PM UTC 24 |
| Finished | Oct 02 07:03:42 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471091559 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1471091559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/44.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.23621749 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 2440212322 ps |
| CPU time | 14.73 seconds |
| Started | Oct 02 07:03:26 PM UTC 24 |
| Finished | Oct 02 07:03:42 PM UTC 24 |
| Peak memory | 212064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23621749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.23621749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.3399806392 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 17312748 ps |
| CPU time | 1.87 seconds |
| Started | Oct 02 07:03:24 PM UTC 24 |
| Finished | Oct 02 07:03:27 PM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399806392 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.3399806392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/44.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.1193562857 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 249235276 ps |
| CPU time | 40.3 seconds |
| Started | Oct 02 07:03:32 PM UTC 24 |
| Finished | Oct 02 07:04:14 PM UTC 24 |
| Peak memory | 214056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193562857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1193562857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/44.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1176364326 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 289879557 ps |
| CPU time | 26.84 seconds |
| Started | Oct 02 07:03:34 PM UTC 24 |
| Finished | Oct 02 07:04:02 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176364326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1176364326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/44.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.4073713948 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 522969689 ps |
| CPU time | 53.06 seconds |
| Started | Oct 02 07:03:34 PM UTC 24 |
| Finished | Oct 02 07:04:29 PM UTC 24 |
| Peak memory | 214056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073713948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.4073713948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.655056022 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 1958513556 ps |
| CPU time | 105.58 seconds |
| Started | Oct 02 07:03:34 PM UTC 24 |
| Finished | Oct 02 07:05:22 PM UTC 24 |
| Peak memory | 218412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655056022 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.655056022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.2332822461 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 53534441 ps |
| CPU time | 4.47 seconds |
| Started | Oct 02 07:03:32 PM UTC 24 |
| Finished | Oct 02 07:03:37 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332822461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2332822461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/44.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.2331460959 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 2497094312 ps |
| CPU time | 18.57 seconds |
| Started | Oct 02 07:03:44 PM UTC 24 |
| Finished | Oct 02 07:04:04 PM UTC 24 |
| Peak memory | 212268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331460959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.2331460959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/45.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.3873492839 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 25225705651 ps |
| CPU time | 147.06 seconds |
| Started | Oct 02 07:03:44 PM UTC 24 |
| Finished | Oct 02 07:06:14 PM UTC 24 |
| Peak memory | 214124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873492839 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.3873492839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.324574889 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 329539607 ps |
| CPU time | 6.83 seconds |
| Started | Oct 02 07:03:47 PM UTC 24 |
| Finished | Oct 02 07:03:55 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324574889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.324574889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.2794015408 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 81105746 ps |
| CPU time | 7.43 seconds |
| Started | Oct 02 07:03:44 PM UTC 24 |
| Finished | Oct 02 07:03:53 PM UTC 24 |
| Peak memory | 211988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794015408 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2794015408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/45.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random.1494794314 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 599662685 ps |
| CPU time | 11.03 seconds |
| Started | Oct 02 07:03:40 PM UTC 24 |
| Finished | Oct 02 07:03:52 PM UTC 24 |
| Peak memory | 212048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494794314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.1494794314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/45.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.4175065471 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 143295761480 ps |
| CPU time | 94.25 seconds |
| Started | Oct 02 07:03:40 PM UTC 24 |
| Finished | Oct 02 07:05:17 PM UTC 24 |
| Peak memory | 212268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175065471 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.4175065471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/45.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.1652937559 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 14282872313 ps |
| CPU time | 114.09 seconds |
| Started | Oct 02 07:03:44 PM UTC 24 |
| Finished | Oct 02 07:05:40 PM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652937559 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.1652937559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/45.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.657164009 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 21210712 ps |
| CPU time | 2.47 seconds |
| Started | Oct 02 07:03:40 PM UTC 24 |
| Finished | Oct 02 07:03:44 PM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657164009 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.657164009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/45.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.2015978430 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 38890266 ps |
| CPU time | 5.83 seconds |
| Started | Oct 02 07:03:44 PM UTC 24 |
| Finished | Oct 02 07:03:51 PM UTC 24 |
| Peak memory | 212064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015978430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.2015978430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/45.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.695124793 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 47124058 ps |
| CPU time | 2.15 seconds |
| Started | Oct 02 07:03:35 PM UTC 24 |
| Finished | Oct 02 07:03:39 PM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695124793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.695124793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/45.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.254635254 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 3565347533 ps |
| CPU time | 6.16 seconds |
| Started | Oct 02 07:03:39 PM UTC 24 |
| Finished | Oct 02 07:03:46 PM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254635254 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.254635254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/45.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1319238105 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 3462410805 ps |
| CPU time | 10.5 seconds |
| Started | Oct 02 07:03:39 PM UTC 24 |
| Finished | Oct 02 07:03:50 PM UTC 24 |
| Peak memory | 212052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319238105 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1319238105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1101969312 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 9355218 ps |
| CPU time | 1.57 seconds |
| Started | Oct 02 07:03:39 PM UTC 24 |
| Finished | Oct 02 07:03:41 PM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101969312 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.1101969312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/45.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.1443265470 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 246112176 ps |
| CPU time | 15.72 seconds |
| Started | Oct 02 07:03:47 PM UTC 24 |
| Finished | Oct 02 07:04:04 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443265470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1443265470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/45.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.3773576692 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 3874415246 ps |
| CPU time | 34.36 seconds |
| Started | Oct 02 07:03:48 PM UTC 24 |
| Finished | Oct 02 07:04:24 PM UTC 24 |
| Peak memory | 212264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773576692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.3773576692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/45.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.985190888 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 1316601349 ps |
| CPU time | 112.8 seconds |
| Started | Oct 02 07:03:47 PM UTC 24 |
| Finished | Oct 02 07:05:42 PM UTC 24 |
| Peak memory | 216100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985190888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.985190888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.839155720 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 1760218893 ps |
| CPU time | 72.2 seconds |
| Started | Oct 02 07:03:50 PM UTC 24 |
| Finished | Oct 02 07:05:04 PM UTC 24 |
| Peak memory | 216108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839155720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.839155720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.3749324694 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 133645418 ps |
| CPU time | 2.05 seconds |
| Started | Oct 02 07:03:45 PM UTC 24 |
| Finished | Oct 02 07:03:48 PM UTC 24 |
| Peak memory | 212252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749324694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3749324694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/45.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.3029726404 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 17056243 ps |
| CPU time | 4.25 seconds |
| Started | Oct 02 07:03:56 PM UTC 24 |
| Finished | Oct 02 07:04:01 PM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029726404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.3029726404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/46.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.2886508132 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 23659218780 ps |
| CPU time | 135.1 seconds |
| Started | Oct 02 07:03:56 PM UTC 24 |
| Finished | Oct 02 07:06:14 PM UTC 24 |
| Peak memory | 212140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886508132 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.2886508132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.1958513797 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 170390926 ps |
| CPU time | 5.99 seconds |
| Started | Oct 02 07:04:05 PM UTC 24 |
| Finished | Oct 02 07:04:13 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958513797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.1958513797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.429783355 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 1030999148 ps |
| CPU time | 16.49 seconds |
| Started | Oct 02 07:04:03 PM UTC 24 |
| Finished | Oct 02 07:04:20 PM UTC 24 |
| Peak memory | 211980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429783355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.429783355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/46.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random.2159646093 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 659207136 ps |
| CPU time | 10.94 seconds |
| Started | Oct 02 07:03:54 PM UTC 24 |
| Finished | Oct 02 07:04:06 PM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159646093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.2159646093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/46.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.1183430008 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 38951666257 ps |
| CPU time | 156.04 seconds |
| Started | Oct 02 07:03:54 PM UTC 24 |
| Finished | Oct 02 07:06:33 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183430008 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1183430008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/46.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.1033444280 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 17685542380 ps |
| CPU time | 107.96 seconds |
| Started | Oct 02 07:03:54 PM UTC 24 |
| Finished | Oct 02 07:05:44 PM UTC 24 |
| Peak memory | 212252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033444280 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1033444280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/46.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.3894186716 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 79334159 ps |
| CPU time | 5.83 seconds |
| Started | Oct 02 07:03:54 PM UTC 24 |
| Finished | Oct 02 07:04:01 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894186716 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.3894186716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/46.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.925528639 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 80225443 ps |
| CPU time | 5.24 seconds |
| Started | Oct 02 07:03:56 PM UTC 24 |
| Finished | Oct 02 07:04:02 PM UTC 24 |
| Peak memory | 212120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925528639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.925528639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/46.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.2760178155 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 9655960 ps |
| CPU time | 1.95 seconds |
| Started | Oct 02 07:03:52 PM UTC 24 |
| Finished | Oct 02 07:03:55 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760178155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.2760178155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/46.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.948191311 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 8754689369 ps |
| CPU time | 19.08 seconds |
| Started | Oct 02 07:03:52 PM UTC 24 |
| Finished | Oct 02 07:04:12 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948191311 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.948191311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/46.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.2327285352 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 3942525618 ps |
| CPU time | 11.78 seconds |
| Started | Oct 02 07:03:52 PM UTC 24 |
| Finished | Oct 02 07:04:05 PM UTC 24 |
| Peak memory | 212052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327285352 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.2327285352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.4059166219 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 9694390 ps |
| CPU time | 1.87 seconds |
| Started | Oct 02 07:03:52 PM UTC 24 |
| Finished | Oct 02 07:03:55 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059166219 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.4059166219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/46.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.1392624315 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 1614418725 ps |
| CPU time | 29.98 seconds |
| Started | Oct 02 07:04:06 PM UTC 24 |
| Finished | Oct 02 07:04:37 PM UTC 24 |
| Peak memory | 214056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392624315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1392624315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/46.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.3622606336 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 3236857794 ps |
| CPU time | 17.22 seconds |
| Started | Oct 02 07:04:06 PM UTC 24 |
| Finished | Oct 02 07:04:24 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622606336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.3622606336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/46.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.3313138175 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 205702540 ps |
| CPU time | 23.34 seconds |
| Started | Oct 02 07:04:06 PM UTC 24 |
| Finished | Oct 02 07:04:30 PM UTC 24 |
| Peak memory | 214256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313138175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.3313138175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.3032059755 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 88986676 ps |
| CPU time | 8.1 seconds |
| Started | Oct 02 07:04:06 PM UTC 24 |
| Finished | Oct 02 07:04:15 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032059755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.3032059755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.4103606996 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 534566815 ps |
| CPU time | 11.53 seconds |
| Started | Oct 02 07:04:03 PM UTC 24 |
| Finished | Oct 02 07:04:15 PM UTC 24 |
| Peak memory | 212260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103606996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.4103606996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/46.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.1557113520 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 56057043 ps |
| CPU time | 7.27 seconds |
| Started | Oct 02 07:04:14 PM UTC 24 |
| Finished | Oct 02 07:04:22 PM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557113520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.1557113520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/47.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.4062838347 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 539625603 ps |
| CPU time | 10.25 seconds |
| Started | Oct 02 07:04:17 PM UTC 24 |
| Finished | Oct 02 07:04:29 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062838347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.4062838347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.2733828653 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 189067696 ps |
| CPU time | 5.82 seconds |
| Started | Oct 02 07:04:16 PM UTC 24 |
| Finished | Oct 02 07:04:23 PM UTC 24 |
| Peak memory | 211988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733828653 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.2733828653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/47.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random.2697511324 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 588802300 ps |
| CPU time | 8.08 seconds |
| Started | Oct 02 07:04:10 PM UTC 24 |
| Finished | Oct 02 07:04:19 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697511324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.2697511324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/47.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.1090070391 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 22640653144 ps |
| CPU time | 94.91 seconds |
| Started | Oct 02 07:04:11 PM UTC 24 |
| Finished | Oct 02 07:05:48 PM UTC 24 |
| Peak memory | 212332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090070391 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1090070391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/47.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.2551638092 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 5883485353 ps |
| CPU time | 43.34 seconds |
| Started | Oct 02 07:04:14 PM UTC 24 |
| Finished | Oct 02 07:04:58 PM UTC 24 |
| Peak memory | 212060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551638092 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.2551638092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/47.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.3320323788 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 64025175 ps |
| CPU time | 4.23 seconds |
| Started | Oct 02 07:04:10 PM UTC 24 |
| Finished | Oct 02 07:04:15 PM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320323788 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.3320323788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/47.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.1513818321 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 19068303 ps |
| CPU time | 2.98 seconds |
| Started | Oct 02 07:04:16 PM UTC 24 |
| Finished | Oct 02 07:04:20 PM UTC 24 |
| Peak memory | 211996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513818321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.1513818321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/47.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.644006492 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 12020580 ps |
| CPU time | 1.75 seconds |
| Started | Oct 02 07:04:06 PM UTC 24 |
| Finished | Oct 02 07:04:09 PM UTC 24 |
| Peak memory | 210932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644006492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.644006492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/47.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1417928630 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 6587305980 ps |
| CPU time | 15.47 seconds |
| Started | Oct 02 07:04:08 PM UTC 24 |
| Finished | Oct 02 07:04:24 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417928630 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1417928630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/47.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.1731107812 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 984492372 ps |
| CPU time | 9.1 seconds |
| Started | Oct 02 07:04:09 PM UTC 24 |
| Finished | Oct 02 07:04:20 PM UTC 24 |
| Peak memory | 211988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731107812 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1731107812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1350778742 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 15251430 ps |
| CPU time | 1.39 seconds |
| Started | Oct 02 07:04:08 PM UTC 24 |
| Finished | Oct 02 07:04:10 PM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350778742 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.1350778742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/47.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.2365094969 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 1030995696 ps |
| CPU time | 15.15 seconds |
| Started | Oct 02 07:04:19 PM UTC 24 |
| Finished | Oct 02 07:04:36 PM UTC 24 |
| Peak memory | 211996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365094969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2365094969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/47.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.190161191 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 25251746908 ps |
| CPU time | 72.08 seconds |
| Started | Oct 02 07:04:21 PM UTC 24 |
| Finished | Oct 02 07:05:35 PM UTC 24 |
| Peak memory | 214124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190161191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.190161191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/47.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.1547736529 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 3979106971 ps |
| CPU time | 101 seconds |
| Started | Oct 02 07:04:21 PM UTC 24 |
| Finished | Oct 02 07:06:04 PM UTC 24 |
| Peak memory | 216364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547736529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.1547736529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.45155089 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 315140640 ps |
| CPU time | 34.4 seconds |
| Started | Oct 02 07:04:23 PM UTC 24 |
| Finished | Oct 02 07:04:59 PM UTC 24 |
| Peak memory | 214252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45155089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.45155089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.199219595 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 41779442 ps |
| CPU time | 3.97 seconds |
| Started | Oct 02 07:04:16 PM UTC 24 |
| Finished | Oct 02 07:04:21 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199219595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.199219595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/47.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.1534152062 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 23137316 ps |
| CPU time | 3.46 seconds |
| Started | Oct 02 07:04:27 PM UTC 24 |
| Finished | Oct 02 07:04:32 PM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534152062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.1534152062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/48.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2432308311 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 67038938220 ps |
| CPU time | 406.39 seconds |
| Started | Oct 02 07:04:30 PM UTC 24 |
| Finished | Oct 02 07:11:21 PM UTC 24 |
| Peak memory | 218004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432308311 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.2432308311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.863563644 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 14892090 ps |
| CPU time | 1.92 seconds |
| Started | Oct 02 07:04:32 PM UTC 24 |
| Finished | Oct 02 07:04:35 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863563644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.863563644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.1477806347 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 603224924 ps |
| CPU time | 8.41 seconds |
| Started | Oct 02 07:04:32 PM UTC 24 |
| Finished | Oct 02 07:04:41 PM UTC 24 |
| Peak memory | 212180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477806347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.1477806347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/48.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random.2829503001 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 125745195 ps |
| CPU time | 4.64 seconds |
| Started | Oct 02 07:04:25 PM UTC 24 |
| Finished | Oct 02 07:04:31 PM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829503001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.2829503001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/48.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.1593996070 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 112363247586 ps |
| CPU time | 107.88 seconds |
| Started | Oct 02 07:04:25 PM UTC 24 |
| Finished | Oct 02 07:06:15 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593996070 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1593996070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/48.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.1403053172 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 33164748411 ps |
| CPU time | 181.72 seconds |
| Started | Oct 02 07:04:27 PM UTC 24 |
| Finished | Oct 02 07:07:32 PM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403053172 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.1403053172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/48.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.1499668262 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 174623885 ps |
| CPU time | 8.47 seconds |
| Started | Oct 02 07:04:25 PM UTC 24 |
| Finished | Oct 02 07:04:35 PM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499668262 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.1499668262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/48.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.279851876 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 28180340 ps |
| CPU time | 2.88 seconds |
| Started | Oct 02 07:04:30 PM UTC 24 |
| Finished | Oct 02 07:04:34 PM UTC 24 |
| Peak memory | 211992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279851876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.279851876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/48.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.179990818 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 9736639 ps |
| CPU time | 1.73 seconds |
| Started | Oct 02 07:04:23 PM UTC 24 |
| Finished | Oct 02 07:04:26 PM UTC 24 |
| Peak memory | 210932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179990818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.179990818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/48.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.668207031 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 3496407761 ps |
| CPU time | 18.82 seconds |
| Started | Oct 02 07:04:25 PM UTC 24 |
| Finished | Oct 02 07:04:45 PM UTC 24 |
| Peak memory | 212064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668207031 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.668207031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/48.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.2647706718 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 1041105618 ps |
| CPU time | 6.06 seconds |
| Started | Oct 02 07:04:25 PM UTC 24 |
| Finished | Oct 02 07:04:32 PM UTC 24 |
| Peak memory | 212184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647706718 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.2647706718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.286578510 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 17956106 ps |
| CPU time | 1.76 seconds |
| Started | Oct 02 07:04:23 PM UTC 24 |
| Finished | Oct 02 07:04:26 PM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286578510 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.286578510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/48.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.352141390 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 427843243 ps |
| CPU time | 16.11 seconds |
| Started | Oct 02 07:04:32 PM UTC 24 |
| Finished | Oct 02 07:04:49 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352141390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.352141390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/48.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.662451597 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 4668564717 ps |
| CPU time | 9.68 seconds |
| Started | Oct 02 07:04:34 PM UTC 24 |
| Finished | Oct 02 07:04:45 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662451597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.662451597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/48.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3208763360 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 1326855969 ps |
| CPU time | 120.79 seconds |
| Started | Oct 02 07:04:34 PM UTC 24 |
| Finished | Oct 02 07:06:38 PM UTC 24 |
| Peak memory | 216104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208763360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.3208763360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1344198835 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 501543808 ps |
| CPU time | 66.19 seconds |
| Started | Oct 02 07:04:35 PM UTC 24 |
| Finished | Oct 02 07:05:42 PM UTC 24 |
| Peak memory | 214252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344198835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.1344198835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.4029694518 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 1504659706 ps |
| CPU time | 10.54 seconds |
| Started | Oct 02 07:04:32 PM UTC 24 |
| Finished | Oct 02 07:04:44 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029694518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.4029694518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/48.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.2979200293 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 69918057 ps |
| CPU time | 10.18 seconds |
| Started | Oct 02 07:04:39 PM UTC 24 |
| Finished | Oct 02 07:04:50 PM UTC 24 |
| Peak memory | 212204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979200293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.2979200293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/49.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.898444084 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 27558109700 ps |
| CPU time | 206.18 seconds |
| Started | Oct 02 07:04:39 PM UTC 24 |
| Finished | Oct 02 07:08:08 PM UTC 24 |
| Peak memory | 214116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898444084 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.898444084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.3099599561 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 525287515 ps |
| CPU time | 6.97 seconds |
| Started | Oct 02 07:04:44 PM UTC 24 |
| Finished | Oct 02 07:04:52 PM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099599561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.3099599561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.4011639378 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 1595996680 ps |
| CPU time | 5.22 seconds |
| Started | Oct 02 07:04:41 PM UTC 24 |
| Finished | Oct 02 07:04:47 PM UTC 24 |
| Peak memory | 212180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011639378 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.4011639378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/49.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random.2732639064 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 58028915 ps |
| CPU time | 4.56 seconds |
| Started | Oct 02 07:04:37 PM UTC 24 |
| Finished | Oct 02 07:04:43 PM UTC 24 |
| Peak memory | 211988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732639064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.2732639064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/49.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.2220475029 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 31881280794 ps |
| CPU time | 112.22 seconds |
| Started | Oct 02 07:04:37 PM UTC 24 |
| Finished | Oct 02 07:06:32 PM UTC 24 |
| Peak memory | 212076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220475029 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2220475029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/49.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.2740672042 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 25206189424 ps |
| CPU time | 149.52 seconds |
| Started | Oct 02 07:04:39 PM UTC 24 |
| Finished | Oct 02 07:07:11 PM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740672042 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.2740672042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/49.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.1444501916 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 77824094 ps |
| CPU time | 8.45 seconds |
| Started | Oct 02 07:04:37 PM UTC 24 |
| Finished | Oct 02 07:04:47 PM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444501916 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.1444501916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/49.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.308940768 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 577432482 ps |
| CPU time | 10.01 seconds |
| Started | Oct 02 07:04:39 PM UTC 24 |
| Finished | Oct 02 07:04:50 PM UTC 24 |
| Peak memory | 212184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308940768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.308940768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/49.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.1693599583 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 448403947 ps |
| CPU time | 2.67 seconds |
| Started | Oct 02 07:04:35 PM UTC 24 |
| Finished | Oct 02 07:04:38 PM UTC 24 |
| Peak memory | 212180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693599583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1693599583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/49.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3806622 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 2487387624 ps |
| CPU time | 13.02 seconds |
| Started | Oct 02 07:04:37 PM UTC 24 |
| Finished | Oct 02 07:04:51 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806622 -assert nopostproc +UVM_TESTNAME=xbar_base_t est +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3806622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/49.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.3531439582 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 1654102476 ps |
| CPU time | 13.01 seconds |
| Started | Oct 02 07:04:37 PM UTC 24 |
| Finished | Oct 02 07:04:51 PM UTC 24 |
| Peak memory | 212184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531439582 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.3531439582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.2581964797 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 17726005 ps |
| CPU time | 1.39 seconds |
| Started | Oct 02 07:04:35 PM UTC 24 |
| Finished | Oct 02 07:04:37 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581964797 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.2581964797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/49.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.3108742638 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 658088111 ps |
| CPU time | 52.67 seconds |
| Started | Oct 02 07:04:48 PM UTC 24 |
| Finished | Oct 02 07:05:42 PM UTC 24 |
| Peak memory | 214244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108742638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3108742638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/49.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.4048230991 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 597674715 ps |
| CPU time | 41.4 seconds |
| Started | Oct 02 07:04:48 PM UTC 24 |
| Finished | Oct 02 07:05:31 PM UTC 24 |
| Peak memory | 214056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048230991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.4048230991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/49.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.3046522821 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 16016662 ps |
| CPU time | 8.39 seconds |
| Started | Oct 02 07:04:48 PM UTC 24 |
| Finished | Oct 02 07:04:57 PM UTC 24 |
| Peak memory | 214056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046522821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.3046522821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.1185706539 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 2437766140 ps |
| CPU time | 84.88 seconds |
| Started | Oct 02 07:04:48 PM UTC 24 |
| Finished | Oct 02 07:06:15 PM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185706539 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.1185706539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.2076210476 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 224579692 ps |
| CPU time | 6.41 seconds |
| Started | Oct 02 07:04:44 PM UTC 24 |
| Finished | Oct 02 07:04:51 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076210476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2076210476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/49.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device.2585325699 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 49538830 ps |
| CPU time | 3.68 seconds |
| Started | Oct 02 06:54:37 PM UTC 24 |
| Finished | Oct 02 06:54:42 PM UTC 24 |
| Peak memory | 212204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585325699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.2585325699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/5.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.72315638 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 318110048 ps |
| CPU time | 7.17 seconds |
| Started | Oct 02 06:54:43 PM UTC 24 |
| Finished | Oct 02 06:54:52 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72315638 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.72315638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_error_random.779075367 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 11725642 ps |
| CPU time | 1.68 seconds |
| Started | Oct 02 06:54:40 PM UTC 24 |
| Finished | Oct 02 06:54:43 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779075367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.779075367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/5.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random.1522797507 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 14758589 ps |
| CPU time | 2.11 seconds |
| Started | Oct 02 06:54:34 PM UTC 24 |
| Finished | Oct 02 06:54:37 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522797507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.1522797507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/5.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_large_delays.2379909565 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 129228585262 ps |
| CPU time | 104.9 seconds |
| Started | Oct 02 06:54:35 PM UTC 24 |
| Finished | Oct 02 06:56:22 PM UTC 24 |
| Peak memory | 212064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379909565 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.2379909565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/5.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_slow_rsp.3715380092 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 194592561315 ps |
| CPU time | 293.94 seconds |
| Started | Oct 02 06:54:35 PM UTC 24 |
| Finished | Oct 02 06:59:34 PM UTC 24 |
| Peak memory | 212056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715380092 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.3715380092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/5.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_zero_delays.4062467966 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 31395007 ps |
| CPU time | 3.08 seconds |
| Started | Oct 02 06:54:34 PM UTC 24 |
| Finished | Oct 02 06:54:38 PM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062467966 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.4062467966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/5.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_same_source.358007502 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1458445084 ps |
| CPU time | 10.51 seconds |
| Started | Oct 02 06:54:39 PM UTC 24 |
| Finished | Oct 02 06:54:51 PM UTC 24 |
| Peak memory | 212264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358007502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.358007502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/5.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke.3703550861 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 32712042 ps |
| CPU time | 1.98 seconds |
| Started | Oct 02 06:54:31 PM UTC 24 |
| Finished | Oct 02 06:54:34 PM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703550861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.3703550861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/5.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_large_delays.2323403515 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 2589145938 ps |
| CPU time | 12.24 seconds |
| Started | Oct 02 06:54:32 PM UTC 24 |
| Finished | Oct 02 06:54:45 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323403515 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.2323403515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/5.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.306751580 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 3547584026 ps |
| CPU time | 13.32 seconds |
| Started | Oct 02 06:54:34 PM UTC 24 |
| Finished | Oct 02 06:54:48 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306751580 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.306751580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.3474812037 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 34476338 ps |
| CPU time | 1.67 seconds |
| Started | Oct 02 06:54:31 PM UTC 24 |
| Finished | Oct 02 06:54:33 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474812037 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.3474812037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/5.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all.1663023506 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 17735324547 ps |
| CPU time | 73.8 seconds |
| Started | Oct 02 06:54:47 PM UTC 24 |
| Finished | Oct 02 06:56:02 PM UTC 24 |
| Peak memory | 214252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663023506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1663023506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/5.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_error.976167858 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 142172911 ps |
| CPU time | 16.18 seconds |
| Started | Oct 02 06:54:50 PM UTC 24 |
| Finished | Oct 02 06:55:08 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976167858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.976167858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/5.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.1554064279 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 4653155574 ps |
| CPU time | 40.86 seconds |
| Started | Oct 02 06:54:48 PM UTC 24 |
| Finished | Oct 02 06:55:30 PM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554064279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.1554064279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.2480103148 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 1091273921 ps |
| CPU time | 89.82 seconds |
| Started | Oct 02 06:54:50 PM UTC 24 |
| Finished | Oct 02 06:56:23 PM UTC 24 |
| Peak memory | 214056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480103148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.2480103148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_unmapped_addr.809294113 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 202063871 ps |
| CPU time | 5.21 seconds |
| Started | Oct 02 06:54:42 PM UTC 24 |
| Finished | Oct 02 06:54:49 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809294113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.809294113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/5.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.2139137694 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 42596612831 ps |
| CPU time | 231.06 seconds |
| Started | Oct 02 06:55:04 PM UTC 24 |
| Finished | Oct 02 06:58:58 PM UTC 24 |
| Peak memory | 214312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139137694 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.2139137694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.4106792249 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 406516306 ps |
| CPU time | 11 seconds |
| Started | Oct 02 06:55:08 PM UTC 24 |
| Finished | Oct 02 06:55:21 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106792249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.4106792249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_error_random.1036167745 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 43840406 ps |
| CPU time | 3.23 seconds |
| Started | Oct 02 06:55:07 PM UTC 24 |
| Finished | Oct 02 06:55:11 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036167745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1036167745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/6.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random.2631004314 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 273881301 ps |
| CPU time | 10.23 seconds |
| Started | Oct 02 06:54:55 PM UTC 24 |
| Finished | Oct 02 06:55:07 PM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631004314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.2631004314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/6.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_large_delays.1225535814 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 34135393383 ps |
| CPU time | 116.81 seconds |
| Started | Oct 02 06:54:56 PM UTC 24 |
| Finished | Oct 02 06:56:56 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225535814 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1225535814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/6.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_slow_rsp.313340521 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 16291027854 ps |
| CPU time | 18.77 seconds |
| Started | Oct 02 06:54:59 PM UTC 24 |
| Finished | Oct 02 06:55:19 PM UTC 24 |
| Peak memory | 212048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313340521 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.313340521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/6.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_zero_delays.3388316115 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 47550453 ps |
| CPU time | 7.17 seconds |
| Started | Oct 02 06:54:55 PM UTC 24 |
| Finished | Oct 02 06:55:04 PM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388316115 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.3388316115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/6.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_same_source.691010191 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 289945259 ps |
| CPU time | 4.44 seconds |
| Started | Oct 02 06:55:05 PM UTC 24 |
| Finished | Oct 02 06:55:10 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691010191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.691010191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/6.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke.2530513544 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 10112987 ps |
| CPU time | 2.11 seconds |
| Started | Oct 02 06:54:51 PM UTC 24 |
| Finished | Oct 02 06:54:54 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530513544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2530513544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/6.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_large_delays.1551615820 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 3423527859 ps |
| CPU time | 21.81 seconds |
| Started | Oct 02 06:54:53 PM UTC 24 |
| Finished | Oct 02 06:55:16 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551615820 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.1551615820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/6.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.2035288471 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1961477341 ps |
| CPU time | 11.38 seconds |
| Started | Oct 02 06:54:55 PM UTC 24 |
| Finished | Oct 02 06:55:08 PM UTC 24 |
| Peak memory | 211964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035288471 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.2035288471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.804276584 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 14054465 ps |
| CPU time | 1.68 seconds |
| Started | Oct 02 06:54:52 PM UTC 24 |
| Finished | Oct 02 06:54:54 PM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804276584 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.804276584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/6.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all.1790740679 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 3126837141 ps |
| CPU time | 45.45 seconds |
| Started | Oct 02 06:55:09 PM UTC 24 |
| Finished | Oct 02 06:55:57 PM UTC 24 |
| Peak memory | 214124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790740679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1790740679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/6.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_error.230879377 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 483690953 ps |
| CPU time | 28.92 seconds |
| Started | Oct 02 06:55:12 PM UTC 24 |
| Finished | Oct 02 06:55:42 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230879377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.230879377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/6.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.1134624165 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 3053163839 ps |
| CPU time | 59.24 seconds |
| Started | Oct 02 06:55:09 PM UTC 24 |
| Finished | Oct 02 06:56:11 PM UTC 24 |
| Peak memory | 216300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134624165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.1134624165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.451967794 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 4191208866 ps |
| CPU time | 109.11 seconds |
| Started | Oct 02 06:55:12 PM UTC 24 |
| Finished | Oct 02 06:57:03 PM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451967794 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.451967794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_unmapped_addr.3828894276 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 93290862 ps |
| CPU time | 5.62 seconds |
| Started | Oct 02 06:55:08 PM UTC 24 |
| Finished | Oct 02 06:55:15 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828894276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3828894276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/6.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device.3217275940 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 983212412 ps |
| CPU time | 11.35 seconds |
| Started | Oct 02 06:55:25 PM UTC 24 |
| Finished | Oct 02 06:55:38 PM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217275940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.3217275940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/7.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.3610336773 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 15776401516 ps |
| CPU time | 127.02 seconds |
| Started | Oct 02 06:55:25 PM UTC 24 |
| Finished | Oct 02 06:57:35 PM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610336773 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.3610336773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.469539035 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 12219958 ps |
| CPU time | 1.68 seconds |
| Started | Oct 02 06:55:28 PM UTC 24 |
| Finished | Oct 02 06:55:30 PM UTC 24 |
| Peak memory | 210948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469539035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.469539035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_error_random.3083314330 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 1030485584 ps |
| CPU time | 16.8 seconds |
| Started | Oct 02 06:55:26 PM UTC 24 |
| Finished | Oct 02 06:55:45 PM UTC 24 |
| Peak memory | 211988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083314330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3083314330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/7.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random.3288850827 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 53730323 ps |
| CPU time | 6.6 seconds |
| Started | Oct 02 06:55:19 PM UTC 24 |
| Finished | Oct 02 06:55:27 PM UTC 24 |
| Peak memory | 211984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288850827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.3288850827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/7.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_large_delays.2841351622 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 69562518849 ps |
| CPU time | 66.42 seconds |
| Started | Oct 02 06:55:20 PM UTC 24 |
| Finished | Oct 02 06:56:28 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841351622 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2841351622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/7.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_slow_rsp.2389702887 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 8948378108 ps |
| CPU time | 32.27 seconds |
| Started | Oct 02 06:55:21 PM UTC 24 |
| Finished | Oct 02 06:55:55 PM UTC 24 |
| Peak memory | 212052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389702887 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.2389702887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/7.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_zero_delays.661636883 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 21527480 ps |
| CPU time | 4.34 seconds |
| Started | Oct 02 06:55:20 PM UTC 24 |
| Finished | Oct 02 06:55:25 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661636883 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.661636883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/7.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_same_source.946942701 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 882284990 ps |
| CPU time | 11.65 seconds |
| Started | Oct 02 06:55:26 PM UTC 24 |
| Finished | Oct 02 06:55:39 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946942701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.946942701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/7.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke.4191609324 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 92873208 ps |
| CPU time | 1.97 seconds |
| Started | Oct 02 06:55:14 PM UTC 24 |
| Finished | Oct 02 06:55:17 PM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191609324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.4191609324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/7.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_large_delays.164352942 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 4113130318 ps |
| CPU time | 6.97 seconds |
| Started | Oct 02 06:55:17 PM UTC 24 |
| Finished | Oct 02 06:55:25 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164352942 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.164352942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/7.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.1099592198 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 2167205603 ps |
| CPU time | 10.81 seconds |
| Started | Oct 02 06:55:18 PM UTC 24 |
| Finished | Oct 02 06:55:30 PM UTC 24 |
| Peak memory | 212048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099592198 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.1099592198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.2335261587 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 11476982 ps |
| CPU time | 1.92 seconds |
| Started | Oct 02 06:55:16 PM UTC 24 |
| Finished | Oct 02 06:55:19 PM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335261587 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.2335261587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/7.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all.3312967674 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 5389918067 ps |
| CPU time | 102.46 seconds |
| Started | Oct 02 06:55:28 PM UTC 24 |
| Finished | Oct 02 06:57:12 PM UTC 24 |
| Peak memory | 214124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312967674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.3312967674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/7.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_error.2480731967 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 455340430 ps |
| CPU time | 15.32 seconds |
| Started | Oct 02 06:55:31 PM UTC 24 |
| Finished | Oct 02 06:55:47 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480731967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2480731967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/7.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.3836714943 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 6380604213 ps |
| CPU time | 114.56 seconds |
| Started | Oct 02 06:55:31 PM UTC 24 |
| Finished | Oct 02 06:57:28 PM UTC 24 |
| Peak memory | 216364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836714943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.3836714943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.3671711521 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 532755477 ps |
| CPU time | 62.24 seconds |
| Started | Oct 02 06:55:31 PM UTC 24 |
| Finished | Oct 02 06:56:35 PM UTC 24 |
| Peak memory | 214056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671711521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.3671711521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_unmapped_addr.499253520 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 94720017 ps |
| CPU time | 8.21 seconds |
| Started | Oct 02 06:55:26 PM UTC 24 |
| Finished | Oct 02 06:55:36 PM UTC 24 |
| Peak memory | 212268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499253520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.499253520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/7.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device.1244487390 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 514361634 ps |
| CPU time | 6.21 seconds |
| Started | Oct 02 06:55:43 PM UTC 24 |
| Finished | Oct 02 06:55:50 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244487390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.1244487390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/8.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.3388254045 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 39778054313 ps |
| CPU time | 335.24 seconds |
| Started | Oct 02 06:55:44 PM UTC 24 |
| Finished | Oct 02 07:01:24 PM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388254045 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.3388254045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.460347441 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 95639300 ps |
| CPU time | 3.6 seconds |
| Started | Oct 02 06:55:46 PM UTC 24 |
| Finished | Oct 02 06:55:51 PM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460347441 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.460347441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_error_random.438537497 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 293245027 ps |
| CPU time | 7.21 seconds |
| Started | Oct 02 06:55:46 PM UTC 24 |
| Finished | Oct 02 06:55:54 PM UTC 24 |
| Peak memory | 211988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438537497 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.438537497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/8.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random.2471643248 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 2218174388 ps |
| CPU time | 9.73 seconds |
| Started | Oct 02 06:55:38 PM UTC 24 |
| Finished | Oct 02 06:55:49 PM UTC 24 |
| Peak memory | 212048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471643248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.2471643248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/8.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_large_delays.3141084206 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 49647950644 ps |
| CPU time | 235.96 seconds |
| Started | Oct 02 06:55:41 PM UTC 24 |
| Finished | Oct 02 06:59:40 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141084206 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.3141084206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/8.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_slow_rsp.1001825388 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 5824313729 ps |
| CPU time | 49.84 seconds |
| Started | Oct 02 06:55:41 PM UTC 24 |
| Finished | Oct 02 06:56:32 PM UTC 24 |
| Peak memory | 212252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001825388 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1001825388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/8.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_zero_delays.897722205 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 41490293 ps |
| CPU time | 3.18 seconds |
| Started | Oct 02 06:55:38 PM UTC 24 |
| Finished | Oct 02 06:55:43 PM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897722205 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.897722205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/8.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_same_source.652877606 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 14023585 ps |
| CPU time | 2.39 seconds |
| Started | Oct 02 06:55:44 PM UTC 24 |
| Finished | Oct 02 06:55:47 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652877606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.652877606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/8.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke.1236077009 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 8509505 ps |
| CPU time | 1.86 seconds |
| Started | Oct 02 06:55:33 PM UTC 24 |
| Finished | Oct 02 06:55:36 PM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236077009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1236077009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/8.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_large_delays.2111322965 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 5875060593 ps |
| CPU time | 7.52 seconds |
| Started | Oct 02 06:55:37 PM UTC 24 |
| Finished | Oct 02 06:55:46 PM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111322965 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.2111322965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/8.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2576459748 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 1826578541 ps |
| CPU time | 15.44 seconds |
| Started | Oct 02 06:55:38 PM UTC 24 |
| Finished | Oct 02 06:55:55 PM UTC 24 |
| Peak memory | 212180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576459748 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2576459748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.2818418222 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 13421556 ps |
| CPU time | 1.64 seconds |
| Started | Oct 02 06:55:37 PM UTC 24 |
| Finished | Oct 02 06:55:40 PM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818418222 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.2818418222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/8.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all.1251381428 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 617142088 ps |
| CPU time | 61.48 seconds |
| Started | Oct 02 06:55:48 PM UTC 24 |
| Finished | Oct 02 06:56:52 PM UTC 24 |
| Peak memory | 214252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251381428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1251381428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/8.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_error.827489889 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 10839193736 ps |
| CPU time | 72.86 seconds |
| Started | Oct 02 06:55:50 PM UTC 24 |
| Finished | Oct 02 06:57:05 PM UTC 24 |
| Peak memory | 214312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827489889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.827489889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/8.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.4111845692 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 834009354 ps |
| CPU time | 106.87 seconds |
| Started | Oct 02 06:55:50 PM UTC 24 |
| Finished | Oct 02 06:57:40 PM UTC 24 |
| Peak memory | 218348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111845692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.4111845692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_unmapped_addr.262280267 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 356783920 ps |
| CPU time | 7.96 seconds |
| Started | Oct 02 06:55:46 PM UTC 24 |
| Finished | Oct 02 06:55:55 PM UTC 24 |
| Peak memory | 212204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262280267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.262280267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/8.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device.1803601239 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 58501326 ps |
| CPU time | 14.18 seconds |
| Started | Oct 02 06:55:58 PM UTC 24 |
| Finished | Oct 02 06:56:14 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803601239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1803601239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/9.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.584220535 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 19885080585 ps |
| CPU time | 83.66 seconds |
| Started | Oct 02 06:55:58 PM UTC 24 |
| Finished | Oct 02 06:57:24 PM UTC 24 |
| Peak memory | 212064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584220535 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.584220535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.71539056 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 27766399 ps |
| CPU time | 3.71 seconds |
| Started | Oct 02 06:56:02 PM UTC 24 |
| Finished | Oct 02 06:56:07 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71539056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.71539056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_error_random.814211082 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 156225413 ps |
| CPU time | 3.85 seconds |
| Started | Oct 02 06:56:02 PM UTC 24 |
| Finished | Oct 02 06:56:07 PM UTC 24 |
| Peak memory | 211988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814211082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.814211082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/9.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random.3079206450 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 75249251 ps |
| CPU time | 4.99 seconds |
| Started | Oct 02 06:55:56 PM UTC 24 |
| Finished | Oct 02 06:56:02 PM UTC 24 |
| Peak memory | 211980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079206450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.3079206450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/9.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_large_delays.219704099 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 40356743869 ps |
| CPU time | 110.31 seconds |
| Started | Oct 02 06:55:56 PM UTC 24 |
| Finished | Oct 02 06:57:48 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219704099 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.219704099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/9.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_slow_rsp.465778033 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 18977737564 ps |
| CPU time | 70.35 seconds |
| Started | Oct 02 06:55:58 PM UTC 24 |
| Finished | Oct 02 06:57:10 PM UTC 24 |
| Peak memory | 212048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465778033 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.465778033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/9.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_zero_delays.1814081523 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 129617954 ps |
| CPU time | 4.1 seconds |
| Started | Oct 02 06:55:56 PM UTC 24 |
| Finished | Oct 02 06:56:01 PM UTC 24 |
| Peak memory | 212260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814081523 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.1814081523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/9.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_same_source.3052180252 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 770753600 ps |
| CPU time | 8.26 seconds |
| Started | Oct 02 06:56:01 PM UTC 24 |
| Finished | Oct 02 06:56:10 PM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052180252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3052180252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/9.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke.3761710473 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 11051935 ps |
| CPU time | 1.44 seconds |
| Started | Oct 02 06:55:52 PM UTC 24 |
| Finished | Oct 02 06:55:54 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761710473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3761710473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/9.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_large_delays.4091875621 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 1786072623 ps |
| CPU time | 11.06 seconds |
| Started | Oct 02 06:55:55 PM UTC 24 |
| Finished | Oct 02 06:56:07 PM UTC 24 |
| Peak memory | 212200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091875621 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.4091875621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/9.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.2936606471 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 827570112 ps |
| CPU time | 8.91 seconds |
| Started | Oct 02 06:55:55 PM UTC 24 |
| Finished | Oct 02 06:56:05 PM UTC 24 |
| Peak memory | 212180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936606471 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2936606471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.2756917379 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 7918197 ps |
| CPU time | 1.51 seconds |
| Started | Oct 02 06:55:55 PM UTC 24 |
| Finished | Oct 02 06:55:57 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756917379 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.2756917379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/9.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all.2336699643 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 920321970 ps |
| CPU time | 35.75 seconds |
| Started | Oct 02 06:56:03 PM UTC 24 |
| Finished | Oct 02 06:56:41 PM UTC 24 |
| Peak memory | 214056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336699643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2336699643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/9.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_error.3034547946 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 353301161 ps |
| CPU time | 18.99 seconds |
| Started | Oct 02 06:56:05 PM UTC 24 |
| Finished | Oct 02 06:56:25 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034547946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3034547946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/9.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.914450884 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 2308356525 ps |
| CPU time | 41.71 seconds |
| Started | Oct 02 06:56:03 PM UTC 24 |
| Finished | Oct 02 06:56:47 PM UTC 24 |
| Peak memory | 216356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914450884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.914450884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.3454160303 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 437695669 ps |
| CPU time | 39.83 seconds |
| Started | Oct 02 06:56:06 PM UTC 24 |
| Finished | Oct 02 06:56:47 PM UTC 24 |
| Peak memory | 214056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454160303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.3454160303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_unmapped_addr.893984811 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 31026984 ps |
| CPU time | 5.14 seconds |
| Started | Oct 02 06:56:02 PM UTC 24 |
| Finished | Oct 02 06:56:08 PM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893984811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.893984811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/9.xbar_unmapped_addr/latest |
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