Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	446	1			T21	2		T271	1		T319	2
all_values[1]	427	1			T25	2		T272	2		T319	1
all_values[2]	449	1			T25	1		T319	1		T278	7
all_values[3]	487	1			T21	1		T25	1		T67	1
all_values[4]	458	1			T21	1		T25	2		T28	1
all_values[5]	447	1			T25	1		T46	2		T67	2
all_values[6]	465	1			T28	1		T272	2		T319	3
all_values[7]	444	1			T25	2		T278	1		T313	6
all_values[8]	468	1			T25	2		T271	1		T46	1
all_values[9]	430	1			T271	2		T46	1		T67	1
all_values[10]	426	1			T25	1		T272	2		T319	3
all_values[11]	424	1			T25	1		T28	1		T272	2
all_values[12]	439	1			T25	1		T271	1		T46	3
all_values[13]	447	1			T25	2		T271	1		T46	1
all_values[14]	454	1			T25	1		T28	1		T271	1
all_values[15]	452	1			T28	1		T46	1		T67	1
all_values[16]	446	1			T25	1		T46	2		T272	3
all_values[17]	494	1			T271	1		T46	1		T319	4
all_values[18]	427	1			T21	2		T28	1		T271	1
all_values[19]	449	1			T25	3		T28	1		T272	2
all_values[20]	428	1			T271	1		T46	1		T272	2
all_values[21]	467	1			T25	1		T46	1		T272	3
all_values[22]	464	1			T25	3		T271	1		T272	1
all_values[23]	441	1			T25	2		T28	1		T46	1
all_values[24]	453	1			T21	1		T46	1		T272	1
all_values[25]	489	1			T21	2		T25	1		T28	1
all_values[26]	459	1			T28	1		T46	3		T272	1