| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.30 | 100.00 | 95.80 | 100.00 | 100.00 | 100.00 | 100.00 |
| T771 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2824307368 | Oct 09 05:19:11 AM UTC 24 | Oct 09 05:19:15 AM UTC 24 | 19784579 ps | ||
| T772 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.2299537218 | Oct 09 05:19:03 AM UTC 24 | Oct 09 05:19:15 AM UTC 24 | 1568181984 ps | ||
| T773 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.3149708793 | Oct 09 05:19:11 AM UTC 24 | Oct 09 05:19:15 AM UTC 24 | 187390946 ps | ||
| T774 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.3728432123 | Oct 09 05:19:14 AM UTC 24 | Oct 09 05:19:17 AM UTC 24 | 14969227 ps | ||
| T775 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.163886848 | Oct 09 05:17:31 AM UTC 24 | Oct 09 05:19:17 AM UTC 24 | 26347601459 ps | ||
| T776 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.182862219 | Oct 09 05:18:46 AM UTC 24 | Oct 09 05:19:17 AM UTC 24 | 489531309 ps | ||
| T777 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.855939925 | Oct 09 05:18:31 AM UTC 24 | Oct 09 05:19:18 AM UTC 24 | 18584786187 ps | ||
| T778 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.1777550330 | Oct 09 05:18:46 AM UTC 24 | Oct 09 05:19:18 AM UTC 24 | 1375487449 ps | ||
| T779 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3128713241 | Oct 09 05:19:11 AM UTC 24 | Oct 09 05:19:18 AM UTC 24 | 608755211 ps | ||
| T780 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.2698000061 | Oct 09 05:19:11 AM UTC 24 | Oct 09 05:19:19 AM UTC 24 | 570633564 ps | ||
| T781 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.3883007153 | Oct 09 05:19:03 AM UTC 24 | Oct 09 05:19:19 AM UTC 24 | 2048671804 ps | ||
| T782 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.3250810216 | Oct 09 05:19:11 AM UTC 24 | Oct 09 05:19:20 AM UTC 24 | 597010784 ps | ||
| T783 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.971903440 | Oct 09 05:19:03 AM UTC 24 | Oct 09 05:19:23 AM UTC 24 | 563740553 ps | ||
| T784 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.4160771534 | Oct 09 05:19:11 AM UTC 24 | Oct 09 05:19:24 AM UTC 24 | 3574561758 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.2455055071 | Oct 09 05:17:35 AM UTC 24 | Oct 09 05:19:24 AM UTC 24 | 5879399055 ps | ||
| T785 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.133622559 | Oct 09 05:19:18 AM UTC 24 | Oct 09 05:19:25 AM UTC 24 | 41612961 ps | ||
| T217 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.2062264454 | Oct 09 05:19:03 AM UTC 24 | Oct 09 05:19:26 AM UTC 24 | 3978511784 ps | ||
| T786 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.3471128881 | Oct 09 05:19:14 AM UTC 24 | Oct 09 05:19:27 AM UTC 24 | 3033223757 ps | ||
| T787 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.3030462200 | Oct 09 05:19:26 AM UTC 24 | Oct 09 05:19:29 AM UTC 24 | 19463080 ps | ||
| T788 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.3633188340 | Oct 09 05:18:15 AM UTC 24 | Oct 09 05:19:29 AM UTC 24 | 538079171 ps | ||
| T789 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.970091306 | Oct 09 05:19:26 AM UTC 24 | Oct 09 05:19:29 AM UTC 24 | 42020182 ps | ||
| T790 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random.2708482214 | Oct 09 05:19:18 AM UTC 24 | Oct 09 05:19:30 AM UTC 24 | 154471642 ps | ||
| T791 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.116121775 | Oct 09 05:19:03 AM UTC 24 | Oct 09 05:19:31 AM UTC 24 | 205685037 ps | ||
| T792 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.686244155 | Oct 09 05:16:22 AM UTC 24 | Oct 09 05:19:31 AM UTC 24 | 3306073891 ps | ||
| T793 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.1259299273 | Oct 09 05:19:26 AM UTC 24 | Oct 09 05:19:32 AM UTC 24 | 1028579935 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.2515660433 | Oct 09 05:19:30 AM UTC 24 | Oct 09 05:19:33 AM UTC 24 | 11233810 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.1457786635 | Oct 09 05:19:30 AM UTC 24 | Oct 09 05:19:34 AM UTC 24 | 86014724 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.682968904 | Oct 09 05:19:10 AM UTC 24 | Oct 09 05:19:34 AM UTC 24 | 1518222625 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.4045658058 | Oct 09 05:15:06 AM UTC 24 | Oct 09 05:19:34 AM UTC 24 | 55520847605 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.2025643483 | Oct 09 05:19:18 AM UTC 24 | Oct 09 05:19:35 AM UTC 24 | 1564553245 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.966561322 | Oct 09 05:17:24 AM UTC 24 | Oct 09 05:19:36 AM UTC 24 | 20158880007 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.1150102830 | Oct 09 05:17:01 AM UTC 24 | Oct 09 05:19:37 AM UTC 24 | 38335768767 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.1753275875 | Oct 09 05:19:26 AM UTC 24 | Oct 09 05:19:37 AM UTC 24 | 2236170989 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.712202153 | Oct 09 05:19:34 AM UTC 24 | Oct 09 05:19:38 AM UTC 24 | 19487447 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.1289494207 | Oct 09 05:19:18 AM UTC 24 | Oct 09 05:19:38 AM UTC 24 | 5591398633 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.1430628694 | Oct 09 05:19:26 AM UTC 24 | Oct 09 05:19:39 AM UTC 24 | 423309420 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.150608963 | Oct 09 05:18:25 AM UTC 24 | Oct 09 05:19:41 AM UTC 24 | 5312682679 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.481976806 | Oct 09 05:19:26 AM UTC 24 | Oct 09 05:19:41 AM UTC 24 | 1262163823 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.4109830970 | Oct 09 05:19:30 AM UTC 24 | Oct 09 05:19:41 AM UTC 24 | 1031359012 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.2301799460 | Oct 09 05:19:11 AM UTC 24 | Oct 09 05:19:42 AM UTC 24 | 199869847 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.1083301936 | Oct 09 05:18:53 AM UTC 24 | Oct 09 05:19:43 AM UTC 24 | 9531434442 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random.3309526506 | Oct 09 05:19:34 AM UTC 24 | Oct 09 05:19:43 AM UTC 24 | 127811171 ps | ||
| T311 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3329355117 | Oct 09 05:17:32 AM UTC 24 | Oct 09 05:19:43 AM UTC 24 | 33908185409 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_large_delays.745497009 | Oct 09 05:16:35 AM UTC 24 | Oct 09 05:19:43 AM UTC 24 | 216352697079 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.1184678238 | Oct 09 05:16:09 AM UTC 24 | Oct 09 05:19:43 AM UTC 24 | 19544080227 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.2550490697 | Oct 09 05:19:37 AM UTC 24 | Oct 09 05:19:44 AM UTC 24 | 269893321 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.3126900270 | Oct 09 05:19:30 AM UTC 24 | Oct 09 05:19:44 AM UTC 24 | 2024350532 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.4087650741 | Oct 09 05:19:37 AM UTC 24 | Oct 09 05:19:44 AM UTC 24 | 59834574 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.2196045269 | Oct 09 05:19:42 AM UTC 24 | Oct 09 05:19:44 AM UTC 24 | 10497615 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.4096590768 | Oct 09 05:19:34 AM UTC 24 | Oct 09 05:19:44 AM UTC 24 | 77516256 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1739002264 | Oct 09 05:19:26 AM UTC 24 | Oct 09 05:19:45 AM UTC 24 | 235321072 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.2785381389 | Oct 09 05:19:42 AM UTC 24 | Oct 09 05:19:45 AM UTC 24 | 58265111 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.92759411 | Oct 09 05:17:49 AM UTC 24 | Oct 09 05:19:45 AM UTC 24 | 9287696255 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.3526627876 | Oct 09 05:19:37 AM UTC 24 | Oct 09 05:19:47 AM UTC 24 | 400897040 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.2445073022 | Oct 09 05:18:41 AM UTC 24 | Oct 09 05:19:47 AM UTC 24 | 21199622329 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.1357233535 | Oct 09 05:19:34 AM UTC 24 | Oct 09 05:19:48 AM UTC 24 | 110712725 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.190473032 | Oct 09 05:19:11 AM UTC 24 | Oct 09 05:19:48 AM UTC 24 | 454944747 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.1059709376 | Oct 09 05:19:47 AM UTC 24 | Oct 09 05:19:50 AM UTC 24 | 108244159 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.826778156 | Oct 09 05:19:47 AM UTC 24 | Oct 09 05:19:52 AM UTC 24 | 49132248 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.986203159 | Oct 09 05:18:31 AM UTC 24 | Oct 09 05:19:53 AM UTC 24 | 13000903389 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.1727197823 | Oct 09 05:19:51 AM UTC 24 | Oct 09 05:19:54 AM UTC 24 | 12454897 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.1870071036 | Oct 09 05:19:51 AM UTC 24 | Oct 09 05:19:54 AM UTC 24 | 11939034 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.2106452158 | Oct 09 05:19:47 AM UTC 24 | Oct 09 05:19:54 AM UTC 24 | 895350472 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.750507341 | Oct 09 05:19:47 AM UTC 24 | Oct 09 05:19:54 AM UTC 24 | 187205591 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.193840935 | Oct 09 05:18:26 AM UTC 24 | Oct 09 05:19:54 AM UTC 24 | 13937778869 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1725585 | Oct 09 05:19:42 AM UTC 24 | Oct 09 05:19:55 AM UTC 24 | 6473842175 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random.557574623 | Oct 09 05:19:51 AM UTC 24 | Oct 09 05:19:55 AM UTC 24 | 76415660 ps | ||
| T832 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2336830533 | Oct 09 05:19:47 AM UTC 24 | Oct 09 05:19:55 AM UTC 24 | 447465932 ps | ||
| T833 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.731395731 | Oct 09 05:19:26 AM UTC 24 | Oct 09 05:19:59 AM UTC 24 | 520109270 ps | ||
| T834 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.3075710107 | Oct 09 05:19:47 AM UTC 24 | Oct 09 05:19:59 AM UTC 24 | 176224262 ps | ||
| T835 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.4166266350 | Oct 09 05:19:51 AM UTC 24 | Oct 09 05:20:00 AM UTC 24 | 2144681129 ps | ||
| T836 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.792319019 | Oct 09 05:19:03 AM UTC 24 | Oct 09 05:20:01 AM UTC 24 | 2194996164 ps | ||
| T837 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.692982139 | Oct 09 05:19:51 AM UTC 24 | Oct 09 05:20:01 AM UTC 24 | 69068093 ps | ||
| T838 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.1283486242 | Oct 09 05:19:58 AM UTC 24 | Oct 09 05:20:02 AM UTC 24 | 6732298 ps | ||
| T839 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.94591647 | Oct 09 05:19:58 AM UTC 24 | Oct 09 05:20:03 AM UTC 24 | 155443387 ps | ||
| T840 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.3002277312 | Oct 09 05:17:15 AM UTC 24 | Oct 09 05:20:04 AM UTC 24 | 34182243610 ps | ||
| T841 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.1267281102 | Oct 09 05:20:01 AM UTC 24 | Oct 09 05:20:04 AM UTC 24 | 9847012 ps | ||
| T842 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.925538524 | Oct 09 05:20:02 AM UTC 24 | Oct 09 05:20:04 AM UTC 24 | 11394631 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3929840464 | Oct 09 05:14:19 AM UTC 24 | Oct 09 05:20:05 AM UTC 24 | 83301050021 ps | ||
| T843 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.4078452620 | Oct 09 05:19:47 AM UTC 24 | Oct 09 05:20:05 AM UTC 24 | 5423019177 ps | ||
| T844 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random.1764451012 | Oct 09 05:19:47 AM UTC 24 | Oct 09 05:20:05 AM UTC 24 | 3983792729 ps | ||
| T845 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1158538940 | Oct 09 05:19:51 AM UTC 24 | Oct 09 05:20:05 AM UTC 24 | 2477997177 ps | ||
| T846 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.3570064235 | Oct 09 05:19:37 AM UTC 24 | Oct 09 05:20:05 AM UTC 24 | 702593583 ps | ||
| T847 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.2182276980 | Oct 09 05:19:58 AM UTC 24 | Oct 09 05:20:06 AM UTC 24 | 69878809 ps | ||
| T246 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.2262765686 | Oct 09 05:18:17 AM UTC 24 | Oct 09 05:20:07 AM UTC 24 | 35545945557 ps | ||
| T848 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.179872826 | Oct 09 05:19:58 AM UTC 24 | Oct 09 05:20:07 AM UTC 24 | 209174232 ps | ||
| T849 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.1522180783 | Oct 09 05:17:49 AM UTC 24 | Oct 09 05:20:08 AM UTC 24 | 726422000 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.101747716 | Oct 09 05:15:51 AM UTC 24 | Oct 09 05:20:09 AM UTC 24 | 39182716715 ps | ||
| T850 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1281435849 | Oct 09 05:19:42 AM UTC 24 | Oct 09 05:20:09 AM UTC 24 | 2078358554 ps | ||
| T851 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.1405441304 | Oct 09 05:20:06 AM UTC 24 | Oct 09 05:20:10 AM UTC 24 | 25811434 ps | ||
| T852 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.3622070531 | Oct 09 05:19:58 AM UTC 24 | Oct 09 05:20:10 AM UTC 24 | 564552827 ps | ||
| T853 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random.1727689879 | Oct 09 05:20:06 AM UTC 24 | Oct 09 05:20:10 AM UTC 24 | 52556495 ps | ||
| T854 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3781981923 | Oct 09 05:20:02 AM UTC 24 | Oct 09 05:20:11 AM UTC 24 | 2336767690 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.3952319453 | Oct 09 05:19:47 AM UTC 24 | Oct 09 05:20:11 AM UTC 24 | 2509374965 ps | ||
| T855 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.615775075 | Oct 09 05:18:43 AM UTC 24 | Oct 09 05:20:11 AM UTC 24 | 60227540305 ps | ||
| T856 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2738535180 | Oct 09 05:17:24 AM UTC 24 | Oct 09 05:20:12 AM UTC 24 | 1032965999 ps | ||
| T857 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.3287584403 | Oct 09 05:20:06 AM UTC 24 | Oct 09 05:20:12 AM UTC 24 | 95130396 ps | ||
| T858 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.712139021 | Oct 09 05:19:58 AM UTC 24 | Oct 09 05:20:14 AM UTC 24 | 310188253 ps | ||
| T859 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.2781552938 | Oct 09 05:19:58 AM UTC 24 | Oct 09 05:20:14 AM UTC 24 | 1191063311 ps | ||
| T860 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1856276715 | Oct 09 05:20:06 AM UTC 24 | Oct 09 05:20:15 AM UTC 24 | 1402606503 ps | ||
| T861 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.3916509829 | Oct 09 05:20:14 AM UTC 24 | Oct 09 05:20:17 AM UTC 24 | 65795915 ps | ||
| T862 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.4281043975 | Oct 09 05:19:42 AM UTC 24 | Oct 09 05:20:17 AM UTC 24 | 440599714 ps | ||
| T863 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.156493281 | Oct 09 05:18:25 AM UTC 24 | Oct 09 05:20:17 AM UTC 24 | 1419088271 ps | ||
| T864 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.146563026 | Oct 09 05:20:13 AM UTC 24 | Oct 09 05:20:19 AM UTC 24 | 47997567 ps | ||
| T865 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.4157980404 | Oct 09 05:20:13 AM UTC 24 | Oct 09 05:20:19 AM UTC 24 | 510103289 ps | ||
| T866 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.2109147584 | Oct 09 05:19:58 AM UTC 24 | Oct 09 05:20:21 AM UTC 24 | 2231033067 ps | ||
| T867 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.2550592046 | Oct 09 05:20:13 AM UTC 24 | Oct 09 05:20:21 AM UTC 24 | 2976482781 ps | ||
| T309 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.663598005 | Oct 09 05:16:07 AM UTC 24 | Oct 09 05:20:24 AM UTC 24 | 63956061205 ps | ||
| T868 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2476709570 | Oct 09 05:20:14 AM UTC 24 | Oct 09 05:20:25 AM UTC 24 | 109325196 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1240967791 | Oct 09 05:19:26 AM UTC 24 | Oct 09 05:20:25 AM UTC 24 | 321241862 ps | ||
| T869 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.2950386192 | Oct 09 05:17:41 AM UTC 24 | Oct 09 05:20:27 AM UTC 24 | 117015028518 ps | ||
| T870 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3747399419 | Oct 09 05:19:47 AM UTC 24 | Oct 09 05:20:29 AM UTC 24 | 4111446121 ps | ||
| T871 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.1798810389 | Oct 09 05:19:10 AM UTC 24 | Oct 09 05:20:30 AM UTC 24 | 10500965104 ps | ||
| T872 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2625802747 | Oct 09 05:19:11 AM UTC 24 | Oct 09 05:20:33 AM UTC 24 | 600427297 ps | ||
| T305 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.3609166530 | Oct 09 05:18:43 AM UTC 24 | Oct 09 05:20:34 AM UTC 24 | 22438776639 ps | ||
| T873 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.676463962 | Oct 09 05:19:47 AM UTC 24 | Oct 09 05:20:38 AM UTC 24 | 14194634480 ps | ||
| T874 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.3897201545 | Oct 09 05:18:46 AM UTC 24 | Oct 09 05:20:39 AM UTC 24 | 1404187208 ps | ||
| T875 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.2634606921 | Oct 09 05:19:04 AM UTC 24 | Oct 09 05:20:40 AM UTC 24 | 12719483429 ps | ||
| T876 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3636998810 | Oct 09 05:19:34 AM UTC 24 | Oct 09 05:20:41 AM UTC 24 | 9264165180 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.1481187354 | Oct 09 05:20:06 AM UTC 24 | Oct 09 05:20:42 AM UTC 24 | 4269745095 ps | ||
| T877 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.4158302434 | Oct 09 05:19:47 AM UTC 24 | Oct 09 05:20:42 AM UTC 24 | 13931534802 ps | ||
| T878 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.1879604696 | Oct 09 05:16:17 AM UTC 24 | Oct 09 05:20:44 AM UTC 24 | 194796355765 ps | ||
| T879 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.734939915 | Oct 09 05:20:06 AM UTC 24 | Oct 09 05:20:47 AM UTC 24 | 5110848026 ps | ||
| T880 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.2370144220 | Oct 09 05:18:36 AM UTC 24 | Oct 09 05:20:49 AM UTC 24 | 3387954968 ps | ||
| T881 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.1320040160 | Oct 09 05:18:53 AM UTC 24 | Oct 09 05:20:53 AM UTC 24 | 34922781603 ps | ||
| T882 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3999151090 | Oct 09 05:18:19 AM UTC 24 | Oct 09 05:20:55 AM UTC 24 | 22660744234 ps | ||
| T883 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.202094057 | Oct 09 05:20:14 AM UTC 24 | Oct 09 05:21:02 AM UTC 24 | 299611869 ps | ||
| T884 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3973851368 | Oct 09 05:19:26 AM UTC 24 | Oct 09 05:21:04 AM UTC 24 | 71136206425 ps | ||
| T885 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.3606804857 | Oct 09 05:19:47 AM UTC 24 | Oct 09 05:21:07 AM UTC 24 | 10507073150 ps | ||
| T886 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.3014857893 | Oct 09 05:19:41 AM UTC 24 | Oct 09 05:21:07 AM UTC 24 | 608645451 ps | ||
| T887 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.636245304 | Oct 09 05:20:01 AM UTC 24 | Oct 09 05:21:10 AM UTC 24 | 4173701762 ps | ||
| T888 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.1163615478 | Oct 09 05:19:34 AM UTC 24 | Oct 09 05:21:11 AM UTC 24 | 31805037981 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.17002786 | Oct 09 05:19:54 AM UTC 24 | Oct 09 05:21:14 AM UTC 24 | 9238986548 ps | ||
| T889 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.3777287973 | Oct 09 05:20:06 AM UTC 24 | Oct 09 05:21:15 AM UTC 24 | 18301160844 ps | ||
| T890 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.1607749049 | Oct 09 05:19:51 AM UTC 24 | Oct 09 05:21:29 AM UTC 24 | 79859912132 ps | ||
| T891 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.3666235002 | Oct 09 05:19:26 AM UTC 24 | Oct 09 05:21:36 AM UTC 24 | 30437326903 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.2775847272 | Oct 09 05:19:03 AM UTC 24 | Oct 09 05:21:37 AM UTC 24 | 3676516453 ps | ||
| T892 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1639758664 | Oct 09 05:19:47 AM UTC 24 | Oct 09 05:21:41 AM UTC 24 | 13816415801 ps | ||
| T893 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.1161686804 | Oct 09 05:20:14 AM UTC 24 | Oct 09 05:21:44 AM UTC 24 | 14560136749 ps | ||
| T894 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.3058522700 | Oct 09 05:20:14 AM UTC 24 | Oct 09 05:22:04 AM UTC 24 | 652733697 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.2305117946 | Oct 09 05:18:33 AM UTC 24 | Oct 09 05:22:32 AM UTC 24 | 113058181572 ps | ||
| T308 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.159051728 | Oct 09 05:17:17 AM UTC 24 | Oct 09 05:22:37 AM UTC 24 | 40093292965 ps | ||
| T895 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1692256400 | Oct 09 05:16:00 AM UTC 24 | Oct 09 05:22:40 AM UTC 24 | 49966596266 ps | ||
| T896 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.2154330902 | Oct 09 05:16:28 AM UTC 24 | Oct 09 05:23:19 AM UTC 24 | 47604815811 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.738346754 | Oct 09 05:18:53 AM UTC 24 | Oct 09 05:23:44 AM UTC 24 | 68344009830 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.122578712 | Oct 09 05:17:04 AM UTC 24 | Oct 09 05:24:46 AM UTC 24 | 70371181152 ps | ||
| T897 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.2900393314 | Oct 09 05:18:01 AM UTC 24 | Oct 09 05:24:52 AM UTC 24 | 274030404780 ps | ||
| T898 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.2076998622 | Oct 09 05:19:34 AM UTC 24 | Oct 09 05:25:20 AM UTC 24 | 44267678582 ps | ||
| T899 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.2873972098 | Oct 09 05:19:47 AM UTC 24 | Oct 09 05:25:25 AM UTC 24 | 85381169509 ps | ||
| T900 | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.576629195 | Oct 09 05:19:58 AM UTC 24 | Oct 09 05:26:46 AM UTC 24 | 200954430748 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.1445482719 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 787689583 ps |
| CPU time | 7.01 seconds |
| Started | Oct 09 05:09:08 AM UTC 24 |
| Finished | Oct 09 05:09:16 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445482719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.1445482719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.4200449320 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 71299865057 ps |
| CPU time | 355.43 seconds |
| Started | Oct 09 05:09:33 AM UTC 24 |
| Finished | Oct 09 05:15:33 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200449320 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.4200449320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.1944148188 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 48121931789 ps |
| CPU time | 411.66 seconds |
| Started | Oct 09 05:09:20 AM UTC 24 |
| Finished | Oct 09 05:16:17 AM UTC 24 |
| Peak memory | 216408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944148188 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.1944148188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.2719899555 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 91656589348 ps |
| CPU time | 375.75 seconds |
| Started | Oct 09 05:12:04 AM UTC 24 |
| Finished | Oct 09 05:18:25 AM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719899555 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.2719899555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.1612486190 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 3626439488 ps |
| CPU time | 47.12 seconds |
| Started | Oct 09 05:09:27 AM UTC 24 |
| Finished | Oct 09 05:10:16 AM UTC 24 |
| Peak memory | 214228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612486190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.1612486190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.975823006 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 54049067748 ps |
| CPU time | 213.39 seconds |
| Started | Oct 09 05:12:49 AM UTC 24 |
| Finished | Oct 09 05:16:27 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975823006 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.975823006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_zero_delays.4016171486 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 84017333 ps |
| CPU time | 6.16 seconds |
| Started | Oct 09 05:09:00 AM UTC 24 |
| Finished | Oct 09 05:09:07 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016171486 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.4016171486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/0.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all.1274330283 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 3314701218 ps |
| CPU time | 65.81 seconds |
| Started | Oct 09 05:09:23 AM UTC 24 |
| Finished | Oct 09 05:10:30 AM UTC 24 |
| Peak memory | 214548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274330283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1274330283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/1.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all.947030839 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 4031948504 ps |
| CPU time | 54.97 seconds |
| Started | Oct 09 05:11:16 AM UTC 24 |
| Finished | Oct 09 05:12:12 AM UTC 24 |
| Peak memory | 214484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947030839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.947030839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/7.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_large_delays.667379281 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 2548336533 ps |
| CPU time | 19.02 seconds |
| Started | Oct 09 05:08:57 AM UTC 24 |
| Finished | Oct 09 05:09:17 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667379281 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.667379281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/0.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.3576795027 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 80207632762 ps |
| CPU time | 342.29 seconds |
| Started | Oct 09 05:09:06 AM UTC 24 |
| Finished | Oct 09 05:14:53 AM UTC 24 |
| Peak memory | 214356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576795027 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.3576795027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device.483230494 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 455291429 ps |
| CPU time | 10.56 seconds |
| Started | Oct 09 05:09:20 AM UTC 24 |
| Finished | Oct 09 05:09:31 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483230494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.483230494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/1.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all.2428005479 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 5943796013 ps |
| CPU time | 76.75 seconds |
| Started | Oct 09 05:10:04 AM UTC 24 |
| Finished | Oct 09 05:11:23 AM UTC 24 |
| Peak memory | 216272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428005479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2428005479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/3.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1926329532 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 42536191515 ps |
| CPU time | 363.49 seconds |
| Started | Oct 09 05:11:51 AM UTC 24 |
| Finished | Oct 09 05:18:00 AM UTC 24 |
| Peak memory | 218004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926329532 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.1926329532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.3794775436 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 681150956 ps |
| CPU time | 38.25 seconds |
| Started | Oct 09 05:11:57 AM UTC 24 |
| Finished | Oct 09 05:12:37 AM UTC 24 |
| Peak memory | 214164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794775436 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.3794775436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_same_source.2055560416 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 2375929550 ps |
| CPU time | 13.32 seconds |
| Started | Oct 09 05:09:06 AM UTC 24 |
| Finished | Oct 09 05:09:20 AM UTC 24 |
| Peak memory | 212432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055560416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2055560416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/0.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.2318468290 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4934827071 ps |
| CPU time | 82.38 seconds |
| Started | Oct 09 05:12:56 AM UTC 24 |
| Finished | Oct 09 05:14:21 AM UTC 24 |
| Peak memory | 216276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318468290 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.2318468290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.2933801941 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 420406160 ps |
| CPU time | 56.01 seconds |
| Started | Oct 09 05:15:43 AM UTC 24 |
| Finished | Oct 09 05:16:40 AM UTC 24 |
| Peak memory | 216212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933801941 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.2933801941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.2003913850 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 867224764 ps |
| CPU time | 174.71 seconds |
| Started | Oct 09 05:15:43 AM UTC 24 |
| Finished | Oct 09 05:18:41 AM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003913850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.2003913850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1240967791 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 321241862 ps |
| CPU time | 56.97 seconds |
| Started | Oct 09 05:19:26 AM UTC 24 |
| Finished | Oct 09 05:20:25 AM UTC 24 |
| Peak memory | 214160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240967791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.1240967791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.3777244263 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 4120567648 ps |
| CPU time | 139.46 seconds |
| Started | Oct 09 05:10:04 AM UTC 24 |
| Finished | Oct 09 05:12:26 AM UTC 24 |
| Peak memory | 216272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777244263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.3777244263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.3311307556 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 7405384304 ps |
| CPU time | 92.53 seconds |
| Started | Oct 09 05:09:25 AM UTC 24 |
| Finished | Oct 09 05:10:59 AM UTC 24 |
| Peak memory | 216276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311307556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.3311307556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.2305117946 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 113058181572 ps |
| CPU time | 234.55 seconds |
| Started | Oct 09 05:18:33 AM UTC 24 |
| Finished | Oct 09 05:22:32 AM UTC 24 |
| Peak memory | 214228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305117946 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.2305117946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device.187611935 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 539616340 ps |
| CPU time | 12.46 seconds |
| Started | Oct 09 05:09:04 AM UTC 24 |
| Finished | Oct 09 05:09:18 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187611935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.187611935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/0.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.2823713953 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 1013668618 ps |
| CPU time | 59.7 seconds |
| Started | Oct 09 05:09:15 AM UTC 24 |
| Finished | Oct 09 05:10:16 AM UTC 24 |
| Peak memory | 216532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823713953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.2823713953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.3952319453 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 2509374965 ps |
| CPU time | 22.44 seconds |
| Started | Oct 09 05:19:47 AM UTC 24 |
| Finished | Oct 09 05:20:11 AM UTC 24 |
| Peak memory | 212432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952319453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.3952319453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/47.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.827280711 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 38380880789 ps |
| CPU time | 259.47 seconds |
| Started | Oct 09 05:13:00 AM UTC 24 |
| Finished | Oct 09 05:17:24 AM UTC 24 |
| Peak memory | 214420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827280711 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.827280711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.3995637153 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 4637118098 ps |
| CPU time | 123.16 seconds |
| Started | Oct 09 05:16:02 AM UTC 24 |
| Finished | Oct 09 05:18:08 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995637153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.3995637153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_large_delays.3529042378 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 57603533036 ps |
| CPU time | 210.89 seconds |
| Started | Oct 09 05:12:27 AM UTC 24 |
| Finished | Oct 09 05:16:02 AM UTC 24 |
| Peak memory | 212436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529042378 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3529042378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/13.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_error_random.4214896814 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 2197354384 ps |
| CPU time | 17.24 seconds |
| Started | Oct 09 05:09:06 AM UTC 24 |
| Finished | Oct 09 05:09:24 AM UTC 24 |
| Peak memory | 212148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214896814 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.4214896814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/0.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all.3264730496 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 4226030295 ps |
| CPU time | 36.61 seconds |
| Started | Oct 09 05:12:07 AM UTC 24 |
| Finished | Oct 09 05:12:45 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264730496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.3264730496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/11.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.3596440832 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 29233249450 ps |
| CPU time | 198.63 seconds |
| Started | Oct 09 05:12:27 AM UTC 24 |
| Finished | Oct 09 05:15:50 AM UTC 24 |
| Peak memory | 214128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596440832 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.3596440832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random.4145240259 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 40720593 ps |
| CPU time | 7.16 seconds |
| Started | Oct 09 05:08:59 AM UTC 24 |
| Finished | Oct 09 05:09:07 AM UTC 24 |
| Peak memory | 212344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145240259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.4145240259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/0.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_large_delays.1778389016 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 100240050374 ps |
| CPU time | 194.1 seconds |
| Started | Oct 09 05:09:04 AM UTC 24 |
| Finished | Oct 09 05:12:21 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778389016 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1778389016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/0.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_slow_rsp.2840185497 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 75983003468 ps |
| CPU time | 122.62 seconds |
| Started | Oct 09 05:09:04 AM UTC 24 |
| Finished | Oct 09 05:11:09 AM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840185497 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.2840185497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/0.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke.2051137294 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 21476011 ps |
| CPU time | 2.08 seconds |
| Started | Oct 09 05:08:54 AM UTC 24 |
| Finished | Oct 09 05:08:57 AM UTC 24 |
| Peak memory | 212436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051137294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2051137294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/0.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.486435698 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1834314578 ps |
| CPU time | 6.85 seconds |
| Started | Oct 09 05:08:58 AM UTC 24 |
| Finished | Oct 09 05:09:06 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486435698 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.486435698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.123725869 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 8209463 ps |
| CPU time | 2.05 seconds |
| Started | Oct 09 05:08:56 AM UTC 24 |
| Finished | Oct 09 05:09:00 AM UTC 24 |
| Peak memory | 212356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123725869 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.123725869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/0.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all.752255457 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 190681575 ps |
| CPU time | 8.71 seconds |
| Started | Oct 09 05:09:08 AM UTC 24 |
| Finished | Oct 09 05:09:18 AM UTC 24 |
| Peak memory | 214248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752255457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.752255457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/0.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_error.2309488161 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 492406720 ps |
| CPU time | 57.54 seconds |
| Started | Oct 09 05:09:15 AM UTC 24 |
| Finished | Oct 09 05:10:14 AM UTC 24 |
| Peak memory | 214480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309488161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.2309488161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/0.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.315159076 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 192751886 ps |
| CPU time | 15.3 seconds |
| Started | Oct 09 05:09:10 AM UTC 24 |
| Finished | Oct 09 05:09:26 AM UTC 24 |
| Peak memory | 214160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315159076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.315159076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_unmapped_addr.2927192627 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 173103315 ps |
| CPU time | 6 seconds |
| Started | Oct 09 05:09:07 AM UTC 24 |
| Finished | Oct 09 05:09:14 AM UTC 24 |
| Peak memory | 212368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927192627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2927192627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/0.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.2284777292 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 515460233 ps |
| CPU time | 11.56 seconds |
| Started | Oct 09 05:09:22 AM UTC 24 |
| Finished | Oct 09 05:09:34 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284777292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.2284777292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_error_random.2161171611 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1590155209 ps |
| CPU time | 18.34 seconds |
| Started | Oct 09 05:09:20 AM UTC 24 |
| Finished | Oct 09 05:09:39 AM UTC 24 |
| Peak memory | 212084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161171611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2161171611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/1.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random.2138135971 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 274261379 ps |
| CPU time | 3.9 seconds |
| Started | Oct 09 05:09:17 AM UTC 24 |
| Finished | Oct 09 05:09:22 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138135971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.2138135971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/1.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_large_delays.1420615895 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 11285603559 ps |
| CPU time | 23.42 seconds |
| Started | Oct 09 05:09:19 AM UTC 24 |
| Finished | Oct 09 05:09:44 AM UTC 24 |
| Peak memory | 212428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420615895 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.1420615895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/1.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_slow_rsp.2811320384 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 42587107497 ps |
| CPU time | 124.44 seconds |
| Started | Oct 09 05:09:20 AM UTC 24 |
| Finished | Oct 09 05:11:26 AM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811320384 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2811320384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/1.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_zero_delays.1511151868 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 130372838 ps |
| CPU time | 9.55 seconds |
| Started | Oct 09 05:09:17 AM UTC 24 |
| Finished | Oct 09 05:09:28 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511151868 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.1511151868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/1.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_same_source.2937294010 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 42323323 ps |
| CPU time | 3.71 seconds |
| Started | Oct 09 05:09:20 AM UTC 24 |
| Finished | Oct 09 05:09:25 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937294010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2937294010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/1.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke.884002904 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11212556 ps |
| CPU time | 2 seconds |
| Started | Oct 09 05:09:15 AM UTC 24 |
| Finished | Oct 09 05:09:18 AM UTC 24 |
| Peak memory | 211144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884002904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.884002904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/1.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_large_delays.3108937266 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1919624218 ps |
| CPU time | 10.55 seconds |
| Started | Oct 09 05:09:15 AM UTC 24 |
| Finished | Oct 09 05:09:27 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108937266 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3108937266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/1.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.3180543413 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2284494470 ps |
| CPU time | 9.28 seconds |
| Started | Oct 09 05:09:17 AM UTC 24 |
| Finished | Oct 09 05:09:28 AM UTC 24 |
| Peak memory | 212220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180543413 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3180543413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.75855084 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11420401 ps |
| CPU time | 2.03 seconds |
| Started | Oct 09 05:09:15 AM UTC 24 |
| Finished | Oct 09 05:09:18 AM UTC 24 |
| Peak memory | 212364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75855084 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.75855084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/1.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_error.2449568291 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 196526724 ps |
| CPU time | 18.61 seconds |
| Started | Oct 09 05:09:26 AM UTC 24 |
| Finished | Oct 09 05:09:46 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449568291 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.2449568291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/1.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_unmapped_addr.2819609980 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 555615758 ps |
| CPU time | 8.81 seconds |
| Started | Oct 09 05:09:22 AM UTC 24 |
| Finished | Oct 09 05:09:32 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819609980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.2819609980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/1.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device.1017732906 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 83085995 ps |
| CPU time | 12.78 seconds |
| Started | Oct 09 05:11:49 AM UTC 24 |
| Finished | Oct 09 05:12:03 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017732906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.1017732906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/10.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.245301544 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 584502214 ps |
| CPU time | 12.19 seconds |
| Started | Oct 09 05:11:55 AM UTC 24 |
| Finished | Oct 09 05:12:09 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245301544 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.245301544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_error_random.1007981646 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 81025610 ps |
| CPU time | 8.69 seconds |
| Started | Oct 09 05:11:52 AM UTC 24 |
| Finished | Oct 09 05:12:02 AM UTC 24 |
| Peak memory | 212352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007981646 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.1007981646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/10.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random.1943211382 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 987157652 ps |
| CPU time | 17.92 seconds |
| Started | Oct 09 05:11:48 AM UTC 24 |
| Finished | Oct 09 05:12:08 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943211382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.1943211382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/10.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_large_delays.1245973272 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 15427533891 ps |
| CPU time | 35.58 seconds |
| Started | Oct 09 05:11:48 AM UTC 24 |
| Finished | Oct 09 05:12:26 AM UTC 24 |
| Peak memory | 212496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245973272 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1245973272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/10.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_slow_rsp.3044388952 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 15304448502 ps |
| CPU time | 98.58 seconds |
| Started | Oct 09 05:11:49 AM UTC 24 |
| Finished | Oct 09 05:13:29 AM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044388952 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3044388952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/10.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_zero_delays.680115416 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 52662859 ps |
| CPU time | 5.38 seconds |
| Started | Oct 09 05:11:48 AM UTC 24 |
| Finished | Oct 09 05:11:55 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680115416 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.680115416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/10.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_same_source.1778065952 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 59403497 ps |
| CPU time | 6.94 seconds |
| Started | Oct 09 05:11:52 AM UTC 24 |
| Finished | Oct 09 05:12:00 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778065952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1778065952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/10.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke.2842209468 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 153032265 ps |
| CPU time | 1.74 seconds |
| Started | Oct 09 05:11:45 AM UTC 24 |
| Finished | Oct 09 05:11:48 AM UTC 24 |
| Peak memory | 211188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842209468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2842209468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/10.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3937669795 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 3619027243 ps |
| CPU time | 13.72 seconds |
| Started | Oct 09 05:11:47 AM UTC 24 |
| Finished | Oct 09 05:12:02 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937669795 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3937669795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/10.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3304086292 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 2743635319 ps |
| CPU time | 19.48 seconds |
| Started | Oct 09 05:11:47 AM UTC 24 |
| Finished | Oct 09 05:12:08 AM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304086292 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3304086292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.968727436 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 17011482 ps |
| CPU time | 1.81 seconds |
| Started | Oct 09 05:11:47 AM UTC 24 |
| Finished | Oct 09 05:11:50 AM UTC 24 |
| Peak memory | 211144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968727436 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.968727436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/10.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all.3235194598 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 148654412 ps |
| CPU time | 1.98 seconds |
| Started | Oct 09 05:11:56 AM UTC 24 |
| Finished | Oct 09 05:11:59 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235194598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3235194598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/10.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_error.121647042 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 3622684704 ps |
| CPU time | 28.98 seconds |
| Started | Oct 09 05:11:57 AM UTC 24 |
| Finished | Oct 09 05:12:27 AM UTC 24 |
| Peak memory | 214220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121647042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.121647042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/10.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.1309112295 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 795141785 ps |
| CPU time | 161.06 seconds |
| Started | Oct 09 05:11:56 AM UTC 24 |
| Finished | Oct 09 05:14:40 AM UTC 24 |
| Peak memory | 216208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309112295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.1309112295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_unmapped_addr.1295501441 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 625804266 ps |
| CPU time | 10.77 seconds |
| Started | Oct 09 05:11:52 AM UTC 24 |
| Finished | Oct 09 05:12:04 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295501441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1295501441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/10.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device.1643588763 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 11220089 ps |
| CPU time | 1.95 seconds |
| Started | Oct 09 05:12:03 AM UTC 24 |
| Finished | Oct 09 05:12:06 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643588763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.1643588763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/11.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.3499151910 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 139601529 ps |
| CPU time | 7.03 seconds |
| Started | Oct 09 05:12:07 AM UTC 24 |
| Finished | Oct 09 05:12:15 AM UTC 24 |
| Peak memory | 212240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499151910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.3499151910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_error_random.1620514288 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 534571046 ps |
| CPU time | 2.3 seconds |
| Started | Oct 09 05:12:05 AM UTC 24 |
| Finished | Oct 09 05:12:09 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620514288 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1620514288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/11.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random.1899573065 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 22820429 ps |
| CPU time | 3.92 seconds |
| Started | Oct 09 05:12:02 AM UTC 24 |
| Finished | Oct 09 05:12:07 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899573065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.1899573065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/11.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_large_delays.4075927130 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 6931066408 ps |
| CPU time | 49.16 seconds |
| Started | Oct 09 05:12:03 AM UTC 24 |
| Finished | Oct 09 05:12:54 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075927130 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.4075927130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/11.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_slow_rsp.2483897916 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 16665373503 ps |
| CPU time | 83.48 seconds |
| Started | Oct 09 05:12:03 AM UTC 24 |
| Finished | Oct 09 05:13:28 AM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483897916 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.2483897916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/11.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_zero_delays.4291014037 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 10154339 ps |
| CPU time | 1.78 seconds |
| Started | Oct 09 05:12:03 AM UTC 24 |
| Finished | Oct 09 05:12:06 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291014037 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.4291014037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/11.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_same_source.3097500399 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 192597160 ps |
| CPU time | 4.39 seconds |
| Started | Oct 09 05:12:04 AM UTC 24 |
| Finished | Oct 09 05:12:10 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097500399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3097500399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/11.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke.3246122404 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 72374241 ps |
| CPU time | 2.62 seconds |
| Started | Oct 09 05:11:58 AM UTC 24 |
| Finished | Oct 09 05:12:02 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246122404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.3246122404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/11.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_large_delays.2959926572 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 6264313099 ps |
| CPU time | 13.73 seconds |
| Started | Oct 09 05:11:59 AM UTC 24 |
| Finished | Oct 09 05:12:14 AM UTC 24 |
| Peak memory | 212432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959926572 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2959926572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/11.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.220033278 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 998713275 ps |
| CPU time | 12.37 seconds |
| Started | Oct 09 05:12:00 AM UTC 24 |
| Finished | Oct 09 05:12:14 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220033278 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.220033278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.374157179 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 9343396 ps |
| CPU time | 1.84 seconds |
| Started | Oct 09 05:11:59 AM UTC 24 |
| Finished | Oct 09 05:12:02 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374157179 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.374157179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/11.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_error.2918523910 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 676992965 ps |
| CPU time | 40.95 seconds |
| Started | Oct 09 05:12:07 AM UTC 24 |
| Finished | Oct 09 05:12:50 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918523910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2918523910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/11.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.1852420968 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 209573060 ps |
| CPU time | 23.77 seconds |
| Started | Oct 09 05:12:07 AM UTC 24 |
| Finished | Oct 09 05:12:32 AM UTC 24 |
| Peak memory | 214356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852420968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.1852420968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.3185564542 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 635777022 ps |
| CPU time | 21.94 seconds |
| Started | Oct 09 05:12:08 AM UTC 24 |
| Finished | Oct 09 05:12:32 AM UTC 24 |
| Peak memory | 214420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185564542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.3185564542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_unmapped_addr.745599786 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 735088783 ps |
| CPU time | 12.06 seconds |
| Started | Oct 09 05:12:07 AM UTC 24 |
| Finished | Oct 09 05:12:20 AM UTC 24 |
| Peak memory | 212240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745599786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.745599786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/11.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device.344756796 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 60016839 ps |
| CPU time | 7.72 seconds |
| Started | Oct 09 05:12:13 AM UTC 24 |
| Finished | Oct 09 05:12:22 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344756796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.344756796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/12.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.2966741220 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 16752589748 ps |
| CPU time | 121.3 seconds |
| Started | Oct 09 05:12:15 AM UTC 24 |
| Finished | Oct 09 05:14:19 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966741220 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.2966741220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.1898545509 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 3503540005 ps |
| CPU time | 10.92 seconds |
| Started | Oct 09 05:12:17 AM UTC 24 |
| Finished | Oct 09 05:12:29 AM UTC 24 |
| Peak memory | 212432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898545509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.1898545509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_error_random.22306021 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 436832343 ps |
| CPU time | 8.64 seconds |
| Started | Oct 09 05:12:15 AM UTC 24 |
| Finished | Oct 09 05:12:25 AM UTC 24 |
| Peak memory | 212096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22306021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.22306021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/12.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random.2122353665 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 291557087 ps |
| CPU time | 4.67 seconds |
| Started | Oct 09 05:12:11 AM UTC 24 |
| Finished | Oct 09 05:12:17 AM UTC 24 |
| Peak memory | 212348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122353665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.2122353665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/12.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_large_delays.3934148169 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 47664126725 ps |
| CPU time | 85.29 seconds |
| Started | Oct 09 05:12:12 AM UTC 24 |
| Finished | Oct 09 05:13:39 AM UTC 24 |
| Peak memory | 212432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934148169 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3934148169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/12.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_slow_rsp.88704619 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 42449955385 ps |
| CPU time | 65.93 seconds |
| Started | Oct 09 05:12:12 AM UTC 24 |
| Finished | Oct 09 05:13:20 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88704619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.88704619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/12.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_zero_delays.2294806109 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 58086616 ps |
| CPU time | 2.38 seconds |
| Started | Oct 09 05:12:12 AM UTC 24 |
| Finished | Oct 09 05:12:15 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294806109 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.2294806109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/12.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_same_source.367004896 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 882216781 ps |
| CPU time | 4.76 seconds |
| Started | Oct 09 05:12:15 AM UTC 24 |
| Finished | Oct 09 05:12:21 AM UTC 24 |
| Peak memory | 212352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367004896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.367004896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/12.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke.2527456343 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 8645304 ps |
| CPU time | 1.68 seconds |
| Started | Oct 09 05:12:08 AM UTC 24 |
| Finished | Oct 09 05:12:11 AM UTC 24 |
| Peak memory | 211084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527456343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.2527456343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/12.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_large_delays.3273341449 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1603395941 ps |
| CPU time | 14.73 seconds |
| Started | Oct 09 05:12:10 AM UTC 24 |
| Finished | Oct 09 05:12:26 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273341449 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3273341449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/12.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.20897544 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 3647692395 ps |
| CPU time | 20.79 seconds |
| Started | Oct 09 05:12:10 AM UTC 24 |
| Finished | Oct 09 05:12:32 AM UTC 24 |
| Peak memory | 212496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20897544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.20897544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.2986991323 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 11207992 ps |
| CPU time | 1.82 seconds |
| Started | Oct 09 05:12:08 AM UTC 24 |
| Finished | Oct 09 05:12:11 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986991323 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.2986991323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/12.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all.1871255591 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 718275422 ps |
| CPU time | 28.9 seconds |
| Started | Oct 09 05:12:18 AM UTC 24 |
| Finished | Oct 09 05:12:48 AM UTC 24 |
| Peak memory | 214420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871255591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1871255591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/12.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_error.2364240466 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 2116608743 ps |
| CPU time | 40.13 seconds |
| Started | Oct 09 05:12:18 AM UTC 24 |
| Finished | Oct 09 05:13:00 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364240466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.2364240466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/12.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.2163195694 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 13670259 ps |
| CPU time | 5.2 seconds |
| Started | Oct 09 05:12:18 AM UTC 24 |
| Finished | Oct 09 05:12:24 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163195694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.2163195694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3181898711 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1567842184 ps |
| CPU time | 79.69 seconds |
| Started | Oct 09 05:12:21 AM UTC 24 |
| Finished | Oct 09 05:13:43 AM UTC 24 |
| Peak memory | 216340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181898711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.3181898711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_unmapped_addr.2347093261 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 753360861 ps |
| CPU time | 15.19 seconds |
| Started | Oct 09 05:12:17 AM UTC 24 |
| Finished | Oct 09 05:12:33 AM UTC 24 |
| Peak memory | 212368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347093261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2347093261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/12.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device.402665314 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 41976671 ps |
| CPU time | 2.6 seconds |
| Started | Oct 09 05:12:27 AM UTC 24 |
| Finished | Oct 09 05:12:31 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402665314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.402665314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/13.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.2972396085 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 274836992 ps |
| CPU time | 4.5 seconds |
| Started | Oct 09 05:12:29 AM UTC 24 |
| Finished | Oct 09 05:12:35 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972396085 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.2972396085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_error_random.278830414 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 2266442488 ps |
| CPU time | 18.88 seconds |
| Started | Oct 09 05:12:28 AM UTC 24 |
| Finished | Oct 09 05:12:48 AM UTC 24 |
| Peak memory | 212144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278830414 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.278830414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/13.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random.532518043 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 1626755751 ps |
| CPU time | 5.84 seconds |
| Started | Oct 09 05:12:27 AM UTC 24 |
| Finished | Oct 09 05:12:34 AM UTC 24 |
| Peak memory | 212348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532518043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.532518043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/13.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_slow_rsp.1797551048 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 6526143027 ps |
| CPU time | 48.32 seconds |
| Started | Oct 09 05:12:27 AM UTC 24 |
| Finished | Oct 09 05:13:17 AM UTC 24 |
| Peak memory | 212484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797551048 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.1797551048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/13.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_zero_delays.1547213538 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 143863724 ps |
| CPU time | 6.95 seconds |
| Started | Oct 09 05:12:27 AM UTC 24 |
| Finished | Oct 09 05:12:36 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547213538 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.1547213538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/13.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_same_source.292132949 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 3584420900 ps |
| CPU time | 16.57 seconds |
| Started | Oct 09 05:12:28 AM UTC 24 |
| Finished | Oct 09 05:12:45 AM UTC 24 |
| Peak memory | 212164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292132949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.292132949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/13.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke.2976850946 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 9834488 ps |
| CPU time | 1.85 seconds |
| Started | Oct 09 05:12:22 AM UTC 24 |
| Finished | Oct 09 05:12:25 AM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976850946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.2976850946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/13.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_large_delays.4025626544 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 3034767132 ps |
| CPU time | 8.86 seconds |
| Started | Oct 09 05:12:23 AM UTC 24 |
| Finished | Oct 09 05:12:33 AM UTC 24 |
| Peak memory | 212432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025626544 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.4025626544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/13.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.4159931291 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 1258477376 ps |
| CPU time | 6.2 seconds |
| Started | Oct 09 05:12:24 AM UTC 24 |
| Finished | Oct 09 05:12:32 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159931291 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.4159931291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.1193600036 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 19165399 ps |
| CPU time | 1.81 seconds |
| Started | Oct 09 05:12:22 AM UTC 24 |
| Finished | Oct 09 05:12:25 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193600036 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.1193600036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/13.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all.1791522229 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 4110976956 ps |
| CPU time | 29.4 seconds |
| Started | Oct 09 05:12:29 AM UTC 24 |
| Finished | Oct 09 05:13:00 AM UTC 24 |
| Peak memory | 212184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791522229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1791522229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/13.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_error.2662595321 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 2408572640 ps |
| CPU time | 42.03 seconds |
| Started | Oct 09 05:12:29 AM UTC 24 |
| Finished | Oct 09 05:13:13 AM UTC 24 |
| Peak memory | 214200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662595321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2662595321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/13.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.529317701 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 519939682 ps |
| CPU time | 44.78 seconds |
| Started | Oct 09 05:12:29 AM UTC 24 |
| Finished | Oct 09 05:13:16 AM UTC 24 |
| Peak memory | 216204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529317701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.529317701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.4244828795 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 204118906 ps |
| CPU time | 19.81 seconds |
| Started | Oct 09 05:12:30 AM UTC 24 |
| Finished | Oct 09 05:12:51 AM UTC 24 |
| Peak memory | 214160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244828795 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.4244828795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_unmapped_addr.61480984 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 86600424 ps |
| CPU time | 3.88 seconds |
| Started | Oct 09 05:12:28 AM UTC 24 |
| Finished | Oct 09 05:12:33 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61480984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.61480984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/13.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device.1109398692 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 96969085 ps |
| CPU time | 12.76 seconds |
| Started | Oct 09 05:12:36 AM UTC 24 |
| Finished | Oct 09 05:12:50 AM UTC 24 |
| Peak memory | 212368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109398692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.1109398692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/14.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.3982812891 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 117740598818 ps |
| CPU time | 331.48 seconds |
| Started | Oct 09 05:12:36 AM UTC 24 |
| Finished | Oct 09 05:18:12 AM UTC 24 |
| Peak memory | 214228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982812891 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.3982812891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.3315282292 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 153797344 ps |
| CPU time | 4.37 seconds |
| Started | Oct 09 05:12:38 AM UTC 24 |
| Finished | Oct 09 05:12:44 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315282292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.3315282292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_error_random.183516833 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 1301350820 ps |
| CPU time | 5.03 seconds |
| Started | Oct 09 05:12:37 AM UTC 24 |
| Finished | Oct 09 05:12:44 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183516833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.183516833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/14.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random.2338723408 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 59948539 ps |
| CPU time | 6.21 seconds |
| Started | Oct 09 05:12:34 AM UTC 24 |
| Finished | Oct 09 05:12:42 AM UTC 24 |
| Peak memory | 212352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338723408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.2338723408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/14.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_large_delays.3392458239 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 68808316596 ps |
| CPU time | 252.4 seconds |
| Started | Oct 09 05:12:34 AM UTC 24 |
| Finished | Oct 09 05:16:51 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392458239 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3392458239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/14.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_slow_rsp.2673776210 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 27393670267 ps |
| CPU time | 82.16 seconds |
| Started | Oct 09 05:12:35 AM UTC 24 |
| Finished | Oct 09 05:13:59 AM UTC 24 |
| Peak memory | 212164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673776210 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.2673776210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/14.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_zero_delays.2695633164 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 16366130 ps |
| CPU time | 2.33 seconds |
| Started | Oct 09 05:12:34 AM UTC 24 |
| Finished | Oct 09 05:12:38 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695633164 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2695633164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/14.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_same_source.185915358 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 2756132030 ps |
| CPU time | 18.98 seconds |
| Started | Oct 09 05:12:36 AM UTC 24 |
| Finished | Oct 09 05:12:56 AM UTC 24 |
| Peak memory | 214184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185915358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.185915358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/14.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke.949094900 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 12034498 ps |
| CPU time | 1.46 seconds |
| Started | Oct 09 05:12:32 AM UTC 24 |
| Finished | Oct 09 05:12:34 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949094900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.949094900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/14.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_large_delays.1217263753 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1806558242 ps |
| CPU time | 10.51 seconds |
| Started | Oct 09 05:12:33 AM UTC 24 |
| Finished | Oct 09 05:12:45 AM UTC 24 |
| Peak memory | 212364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217263753 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.1217263753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/14.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2752757419 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 810531524 ps |
| CPU time | 10.68 seconds |
| Started | Oct 09 05:12:33 AM UTC 24 |
| Finished | Oct 09 05:12:45 AM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752757419 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2752757419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.3159602361 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 8165432 ps |
| CPU time | 1.57 seconds |
| Started | Oct 09 05:12:33 AM UTC 24 |
| Finished | Oct 09 05:12:36 AM UTC 24 |
| Peak memory | 211136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159602361 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.3159602361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/14.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all.3820590047 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 4995115377 ps |
| CPU time | 79.29 seconds |
| Started | Oct 09 05:12:38 AM UTC 24 |
| Finished | Oct 09 05:14:00 AM UTC 24 |
| Peak memory | 214356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820590047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3820590047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/14.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_error.545780527 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 349983070 ps |
| CPU time | 24.03 seconds |
| Started | Oct 09 05:12:41 AM UTC 24 |
| Finished | Oct 09 05:13:07 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545780527 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.545780527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/14.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.1436932334 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1016420790 ps |
| CPU time | 94.21 seconds |
| Started | Oct 09 05:12:39 AM UTC 24 |
| Finished | Oct 09 05:14:16 AM UTC 24 |
| Peak memory | 216208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436932334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.1436932334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.2577870370 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 4610383346 ps |
| CPU time | 98.23 seconds |
| Started | Oct 09 05:12:43 AM UTC 24 |
| Finished | Oct 09 05:14:24 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577870370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.2577870370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_unmapped_addr.2521205855 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 1649799757 ps |
| CPU time | 17.81 seconds |
| Started | Oct 09 05:12:37 AM UTC 24 |
| Finished | Oct 09 05:12:56 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521205855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2521205855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/14.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device.1714278651 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 26661407 ps |
| CPU time | 5.54 seconds |
| Started | Oct 09 05:12:49 AM UTC 24 |
| Finished | Oct 09 05:12:56 AM UTC 24 |
| Peak memory | 212436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714278651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.1714278651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/15.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.3776465733 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 165729109 ps |
| CPU time | 2.93 seconds |
| Started | Oct 09 05:12:52 AM UTC 24 |
| Finished | Oct 09 05:12:56 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776465733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.3776465733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_error_random.1384725993 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 92276982 ps |
| CPU time | 6.56 seconds |
| Started | Oct 09 05:12:51 AM UTC 24 |
| Finished | Oct 09 05:12:58 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384725993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.1384725993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/15.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random.2622250310 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 702494148 ps |
| CPU time | 9.82 seconds |
| Started | Oct 09 05:12:46 AM UTC 24 |
| Finished | Oct 09 05:12:57 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622250310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2622250310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/15.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_large_delays.2846550904 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 22316547247 ps |
| CPU time | 99.93 seconds |
| Started | Oct 09 05:12:48 AM UTC 24 |
| Finished | Oct 09 05:14:31 AM UTC 24 |
| Peak memory | 212180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846550904 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2846550904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/15.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_slow_rsp.2624560160 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 11843511097 ps |
| CPU time | 69.51 seconds |
| Started | Oct 09 05:12:49 AM UTC 24 |
| Finished | Oct 09 05:14:01 AM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624560160 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.2624560160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/15.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_zero_delays.3064124997 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 18093423 ps |
| CPU time | 1.83 seconds |
| Started | Oct 09 05:12:47 AM UTC 24 |
| Finished | Oct 09 05:12:50 AM UTC 24 |
| Peak memory | 211084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064124997 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.3064124997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/15.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_same_source.4102512928 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 59573848 ps |
| CPU time | 8.04 seconds |
| Started | Oct 09 05:12:50 AM UTC 24 |
| Finished | Oct 09 05:13:00 AM UTC 24 |
| Peak memory | 212100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102512928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.4102512928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/15.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke.3461853651 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 57495391 ps |
| CPU time | 2.19 seconds |
| Started | Oct 09 05:12:44 AM UTC 24 |
| Finished | Oct 09 05:12:48 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461853651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3461853651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/15.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_large_delays.2162763965 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 6930408292 ps |
| CPU time | 10.52 seconds |
| Started | Oct 09 05:12:46 AM UTC 24 |
| Finished | Oct 09 05:12:57 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162763965 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2162763965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/15.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.1861676415 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 3475038295 ps |
| CPU time | 8.35 seconds |
| Started | Oct 09 05:12:46 AM UTC 24 |
| Finished | Oct 09 05:12:55 AM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861676415 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.1861676415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.1762715161 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 14388526 ps |
| CPU time | 1.99 seconds |
| Started | Oct 09 05:12:44 AM UTC 24 |
| Finished | Oct 09 05:12:48 AM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762715161 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.1762715161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/15.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all.784346002 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 6256765707 ps |
| CPU time | 74.44 seconds |
| Started | Oct 09 05:12:55 AM UTC 24 |
| Finished | Oct 09 05:14:11 AM UTC 24 |
| Peak memory | 214220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784346002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.784346002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/15.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3231252096 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 4416300725 ps |
| CPU time | 76.62 seconds |
| Started | Oct 09 05:12:56 AM UTC 24 |
| Finished | Oct 09 05:14:15 AM UTC 24 |
| Peak memory | 214480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231252096 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3231252096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/15.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.1773778430 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 853898603 ps |
| CPU time | 86.78 seconds |
| Started | Oct 09 05:12:56 AM UTC 24 |
| Finished | Oct 09 05:14:26 AM UTC 24 |
| Peak memory | 216208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773778430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.1773778430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_unmapped_addr.2326539881 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 156600489 ps |
| CPU time | 7.56 seconds |
| Started | Oct 09 05:12:51 AM UTC 24 |
| Finished | Oct 09 05:12:59 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326539881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.2326539881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/15.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device.624545808 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 100423593 ps |
| CPU time | 5.57 seconds |
| Started | Oct 09 05:13:00 AM UTC 24 |
| Finished | Oct 09 05:13:07 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624545808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.624545808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/16.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.2255355711 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 78033448 ps |
| CPU time | 2.97 seconds |
| Started | Oct 09 05:13:02 AM UTC 24 |
| Finished | Oct 09 05:13:06 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255355711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.2255355711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_error_random.484562402 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 81489478 ps |
| CPU time | 2.94 seconds |
| Started | Oct 09 05:13:02 AM UTC 24 |
| Finished | Oct 09 05:13:06 AM UTC 24 |
| Peak memory | 212344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484562402 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.484562402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/16.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random.1602251357 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 154416557 ps |
| CPU time | 1.98 seconds |
| Started | Oct 09 05:12:58 AM UTC 24 |
| Finished | Oct 09 05:13:01 AM UTC 24 |
| Peak memory | 211084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602251357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.1602251357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/16.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_large_delays.2587661638 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 104526203542 ps |
| CPU time | 168.59 seconds |
| Started | Oct 09 05:12:59 AM UTC 24 |
| Finished | Oct 09 05:15:50 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587661638 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2587661638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/16.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_slow_rsp.515618212 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 8229378528 ps |
| CPU time | 73.4 seconds |
| Started | Oct 09 05:13:00 AM UTC 24 |
| Finished | Oct 09 05:14:16 AM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515618212 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.515618212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/16.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_zero_delays.3237865052 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 25311017 ps |
| CPU time | 3.08 seconds |
| Started | Oct 09 05:12:59 AM UTC 24 |
| Finished | Oct 09 05:13:03 AM UTC 24 |
| Peak memory | 212364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237865052 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.3237865052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/16.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_same_source.2940058171 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 2614616547 ps |
| CPU time | 17.16 seconds |
| Started | Oct 09 05:13:01 AM UTC 24 |
| Finished | Oct 09 05:13:19 AM UTC 24 |
| Peak memory | 212168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940058171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2940058171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/16.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke.256480804 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 60351463 ps |
| CPU time | 2.6 seconds |
| Started | Oct 09 05:12:57 AM UTC 24 |
| Finished | Oct 09 05:13:00 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256480804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.256480804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/16.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_large_delays.2555209990 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 5274840019 ps |
| CPU time | 13.27 seconds |
| Started | Oct 09 05:12:58 AM UTC 24 |
| Finished | Oct 09 05:13:12 AM UTC 24 |
| Peak memory | 212496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555209990 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2555209990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/16.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.2227130541 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1636967449 ps |
| CPU time | 10.86 seconds |
| Started | Oct 09 05:12:58 AM UTC 24 |
| Finished | Oct 09 05:13:10 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227130541 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2227130541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.873715997 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 11247178 ps |
| CPU time | 1.92 seconds |
| Started | Oct 09 05:12:57 AM UTC 24 |
| Finished | Oct 09 05:13:00 AM UTC 24 |
| Peak memory | 211084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873715997 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.873715997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/16.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all.1487530954 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 9320813341 ps |
| CPU time | 43.63 seconds |
| Started | Oct 09 05:13:03 AM UTC 24 |
| Finished | Oct 09 05:13:49 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487530954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.1487530954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/16.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_error.717149402 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 466204354 ps |
| CPU time | 16.12 seconds |
| Started | Oct 09 05:13:06 AM UTC 24 |
| Finished | Oct 09 05:13:24 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717149402 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.717149402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/16.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.2220993350 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 468635407 ps |
| CPU time | 66.16 seconds |
| Started | Oct 09 05:13:04 AM UTC 24 |
| Finished | Oct 09 05:14:12 AM UTC 24 |
| Peak memory | 214420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220993350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.2220993350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.3965622204 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 1414201855 ps |
| CPU time | 54.02 seconds |
| Started | Oct 09 05:13:06 AM UTC 24 |
| Finished | Oct 09 05:14:02 AM UTC 24 |
| Peak memory | 216212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965622204 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.3965622204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_unmapped_addr.504975197 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 292470261 ps |
| CPU time | 10.3 seconds |
| Started | Oct 09 05:13:02 AM UTC 24 |
| Finished | Oct 09 05:13:13 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504975197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.504975197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/16.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device.397212062 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1110772780 ps |
| CPU time | 21.66 seconds |
| Started | Oct 09 05:13:14 AM UTC 24 |
| Finished | Oct 09 05:13:37 AM UTC 24 |
| Peak memory | 212436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397212062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.397212062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/17.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.896879326 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 87494017183 ps |
| CPU time | 257.11 seconds |
| Started | Oct 09 05:13:17 AM UTC 24 |
| Finished | Oct 09 05:17:38 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896879326 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.896879326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.565949036 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 89163915 ps |
| CPU time | 6.22 seconds |
| Started | Oct 09 05:13:19 AM UTC 24 |
| Finished | Oct 09 05:13:27 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565949036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.565949036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_error_random.2254169051 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 99910478 ps |
| CPU time | 3.59 seconds |
| Started | Oct 09 05:13:18 AM UTC 24 |
| Finished | Oct 09 05:13:23 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254169051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2254169051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/17.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random.4044718400 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1090313353 ps |
| CPU time | 14.06 seconds |
| Started | Oct 09 05:13:12 AM UTC 24 |
| Finished | Oct 09 05:13:27 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044718400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.4044718400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/17.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_large_delays.191412001 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 29817931425 ps |
| CPU time | 167.32 seconds |
| Started | Oct 09 05:13:14 AM UTC 24 |
| Finished | Oct 09 05:16:04 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191412001 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.191412001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/17.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_slow_rsp.1249732317 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 22778106223 ps |
| CPU time | 181.85 seconds |
| Started | Oct 09 05:13:14 AM UTC 24 |
| Finished | Oct 09 05:16:19 AM UTC 24 |
| Peak memory | 212420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249732317 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.1249732317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/17.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_zero_delays.4270855759 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 66395363 ps |
| CPU time | 8.82 seconds |
| Started | Oct 09 05:13:13 AM UTC 24 |
| Finished | Oct 09 05:13:23 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270855759 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.4270855759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/17.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_same_source.3717492328 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 991202758 ps |
| CPU time | 13.05 seconds |
| Started | Oct 09 05:13:18 AM UTC 24 |
| Finished | Oct 09 05:13:32 AM UTC 24 |
| Peak memory | 212100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717492328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3717492328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/17.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke.852409487 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 184892804 ps |
| CPU time | 2.14 seconds |
| Started | Oct 09 05:13:08 AM UTC 24 |
| Finished | Oct 09 05:13:11 AM UTC 24 |
| Peak memory | 212364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852409487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.852409487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/17.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_large_delays.967280035 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 1830489867 ps |
| CPU time | 13.61 seconds |
| Started | Oct 09 05:13:11 AM UTC 24 |
| Finished | Oct 09 05:13:26 AM UTC 24 |
| Peak memory | 212240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967280035 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.967280035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/17.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.2090248359 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 1350358109 ps |
| CPU time | 9.52 seconds |
| Started | Oct 09 05:13:12 AM UTC 24 |
| Finished | Oct 09 05:13:23 AM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090248359 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2090248359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.3313558010 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 9420804 ps |
| CPU time | 1.74 seconds |
| Started | Oct 09 05:13:08 AM UTC 24 |
| Finished | Oct 09 05:13:10 AM UTC 24 |
| Peak memory | 211080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313558010 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.3313558010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/17.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all.2525048859 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 4747802269 ps |
| CPU time | 68.47 seconds |
| Started | Oct 09 05:13:19 AM UTC 24 |
| Finished | Oct 09 05:14:30 AM UTC 24 |
| Peak memory | 214484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525048859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.2525048859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/17.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_error.1278377101 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 6286617820 ps |
| CPU time | 49.97 seconds |
| Started | Oct 09 05:13:24 AM UTC 24 |
| Finished | Oct 09 05:14:15 AM UTC 24 |
| Peak memory | 214472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278377101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.1278377101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/17.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.362981167 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 633440801 ps |
| CPU time | 104.2 seconds |
| Started | Oct 09 05:13:21 AM UTC 24 |
| Finished | Oct 09 05:15:07 AM UTC 24 |
| Peak memory | 218512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362981167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.362981167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.3653030306 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 2233687346 ps |
| CPU time | 69.85 seconds |
| Started | Oct 09 05:13:24 AM UTC 24 |
| Finished | Oct 09 05:14:36 AM UTC 24 |
| Peak memory | 216272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653030306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.3653030306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_unmapped_addr.2719787762 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 64545272 ps |
| CPU time | 8.04 seconds |
| Started | Oct 09 05:13:18 AM UTC 24 |
| Finished | Oct 09 05:13:27 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719787762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2719787762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/17.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device.3850521880 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 1027869844 ps |
| CPU time | 15.07 seconds |
| Started | Oct 09 05:13:30 AM UTC 24 |
| Finished | Oct 09 05:13:46 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850521880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.3850521880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/18.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.2177021860 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 50905827058 ps |
| CPU time | 318.36 seconds |
| Started | Oct 09 05:13:31 AM UTC 24 |
| Finished | Oct 09 05:18:54 AM UTC 24 |
| Peak memory | 215796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177021860 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.2177021860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3477901867 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 17840977 ps |
| CPU time | 2.42 seconds |
| Started | Oct 09 05:13:34 AM UTC 24 |
| Finished | Oct 09 05:13:37 AM UTC 24 |
| Peak memory | 212368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477901867 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3477901867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_error_random.96278261 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 22848611 ps |
| CPU time | 2.67 seconds |
| Started | Oct 09 05:13:32 AM UTC 24 |
| Finished | Oct 09 05:13:36 AM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96278261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.96278261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/18.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random.452846913 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 108653106 ps |
| CPU time | 10.04 seconds |
| Started | Oct 09 05:13:28 AM UTC 24 |
| Finished | Oct 09 05:13:40 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452846913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.452846913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/18.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_large_delays.2227486891 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 10581633392 ps |
| CPU time | 50 seconds |
| Started | Oct 09 05:13:28 AM UTC 24 |
| Finished | Oct 09 05:14:21 AM UTC 24 |
| Peak memory | 212428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227486891 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.2227486891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/18.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_slow_rsp.1602618042 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 3170855169 ps |
| CPU time | 39.47 seconds |
| Started | Oct 09 05:13:29 AM UTC 24 |
| Finished | Oct 09 05:14:10 AM UTC 24 |
| Peak memory | 212164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602618042 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1602618042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/18.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_zero_delays.819861242 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 29807184 ps |
| CPU time | 2.9 seconds |
| Started | Oct 09 05:13:28 AM UTC 24 |
| Finished | Oct 09 05:13:33 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819861242 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.819861242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/18.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_same_source.1393013487 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 976714023 ps |
| CPU time | 18.23 seconds |
| Started | Oct 09 05:13:32 AM UTC 24 |
| Finished | Oct 09 05:13:52 AM UTC 24 |
| Peak memory | 212424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393013487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.1393013487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/18.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke.1617653266 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 36357143 ps |
| CPU time | 1.35 seconds |
| Started | Oct 09 05:13:24 AM UTC 24 |
| Finished | Oct 09 05:13:26 AM UTC 24 |
| Peak memory | 211080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617653266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.1617653266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/18.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_large_delays.3691512649 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1480508144 ps |
| CPU time | 9.42 seconds |
| Started | Oct 09 05:13:26 AM UTC 24 |
| Finished | Oct 09 05:13:37 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691512649 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.3691512649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/18.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.1834106772 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 5011498005 ps |
| CPU time | 12.12 seconds |
| Started | Oct 09 05:13:27 AM UTC 24 |
| Finished | Oct 09 05:13:41 AM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834106772 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.1834106772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.3820308586 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 11515915 ps |
| CPU time | 1.54 seconds |
| Started | Oct 09 05:13:25 AM UTC 24 |
| Finished | Oct 09 05:13:28 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820308586 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.3820308586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/18.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all.970103494 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 58272159 ps |
| CPU time | 7.06 seconds |
| Started | Oct 09 05:13:37 AM UTC 24 |
| Finished | Oct 09 05:13:45 AM UTC 24 |
| Peak memory | 212240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970103494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.970103494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/18.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_error.3104286329 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 6391222 ps |
| CPU time | 1.33 seconds |
| Started | Oct 09 05:13:38 AM UTC 24 |
| Finished | Oct 09 05:13:40 AM UTC 24 |
| Peak memory | 202264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104286329 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3104286329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/18.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.1733666976 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 556450221 ps |
| CPU time | 41.98 seconds |
| Started | Oct 09 05:13:38 AM UTC 24 |
| Finished | Oct 09 05:14:22 AM UTC 24 |
| Peak memory | 216212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733666976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.1733666976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.2268800993 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 724592921 ps |
| CPU time | 74.16 seconds |
| Started | Oct 09 05:13:38 AM UTC 24 |
| Finished | Oct 09 05:14:54 AM UTC 24 |
| Peak memory | 216340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268800993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.2268800993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_unmapped_addr.2974021091 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 74326322 ps |
| CPU time | 7.59 seconds |
| Started | Oct 09 05:13:33 AM UTC 24 |
| Finished | Oct 09 05:13:43 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974021091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.2974021091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/18.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device.3581587281 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 247183288 ps |
| CPU time | 16.07 seconds |
| Started | Oct 09 05:13:45 AM UTC 24 |
| Finished | Oct 09 05:14:03 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581587281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.3581587281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/19.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.2978143087 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 58852614907 ps |
| CPU time | 270.02 seconds |
| Started | Oct 09 05:13:46 AM UTC 24 |
| Finished | Oct 09 05:18:20 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978143087 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.2978143087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.3170011486 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 19027847 ps |
| CPU time | 2.6 seconds |
| Started | Oct 09 05:13:53 AM UTC 24 |
| Finished | Oct 09 05:13:56 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170011486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.3170011486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_error_random.1234746969 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 364908151 ps |
| CPU time | 7.41 seconds |
| Started | Oct 09 05:13:49 AM UTC 24 |
| Finished | Oct 09 05:13:58 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234746969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1234746969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/19.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random.3760430111 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 101250073 ps |
| CPU time | 9.77 seconds |
| Started | Oct 09 05:13:42 AM UTC 24 |
| Finished | Oct 09 05:13:53 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760430111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.3760430111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/19.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_large_delays.2230382494 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 71657684694 ps |
| CPU time | 126.8 seconds |
| Started | Oct 09 05:13:44 AM UTC 24 |
| Finished | Oct 09 05:15:53 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230382494 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2230382494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/19.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_slow_rsp.627886255 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 21521739588 ps |
| CPU time | 106.37 seconds |
| Started | Oct 09 05:13:44 AM UTC 24 |
| Finished | Oct 09 05:15:33 AM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627886255 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.627886255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/19.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_zero_delays.1769273656 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 51639854 ps |
| CPU time | 6.61 seconds |
| Started | Oct 09 05:13:43 AM UTC 24 |
| Finished | Oct 09 05:13:51 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769273656 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.1769273656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/19.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_same_source.4186835071 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 102900168 ps |
| CPU time | 7.24 seconds |
| Started | Oct 09 05:13:47 AM UTC 24 |
| Finished | Oct 09 05:13:56 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186835071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.4186835071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/19.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke.625928902 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 24278905 ps |
| CPU time | 1.94 seconds |
| Started | Oct 09 05:13:39 AM UTC 24 |
| Finished | Oct 09 05:13:42 AM UTC 24 |
| Peak memory | 211144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625928902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.625928902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/19.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_large_delays.826748104 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 2472359216 ps |
| CPU time | 13.17 seconds |
| Started | Oct 09 05:13:41 AM UTC 24 |
| Finished | Oct 09 05:13:57 AM UTC 24 |
| Peak memory | 211668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826748104 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.826748104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/19.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.3167599540 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 811093327 ps |
| CPU time | 11.84 seconds |
| Started | Oct 09 05:13:41 AM UTC 24 |
| Finished | Oct 09 05:13:55 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167599540 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3167599540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.4175271096 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 8282076 ps |
| CPU time | 1.63 seconds |
| Started | Oct 09 05:13:40 AM UTC 24 |
| Finished | Oct 09 05:13:44 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175271096 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.4175271096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/19.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all.613762063 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 485706159 ps |
| CPU time | 24.76 seconds |
| Started | Oct 09 05:13:54 AM UTC 24 |
| Finished | Oct 09 05:14:20 AM UTC 24 |
| Peak memory | 214156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613762063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.613762063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/19.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_error.1575266454 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 2092988915 ps |
| CPU time | 33 seconds |
| Started | Oct 09 05:13:57 AM UTC 24 |
| Finished | Oct 09 05:14:32 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575266454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1575266454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/19.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.3428488505 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 1208913352 ps |
| CPU time | 77.8 seconds |
| Started | Oct 09 05:13:57 AM UTC 24 |
| Finished | Oct 09 05:15:17 AM UTC 24 |
| Peak memory | 216208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428488505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.3428488505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.3321352490 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 1064547231 ps |
| CPU time | 132.18 seconds |
| Started | Oct 09 05:13:57 AM UTC 24 |
| Finished | Oct 09 05:16:12 AM UTC 24 |
| Peak memory | 218256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321352490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.3321352490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_unmapped_addr.4249673713 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 54718561 ps |
| CPU time | 5.93 seconds |
| Started | Oct 09 05:13:53 AM UTC 24 |
| Finished | Oct 09 05:14:00 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249673713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.4249673713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/19.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device.1611437940 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 83053332 ps |
| CPU time | 15.4 seconds |
| Started | Oct 09 05:09:32 AM UTC 24 |
| Finished | Oct 09 05:09:49 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611437940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.1611437940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/2.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.2809341140 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 194399263 ps |
| CPU time | 4.66 seconds |
| Started | Oct 09 05:09:45 AM UTC 24 |
| Finished | Oct 09 05:09:50 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809341140 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.2809341140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_error_random.282745832 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 49063443 ps |
| CPU time | 8 seconds |
| Started | Oct 09 05:09:40 AM UTC 24 |
| Finished | Oct 09 05:09:50 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282745832 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.282745832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/2.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random.1403205804 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 130006384 ps |
| CPU time | 11.27 seconds |
| Started | Oct 09 05:09:31 AM UTC 24 |
| Finished | Oct 09 05:09:43 AM UTC 24 |
| Peak memory | 212084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403205804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.1403205804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/2.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_large_delays.166331235 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 23875614562 ps |
| CPU time | 83.23 seconds |
| Started | Oct 09 05:09:31 AM UTC 24 |
| Finished | Oct 09 05:10:56 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166331235 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.166331235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/2.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_slow_rsp.696745280 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 46545787379 ps |
| CPU time | 220.8 seconds |
| Started | Oct 09 05:09:32 AM UTC 24 |
| Finished | Oct 09 05:13:16 AM UTC 24 |
| Peak memory | 212152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696745280 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.696745280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/2.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_zero_delays.3612018317 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 121273678 ps |
| CPU time | 9 seconds |
| Started | Oct 09 05:09:31 AM UTC 24 |
| Finished | Oct 09 05:09:41 AM UTC 24 |
| Peak memory | 212364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612018317 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.3612018317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/2.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_same_source.2700227020 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1795543018 ps |
| CPU time | 17.49 seconds |
| Started | Oct 09 05:09:35 AM UTC 24 |
| Finished | Oct 09 05:09:54 AM UTC 24 |
| Peak memory | 212100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700227020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.2700227020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/2.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke.1629889460 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 12070266 ps |
| CPU time | 1.6 seconds |
| Started | Oct 09 05:09:27 AM UTC 24 |
| Finished | Oct 09 05:09:30 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629889460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.1629889460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/2.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_large_delays.42512288 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 13049608238 ps |
| CPU time | 20.18 seconds |
| Started | Oct 09 05:09:29 AM UTC 24 |
| Finished | Oct 09 05:09:50 AM UTC 24 |
| Peak memory | 212432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42512288 -assert nopostproc +UVM_TESTNAME=xbar_base_ test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.42512288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/2.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.3296722130 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 3319628929 ps |
| CPU time | 22.66 seconds |
| Started | Oct 09 05:09:29 AM UTC 24 |
| Finished | Oct 09 05:09:53 AM UTC 24 |
| Peak memory | 211756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296722130 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.3296722130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.2628693637 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 9514979 ps |
| CPU time | 2.14 seconds |
| Started | Oct 09 05:09:29 AM UTC 24 |
| Finished | Oct 09 05:09:32 AM UTC 24 |
| Peak memory | 211712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628693637 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.2628693637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/2.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all.342995372 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 4291331435 ps |
| CPU time | 33.64 seconds |
| Started | Oct 09 05:09:45 AM UTC 24 |
| Finished | Oct 09 05:10:20 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342995372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.342995372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/2.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_error.1545957303 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 883888386 ps |
| CPU time | 51.78 seconds |
| Started | Oct 09 05:09:47 AM UTC 24 |
| Finished | Oct 09 05:10:41 AM UTC 24 |
| Peak memory | 214164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545957303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1545957303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/2.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.1792618740 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 9392279903 ps |
| CPU time | 207.43 seconds |
| Started | Oct 09 05:09:47 AM UTC 24 |
| Finished | Oct 09 05:13:19 AM UTC 24 |
| Peak memory | 216276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792618740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.1792618740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.3330070579 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 108421207 ps |
| CPU time | 19.95 seconds |
| Started | Oct 09 05:09:50 AM UTC 24 |
| Finished | Oct 09 05:10:11 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330070579 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.3330070579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_unmapped_addr.3423444779 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 609115910 ps |
| CPU time | 9.19 seconds |
| Started | Oct 09 05:09:41 AM UTC 24 |
| Finished | Oct 09 05:09:52 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423444779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.3423444779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/2.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device.2046003797 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 24367794 ps |
| CPU time | 3.87 seconds |
| Started | Oct 09 05:14:02 AM UTC 24 |
| Finished | Oct 09 05:14:07 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046003797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.2046003797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/20.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.2569368958 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 22122662980 ps |
| CPU time | 110.67 seconds |
| Started | Oct 09 05:14:04 AM UTC 24 |
| Finished | Oct 09 05:15:57 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569368958 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.2569368958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.3371241261 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 495383319 ps |
| CPU time | 10.02 seconds |
| Started | Oct 09 05:14:08 AM UTC 24 |
| Finished | Oct 09 05:14:19 AM UTC 24 |
| Peak memory | 212368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371241261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.3371241261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_error_random.1504404174 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 470013656 ps |
| CPU time | 11.11 seconds |
| Started | Oct 09 05:14:06 AM UTC 24 |
| Finished | Oct 09 05:14:18 AM UTC 24 |
| Peak memory | 212288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504404174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.1504404174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/20.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random.4214834721 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 343321411 ps |
| CPU time | 13.02 seconds |
| Started | Oct 09 05:14:01 AM UTC 24 |
| Finished | Oct 09 05:14:16 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214834721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.4214834721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/20.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_large_delays.3964154113 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 45035838599 ps |
| CPU time | 100.98 seconds |
| Started | Oct 09 05:14:01 AM UTC 24 |
| Finished | Oct 09 05:15:45 AM UTC 24 |
| Peak memory | 212432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964154113 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.3964154113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/20.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1601418647 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 1773048258 ps |
| CPU time | 19.39 seconds |
| Started | Oct 09 05:14:02 AM UTC 24 |
| Finished | Oct 09 05:14:23 AM UTC 24 |
| Peak memory | 212100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601418647 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1601418647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/20.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_zero_delays.2731653573 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 114795087 ps |
| CPU time | 7.49 seconds |
| Started | Oct 09 05:14:01 AM UTC 24 |
| Finished | Oct 09 05:14:10 AM UTC 24 |
| Peak memory | 212100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731653573 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2731653573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/20.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_same_source.3578256829 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 11147715 ps |
| CPU time | 1.8 seconds |
| Started | Oct 09 05:14:04 AM UTC 24 |
| Finished | Oct 09 05:14:07 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578256829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3578256829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/20.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke.2385738029 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 10247839 ps |
| CPU time | 1.28 seconds |
| Started | Oct 09 05:13:59 AM UTC 24 |
| Finished | Oct 09 05:14:01 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385738029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2385738029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/20.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_large_delays.1976847505 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 3046631369 ps |
| CPU time | 14.79 seconds |
| Started | Oct 09 05:14:00 AM UTC 24 |
| Finished | Oct 09 05:14:16 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976847505 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1976847505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/20.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.1447774501 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 737973216 ps |
| CPU time | 9.19 seconds |
| Started | Oct 09 05:14:00 AM UTC 24 |
| Finished | Oct 09 05:14:10 AM UTC 24 |
| Peak memory | 212268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447774501 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.1447774501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.884211804 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 8220393 ps |
| CPU time | 1.42 seconds |
| Started | Oct 09 05:13:59 AM UTC 24 |
| Finished | Oct 09 05:14:01 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884211804 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.884211804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/20.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all.2848511035 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1256988566 ps |
| CPU time | 22.04 seconds |
| Started | Oct 09 05:14:11 AM UTC 24 |
| Finished | Oct 09 05:14:35 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848511035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2848511035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/20.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_error.2242501570 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 1050295610 ps |
| CPU time | 15.5 seconds |
| Started | Oct 09 05:14:11 AM UTC 24 |
| Finished | Oct 09 05:14:28 AM UTC 24 |
| Peak memory | 214160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242501570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.2242501570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/20.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.2031082269 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4092272661 ps |
| CPU time | 101 seconds |
| Started | Oct 09 05:14:11 AM UTC 24 |
| Finished | Oct 09 05:15:55 AM UTC 24 |
| Peak memory | 216524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031082269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.2031082269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.2292540726 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1398567100 ps |
| CPU time | 132.25 seconds |
| Started | Oct 09 05:14:13 AM UTC 24 |
| Finished | Oct 09 05:16:28 AM UTC 24 |
| Peak memory | 218252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292540726 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.2292540726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_unmapped_addr.4278601942 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 2463649257 ps |
| CPU time | 9.57 seconds |
| Started | Oct 09 05:14:07 AM UTC 24 |
| Finished | Oct 09 05:14:18 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278601942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.4278601942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/20.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device.2620339440 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 90685918 ps |
| CPU time | 15.25 seconds |
| Started | Oct 09 05:14:18 AM UTC 24 |
| Finished | Oct 09 05:14:34 AM UTC 24 |
| Peak memory | 212244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620339440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.2620339440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/21.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3929840464 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 83301050021 ps |
| CPU time | 340.83 seconds |
| Started | Oct 09 05:14:19 AM UTC 24 |
| Finished | Oct 09 05:20:05 AM UTC 24 |
| Peak memory | 218032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929840464 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.3929840464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.2015886977 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 83111894 ps |
| CPU time | 5.22 seconds |
| Started | Oct 09 05:14:20 AM UTC 24 |
| Finished | Oct 09 05:14:27 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015886977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.2015886977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_error_random.1757351476 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 2865923671 ps |
| CPU time | 23.51 seconds |
| Started | Oct 09 05:14:19 AM UTC 24 |
| Finished | Oct 09 05:14:44 AM UTC 24 |
| Peak memory | 212152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757351476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1757351476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/21.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random.4231324839 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 61780153 ps |
| CPU time | 2.97 seconds |
| Started | Oct 09 05:14:17 AM UTC 24 |
| Finished | Oct 09 05:14:21 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231324839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.4231324839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/21.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_large_delays.1952947698 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 137772321331 ps |
| CPU time | 87.91 seconds |
| Started | Oct 09 05:14:17 AM UTC 24 |
| Finished | Oct 09 05:15:47 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952947698 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.1952947698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/21.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_slow_rsp.1066384515 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 8795814267 ps |
| CPU time | 65.19 seconds |
| Started | Oct 09 05:14:18 AM UTC 24 |
| Finished | Oct 09 05:15:25 AM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066384515 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1066384515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/21.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_zero_delays.122266764 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 27651062 ps |
| CPU time | 3.16 seconds |
| Started | Oct 09 05:14:17 AM UTC 24 |
| Finished | Oct 09 05:14:21 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122266764 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.122266764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/21.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_same_source.3411918149 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 721727648 ps |
| CPU time | 5.74 seconds |
| Started | Oct 09 05:14:19 AM UTC 24 |
| Finished | Oct 09 05:14:26 AM UTC 24 |
| Peak memory | 212360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411918149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3411918149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/21.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke.2139015335 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 71560175 ps |
| CPU time | 2.3 seconds |
| Started | Oct 09 05:14:14 AM UTC 24 |
| Finished | Oct 09 05:14:17 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139015335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2139015335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/21.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_large_delays.586363606 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 3740773471 ps |
| CPU time | 11.07 seconds |
| Started | Oct 09 05:14:17 AM UTC 24 |
| Finished | Oct 09 05:14:29 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586363606 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.586363606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/21.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2343246318 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 2116571310 ps |
| CPU time | 13.36 seconds |
| Started | Oct 09 05:14:17 AM UTC 24 |
| Finished | Oct 09 05:14:31 AM UTC 24 |
| Peak memory | 212352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343246318 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2343246318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.2047022610 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 9560089 ps |
| CPU time | 1.91 seconds |
| Started | Oct 09 05:14:15 AM UTC 24 |
| Finished | Oct 09 05:14:18 AM UTC 24 |
| Peak memory | 211136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047022610 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.2047022610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/21.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all.327577466 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 259698839 ps |
| CPU time | 37.03 seconds |
| Started | Oct 09 05:14:21 AM UTC 24 |
| Finished | Oct 09 05:14:59 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327577466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.327577466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/21.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_error.3210738859 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 4536747559 ps |
| CPU time | 33.86 seconds |
| Started | Oct 09 05:14:22 AM UTC 24 |
| Finished | Oct 09 05:14:57 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210738859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3210738859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/21.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.3302063880 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 782948660 ps |
| CPU time | 147.95 seconds |
| Started | Oct 09 05:14:22 AM UTC 24 |
| Finished | Oct 09 05:16:52 AM UTC 24 |
| Peak memory | 216472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302063880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.3302063880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.741973175 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 369423081 ps |
| CPU time | 38.42 seconds |
| Started | Oct 09 05:14:22 AM UTC 24 |
| Finished | Oct 09 05:15:02 AM UTC 24 |
| Peak memory | 214164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741973175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.741973175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_unmapped_addr.1652583982 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 1067025977 ps |
| CPU time | 9.38 seconds |
| Started | Oct 09 05:14:20 AM UTC 24 |
| Finished | Oct 09 05:14:31 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652583982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1652583982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/21.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device.3572378448 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 365821218 ps |
| CPU time | 9.54 seconds |
| Started | Oct 09 05:14:28 AM UTC 24 |
| Finished | Oct 09 05:14:39 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572378448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.3572378448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/22.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.2847310344 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 16905378903 ps |
| CPU time | 106.76 seconds |
| Started | Oct 09 05:14:29 AM UTC 24 |
| Finished | Oct 09 05:16:18 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847310344 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.2847310344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.4075406400 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 308539138 ps |
| CPU time | 6.2 seconds |
| Started | Oct 09 05:14:32 AM UTC 24 |
| Finished | Oct 09 05:14:39 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075406400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.4075406400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_error_random.3634501776 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 85012316 ps |
| CPU time | 5.85 seconds |
| Started | Oct 09 05:14:30 AM UTC 24 |
| Finished | Oct 09 05:14:37 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634501776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.3634501776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/22.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random.177226852 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 144742728 ps |
| CPU time | 2.04 seconds |
| Started | Oct 09 05:14:27 AM UTC 24 |
| Finished | Oct 09 05:14:30 AM UTC 24 |
| Peak memory | 212348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177226852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.177226852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/22.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_large_delays.3461617701 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 25034696612 ps |
| CPU time | 100.58 seconds |
| Started | Oct 09 05:14:27 AM UTC 24 |
| Finished | Oct 09 05:16:10 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461617701 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3461617701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/22.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_slow_rsp.90800497 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 13083509556 ps |
| CPU time | 112.16 seconds |
| Started | Oct 09 05:14:27 AM UTC 24 |
| Finished | Oct 09 05:16:21 AM UTC 24 |
| Peak memory | 212152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90800497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.90800497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/22.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_zero_delays.2246485052 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 51984396 ps |
| CPU time | 5.32 seconds |
| Started | Oct 09 05:14:27 AM UTC 24 |
| Finished | Oct 09 05:14:33 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246485052 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.2246485052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/22.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_same_source.2030208475 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 210853083 ps |
| CPU time | 3.57 seconds |
| Started | Oct 09 05:14:30 AM UTC 24 |
| Finished | Oct 09 05:14:35 AM UTC 24 |
| Peak memory | 212360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030208475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.2030208475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/22.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke.2287312275 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 101740861 ps |
| CPU time | 2.81 seconds |
| Started | Oct 09 05:14:22 AM UTC 24 |
| Finished | Oct 09 05:14:26 AM UTC 24 |
| Peak memory | 212348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287312275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2287312275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/22.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_large_delays.3848864063 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 7356721070 ps |
| CPU time | 13.65 seconds |
| Started | Oct 09 05:14:24 AM UTC 24 |
| Finished | Oct 09 05:14:39 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848864063 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.3848864063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/22.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.3176755880 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 1445200095 ps |
| CPU time | 7.39 seconds |
| Started | Oct 09 05:14:25 AM UTC 24 |
| Finished | Oct 09 05:14:34 AM UTC 24 |
| Peak memory | 212352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176755880 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3176755880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.2815156789 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 12179929 ps |
| CPU time | 1.83 seconds |
| Started | Oct 09 05:14:23 AM UTC 24 |
| Finished | Oct 09 05:14:26 AM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815156789 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.2815156789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/22.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all.1364059275 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 643186782 ps |
| CPU time | 43.84 seconds |
| Started | Oct 09 05:14:32 AM UTC 24 |
| Finished | Oct 09 05:15:17 AM UTC 24 |
| Peak memory | 214484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364059275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.1364059275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/22.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_error.4088355674 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 5848439 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 05:14:33 AM UTC 24 |
| Finished | Oct 09 05:14:35 AM UTC 24 |
| Peak memory | 202380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088355674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.4088355674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/22.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.4278623139 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 683759024 ps |
| CPU time | 110.07 seconds |
| Started | Oct 09 05:14:32 AM UTC 24 |
| Finished | Oct 09 05:16:24 AM UTC 24 |
| Peak memory | 216208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278623139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.4278623139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.2831146749 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 328079341 ps |
| CPU time | 30.22 seconds |
| Started | Oct 09 05:14:34 AM UTC 24 |
| Finished | Oct 09 05:15:06 AM UTC 24 |
| Peak memory | 214420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831146749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.2831146749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_unmapped_addr.2850278954 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 71590068 ps |
| CPU time | 8.51 seconds |
| Started | Oct 09 05:14:30 AM UTC 24 |
| Finished | Oct 09 05:14:40 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850278954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.2850278954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/22.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device.2939419577 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 17968129 ps |
| CPU time | 3.65 seconds |
| Started | Oct 09 05:14:39 AM UTC 24 |
| Finished | Oct 09 05:14:44 AM UTC 24 |
| Peak memory | 212436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939419577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.2939419577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/23.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.3365026852 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 141662897128 ps |
| CPU time | 170.59 seconds |
| Started | Oct 09 05:14:39 AM UTC 24 |
| Finished | Oct 09 05:17:32 AM UTC 24 |
| Peak memory | 214356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365026852 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.3365026852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.604310967 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 77832574 ps |
| CPU time | 2.07 seconds |
| Started | Oct 09 05:14:40 AM UTC 24 |
| Finished | Oct 09 05:14:44 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604310967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.604310967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_error_random.4052731945 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 41127629 ps |
| CPU time | 6.57 seconds |
| Started | Oct 09 05:14:40 AM UTC 24 |
| Finished | Oct 09 05:14:48 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052731945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.4052731945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/23.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random.1412329192 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 4886007172 ps |
| CPU time | 15.06 seconds |
| Started | Oct 09 05:14:37 AM UTC 24 |
| Finished | Oct 09 05:14:53 AM UTC 24 |
| Peak memory | 212284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412329192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.1412329192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/23.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_large_delays.3629887291 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 17401213610 ps |
| CPU time | 62.5 seconds |
| Started | Oct 09 05:14:37 AM UTC 24 |
| Finished | Oct 09 05:15:41 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629887291 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.3629887291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/23.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_slow_rsp.1337680275 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 26090136846 ps |
| CPU time | 120.21 seconds |
| Started | Oct 09 05:14:38 AM UTC 24 |
| Finished | Oct 09 05:16:40 AM UTC 24 |
| Peak memory | 212420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337680275 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.1337680275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/23.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_zero_delays.613833125 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 17690762 ps |
| CPU time | 1.73 seconds |
| Started | Oct 09 05:14:37 AM UTC 24 |
| Finished | Oct 09 05:14:39 AM UTC 24 |
| Peak memory | 211144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613833125 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.613833125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/23.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_same_source.1086675055 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 438602889 ps |
| CPU time | 4.82 seconds |
| Started | Oct 09 05:14:40 AM UTC 24 |
| Finished | Oct 09 05:14:46 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086675055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.1086675055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/23.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke.1777026198 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 182757426 ps |
| CPU time | 2.26 seconds |
| Started | Oct 09 05:14:35 AM UTC 24 |
| Finished | Oct 09 05:14:39 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777026198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.1777026198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/23.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_large_delays.4261161231 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 3226319736 ps |
| CPU time | 13.77 seconds |
| Started | Oct 09 05:14:35 AM UTC 24 |
| Finished | Oct 09 05:14:50 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261161231 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.4261161231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/23.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.89126737 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 1965372473 ps |
| CPU time | 17.36 seconds |
| Started | Oct 09 05:14:36 AM UTC 24 |
| Finished | Oct 09 05:14:55 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89126737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.89126737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.1247509916 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 11977175 ps |
| CPU time | 1.35 seconds |
| Started | Oct 09 05:14:35 AM UTC 24 |
| Finished | Oct 09 05:14:38 AM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247509916 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.1247509916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/23.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all.4274052493 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 3213404348 ps |
| CPU time | 72.73 seconds |
| Started | Oct 09 05:14:40 AM UTC 24 |
| Finished | Oct 09 05:15:55 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274052493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.4274052493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/23.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_error.3254337452 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 310550976 ps |
| CPU time | 39.39 seconds |
| Started | Oct 09 05:14:42 AM UTC 24 |
| Finished | Oct 09 05:15:23 AM UTC 24 |
| Peak memory | 212368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254337452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.3254337452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/23.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.2879210839 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 174007397 ps |
| CPU time | 19.96 seconds |
| Started | Oct 09 05:14:42 AM UTC 24 |
| Finished | Oct 09 05:15:03 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879210839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.2879210839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.3465080670 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 634268491 ps |
| CPU time | 51.32 seconds |
| Started | Oct 09 05:14:45 AM UTC 24 |
| Finished | Oct 09 05:15:38 AM UTC 24 |
| Peak memory | 214420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465080670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.3465080670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_unmapped_addr.2262757400 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 552177966 ps |
| CPU time | 15.71 seconds |
| Started | Oct 09 05:14:40 AM UTC 24 |
| Finished | Oct 09 05:14:57 AM UTC 24 |
| Peak memory | 212364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262757400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2262757400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/23.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device.1342450886 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 86711934 ps |
| CPU time | 11.93 seconds |
| Started | Oct 09 05:14:53 AM UTC 24 |
| Finished | Oct 09 05:15:06 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342450886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.1342450886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/24.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.1586226697 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 23767337444 ps |
| CPU time | 72.36 seconds |
| Started | Oct 09 05:14:53 AM UTC 24 |
| Finished | Oct 09 05:16:08 AM UTC 24 |
| Peak memory | 214548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586226697 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.1586226697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.4059870054 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 262677363 ps |
| CPU time | 8.46 seconds |
| Started | Oct 09 05:14:56 AM UTC 24 |
| Finished | Oct 09 05:15:06 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059870054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.4059870054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_error_random.2979886367 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 14924709 ps |
| CPU time | 2.23 seconds |
| Started | Oct 09 05:14:55 AM UTC 24 |
| Finished | Oct 09 05:14:59 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979886367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.2979886367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/24.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random.2218179409 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 1469796604 ps |
| CPU time | 15.05 seconds |
| Started | Oct 09 05:14:48 AM UTC 24 |
| Finished | Oct 09 05:15:05 AM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218179409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.2218179409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/24.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_large_delays.3768918380 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 6280449139 ps |
| CPU time | 11.45 seconds |
| Started | Oct 09 05:14:50 AM UTC 24 |
| Finished | Oct 09 05:15:03 AM UTC 24 |
| Peak memory | 212368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768918380 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3768918380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/24.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_slow_rsp.2788051662 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 39411135241 ps |
| CPU time | 100.19 seconds |
| Started | Oct 09 05:14:51 AM UTC 24 |
| Finished | Oct 09 05:16:33 AM UTC 24 |
| Peak memory | 212164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788051662 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2788051662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/24.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_zero_delays.1949044428 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 58453264 ps |
| CPU time | 4.98 seconds |
| Started | Oct 09 05:14:50 AM UTC 24 |
| Finished | Oct 09 05:14:56 AM UTC 24 |
| Peak memory | 212364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949044428 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.1949044428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/24.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_same_source.2107608819 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 821290982 ps |
| CPU time | 8.41 seconds |
| Started | Oct 09 05:14:55 AM UTC 24 |
| Finished | Oct 09 05:15:05 AM UTC 24 |
| Peak memory | 212360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107608819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.2107608819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/24.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke.3367659280 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 60999173 ps |
| CPU time | 1.88 seconds |
| Started | Oct 09 05:14:45 AM UTC 24 |
| Finished | Oct 09 05:14:48 AM UTC 24 |
| Peak memory | 211184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367659280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3367659280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/24.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_large_delays.1786662996 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 1896487023 ps |
| CPU time | 15.9 seconds |
| Started | Oct 09 05:14:47 AM UTC 24 |
| Finished | Oct 09 05:15:04 AM UTC 24 |
| Peak memory | 212368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786662996 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1786662996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/24.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.366417204 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 905381530 ps |
| CPU time | 11.64 seconds |
| Started | Oct 09 05:14:48 AM UTC 24 |
| Finished | Oct 09 05:15:01 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366417204 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.366417204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1121612127 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 14170724 ps |
| CPU time | 1.26 seconds |
| Started | Oct 09 05:14:45 AM UTC 24 |
| Finished | Oct 09 05:14:47 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121612127 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1121612127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/24.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all.3996794327 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 16557850564 ps |
| CPU time | 61.28 seconds |
| Started | Oct 09 05:14:58 AM UTC 24 |
| Finished | Oct 09 05:16:01 AM UTC 24 |
| Peak memory | 214220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996794327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.3996794327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/24.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_error.1969564812 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 223251829 ps |
| CPU time | 20.85 seconds |
| Started | Oct 09 05:15:00 AM UTC 24 |
| Finished | Oct 09 05:15:22 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969564812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.1969564812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/24.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.1149835760 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 2839299461 ps |
| CPU time | 113.9 seconds |
| Started | Oct 09 05:14:59 AM UTC 24 |
| Finished | Oct 09 05:16:55 AM UTC 24 |
| Peak memory | 216532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149835760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.1149835760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.257221062 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 257135510 ps |
| CPU time | 30.42 seconds |
| Started | Oct 09 05:15:00 AM UTC 24 |
| Finished | Oct 09 05:15:32 AM UTC 24 |
| Peak memory | 214420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257221062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.257221062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_unmapped_addr.2073983101 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 71212325 ps |
| CPU time | 4.11 seconds |
| Started | Oct 09 05:14:56 AM UTC 24 |
| Finished | Oct 09 05:15:02 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073983101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2073983101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/24.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device.531881407 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 236415206 ps |
| CPU time | 12.68 seconds |
| Started | Oct 09 05:15:06 AM UTC 24 |
| Finished | Oct 09 05:15:20 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531881407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.531881407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/25.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.4045658058 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 55520847605 ps |
| CPU time | 263.79 seconds |
| Started | Oct 09 05:15:06 AM UTC 24 |
| Finished | Oct 09 05:19:34 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045658058 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.4045658058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.2578106988 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 2896198679 ps |
| CPU time | 13.79 seconds |
| Started | Oct 09 05:15:09 AM UTC 24 |
| Finished | Oct 09 05:15:24 AM UTC 24 |
| Peak memory | 212496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578106988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.2578106988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_error_random.2220916963 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 13726659 ps |
| CPU time | 1.95 seconds |
| Started | Oct 09 05:15:07 AM UTC 24 |
| Finished | Oct 09 05:15:10 AM UTC 24 |
| Peak memory | 211080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220916963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2220916963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/25.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random.3861936413 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 370930597 ps |
| CPU time | 7.8 seconds |
| Started | Oct 09 05:15:04 AM UTC 24 |
| Finished | Oct 09 05:15:12 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861936413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.3861936413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/25.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_large_delays.2766725083 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 15803019111 ps |
| CPU time | 42.6 seconds |
| Started | Oct 09 05:15:06 AM UTC 24 |
| Finished | Oct 09 05:15:50 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766725083 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2766725083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/25.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_slow_rsp.4135349790 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 13008470696 ps |
| CPU time | 42.37 seconds |
| Started | Oct 09 05:15:06 AM UTC 24 |
| Finished | Oct 09 05:15:50 AM UTC 24 |
| Peak memory | 212484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135349790 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.4135349790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/25.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_zero_delays.2077049939 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 38703327 ps |
| CPU time | 1.59 seconds |
| Started | Oct 09 05:15:05 AM UTC 24 |
| Finished | Oct 09 05:15:07 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077049939 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.2077049939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/25.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_same_source.1536099611 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 222015315 ps |
| CPU time | 4.96 seconds |
| Started | Oct 09 05:15:07 AM UTC 24 |
| Finished | Oct 09 05:15:13 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536099611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.1536099611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/25.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke.220801623 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 45990867 ps |
| CPU time | 1.64 seconds |
| Started | Oct 09 05:15:02 AM UTC 24 |
| Finished | Oct 09 05:15:05 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220801623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.220801623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/25.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_large_delays.2612604619 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 6697103677 ps |
| CPU time | 11.18 seconds |
| Started | Oct 09 05:15:03 AM UTC 24 |
| Finished | Oct 09 05:15:16 AM UTC 24 |
| Peak memory | 212496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612604619 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2612604619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/25.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.928793424 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 658057567 ps |
| CPU time | 7.05 seconds |
| Started | Oct 09 05:15:03 AM UTC 24 |
| Finished | Oct 09 05:15:12 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928793424 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.928793424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.3580244278 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 16343516 ps |
| CPU time | 1.62 seconds |
| Started | Oct 09 05:15:02 AM UTC 24 |
| Finished | Oct 09 05:15:05 AM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580244278 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.3580244278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/25.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all.562353680 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 3430010829 ps |
| CPU time | 27.87 seconds |
| Started | Oct 09 05:15:09 AM UTC 24 |
| Finished | Oct 09 05:15:38 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562353680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.562353680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/25.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_error.3143442600 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 2618575544 ps |
| CPU time | 42.65 seconds |
| Started | Oct 09 05:15:11 AM UTC 24 |
| Finished | Oct 09 05:15:55 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143442600 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.3143442600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/25.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.4044858112 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 63107491 ps |
| CPU time | 14.26 seconds |
| Started | Oct 09 05:15:11 AM UTC 24 |
| Finished | Oct 09 05:15:26 AM UTC 24 |
| Peak memory | 214164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044858112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.4044858112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.3843017806 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 229215543 ps |
| CPU time | 22.14 seconds |
| Started | Oct 09 05:15:12 AM UTC 24 |
| Finished | Oct 09 05:15:36 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843017806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.3843017806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_unmapped_addr.3554946067 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 25257012 ps |
| CPU time | 1.62 seconds |
| Started | Oct 09 05:15:07 AM UTC 24 |
| Finished | Oct 09 05:15:10 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554946067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3554946067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/25.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device.763384336 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 11053651 ps |
| CPU time | 2.76 seconds |
| Started | Oct 09 05:15:21 AM UTC 24 |
| Finished | Oct 09 05:15:25 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763384336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.763384336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/26.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.2181818434 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 10775901190 ps |
| CPU time | 79.42 seconds |
| Started | Oct 09 05:15:23 AM UTC 24 |
| Finished | Oct 09 05:16:45 AM UTC 24 |
| Peak memory | 214220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181818434 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.2181818434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.2824707550 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 283425319 ps |
| CPU time | 4.87 seconds |
| Started | Oct 09 05:15:26 AM UTC 24 |
| Finished | Oct 09 05:15:32 AM UTC 24 |
| Peak memory | 212240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824707550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.2824707550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_error_random.787816754 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 1129536960 ps |
| CPU time | 15.06 seconds |
| Started | Oct 09 05:15:25 AM UTC 24 |
| Finished | Oct 09 05:15:41 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787816754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.787816754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/26.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random.2489469492 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 627806705 ps |
| CPU time | 18.43 seconds |
| Started | Oct 09 05:15:18 AM UTC 24 |
| Finished | Oct 09 05:15:38 AM UTC 24 |
| Peak memory | 212344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489469492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.2489469492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/26.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_large_delays.1302896976 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 2043065030 ps |
| CPU time | 17.63 seconds |
| Started | Oct 09 05:15:18 AM UTC 24 |
| Finished | Oct 09 05:15:37 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302896976 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1302896976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/26.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_slow_rsp.3001961039 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 77485467997 ps |
| CPU time | 178.6 seconds |
| Started | Oct 09 05:15:21 AM UTC 24 |
| Finished | Oct 09 05:18:23 AM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001961039 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.3001961039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/26.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_zero_delays.1466291085 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 11695234 ps |
| CPU time | 1.73 seconds |
| Started | Oct 09 05:15:18 AM UTC 24 |
| Finished | Oct 09 05:15:21 AM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466291085 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.1466291085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/26.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_same_source.986555610 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 43385470 ps |
| CPU time | 3.02 seconds |
| Started | Oct 09 05:15:24 AM UTC 24 |
| Finished | Oct 09 05:15:28 AM UTC 24 |
| Peak memory | 214116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986555610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.986555610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/26.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke.2625595453 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 7725943 ps |
| CPU time | 1.52 seconds |
| Started | Oct 09 05:15:13 AM UTC 24 |
| Finished | Oct 09 05:15:16 AM UTC 24 |
| Peak memory | 211080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625595453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.2625595453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/26.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_large_delays.3610034491 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 9613899726 ps |
| CPU time | 11.22 seconds |
| Started | Oct 09 05:15:16 AM UTC 24 |
| Finished | Oct 09 05:15:29 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610034491 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3610034491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/26.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.4066995179 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 855674179 ps |
| CPU time | 7.04 seconds |
| Started | Oct 09 05:15:17 AM UTC 24 |
| Finished | Oct 09 05:15:25 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066995179 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.4066995179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.2886427581 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 10670079 ps |
| CPU time | 1.7 seconds |
| Started | Oct 09 05:15:14 AM UTC 24 |
| Finished | Oct 09 05:15:17 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886427581 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.2886427581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/26.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all.1911002276 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 461254042 ps |
| CPU time | 64.92 seconds |
| Started | Oct 09 05:15:26 AM UTC 24 |
| Finished | Oct 09 05:16:33 AM UTC 24 |
| Peak memory | 214112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911002276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.1911002276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/26.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_error.2634592810 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 334713960 ps |
| CPU time | 31.27 seconds |
| Started | Oct 09 05:15:27 AM UTC 24 |
| Finished | Oct 09 05:16:00 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634592810 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.2634592810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/26.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.53869167 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 284367216 ps |
| CPU time | 30.75 seconds |
| Started | Oct 09 05:15:27 AM UTC 24 |
| Finished | Oct 09 05:15:59 AM UTC 24 |
| Peak memory | 214160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53869167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.53869167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.2521908325 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 112512884 ps |
| CPU time | 22.2 seconds |
| Started | Oct 09 05:15:28 AM UTC 24 |
| Finished | Oct 09 05:15:52 AM UTC 24 |
| Peak memory | 214228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521908325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.2521908325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_unmapped_addr.445924181 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 565373541 ps |
| CPU time | 10.3 seconds |
| Started | Oct 09 05:15:26 AM UTC 24 |
| Finished | Oct 09 05:15:37 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445924181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.445924181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/26.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device.3592149131 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 815681361 ps |
| CPU time | 10.56 seconds |
| Started | Oct 09 05:15:38 AM UTC 24 |
| Finished | Oct 09 05:15:50 AM UTC 24 |
| Peak memory | 212244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592149131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.3592149131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/27.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2472410250 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 2375001148 ps |
| CPU time | 22.62 seconds |
| Started | Oct 09 05:15:39 AM UTC 24 |
| Finished | Oct 09 05:16:03 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472410250 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.2472410250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.3849105542 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 1118678453 ps |
| CPU time | 7.4 seconds |
| Started | Oct 09 05:15:39 AM UTC 24 |
| Finished | Oct 09 05:15:48 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849105542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.3849105542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_error_random.1200518785 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 546320880 ps |
| CPU time | 11.67 seconds |
| Started | Oct 09 05:15:39 AM UTC 24 |
| Finished | Oct 09 05:15:52 AM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200518785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.1200518785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/27.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random.392919639 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 56001346 ps |
| CPU time | 2.38 seconds |
| Started | Oct 09 05:15:34 AM UTC 24 |
| Finished | Oct 09 05:15:38 AM UTC 24 |
| Peak memory | 212348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392919639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.392919639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/27.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_large_delays.1843211935 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 72540269726 ps |
| CPU time | 96.15 seconds |
| Started | Oct 09 05:15:36 AM UTC 24 |
| Finished | Oct 09 05:17:15 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843211935 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1843211935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/27.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_slow_rsp.3253051306 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 2843627779 ps |
| CPU time | 19.68 seconds |
| Started | Oct 09 05:15:36 AM UTC 24 |
| Finished | Oct 09 05:15:58 AM UTC 24 |
| Peak memory | 212484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253051306 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3253051306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/27.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_zero_delays.1926825984 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 60708068 ps |
| CPU time | 6.74 seconds |
| Started | Oct 09 05:15:34 AM UTC 24 |
| Finished | Oct 09 05:15:43 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926825984 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.1926825984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/27.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_same_source.2656490475 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 1121236435 ps |
| CPU time | 11.26 seconds |
| Started | Oct 09 05:15:39 AM UTC 24 |
| Finished | Oct 09 05:15:52 AM UTC 24 |
| Peak memory | 212100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656490475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.2656490475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/27.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke.144783523 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 68353821 ps |
| CPU time | 2.13 seconds |
| Started | Oct 09 05:15:29 AM UTC 24 |
| Finished | Oct 09 05:15:33 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144783523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.144783523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/27.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_large_delays.3142504325 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 2665655788 ps |
| CPU time | 7.11 seconds |
| Started | Oct 09 05:15:33 AM UTC 24 |
| Finished | Oct 09 05:15:41 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142504325 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.3142504325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/27.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.638225197 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 2233892535 ps |
| CPU time | 14.14 seconds |
| Started | Oct 09 05:15:34 AM UTC 24 |
| Finished | Oct 09 05:15:50 AM UTC 24 |
| Peak memory | 212152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638225197 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.638225197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.2482002081 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 30906562 ps |
| CPU time | 1.3 seconds |
| Started | Oct 09 05:15:33 AM UTC 24 |
| Finished | Oct 09 05:15:35 AM UTC 24 |
| Peak memory | 211136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482002081 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.2482002081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/27.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all.2694136829 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 3648445736 ps |
| CPU time | 51.19 seconds |
| Started | Oct 09 05:15:41 AM UTC 24 |
| Finished | Oct 09 05:16:34 AM UTC 24 |
| Peak memory | 214228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694136829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2694136829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/27.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_error.1089038879 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 335326194 ps |
| CPU time | 33.84 seconds |
| Started | Oct 09 05:15:43 AM UTC 24 |
| Finished | Oct 09 05:16:18 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089038879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.1089038879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/27.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_unmapped_addr.1498684864 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 1295401608 ps |
| CPU time | 9 seconds |
| Started | Oct 09 05:15:39 AM UTC 24 |
| Finished | Oct 09 05:15:49 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498684864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.1498684864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/27.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device.2867666461 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 422380930 ps |
| CPU time | 6.21 seconds |
| Started | Oct 09 05:15:51 AM UTC 24 |
| Finished | Oct 09 05:15:58 AM UTC 24 |
| Peak memory | 212376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867666461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.2867666461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/28.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.101747716 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 39182716715 ps |
| CPU time | 253.99 seconds |
| Started | Oct 09 05:15:51 AM UTC 24 |
| Finished | Oct 09 05:20:09 AM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101747716 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.101747716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.1827325696 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 25575468 ps |
| CPU time | 2.26 seconds |
| Started | Oct 09 05:15:52 AM UTC 24 |
| Finished | Oct 09 05:15:56 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827325696 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.1827325696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_error_random.3360507617 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 80714952 ps |
| CPU time | 2.47 seconds |
| Started | Oct 09 05:15:51 AM UTC 24 |
| Finished | Oct 09 05:15:55 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360507617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3360507617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/28.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random.3838708374 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 592367397 ps |
| CPU time | 12.15 seconds |
| Started | Oct 09 05:15:49 AM UTC 24 |
| Finished | Oct 09 05:16:03 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838708374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.3838708374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/28.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_large_delays.3108384358 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 16562514975 ps |
| CPU time | 44.61 seconds |
| Started | Oct 09 05:15:51 AM UTC 24 |
| Finished | Oct 09 05:16:37 AM UTC 24 |
| Peak memory | 212428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108384358 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.3108384358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/28.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_slow_rsp.328544030 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 26331233232 ps |
| CPU time | 36.23 seconds |
| Started | Oct 09 05:15:51 AM UTC 24 |
| Finished | Oct 09 05:16:29 AM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328544030 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.328544030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/28.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_zero_delays.792024911 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 27351833 ps |
| CPU time | 3.81 seconds |
| Started | Oct 09 05:15:49 AM UTC 24 |
| Finished | Oct 09 05:15:54 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792024911 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.792024911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/28.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_same_source.1665300179 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 49769817 ps |
| CPU time | 4.8 seconds |
| Started | Oct 09 05:15:51 AM UTC 24 |
| Finished | Oct 09 05:15:57 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665300179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1665300179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/28.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke.224802506 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 79626401 ps |
| CPU time | 1.91 seconds |
| Started | Oct 09 05:15:44 AM UTC 24 |
| Finished | Oct 09 05:15:47 AM UTC 24 |
| Peak memory | 211196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224802506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.224802506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/28.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_large_delays.1978785341 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 4266377664 ps |
| CPU time | 9.57 seconds |
| Started | Oct 09 05:15:48 AM UTC 24 |
| Finished | Oct 09 05:15:59 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978785341 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.1978785341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/28.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.2337279299 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 1669173551 ps |
| CPU time | 10.98 seconds |
| Started | Oct 09 05:15:48 AM UTC 24 |
| Finished | Oct 09 05:16:00 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337279299 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.2337279299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.3772392244 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 9823449 ps |
| CPU time | 1.66 seconds |
| Started | Oct 09 05:15:45 AM UTC 24 |
| Finished | Oct 09 05:15:48 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772392244 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.3772392244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/28.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all.2843112604 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 3440664243 ps |
| CPU time | 50.76 seconds |
| Started | Oct 09 05:15:54 AM UTC 24 |
| Finished | Oct 09 05:16:46 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843112604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.2843112604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/28.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_error.3870318488 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 351202452 ps |
| CPU time | 17.14 seconds |
| Started | Oct 09 05:15:55 AM UTC 24 |
| Finished | Oct 09 05:16:13 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870318488 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.3870318488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/28.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.2993039986 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 336849299 ps |
| CPU time | 40.04 seconds |
| Started | Oct 09 05:15:54 AM UTC 24 |
| Finished | Oct 09 05:16:35 AM UTC 24 |
| Peak memory | 214164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993039986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.2993039986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.2285377758 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 242592696 ps |
| CPU time | 28.7 seconds |
| Started | Oct 09 05:15:56 AM UTC 24 |
| Finished | Oct 09 05:16:26 AM UTC 24 |
| Peak memory | 214132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285377758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.2285377758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_unmapped_addr.2386446911 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 427454365 ps |
| CPU time | 6.54 seconds |
| Started | Oct 09 05:15:52 AM UTC 24 |
| Finished | Oct 09 05:16:00 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386446911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.2386446911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/28.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device.1589363819 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 568158021 ps |
| CPU time | 5.61 seconds |
| Started | Oct 09 05:16:00 AM UTC 24 |
| Finished | Oct 09 05:16:07 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589363819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.1589363819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/29.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1692256400 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 49966596266 ps |
| CPU time | 394.36 seconds |
| Started | Oct 09 05:16:00 AM UTC 24 |
| Finished | Oct 09 05:22:40 AM UTC 24 |
| Peak memory | 219952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692256400 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.1692256400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.1506949269 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 77479559 ps |
| CPU time | 2.33 seconds |
| Started | Oct 09 05:16:02 AM UTC 24 |
| Finished | Oct 09 05:16:05 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506949269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.1506949269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_error_random.3114068023 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 58849022 ps |
| CPU time | 4.43 seconds |
| Started | Oct 09 05:16:00 AM UTC 24 |
| Finished | Oct 09 05:16:06 AM UTC 24 |
| Peak memory | 212352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114068023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3114068023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/29.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random.1149541385 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 29939839 ps |
| CPU time | 2.56 seconds |
| Started | Oct 09 05:15:57 AM UTC 24 |
| Finished | Oct 09 05:16:01 AM UTC 24 |
| Peak memory | 212320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149541385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.1149541385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/29.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_large_delays.3159161414 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 21863103542 ps |
| CPU time | 95.16 seconds |
| Started | Oct 09 05:15:59 AM UTC 24 |
| Finished | Oct 09 05:17:36 AM UTC 24 |
| Peak memory | 212304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159161414 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.3159161414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/29.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_slow_rsp.3479283499 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 16775345118 ps |
| CPU time | 49.55 seconds |
| Started | Oct 09 05:15:59 AM UTC 24 |
| Finished | Oct 09 05:16:50 AM UTC 24 |
| Peak memory | 212420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479283499 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.3479283499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/29.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_zero_delays.3225042608 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 41930406 ps |
| CPU time | 5.19 seconds |
| Started | Oct 09 05:15:57 AM UTC 24 |
| Finished | Oct 09 05:16:04 AM UTC 24 |
| Peak memory | 212080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225042608 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.3225042608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/29.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_same_source.521723976 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 39474547 ps |
| CPU time | 2.77 seconds |
| Started | Oct 09 05:16:00 AM UTC 24 |
| Finished | Oct 09 05:16:04 AM UTC 24 |
| Peak memory | 212100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521723976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.521723976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/29.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke.4248983794 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 398016812 ps |
| CPU time | 1.99 seconds |
| Started | Oct 09 05:15:56 AM UTC 24 |
| Finished | Oct 09 05:15:59 AM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248983794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.4248983794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/29.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_large_delays.3269114868 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 1047986356 ps |
| CPU time | 11.27 seconds |
| Started | Oct 09 05:15:56 AM UTC 24 |
| Finished | Oct 09 05:16:09 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269114868 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3269114868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/29.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.567021491 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 732455318 ps |
| CPU time | 8.87 seconds |
| Started | Oct 09 05:15:56 AM UTC 24 |
| Finished | Oct 09 05:16:06 AM UTC 24 |
| Peak memory | 212348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567021491 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.567021491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.216018088 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 28591910 ps |
| CPU time | 1.97 seconds |
| Started | Oct 09 05:15:56 AM UTC 24 |
| Finished | Oct 09 05:15:59 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216018088 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.216018088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/29.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all.265542867 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 5388918249 ps |
| CPU time | 80.68 seconds |
| Started | Oct 09 05:16:02 AM UTC 24 |
| Finished | Oct 09 05:17:25 AM UTC 24 |
| Peak memory | 216268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265542867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.265542867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/29.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_error.3675058860 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 295225394 ps |
| CPU time | 22.5 seconds |
| Started | Oct 09 05:16:02 AM UTC 24 |
| Finished | Oct 09 05:16:26 AM UTC 24 |
| Peak memory | 212364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675058860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3675058860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/29.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.4061169282 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 668858841 ps |
| CPU time | 118.89 seconds |
| Started | Oct 09 05:16:02 AM UTC 24 |
| Finished | Oct 09 05:18:04 AM UTC 24 |
| Peak memory | 216468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061169282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.4061169282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_unmapped_addr.3824722410 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 25905878 ps |
| CPU time | 1.89 seconds |
| Started | Oct 09 05:16:02 AM UTC 24 |
| Finished | Oct 09 05:16:05 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824722410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.3824722410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/29.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device.3161431484 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 28583500 ps |
| CPU time | 6.61 seconds |
| Started | Oct 09 05:09:54 AM UTC 24 |
| Finished | Oct 09 05:10:02 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161431484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.3161431484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/3.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.2302275193 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 51106160435 ps |
| CPU time | 276.38 seconds |
| Started | Oct 09 05:09:55 AM UTC 24 |
| Finished | Oct 09 05:14:36 AM UTC 24 |
| Peak memory | 214356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302275193 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.2302275193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.542960278 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 599010752 ps |
| CPU time | 13.56 seconds |
| Started | Oct 09 05:09:59 AM UTC 24 |
| Finished | Oct 09 05:10:13 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542960278 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.542960278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_error_random.3775703653 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1139842348 ps |
| CPU time | 13.57 seconds |
| Started | Oct 09 05:09:56 AM UTC 24 |
| Finished | Oct 09 05:10:11 AM UTC 24 |
| Peak memory | 212344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775703653 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.3775703653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/3.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random.1032934222 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 35007849 ps |
| CPU time | 3.45 seconds |
| Started | Oct 09 05:09:53 AM UTC 24 |
| Finished | Oct 09 05:09:58 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032934222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.1032934222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/3.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_large_delays.322208522 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 47902171471 ps |
| CPU time | 105.77 seconds |
| Started | Oct 09 05:09:53 AM UTC 24 |
| Finished | Oct 09 05:11:41 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322208522 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.322208522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/3.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_slow_rsp.3516713651 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 49085367058 ps |
| CPU time | 150.84 seconds |
| Started | Oct 09 05:09:54 AM UTC 24 |
| Finished | Oct 09 05:12:28 AM UTC 24 |
| Peak memory | 212164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516713651 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3516713651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/3.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_zero_delays.3975675785 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 9190894 ps |
| CPU time | 1.62 seconds |
| Started | Oct 09 05:09:53 AM UTC 24 |
| Finished | Oct 09 05:09:56 AM UTC 24 |
| Peak memory | 210552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975675785 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.3975675785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/3.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_same_source.4166677170 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 373887688 ps |
| CPU time | 7 seconds |
| Started | Oct 09 05:09:55 AM UTC 24 |
| Finished | Oct 09 05:10:04 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166677170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.4166677170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/3.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke.4034763698 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 129239936 ps |
| CPU time | 1.67 seconds |
| Started | Oct 09 05:09:50 AM UTC 24 |
| Finished | Oct 09 05:09:53 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034763698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.4034763698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/3.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_large_delays.3849462833 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 3255549604 ps |
| CPU time | 9.59 seconds |
| Started | Oct 09 05:09:51 AM UTC 24 |
| Finished | Oct 09 05:10:03 AM UTC 24 |
| Peak memory | 212432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849462833 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3849462833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/3.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1951139008 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 2280588680 ps |
| CPU time | 13.52 seconds |
| Started | Oct 09 05:09:51 AM UTC 24 |
| Finished | Oct 09 05:10:07 AM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951139008 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1951139008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.3711098085 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 20888184 ps |
| CPU time | 1.92 seconds |
| Started | Oct 09 05:09:51 AM UTC 24 |
| Finished | Oct 09 05:09:55 AM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711098085 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.3711098085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/3.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_error.3368741006 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1408137980 ps |
| CPU time | 36.19 seconds |
| Started | Oct 09 05:10:05 AM UTC 24 |
| Finished | Oct 09 05:10:43 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368741006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3368741006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/3.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.145263481 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 808294847 ps |
| CPU time | 80.16 seconds |
| Started | Oct 09 05:10:08 AM UTC 24 |
| Finished | Oct 09 05:11:31 AM UTC 24 |
| Peak memory | 216340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145263481 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.145263481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_unmapped_addr.371266889 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 304327220 ps |
| CPU time | 6.36 seconds |
| Started | Oct 09 05:09:59 AM UTC 24 |
| Finished | Oct 09 05:10:06 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371266889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.371266889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/3.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device.3473987683 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 319583540 ps |
| CPU time | 8.25 seconds |
| Started | Oct 09 05:16:07 AM UTC 24 |
| Finished | Oct 09 05:16:16 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473987683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.3473987683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/30.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.663598005 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 63956061205 ps |
| CPU time | 253.03 seconds |
| Started | Oct 09 05:16:07 AM UTC 24 |
| Finished | Oct 09 05:20:24 AM UTC 24 |
| Peak memory | 214476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663598005 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.663598005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.4062098427 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 970148755 ps |
| CPU time | 11.49 seconds |
| Started | Oct 09 05:16:08 AM UTC 24 |
| Finished | Oct 09 05:16:21 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062098427 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.4062098427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_error_random.2904318379 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 98727163 ps |
| CPU time | 2.11 seconds |
| Started | Oct 09 05:16:08 AM UTC 24 |
| Finished | Oct 09 05:16:11 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904318379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.2904318379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/30.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random.328988396 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 251340729 ps |
| CPU time | 4.03 seconds |
| Started | Oct 09 05:16:05 AM UTC 24 |
| Finished | Oct 09 05:16:10 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328988396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.328988396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/30.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.2577310023 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 42608704258 ps |
| CPU time | 139.49 seconds |
| Started | Oct 09 05:16:05 AM UTC 24 |
| Finished | Oct 09 05:18:27 AM UTC 24 |
| Peak memory | 212432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577310023 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2577310023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/30.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_slow_rsp.3611553246 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 63183552323 ps |
| CPU time | 120.76 seconds |
| Started | Oct 09 05:16:07 AM UTC 24 |
| Finished | Oct 09 05:18:10 AM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611553246 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3611553246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/30.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_zero_delays.555354223 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 41085573 ps |
| CPU time | 4.07 seconds |
| Started | Oct 09 05:16:05 AM UTC 24 |
| Finished | Oct 09 05:16:10 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555354223 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.555354223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/30.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_same_source.2633210727 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 436641525 ps |
| CPU time | 5.59 seconds |
| Started | Oct 09 05:16:07 AM UTC 24 |
| Finished | Oct 09 05:16:13 AM UTC 24 |
| Peak memory | 214384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633210727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2633210727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/30.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke.2266329519 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 26293571 ps |
| CPU time | 1.73 seconds |
| Started | Oct 09 05:16:03 AM UTC 24 |
| Finished | Oct 09 05:16:06 AM UTC 24 |
| Peak memory | 211060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266329519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2266329519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/30.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_large_delays.3051249011 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 16119073824 ps |
| CPU time | 22.6 seconds |
| Started | Oct 09 05:16:04 AM UTC 24 |
| Finished | Oct 09 05:16:27 AM UTC 24 |
| Peak memory | 212472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051249011 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.3051249011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/30.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2038391150 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 1086293029 ps |
| CPU time | 10.96 seconds |
| Started | Oct 09 05:16:04 AM UTC 24 |
| Finished | Oct 09 05:16:16 AM UTC 24 |
| Peak memory | 212352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038391150 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2038391150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.3636198145 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 22183715 ps |
| CPU time | 1.66 seconds |
| Started | Oct 09 05:16:04 AM UTC 24 |
| Finished | Oct 09 05:16:06 AM UTC 24 |
| Peak memory | 211136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636198145 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.3636198145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/30.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all.2979109530 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 7786635864 ps |
| CPU time | 70.55 seconds |
| Started | Oct 09 05:16:08 AM UTC 24 |
| Finished | Oct 09 05:17:21 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979109530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2979109530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/30.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_error.2749619344 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 2220031149 ps |
| CPU time | 45.24 seconds |
| Started | Oct 09 05:16:09 AM UTC 24 |
| Finished | Oct 09 05:16:56 AM UTC 24 |
| Peak memory | 212496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749619344 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2749619344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/30.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.1184678238 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 19544080227 ps |
| CPU time | 210.5 seconds |
| Started | Oct 09 05:16:09 AM UTC 24 |
| Finished | Oct 09 05:19:43 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184678238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.1184678238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.78793878 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 2026984827 ps |
| CPU time | 118.63 seconds |
| Started | Oct 09 05:16:11 AM UTC 24 |
| Finished | Oct 09 05:18:12 AM UTC 24 |
| Peak memory | 218760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78793878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.78793878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_unmapped_addr.4139696262 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 3053643591 ps |
| CPU time | 11.63 seconds |
| Started | Oct 09 05:16:08 AM UTC 24 |
| Finished | Oct 09 05:16:21 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139696262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.4139696262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/30.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device.2559517215 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 73645744 ps |
| CPU time | 5.71 seconds |
| Started | Oct 09 05:16:17 AM UTC 24 |
| Finished | Oct 09 05:16:23 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559517215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.2559517215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/31.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.1879604696 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 194796355765 ps |
| CPU time | 263.89 seconds |
| Started | Oct 09 05:16:17 AM UTC 24 |
| Finished | Oct 09 05:20:44 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879604696 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.1879604696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.579510774 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 81416676 ps |
| CPU time | 1.93 seconds |
| Started | Oct 09 05:16:20 AM UTC 24 |
| Finished | Oct 09 05:16:23 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579510774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.579510774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_error_random.4143882051 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 211889258 ps |
| CPU time | 3.84 seconds |
| Started | Oct 09 05:16:19 AM UTC 24 |
| Finished | Oct 09 05:16:24 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143882051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.4143882051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/31.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random.670748160 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 104662279 ps |
| CPU time | 2.25 seconds |
| Started | Oct 09 05:16:14 AM UTC 24 |
| Finished | Oct 09 05:16:18 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670748160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.670748160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/31.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_large_delays.2398927789 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 45116871383 ps |
| CPU time | 146.27 seconds |
| Started | Oct 09 05:16:15 AM UTC 24 |
| Finished | Oct 09 05:18:43 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398927789 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.2398927789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/31.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_slow_rsp.2647209004 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 13546674887 ps |
| CPU time | 102.66 seconds |
| Started | Oct 09 05:16:16 AM UTC 24 |
| Finished | Oct 09 05:18:00 AM UTC 24 |
| Peak memory | 212164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647209004 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.2647209004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/31.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_zero_delays.298663066 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 110375049 ps |
| CPU time | 6.08 seconds |
| Started | Oct 09 05:16:14 AM UTC 24 |
| Finished | Oct 09 05:16:22 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298663066 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.298663066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/31.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_same_source.571641148 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 34118389 ps |
| CPU time | 3.6 seconds |
| Started | Oct 09 05:16:18 AM UTC 24 |
| Finished | Oct 09 05:16:23 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571641148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.571641148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/31.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke.2200564515 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 82249991 ps |
| CPU time | 2.07 seconds |
| Started | Oct 09 05:16:11 AM UTC 24 |
| Finished | Oct 09 05:16:14 AM UTC 24 |
| Peak memory | 212348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200564515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2200564515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/31.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_large_delays.1662037705 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 6315492634 ps |
| CPU time | 10.62 seconds |
| Started | Oct 09 05:16:12 AM UTC 24 |
| Finished | Oct 09 05:16:24 AM UTC 24 |
| Peak memory | 212432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662037705 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.1662037705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/31.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.435858243 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 1449729636 ps |
| CPU time | 8.06 seconds |
| Started | Oct 09 05:16:13 AM UTC 24 |
| Finished | Oct 09 05:16:22 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435858243 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.435858243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.2688747693 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 10199331 ps |
| CPU time | 1.95 seconds |
| Started | Oct 09 05:16:12 AM UTC 24 |
| Finished | Oct 09 05:16:15 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688747693 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.2688747693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/31.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all.3868477264 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 4953928532 ps |
| CPU time | 64.13 seconds |
| Started | Oct 09 05:16:21 AM UTC 24 |
| Finished | Oct 09 05:17:27 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868477264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3868477264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/31.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_error.4274847425 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 2673156607 ps |
| CPU time | 28.63 seconds |
| Started | Oct 09 05:16:22 AM UTC 24 |
| Finished | Oct 09 05:16:52 AM UTC 24 |
| Peak memory | 212180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274847425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.4274847425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/31.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.686244155 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 3306073891 ps |
| CPU time | 185.85 seconds |
| Started | Oct 09 05:16:22 AM UTC 24 |
| Finished | Oct 09 05:19:31 AM UTC 24 |
| Peak memory | 218316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686244155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.686244155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.2900295393 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 4413131112 ps |
| CPU time | 48.07 seconds |
| Started | Oct 09 05:16:22 AM UTC 24 |
| Finished | Oct 09 05:17:12 AM UTC 24 |
| Peak memory | 214484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900295393 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.2900295393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_unmapped_addr.1215139590 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 2337493787 ps |
| CPU time | 9.79 seconds |
| Started | Oct 09 05:16:20 AM UTC 24 |
| Finished | Oct 09 05:16:30 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215139590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1215139590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/31.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device.201168832 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 607632805 ps |
| CPU time | 11.93 seconds |
| Started | Oct 09 05:16:27 AM UTC 24 |
| Finished | Oct 09 05:16:41 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201168832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.201168832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/32.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.2154330902 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 47604815811 ps |
| CPU time | 405.63 seconds |
| Started | Oct 09 05:16:28 AM UTC 24 |
| Finished | Oct 09 05:23:19 AM UTC 24 |
| Peak memory | 218032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154330902 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.2154330902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.702478330 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 116072272 ps |
| CPU time | 3.98 seconds |
| Started | Oct 09 05:16:29 AM UTC 24 |
| Finished | Oct 09 05:16:34 AM UTC 24 |
| Peak memory | 212308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702478330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.702478330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_error_random.2240636793 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 133545900 ps |
| CPU time | 6.04 seconds |
| Started | Oct 09 05:16:28 AM UTC 24 |
| Finished | Oct 09 05:16:35 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240636793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2240636793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/32.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random.3001217639 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 342493387 ps |
| CPU time | 5.3 seconds |
| Started | Oct 09 05:16:25 AM UTC 24 |
| Finished | Oct 09 05:16:32 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001217639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.3001217639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/32.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.3549115139 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 50275693962 ps |
| CPU time | 150.44 seconds |
| Started | Oct 09 05:16:26 AM UTC 24 |
| Finished | Oct 09 05:18:59 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549115139 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3549115139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/32.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.488510925 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 4554559908 ps |
| CPU time | 38.64 seconds |
| Started | Oct 09 05:16:26 AM UTC 24 |
| Finished | Oct 09 05:17:06 AM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488510925 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.488510925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/32.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_zero_delays.4044039284 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 71495349 ps |
| CPU time | 6.14 seconds |
| Started | Oct 09 05:16:25 AM UTC 24 |
| Finished | Oct 09 05:16:33 AM UTC 24 |
| Peak memory | 212364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044039284 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.4044039284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/32.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_same_source.1305293675 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 124265873 ps |
| CPU time | 2.88 seconds |
| Started | Oct 09 05:16:28 AM UTC 24 |
| Finished | Oct 09 05:16:32 AM UTC 24 |
| Peak memory | 214116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305293675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1305293675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/32.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke.2529256542 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 11144824 ps |
| CPU time | 1.82 seconds |
| Started | Oct 09 05:16:22 AM UTC 24 |
| Finished | Oct 09 05:16:25 AM UTC 24 |
| Peak memory | 211068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529256542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.2529256542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/32.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_large_delays.1542313586 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 1561014777 ps |
| CPU time | 10.6 seconds |
| Started | Oct 09 05:16:24 AM UTC 24 |
| Finished | Oct 09 05:16:36 AM UTC 24 |
| Peak memory | 212368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542313586 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.1542313586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/32.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.2432403363 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 935675946 ps |
| CPU time | 6.76 seconds |
| Started | Oct 09 05:16:24 AM UTC 24 |
| Finished | Oct 09 05:16:32 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432403363 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2432403363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.3912010359 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 18424025 ps |
| CPU time | 1.65 seconds |
| Started | Oct 09 05:16:24 AM UTC 24 |
| Finished | Oct 09 05:16:27 AM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912010359 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.3912010359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/32.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all.2450229202 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 984768502 ps |
| CPU time | 22.17 seconds |
| Started | Oct 09 05:16:29 AM UTC 24 |
| Finished | Oct 09 05:16:53 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450229202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2450229202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/32.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_error.445233607 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 5023936956 ps |
| CPU time | 47.27 seconds |
| Started | Oct 09 05:16:32 AM UTC 24 |
| Finished | Oct 09 05:17:21 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445233607 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.445233607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/32.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.1119580701 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 2135182649 ps |
| CPU time | 38.19 seconds |
| Started | Oct 09 05:16:31 AM UTC 24 |
| Finished | Oct 09 05:17:10 AM UTC 24 |
| Peak memory | 216208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119580701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.1119580701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.3395082720 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 977075616 ps |
| CPU time | 122.4 seconds |
| Started | Oct 09 05:16:33 AM UTC 24 |
| Finished | Oct 09 05:18:38 AM UTC 24 |
| Peak memory | 216212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395082720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.3395082720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_unmapped_addr.2622505899 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 155875123 ps |
| CPU time | 5.84 seconds |
| Started | Oct 09 05:16:28 AM UTC 24 |
| Finished | Oct 09 05:16:35 AM UTC 24 |
| Peak memory | 212240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622505899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.2622505899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/32.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device.842318939 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 33669100 ps |
| CPU time | 4.22 seconds |
| Started | Oct 09 05:16:38 AM UTC 24 |
| Finished | Oct 09 05:16:43 AM UTC 24 |
| Peak memory | 212432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842318939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.842318939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/33.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2871225790 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 11930823457 ps |
| CPU time | 95.25 seconds |
| Started | Oct 09 05:16:38 AM UTC 24 |
| Finished | Oct 09 05:18:15 AM UTC 24 |
| Peak memory | 212180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871225790 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.2871225790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.3536690207 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 61464768 ps |
| CPU time | 4.32 seconds |
| Started | Oct 09 05:16:39 AM UTC 24 |
| Finished | Oct 09 05:16:45 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536690207 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.3536690207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_error_random.1764686543 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 1061056683 ps |
| CPU time | 10.73 seconds |
| Started | Oct 09 05:16:38 AM UTC 24 |
| Finished | Oct 09 05:16:50 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764686543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.1764686543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/33.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random.185209237 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 887524135 ps |
| CPU time | 11.36 seconds |
| Started | Oct 09 05:16:35 AM UTC 24 |
| Finished | Oct 09 05:16:48 AM UTC 24 |
| Peak memory | 212348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185209237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.185209237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/33.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_large_delays.745497009 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 216352697079 ps |
| CPU time | 184.69 seconds |
| Started | Oct 09 05:16:35 AM UTC 24 |
| Finished | Oct 09 05:19:43 AM UTC 24 |
| Peak memory | 212300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745497009 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.745497009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/33.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_slow_rsp.3852331367 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 10301937022 ps |
| CPU time | 51.98 seconds |
| Started | Oct 09 05:16:38 AM UTC 24 |
| Finished | Oct 09 05:17:31 AM UTC 24 |
| Peak memory | 212164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852331367 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3852331367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/33.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_zero_delays.4098848880 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 400159137 ps |
| CPU time | 8.03 seconds |
| Started | Oct 09 05:16:35 AM UTC 24 |
| Finished | Oct 09 05:16:44 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098848880 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.4098848880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/33.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_same_source.2756067257 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 759733209 ps |
| CPU time | 6.51 seconds |
| Started | Oct 09 05:16:38 AM UTC 24 |
| Finished | Oct 09 05:16:46 AM UTC 24 |
| Peak memory | 212364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756067257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.2756067257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/33.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke.2216609254 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 145814037 ps |
| CPU time | 1.79 seconds |
| Started | Oct 09 05:16:33 AM UTC 24 |
| Finished | Oct 09 05:16:36 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216609254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2216609254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/33.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_large_delays.2107834584 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 11333807358 ps |
| CPU time | 18.68 seconds |
| Started | Oct 09 05:16:33 AM UTC 24 |
| Finished | Oct 09 05:16:54 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107834584 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2107834584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/33.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.1505442356 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 1569624351 ps |
| CPU time | 13.43 seconds |
| Started | Oct 09 05:16:35 AM UTC 24 |
| Finished | Oct 09 05:16:50 AM UTC 24 |
| Peak memory | 212340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505442356 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1505442356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.2400787975 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 9777845 ps |
| CPU time | 1.79 seconds |
| Started | Oct 09 05:16:33 AM UTC 24 |
| Finished | Oct 09 05:16:36 AM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400787975 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.2400787975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/33.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all.1601041792 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 771990423 ps |
| CPU time | 19.06 seconds |
| Started | Oct 09 05:16:42 AM UTC 24 |
| Finished | Oct 09 05:17:03 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601041792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.1601041792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/33.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_error.524701487 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 359640093 ps |
| CPU time | 34.55 seconds |
| Started | Oct 09 05:16:43 AM UTC 24 |
| Finished | Oct 09 05:17:18 AM UTC 24 |
| Peak memory | 212304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524701487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.524701487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/33.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3902346437 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 866877961 ps |
| CPU time | 85.8 seconds |
| Started | Oct 09 05:16:43 AM UTC 24 |
| Finished | Oct 09 05:18:10 AM UTC 24 |
| Peak memory | 216212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902346437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.3902346437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.3550879024 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 1308901289 ps |
| CPU time | 129.01 seconds |
| Started | Oct 09 05:16:44 AM UTC 24 |
| Finished | Oct 09 05:18:55 AM UTC 24 |
| Peak memory | 218516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550879024 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.3550879024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_unmapped_addr.3438538438 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 215264401 ps |
| CPU time | 3.92 seconds |
| Started | Oct 09 05:16:38 AM UTC 24 |
| Finished | Oct 09 05:16:43 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438538438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3438538438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/33.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device.2707613645 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 53674022 ps |
| CPU time | 15.82 seconds |
| Started | Oct 09 05:16:49 AM UTC 24 |
| Finished | Oct 09 05:17:06 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707613645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.2707613645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/34.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.3427640380 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 13222211570 ps |
| CPU time | 101.94 seconds |
| Started | Oct 09 05:16:50 AM UTC 24 |
| Finished | Oct 09 05:18:34 AM UTC 24 |
| Peak memory | 212432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427640380 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.3427640380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.1306410137 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 138115834 ps |
| CPU time | 8.2 seconds |
| Started | Oct 09 05:16:53 AM UTC 24 |
| Finished | Oct 09 05:17:02 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306410137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.1306410137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_error_random.1295263833 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 592521024 ps |
| CPU time | 7.62 seconds |
| Started | Oct 09 05:16:52 AM UTC 24 |
| Finished | Oct 09 05:17:00 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295263833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1295263833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/34.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random.3608908527 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 168260003 ps |
| CPU time | 6.34 seconds |
| Started | Oct 09 05:16:47 AM UTC 24 |
| Finished | Oct 09 05:16:55 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608908527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.3608908527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/34.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.4057379175 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 27660194463 ps |
| CPU time | 42.34 seconds |
| Started | Oct 09 05:16:48 AM UTC 24 |
| Finished | Oct 09 05:17:31 AM UTC 24 |
| Peak memory | 212432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057379175 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.4057379175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/34.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_slow_rsp.1737291882 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 10581900580 ps |
| CPU time | 14.73 seconds |
| Started | Oct 09 05:16:49 AM UTC 24 |
| Finished | Oct 09 05:17:05 AM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737291882 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1737291882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/34.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_zero_delays.2102694541 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 102876643 ps |
| CPU time | 7.92 seconds |
| Started | Oct 09 05:16:48 AM UTC 24 |
| Finished | Oct 09 05:16:57 AM UTC 24 |
| Peak memory | 212364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102694541 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.2102694541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/34.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_same_source.4252557958 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 28495495 ps |
| CPU time | 4.42 seconds |
| Started | Oct 09 05:16:51 AM UTC 24 |
| Finished | Oct 09 05:16:57 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252557958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.4252557958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/34.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke.584925119 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 9560262 ps |
| CPU time | 1.76 seconds |
| Started | Oct 09 05:16:44 AM UTC 24 |
| Finished | Oct 09 05:16:47 AM UTC 24 |
| Peak memory | 211136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584925119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.584925119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/34.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_large_delays.1294408798 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 2466275045 ps |
| CPU time | 7.61 seconds |
| Started | Oct 09 05:16:45 AM UTC 24 |
| Finished | Oct 09 05:16:54 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294408798 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.1294408798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/34.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1193834184 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 5475637044 ps |
| CPU time | 22.07 seconds |
| Started | Oct 09 05:16:47 AM UTC 24 |
| Finished | Oct 09 05:17:11 AM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193834184 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1193834184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.953821455 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 10800147 ps |
| CPU time | 1.8 seconds |
| Started | Oct 09 05:16:45 AM UTC 24 |
| Finished | Oct 09 05:16:48 AM UTC 24 |
| Peak memory | 211144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953821455 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.953821455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/34.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all.3043328408 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 595896184 ps |
| CPU time | 14.57 seconds |
| Started | Oct 09 05:16:55 AM UTC 24 |
| Finished | Oct 09 05:17:11 AM UTC 24 |
| Peak memory | 212432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043328408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.3043328408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/34.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_error.1177192797 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 6802645965 ps |
| CPU time | 37.85 seconds |
| Started | Oct 09 05:16:55 AM UTC 24 |
| Finished | Oct 09 05:17:35 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177192797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1177192797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/34.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.2851813141 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 2284812967 ps |
| CPU time | 44.02 seconds |
| Started | Oct 09 05:16:55 AM UTC 24 |
| Finished | Oct 09 05:17:41 AM UTC 24 |
| Peak memory | 214228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851813141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.2851813141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.2049023129 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 117544384 ps |
| CPU time | 10.66 seconds |
| Started | Oct 09 05:16:55 AM UTC 24 |
| Finished | Oct 09 05:17:07 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049023129 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.2049023129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_unmapped_addr.850347297 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 11037477 ps |
| CPU time | 1.88 seconds |
| Started | Oct 09 05:16:53 AM UTC 24 |
| Finished | Oct 09 05:16:56 AM UTC 24 |
| Peak memory | 211144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850347297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.850347297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/34.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device.4266828557 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 799664392 ps |
| CPU time | 18.78 seconds |
| Started | Oct 09 05:17:02 AM UTC 24 |
| Finished | Oct 09 05:17:23 AM UTC 24 |
| Peak memory | 212120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266828557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.4266828557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/35.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.122578712 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 70371181152 ps |
| CPU time | 456.49 seconds |
| Started | Oct 09 05:17:04 AM UTC 24 |
| Finished | Oct 09 05:24:46 AM UTC 24 |
| Peak memory | 218160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122578712 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.122578712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.366254460 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 572066542 ps |
| CPU time | 13.97 seconds |
| Started | Oct 09 05:17:07 AM UTC 24 |
| Finished | Oct 09 05:17:22 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366254460 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.366254460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_error_random.2241249611 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 350275717 ps |
| CPU time | 4.19 seconds |
| Started | Oct 09 05:17:05 AM UTC 24 |
| Finished | Oct 09 05:17:11 AM UTC 24 |
| Peak memory | 212216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241249611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.2241249611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/35.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random.498019870 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 110463629 ps |
| CPU time | 3.86 seconds |
| Started | Oct 09 05:16:58 AM UTC 24 |
| Finished | Oct 09 05:17:03 AM UTC 24 |
| Peak memory | 212348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498019870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.498019870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/35.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.1743901079 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 30273943301 ps |
| CPU time | 55.7 seconds |
| Started | Oct 09 05:17:01 AM UTC 24 |
| Finished | Oct 09 05:17:59 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743901079 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.1743901079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/35.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.1150102830 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 38335768767 ps |
| CPU time | 152.34 seconds |
| Started | Oct 09 05:17:01 AM UTC 24 |
| Finished | Oct 09 05:19:37 AM UTC 24 |
| Peak memory | 212164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150102830 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.1150102830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/35.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_zero_delays.3902877220 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 65901479 ps |
| CPU time | 9.24 seconds |
| Started | Oct 09 05:16:59 AM UTC 24 |
| Finished | Oct 09 05:17:09 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902877220 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.3902877220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/35.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_same_source.3119273581 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 12825260 ps |
| CPU time | 2.14 seconds |
| Started | Oct 09 05:17:04 AM UTC 24 |
| Finished | Oct 09 05:17:07 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119273581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3119273581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/35.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke.638444462 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 12619754 ps |
| CPU time | 1.67 seconds |
| Started | Oct 09 05:16:57 AM UTC 24 |
| Finished | Oct 09 05:17:00 AM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638444462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.638444462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/35.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_large_delays.3441813783 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 2659045704 ps |
| CPU time | 22.66 seconds |
| Started | Oct 09 05:16:57 AM UTC 24 |
| Finished | Oct 09 05:17:21 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441813783 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3441813783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/35.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.2280726140 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 1249352847 ps |
| CPU time | 9.96 seconds |
| Started | Oct 09 05:16:58 AM UTC 24 |
| Finished | Oct 09 05:17:10 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280726140 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.2280726140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.3776307527 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 9748612 ps |
| CPU time | 1.84 seconds |
| Started | Oct 09 05:16:57 AM UTC 24 |
| Finished | Oct 09 05:17:00 AM UTC 24 |
| Peak memory | 211080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776307527 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.3776307527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/35.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all.2695225059 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 3912544020 ps |
| CPU time | 80.62 seconds |
| Started | Oct 09 05:17:07 AM UTC 24 |
| Finished | Oct 09 05:18:30 AM UTC 24 |
| Peak memory | 214228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695225059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2695225059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/35.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_error.1663651848 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 2049735278 ps |
| CPU time | 29.94 seconds |
| Started | Oct 09 05:17:09 AM UTC 24 |
| Finished | Oct 09 05:17:40 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663651848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.1663651848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/35.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1113221921 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 3285775615 ps |
| CPU time | 72.62 seconds |
| Started | Oct 09 05:17:09 AM UTC 24 |
| Finished | Oct 09 05:18:23 AM UTC 24 |
| Peak memory | 214228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113221921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.1113221921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.2190005171 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 6979095435 ps |
| CPU time | 97.18 seconds |
| Started | Oct 09 05:17:10 AM UTC 24 |
| Finished | Oct 09 05:18:49 AM UTC 24 |
| Peak memory | 216532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190005171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.2190005171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_unmapped_addr.3052323049 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 207807739 ps |
| CPU time | 7.69 seconds |
| Started | Oct 09 05:17:07 AM UTC 24 |
| Finished | Oct 09 05:17:16 AM UTC 24 |
| Peak memory | 212368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052323049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3052323049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/35.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device.2759624202 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 44891109 ps |
| CPU time | 13.04 seconds |
| Started | Oct 09 05:17:17 AM UTC 24 |
| Finished | Oct 09 05:17:31 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759624202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.2759624202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/36.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.159051728 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 40093292965 ps |
| CPU time | 315.21 seconds |
| Started | Oct 09 05:17:17 AM UTC 24 |
| Finished | Oct 09 05:22:37 AM UTC 24 |
| Peak memory | 214228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159051728 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.159051728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.969140237 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 3028623517 ps |
| CPU time | 12.73 seconds |
| Started | Oct 09 05:17:23 AM UTC 24 |
| Finished | Oct 09 05:17:37 AM UTC 24 |
| Peak memory | 212248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969140237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.969140237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_error_random.661871787 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 58840810 ps |
| CPU time | 5.98 seconds |
| Started | Oct 09 05:17:23 AM UTC 24 |
| Finished | Oct 09 05:17:30 AM UTC 24 |
| Peak memory | 212344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661871787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.661871787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/36.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random.3799611378 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 479105046 ps |
| CPU time | 13.82 seconds |
| Started | Oct 09 05:17:13 AM UTC 24 |
| Finished | Oct 09 05:17:28 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799611378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.3799611378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/36.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.3002277312 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 34182243610 ps |
| CPU time | 165.32 seconds |
| Started | Oct 09 05:17:15 AM UTC 24 |
| Finished | Oct 09 05:20:04 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002277312 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3002277312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/36.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.1005175973 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 1303061790 ps |
| CPU time | 13.96 seconds |
| Started | Oct 09 05:17:17 AM UTC 24 |
| Finished | Oct 09 05:17:32 AM UTC 24 |
| Peak memory | 212096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005175973 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.1005175973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/36.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_zero_delays.2695838719 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 81576005 ps |
| CPU time | 10.97 seconds |
| Started | Oct 09 05:17:13 AM UTC 24 |
| Finished | Oct 09 05:17:25 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695838719 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.2695838719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/36.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_same_source.3500954319 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 2255650450 ps |
| CPU time | 9.18 seconds |
| Started | Oct 09 05:17:19 AM UTC 24 |
| Finished | Oct 09 05:17:30 AM UTC 24 |
| Peak memory | 214184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500954319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3500954319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/36.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke.1609820487 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 165199412 ps |
| CPU time | 2.42 seconds |
| Started | Oct 09 05:17:11 AM UTC 24 |
| Finished | Oct 09 05:17:15 AM UTC 24 |
| Peak memory | 212084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609820487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1609820487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/36.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_large_delays.3553028937 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 4353856997 ps |
| CPU time | 16.99 seconds |
| Started | Oct 09 05:17:11 AM UTC 24 |
| Finished | Oct 09 05:17:30 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553028937 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.3553028937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/36.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.3185818605 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 1407275393 ps |
| CPU time | 9.01 seconds |
| Started | Oct 09 05:17:13 AM UTC 24 |
| Finished | Oct 09 05:17:23 AM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185818605 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3185818605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.1020151198 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 12984079 ps |
| CPU time | 1.79 seconds |
| Started | Oct 09 05:17:11 AM UTC 24 |
| Finished | Oct 09 05:17:14 AM UTC 24 |
| Peak memory | 211136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020151198 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.1020151198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/36.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all.1490629819 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 6760791307 ps |
| CPU time | 85.67 seconds |
| Started | Oct 09 05:17:24 AM UTC 24 |
| Finished | Oct 09 05:18:52 AM UTC 24 |
| Peak memory | 214548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490629819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.1490629819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/36.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_error.561542947 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 532639803 ps |
| CPU time | 8.16 seconds |
| Started | Oct 09 05:17:24 AM UTC 24 |
| Finished | Oct 09 05:17:34 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561542947 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.561542947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/36.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2738535180 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 1032965999 ps |
| CPU time | 164.89 seconds |
| Started | Oct 09 05:17:24 AM UTC 24 |
| Finished | Oct 09 05:20:12 AM UTC 24 |
| Peak memory | 218516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738535180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.2738535180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.966561322 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 20158880007 ps |
| CPU time | 129.28 seconds |
| Started | Oct 09 05:17:24 AM UTC 24 |
| Finished | Oct 09 05:19:36 AM UTC 24 |
| Peak memory | 216280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966561322 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.966561322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_unmapped_addr.3020071011 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 126756775 ps |
| CPU time | 6.53 seconds |
| Started | Oct 09 05:17:23 AM UTC 24 |
| Finished | Oct 09 05:17:31 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020071011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.3020071011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/36.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device.3339293017 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 288838798 ps |
| CPU time | 7.2 seconds |
| Started | Oct 09 05:17:32 AM UTC 24 |
| Finished | Oct 09 05:17:40 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339293017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.3339293017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/37.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3329355117 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 33908185409 ps |
| CPU time | 128.33 seconds |
| Started | Oct 09 05:17:32 AM UTC 24 |
| Finished | Oct 09 05:19:43 AM UTC 24 |
| Peak memory | 214484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329355117 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.3329355117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.2281935129 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 1269868246 ps |
| CPU time | 4.23 seconds |
| Started | Oct 09 05:17:35 AM UTC 24 |
| Finished | Oct 09 05:17:40 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281935129 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.2281935129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_error_random.72673159 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 318885516 ps |
| CPU time | 4.56 seconds |
| Started | Oct 09 05:17:35 AM UTC 24 |
| Finished | Oct 09 05:17:40 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72673159 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.72673159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/37.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random.1204253578 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 2874274234 ps |
| CPU time | 20.39 seconds |
| Started | Oct 09 05:17:30 AM UTC 24 |
| Finished | Oct 09 05:17:52 AM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204253578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.1204253578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/37.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.163886848 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 26347601459 ps |
| CPU time | 104.39 seconds |
| Started | Oct 09 05:17:31 AM UTC 24 |
| Finished | Oct 09 05:19:17 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163886848 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.163886848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/37.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.1429350185 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 35940908657 ps |
| CPU time | 70.37 seconds |
| Started | Oct 09 05:17:31 AM UTC 24 |
| Finished | Oct 09 05:18:43 AM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429350185 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1429350185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/37.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_zero_delays.2188154595 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 319384556 ps |
| CPU time | 6.42 seconds |
| Started | Oct 09 05:17:31 AM UTC 24 |
| Finished | Oct 09 05:17:38 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188154595 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.2188154595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/37.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_same_source.3892120896 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 108302633 ps |
| CPU time | 2.39 seconds |
| Started | Oct 09 05:17:32 AM UTC 24 |
| Finished | Oct 09 05:17:36 AM UTC 24 |
| Peak memory | 212428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892120896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3892120896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/37.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke.1248783059 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 57771854 ps |
| CPU time | 2.6 seconds |
| Started | Oct 09 05:17:26 AM UTC 24 |
| Finished | Oct 09 05:17:30 AM UTC 24 |
| Peak memory | 212348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248783059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.1248783059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/37.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_large_delays.3105595829 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 1938655544 ps |
| CPU time | 16.4 seconds |
| Started | Oct 09 05:17:28 AM UTC 24 |
| Finished | Oct 09 05:17:45 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105595829 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.3105595829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/37.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.3655643173 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 2513632982 ps |
| CPU time | 6.55 seconds |
| Started | Oct 09 05:17:29 AM UTC 24 |
| Finished | Oct 09 05:17:36 AM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655643173 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.3655643173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.1504826238 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 10106047 ps |
| CPU time | 1.83 seconds |
| Started | Oct 09 05:17:26 AM UTC 24 |
| Finished | Oct 09 05:17:29 AM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504826238 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.1504826238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/37.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.1911006947 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 4586412993 ps |
| CPU time | 78.52 seconds |
| Started | Oct 09 05:17:35 AM UTC 24 |
| Finished | Oct 09 05:18:55 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911006947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.1911006947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/37.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_error.3838735539 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 777887567 ps |
| CPU time | 9.92 seconds |
| Started | Oct 09 05:17:36 AM UTC 24 |
| Finished | Oct 09 05:17:47 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838735539 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.3838735539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/37.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.2455055071 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 5879399055 ps |
| CPU time | 107.23 seconds |
| Started | Oct 09 05:17:35 AM UTC 24 |
| Finished | Oct 09 05:19:24 AM UTC 24 |
| Peak memory | 216276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455055071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.2455055071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3822764546 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 9268335349 ps |
| CPU time | 51.17 seconds |
| Started | Oct 09 05:17:36 AM UTC 24 |
| Finished | Oct 09 05:18:29 AM UTC 24 |
| Peak memory | 214228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822764546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.3822764546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_unmapped_addr.4059643890 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 715361657 ps |
| CPU time | 13.8 seconds |
| Started | Oct 09 05:17:35 AM UTC 24 |
| Finished | Oct 09 05:17:50 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059643890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.4059643890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/37.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device.347821736 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 55321124 ps |
| CPU time | 12.31 seconds |
| Started | Oct 09 05:17:41 AM UTC 24 |
| Finished | Oct 09 05:17:55 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347821736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.347821736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/38.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.1891485105 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 6464770449 ps |
| CPU time | 63.43 seconds |
| Started | Oct 09 05:17:43 AM UTC 24 |
| Finished | Oct 09 05:18:48 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891485105 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.1891485105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.1299583516 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 32578796 ps |
| CPU time | 1.8 seconds |
| Started | Oct 09 05:17:47 AM UTC 24 |
| Finished | Oct 09 05:17:50 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299583516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.1299583516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_error_random.3352923618 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 4401935473 ps |
| CPU time | 19.46 seconds |
| Started | Oct 09 05:17:43 AM UTC 24 |
| Finished | Oct 09 05:18:04 AM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352923618 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.3352923618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/38.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random.3336717413 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 55410353 ps |
| CPU time | 8.29 seconds |
| Started | Oct 09 05:17:40 AM UTC 24 |
| Finished | Oct 09 05:17:49 AM UTC 24 |
| Peak memory | 212344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336717413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.3336717413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/38.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.1788939466 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 10754274357 ps |
| CPU time | 46.9 seconds |
| Started | Oct 09 05:17:41 AM UTC 24 |
| Finished | Oct 09 05:18:30 AM UTC 24 |
| Peak memory | 212304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788939466 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.1788939466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/38.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.2950386192 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 117015028518 ps |
| CPU time | 162.46 seconds |
| Started | Oct 09 05:17:41 AM UTC 24 |
| Finished | Oct 09 05:20:27 AM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950386192 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.2950386192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/38.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_zero_delays.3700805991 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 15782013 ps |
| CPU time | 1.98 seconds |
| Started | Oct 09 05:17:41 AM UTC 24 |
| Finished | Oct 09 05:17:44 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700805991 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.3700805991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/38.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_same_source.747382315 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 1276158324 ps |
| CPU time | 15.15 seconds |
| Started | Oct 09 05:17:43 AM UTC 24 |
| Finished | Oct 09 05:18:00 AM UTC 24 |
| Peak memory | 212100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747382315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.747382315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/38.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke.951861757 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 60490038 ps |
| CPU time | 2.25 seconds |
| Started | Oct 09 05:17:38 AM UTC 24 |
| Finished | Oct 09 05:17:42 AM UTC 24 |
| Peak memory | 212364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951861757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.951861757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/38.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_large_delays.365418054 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 2793619836 ps |
| CPU time | 11.18 seconds |
| Started | Oct 09 05:17:39 AM UTC 24 |
| Finished | Oct 09 05:17:51 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365418054 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.365418054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/38.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.3254368030 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 1216748564 ps |
| CPU time | 7.97 seconds |
| Started | Oct 09 05:17:39 AM UTC 24 |
| Finished | Oct 09 05:17:48 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254368030 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.3254368030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.2991978943 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 13492676 ps |
| CPU time | 1.47 seconds |
| Started | Oct 09 05:17:39 AM UTC 24 |
| Finished | Oct 09 05:17:41 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991978943 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.2991978943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/38.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.92759411 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 9287696255 ps |
| CPU time | 114.53 seconds |
| Started | Oct 09 05:17:49 AM UTC 24 |
| Finished | Oct 09 05:19:45 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92759411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-si m-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.92759411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/38.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.3247518092 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 2406955256 ps |
| CPU time | 41.96 seconds |
| Started | Oct 09 05:17:51 AM UTC 24 |
| Finished | Oct 09 05:18:35 AM UTC 24 |
| Peak memory | 214480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247518092 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3247518092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/38.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.1522180783 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 726422000 ps |
| CPU time | 136.89 seconds |
| Started | Oct 09 05:17:49 AM UTC 24 |
| Finished | Oct 09 05:20:08 AM UTC 24 |
| Peak memory | 214132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522180783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.1522180783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.1855268022 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 302147529 ps |
| CPU time | 37.09 seconds |
| Started | Oct 09 05:17:51 AM UTC 24 |
| Finished | Oct 09 05:18:30 AM UTC 24 |
| Peak memory | 214164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855268022 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.1855268022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_unmapped_addr.142859281 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 599041006 ps |
| CPU time | 7.52 seconds |
| Started | Oct 09 05:17:45 AM UTC 24 |
| Finished | Oct 09 05:17:54 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142859281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.142859281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/38.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device.2677856754 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 270887675 ps |
| CPU time | 10.97 seconds |
| Started | Oct 09 05:18:01 AM UTC 24 |
| Finished | Oct 09 05:18:13 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677856754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.2677856754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/39.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.2900393314 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 274030404780 ps |
| CPU time | 405.86 seconds |
| Started | Oct 09 05:18:01 AM UTC 24 |
| Finished | Oct 09 05:24:52 AM UTC 24 |
| Peak memory | 219948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900393314 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.2900393314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.3034191859 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 4304925393 ps |
| CPU time | 10.64 seconds |
| Started | Oct 09 05:18:05 AM UTC 24 |
| Finished | Oct 09 05:18:17 AM UTC 24 |
| Peak memory | 212180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034191859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.3034191859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_error_random.1543848874 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 631421936 ps |
| CPU time | 11.75 seconds |
| Started | Oct 09 05:18:02 AM UTC 24 |
| Finished | Oct 09 05:18:15 AM UTC 24 |
| Peak memory | 212348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543848874 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1543848874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/39.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random.1598040405 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 2168144976 ps |
| CPU time | 18.28 seconds |
| Started | Oct 09 05:17:55 AM UTC 24 |
| Finished | Oct 09 05:18:15 AM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598040405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.1598040405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/39.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.2432374466 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 14762633746 ps |
| CPU time | 41.71 seconds |
| Started | Oct 09 05:17:56 AM UTC 24 |
| Finished | Oct 09 05:18:40 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432374466 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2432374466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/39.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.2854566924 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 9709081315 ps |
| CPU time | 41.87 seconds |
| Started | Oct 09 05:18:00 AM UTC 24 |
| Finished | Oct 09 05:18:43 AM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854566924 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.2854566924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/39.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_zero_delays.2420472355 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 57993793 ps |
| CPU time | 2.94 seconds |
| Started | Oct 09 05:17:56 AM UTC 24 |
| Finished | Oct 09 05:18:00 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420472355 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.2420472355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/39.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_same_source.3824662061 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 1165490346 ps |
| CPU time | 11.32 seconds |
| Started | Oct 09 05:18:01 AM UTC 24 |
| Finished | Oct 09 05:18:14 AM UTC 24 |
| Peak memory | 212100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824662061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3824662061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/39.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke.2160921503 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 17663581 ps |
| CPU time | 1.81 seconds |
| Started | Oct 09 05:17:51 AM UTC 24 |
| Finished | Oct 09 05:17:54 AM UTC 24 |
| Peak memory | 211080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160921503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2160921503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/39.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_large_delays.998576344 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 6350553036 ps |
| CPU time | 18.66 seconds |
| Started | Oct 09 05:17:54 AM UTC 24 |
| Finished | Oct 09 05:18:13 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998576344 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.998576344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/39.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.2629921309 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 1807177524 ps |
| CPU time | 23.24 seconds |
| Started | Oct 09 05:17:55 AM UTC 24 |
| Finished | Oct 09 05:18:20 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629921309 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.2629921309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2736563634 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 12201792 ps |
| CPU time | 2.04 seconds |
| Started | Oct 09 05:17:52 AM UTC 24 |
| Finished | Oct 09 05:17:55 AM UTC 24 |
| Peak memory | 212360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736563634 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.2736563634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/39.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.494317364 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 419709995 ps |
| CPU time | 41.44 seconds |
| Started | Oct 09 05:18:09 AM UTC 24 |
| Finished | Oct 09 05:18:52 AM UTC 24 |
| Peak memory | 214160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494317364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.494317364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/39.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.733447371 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 2281325695 ps |
| CPU time | 26.41 seconds |
| Started | Oct 09 05:18:12 AM UTC 24 |
| Finished | Oct 09 05:18:40 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733447371 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.733447371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/39.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.2049965342 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 2955024600 ps |
| CPU time | 32.6 seconds |
| Started | Oct 09 05:18:11 AM UTC 24 |
| Finished | Oct 09 05:18:45 AM UTC 24 |
| Peak memory | 214412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049965342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.2049965342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.3633188340 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 538079171 ps |
| CPU time | 72.3 seconds |
| Started | Oct 09 05:18:15 AM UTC 24 |
| Finished | Oct 09 05:19:29 AM UTC 24 |
| Peak memory | 216468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633188340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.3633188340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_unmapped_addr.693248735 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 750127145 ps |
| CPU time | 16.26 seconds |
| Started | Oct 09 05:18:05 AM UTC 24 |
| Finished | Oct 09 05:18:22 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693248735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.693248735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/39.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device.2549680203 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 147225473 ps |
| CPU time | 11.87 seconds |
| Started | Oct 09 05:10:15 AM UTC 24 |
| Finished | Oct 09 05:10:28 AM UTC 24 |
| Peak memory | 212368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549680203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.2549680203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/4.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.1473478134 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 30988145867 ps |
| CPU time | 303.97 seconds |
| Started | Oct 09 05:10:17 AM UTC 24 |
| Finished | Oct 09 05:15:26 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473478134 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.1473478134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.2850710446 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 283823873 ps |
| CPU time | 4.4 seconds |
| Started | Oct 09 05:10:20 AM UTC 24 |
| Finished | Oct 09 05:10:26 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850710446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.2850710446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_error_random.2658894223 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 1100582231 ps |
| CPU time | 14.92 seconds |
| Started | Oct 09 05:10:18 AM UTC 24 |
| Finished | Oct 09 05:10:34 AM UTC 24 |
| Peak memory | 212348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658894223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.2658894223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/4.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random.3812029315 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 42389361 ps |
| CPU time | 5.66 seconds |
| Started | Oct 09 05:10:13 AM UTC 24 |
| Finished | Oct 09 05:10:20 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812029315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.3812029315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/4.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_large_delays.3118078351 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 60928072640 ps |
| CPU time | 109.11 seconds |
| Started | Oct 09 05:10:14 AM UTC 24 |
| Finished | Oct 09 05:12:06 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118078351 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.3118078351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/4.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_slow_rsp.2235286344 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 13568360681 ps |
| CPU time | 100.7 seconds |
| Started | Oct 09 05:10:15 AM UTC 24 |
| Finished | Oct 09 05:11:58 AM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235286344 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.2235286344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/4.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_zero_delays.2938238734 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 17715836 ps |
| CPU time | 1.64 seconds |
| Started | Oct 09 05:10:13 AM UTC 24 |
| Finished | Oct 09 05:10:16 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938238734 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.2938238734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/4.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_same_source.812885218 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 18419607 ps |
| CPU time | 3.11 seconds |
| Started | Oct 09 05:10:17 AM UTC 24 |
| Finished | Oct 09 05:10:22 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812885218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.812885218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/4.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke.1296549767 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 8364363 ps |
| CPU time | 1.87 seconds |
| Started | Oct 09 05:10:08 AM UTC 24 |
| Finished | Oct 09 05:10:12 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296549767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1296549767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/4.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_large_delays.3510112260 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 1521260553 ps |
| CPU time | 7.97 seconds |
| Started | Oct 09 05:10:13 AM UTC 24 |
| Finished | Oct 09 05:10:22 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510112260 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.3510112260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/4.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.2526946336 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 4650880907 ps |
| CPU time | 11.08 seconds |
| Started | Oct 09 05:10:13 AM UTC 24 |
| Finished | Oct 09 05:10:25 AM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526946336 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2526946336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.4237658870 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 8576226 ps |
| CPU time | 1.44 seconds |
| Started | Oct 09 05:10:09 AM UTC 24 |
| Finished | Oct 09 05:10:11 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237658870 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.4237658870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/4.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all.279447652 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 10005707724 ps |
| CPU time | 74.73 seconds |
| Started | Oct 09 05:10:20 AM UTC 24 |
| Finished | Oct 09 05:11:37 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279447652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.279447652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/4.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_error.1484008714 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 13864078008 ps |
| CPU time | 91.51 seconds |
| Started | Oct 09 05:10:22 AM UTC 24 |
| Finished | Oct 09 05:11:56 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484008714 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1484008714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/4.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.3398330998 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 402407551 ps |
| CPU time | 83.69 seconds |
| Started | Oct 09 05:10:21 AM UTC 24 |
| Finished | Oct 09 05:11:47 AM UTC 24 |
| Peak memory | 216208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398330998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.3398330998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.3563377761 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 363081485 ps |
| CPU time | 22.32 seconds |
| Started | Oct 09 05:10:23 AM UTC 24 |
| Finished | Oct 09 05:10:46 AM UTC 24 |
| Peak memory | 214416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563377761 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.3563377761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_unmapped_addr.4149494663 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 308852614 ps |
| CPU time | 8.73 seconds |
| Started | Oct 09 05:10:18 AM UTC 24 |
| Finished | Oct 09 05:10:27 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149494663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.4149494663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/4.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device.3335597266 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 40481617 ps |
| CPU time | 6.85 seconds |
| Started | Oct 09 05:18:19 AM UTC 24 |
| Finished | Oct 09 05:18:27 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335597266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.3335597266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/40.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3999151090 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 22660744234 ps |
| CPU time | 153.53 seconds |
| Started | Oct 09 05:18:19 AM UTC 24 |
| Finished | Oct 09 05:20:55 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999151090 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.3999151090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.1120922584 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 392791083 ps |
| CPU time | 9.27 seconds |
| Started | Oct 09 05:18:23 AM UTC 24 |
| Finished | Oct 09 05:18:34 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120922584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.1120922584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_error_random.3055542994 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 189196232 ps |
| CPU time | 4.31 seconds |
| Started | Oct 09 05:18:21 AM UTC 24 |
| Finished | Oct 09 05:18:27 AM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055542994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3055542994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/40.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random.4279361344 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 176920691 ps |
| CPU time | 6.84 seconds |
| Started | Oct 09 05:18:17 AM UTC 24 |
| Finished | Oct 09 05:18:24 AM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279361344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.4279361344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/40.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.2262765686 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 35545945557 ps |
| CPU time | 107.77 seconds |
| Started | Oct 09 05:18:17 AM UTC 24 |
| Finished | Oct 09 05:20:07 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262765686 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.2262765686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/40.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.4282043576 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 2320129847 ps |
| CPU time | 18.16 seconds |
| Started | Oct 09 05:18:18 AM UTC 24 |
| Finished | Oct 09 05:18:37 AM UTC 24 |
| Peak memory | 212420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282043576 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.4282043576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/40.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_zero_delays.2880172663 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 40160506 ps |
| CPU time | 4.05 seconds |
| Started | Oct 09 05:18:17 AM UTC 24 |
| Finished | Oct 09 05:18:22 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880172663 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.2880172663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/40.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_same_source.1132134788 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 3673462424 ps |
| CPU time | 16.32 seconds |
| Started | Oct 09 05:18:21 AM UTC 24 |
| Finished | Oct 09 05:18:39 AM UTC 24 |
| Peak memory | 212168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132134788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.1132134788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/40.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke.2232157402 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 45580826 ps |
| CPU time | 1.79 seconds |
| Started | Oct 09 05:18:15 AM UTC 24 |
| Finished | Oct 09 05:18:18 AM UTC 24 |
| Peak memory | 211084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232157402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2232157402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/40.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_large_delays.1212192022 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 2104247962 ps |
| CPU time | 9.74 seconds |
| Started | Oct 09 05:18:15 AM UTC 24 |
| Finished | Oct 09 05:18:26 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212192022 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.1212192022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/40.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.1628761821 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 2375844178 ps |
| CPU time | 13.95 seconds |
| Started | Oct 09 05:18:16 AM UTC 24 |
| Finished | Oct 09 05:18:32 AM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628761821 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1628761821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.2111063173 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 9068678 ps |
| CPU time | 1.86 seconds |
| Started | Oct 09 05:18:15 AM UTC 24 |
| Finished | Oct 09 05:18:18 AM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111063173 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.2111063173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/40.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.2900077056 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 537119080 ps |
| CPU time | 34.34 seconds |
| Started | Oct 09 05:18:25 AM UTC 24 |
| Finished | Oct 09 05:19:00 AM UTC 24 |
| Peak memory | 214152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900077056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.2900077056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/40.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.150608963 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 5312682679 ps |
| CPU time | 74.06 seconds |
| Started | Oct 09 05:18:25 AM UTC 24 |
| Finished | Oct 09 05:19:41 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150608963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.150608963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/40.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.156493281 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 1419088271 ps |
| CPU time | 110.26 seconds |
| Started | Oct 09 05:18:25 AM UTC 24 |
| Finished | Oct 09 05:20:17 AM UTC 24 |
| Peak memory | 216204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156493281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.156493281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.193840935 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 13937778869 ps |
| CPU time | 86.19 seconds |
| Started | Oct 09 05:18:26 AM UTC 24 |
| Finished | Oct 09 05:19:54 AM UTC 24 |
| Peak memory | 216276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193840935 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.193840935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_unmapped_addr.3554262429 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 213611074 ps |
| CPU time | 8.59 seconds |
| Started | Oct 09 05:18:21 AM UTC 24 |
| Finished | Oct 09 05:18:31 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554262429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3554262429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/40.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device.1006710903 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1351981656 ps |
| CPU time | 22.29 seconds |
| Started | Oct 09 05:18:32 AM UTC 24 |
| Finished | Oct 09 05:18:55 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006710903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.1006710903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/41.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.375128798 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 46996702 ps |
| CPU time | 2.1 seconds |
| Started | Oct 09 05:18:35 AM UTC 24 |
| Finished | Oct 09 05:18:38 AM UTC 24 |
| Peak memory | 212436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375128798 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.375128798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_error_random.2853457192 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 25923492 ps |
| CPU time | 2.07 seconds |
| Started | Oct 09 05:18:33 AM UTC 24 |
| Finished | Oct 09 05:18:37 AM UTC 24 |
| Peak memory | 212352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853457192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.2853457192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/41.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random.2655526865 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 477129398 ps |
| CPU time | 6.89 seconds |
| Started | Oct 09 05:18:29 AM UTC 24 |
| Finished | Oct 09 05:18:38 AM UTC 24 |
| Peak memory | 212344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655526865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.2655526865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/41.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.855939925 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 18584786187 ps |
| CPU time | 44.64 seconds |
| Started | Oct 09 05:18:31 AM UTC 24 |
| Finished | Oct 09 05:19:18 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855939925 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.855939925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/41.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.986203159 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 13000903389 ps |
| CPU time | 79 seconds |
| Started | Oct 09 05:18:31 AM UTC 24 |
| Finished | Oct 09 05:19:53 AM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986203159 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.986203159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/41.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_zero_delays.3366849316 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 21606351 ps |
| CPU time | 3.93 seconds |
| Started | Oct 09 05:18:31 AM UTC 24 |
| Finished | Oct 09 05:18:37 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366849316 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.3366849316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/41.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_same_source.3631479440 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 715123146 ps |
| CPU time | 12.03 seconds |
| Started | Oct 09 05:18:33 AM UTC 24 |
| Finished | Oct 09 05:18:47 AM UTC 24 |
| Peak memory | 212428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631479440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.3631479440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/41.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke.1802015700 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 62662336 ps |
| CPU time | 2.23 seconds |
| Started | Oct 09 05:18:26 AM UTC 24 |
| Finished | Oct 09 05:18:30 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802015700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1802015700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/41.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_large_delays.940755566 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 2010846111 ps |
| CPU time | 14.91 seconds |
| Started | Oct 09 05:18:28 AM UTC 24 |
| Finished | Oct 09 05:18:45 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940755566 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.940755566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/41.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.3498792257 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 1897441782 ps |
| CPU time | 5.42 seconds |
| Started | Oct 09 05:18:29 AM UTC 24 |
| Finished | Oct 09 05:18:36 AM UTC 24 |
| Peak memory | 212096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498792257 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.3498792257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.4279205903 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 11789334 ps |
| CPU time | 1.54 seconds |
| Started | Oct 09 05:18:27 AM UTC 24 |
| Finished | Oct 09 05:18:31 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279205903 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.4279205903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/41.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.2388587053 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 341375057 ps |
| CPU time | 21.24 seconds |
| Started | Oct 09 05:18:36 AM UTC 24 |
| Finished | Oct 09 05:18:59 AM UTC 24 |
| Peak memory | 214160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388587053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.2388587053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/41.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.4052321433 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 1319668354 ps |
| CPU time | 22.08 seconds |
| Started | Oct 09 05:18:38 AM UTC 24 |
| Finished | Oct 09 05:19:01 AM UTC 24 |
| Peak memory | 212368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052321433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.4052321433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/41.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.2370144220 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 3387954968 ps |
| CPU time | 129.8 seconds |
| Started | Oct 09 05:18:36 AM UTC 24 |
| Finished | Oct 09 05:20:49 AM UTC 24 |
| Peak memory | 216532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370144220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.2370144220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.1232743230 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 1957206372 ps |
| CPU time | 24.09 seconds |
| Started | Oct 09 05:18:38 AM UTC 24 |
| Finished | Oct 09 05:19:03 AM UTC 24 |
| Peak memory | 214400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232743230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.1232743230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_unmapped_addr.1306879092 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 134504507 ps |
| CPU time | 5.61 seconds |
| Started | Oct 09 05:18:33 AM UTC 24 |
| Finished | Oct 09 05:18:41 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306879092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1306879092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/41.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device.1733289926 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 152698927 ps |
| CPU time | 11.39 seconds |
| Started | Oct 09 05:18:43 AM UTC 24 |
| Finished | Oct 09 05:18:56 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733289926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.1733289926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/42.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.3609166530 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 22438776639 ps |
| CPU time | 108.29 seconds |
| Started | Oct 09 05:18:43 AM UTC 24 |
| Finished | Oct 09 05:20:34 AM UTC 24 |
| Peak memory | 214228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609166530 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.3609166530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.512021985 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 79442122 ps |
| CPU time | 2.62 seconds |
| Started | Oct 09 05:18:46 AM UTC 24 |
| Finished | Oct 09 05:18:50 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512021985 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.512021985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_error_random.3514463781 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 77307954 ps |
| CPU time | 3.54 seconds |
| Started | Oct 09 05:18:43 AM UTC 24 |
| Finished | Oct 09 05:18:48 AM UTC 24 |
| Peak memory | 212220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514463781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3514463781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/42.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random.2044665452 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 74738123 ps |
| CPU time | 4.9 seconds |
| Started | Oct 09 05:18:41 AM UTC 24 |
| Finished | Oct 09 05:18:47 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044665452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2044665452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/42.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.2445073022 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 21199622329 ps |
| CPU time | 64 seconds |
| Started | Oct 09 05:18:41 AM UTC 24 |
| Finished | Oct 09 05:19:47 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445073022 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2445073022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/42.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.615775075 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 60227540305 ps |
| CPU time | 86.09 seconds |
| Started | Oct 09 05:18:43 AM UTC 24 |
| Finished | Oct 09 05:20:11 AM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615775075 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.615775075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/42.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_zero_delays.4087562238 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 47579959 ps |
| CPU time | 7.89 seconds |
| Started | Oct 09 05:18:41 AM UTC 24 |
| Finished | Oct 09 05:18:50 AM UTC 24 |
| Peak memory | 212428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087562238 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.4087562238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/42.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_same_source.1609865356 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 2471668756 ps |
| CPU time | 10.44 seconds |
| Started | Oct 09 05:18:43 AM UTC 24 |
| Finished | Oct 09 05:18:55 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609865356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.1609865356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/42.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke.3445115761 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 138409940 ps |
| CPU time | 1.91 seconds |
| Started | Oct 09 05:18:38 AM UTC 24 |
| Finished | Oct 09 05:18:41 AM UTC 24 |
| Peak memory | 211084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445115761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.3445115761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/42.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1208881561 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 4970396979 ps |
| CPU time | 13.1 seconds |
| Started | Oct 09 05:18:41 AM UTC 24 |
| Finished | Oct 09 05:18:55 AM UTC 24 |
| Peak memory | 212432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208881561 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1208881561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/42.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.3513301495 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 1349567707 ps |
| CPU time | 8.82 seconds |
| Started | Oct 09 05:18:41 AM UTC 24 |
| Finished | Oct 09 05:18:51 AM UTC 24 |
| Peak memory | 212352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513301495 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3513301495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.1228237432 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 9556254 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 05:18:38 AM UTC 24 |
| Finished | Oct 09 05:18:40 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228237432 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.1228237432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/42.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.1777550330 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 1375487449 ps |
| CPU time | 29.74 seconds |
| Started | Oct 09 05:18:46 AM UTC 24 |
| Finished | Oct 09 05:19:18 AM UTC 24 |
| Peak memory | 214420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777550330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1777550330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/42.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.182862219 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 489531309 ps |
| CPU time | 29.15 seconds |
| Started | Oct 09 05:18:46 AM UTC 24 |
| Finished | Oct 09 05:19:17 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182862219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.182862219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/42.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.148986710 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 60647728 ps |
| CPU time | 9.44 seconds |
| Started | Oct 09 05:18:46 AM UTC 24 |
| Finished | Oct 09 05:18:57 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148986710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.148986710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.3897201545 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 1404187208 ps |
| CPU time | 110.17 seconds |
| Started | Oct 09 05:18:46 AM UTC 24 |
| Finished | Oct 09 05:20:39 AM UTC 24 |
| Peak memory | 216212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897201545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.3897201545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_unmapped_addr.3712795523 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 685753419 ps |
| CPU time | 10.4 seconds |
| Started | Oct 09 05:18:43 AM UTC 24 |
| Finished | Oct 09 05:18:55 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712795523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3712795523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/42.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.3097000400 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 408069321 ps |
| CPU time | 10.84 seconds |
| Started | Oct 09 05:18:53 AM UTC 24 |
| Finished | Oct 09 05:19:05 AM UTC 24 |
| Peak memory | 212376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097000400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.3097000400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/43.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.738346754 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 68344009830 ps |
| CPU time | 287 seconds |
| Started | Oct 09 05:18:53 AM UTC 24 |
| Finished | Oct 09 05:23:44 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738346754 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.738346754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.514755426 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 217570696 ps |
| CPU time | 4.95 seconds |
| Started | Oct 09 05:19:03 AM UTC 24 |
| Finished | Oct 09 05:19:09 AM UTC 24 |
| Peak memory | 212240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514755426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.514755426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.753115892 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 548356748 ps |
| CPU time | 3.06 seconds |
| Started | Oct 09 05:18:57 AM UTC 24 |
| Finished | Oct 09 05:19:01 AM UTC 24 |
| Peak memory | 212084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753115892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.753115892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/43.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random.2497670742 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 1328763587 ps |
| CPU time | 8.01 seconds |
| Started | Oct 09 05:18:53 AM UTC 24 |
| Finished | Oct 09 05:19:02 AM UTC 24 |
| Peak memory | 212084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497670742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.2497670742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/43.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.1320040160 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 34922781603 ps |
| CPU time | 118.04 seconds |
| Started | Oct 09 05:18:53 AM UTC 24 |
| Finished | Oct 09 05:20:53 AM UTC 24 |
| Peak memory | 212432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320040160 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.1320040160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/43.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.1083301936 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 9531434442 ps |
| CPU time | 47.72 seconds |
| Started | Oct 09 05:18:53 AM UTC 24 |
| Finished | Oct 09 05:19:43 AM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083301936 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1083301936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/43.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.3037366174 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 54055162 ps |
| CPU time | 8.26 seconds |
| Started | Oct 09 05:18:53 AM UTC 24 |
| Finished | Oct 09 05:19:03 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037366174 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.3037366174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/43.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.282021510 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 48584292 ps |
| CPU time | 3.8 seconds |
| Started | Oct 09 05:18:57 AM UTC 24 |
| Finished | Oct 09 05:19:02 AM UTC 24 |
| Peak memory | 212096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282021510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.282021510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/43.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke.1275868540 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 14028686 ps |
| CPU time | 1.72 seconds |
| Started | Oct 09 05:18:48 AM UTC 24 |
| Finished | Oct 09 05:18:51 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275868540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1275868540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/43.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.3589047707 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 2498725925 ps |
| CPU time | 6.82 seconds |
| Started | Oct 09 05:18:50 AM UTC 24 |
| Finished | Oct 09 05:18:58 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589047707 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.3589047707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/43.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.3714938412 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 956602784 ps |
| CPU time | 8.89 seconds |
| Started | Oct 09 05:18:50 AM UTC 24 |
| Finished | Oct 09 05:19:00 AM UTC 24 |
| Peak memory | 212096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714938412 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3714938412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.678248286 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 8664579 ps |
| CPU time | 1.88 seconds |
| Started | Oct 09 05:18:48 AM UTC 24 |
| Finished | Oct 09 05:18:52 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678248286 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.678248286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/43.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.116121775 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 205685037 ps |
| CPU time | 26.44 seconds |
| Started | Oct 09 05:19:03 AM UTC 24 |
| Finished | Oct 09 05:19:31 AM UTC 24 |
| Peak memory | 214156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116121775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.116121775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/43.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.971903440 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 563740553 ps |
| CPU time | 18.91 seconds |
| Started | Oct 09 05:19:03 AM UTC 24 |
| Finished | Oct 09 05:19:23 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971903440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.971903440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/43.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.2775847272 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 3676516453 ps |
| CPU time | 151.48 seconds |
| Started | Oct 09 05:19:03 AM UTC 24 |
| Finished | Oct 09 05:21:37 AM UTC 24 |
| Peak memory | 216264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775847272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.2775847272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.792319019 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 2194996164 ps |
| CPU time | 55.85 seconds |
| Started | Oct 09 05:19:03 AM UTC 24 |
| Finished | Oct 09 05:20:01 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792319019 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.792319019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.2012657490 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 365829938 ps |
| CPU time | 5.01 seconds |
| Started | Oct 09 05:18:57 AM UTC 24 |
| Finished | Oct 09 05:19:03 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012657490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.2012657490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/43.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.682968904 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 1518222625 ps |
| CPU time | 22.04 seconds |
| Started | Oct 09 05:19:10 AM UTC 24 |
| Finished | Oct 09 05:19:34 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682968904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.682968904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/44.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.1798810389 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 10500965104 ps |
| CPU time | 78.17 seconds |
| Started | Oct 09 05:19:10 AM UTC 24 |
| Finished | Oct 09 05:20:30 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798810389 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.1798810389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2824307368 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 19784579 ps |
| CPU time | 2.71 seconds |
| Started | Oct 09 05:19:11 AM UTC 24 |
| Finished | Oct 09 05:19:15 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824307368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.2824307368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.4160771534 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 3574561758 ps |
| CPU time | 11.82 seconds |
| Started | Oct 09 05:19:11 AM UTC 24 |
| Finished | Oct 09 05:19:24 AM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160771534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.4160771534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/44.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random.3364679163 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 21228368 ps |
| CPU time | 3.51 seconds |
| Started | Oct 09 05:19:03 AM UTC 24 |
| Finished | Oct 09 05:19:08 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364679163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.3364679163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/44.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.2062264454 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 3978511784 ps |
| CPU time | 21.58 seconds |
| Started | Oct 09 05:19:03 AM UTC 24 |
| Finished | Oct 09 05:19:26 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062264454 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2062264454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/44.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.2634606921 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 12719483429 ps |
| CPU time | 94.52 seconds |
| Started | Oct 09 05:19:04 AM UTC 24 |
| Finished | Oct 09 05:20:40 AM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634606921 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.2634606921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/44.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.117902079 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 100672828 ps |
| CPU time | 7.16 seconds |
| Started | Oct 09 05:19:03 AM UTC 24 |
| Finished | Oct 09 05:19:12 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117902079 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.117902079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/44.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.3250810216 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 597010784 ps |
| CPU time | 7.93 seconds |
| Started | Oct 09 05:19:11 AM UTC 24 |
| Finished | Oct 09 05:19:20 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250810216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3250810216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/44.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.1316598618 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 40103608 ps |
| CPU time | 2 seconds |
| Started | Oct 09 05:19:03 AM UTC 24 |
| Finished | Oct 09 05:19:06 AM UTC 24 |
| Peak memory | 211188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316598618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1316598618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/44.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.2299537218 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 1568181984 ps |
| CPU time | 10.11 seconds |
| Started | Oct 09 05:19:03 AM UTC 24 |
| Finished | Oct 09 05:19:15 AM UTC 24 |
| Peak memory | 212368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299537218 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.2299537218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/44.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.3883007153 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 2048671804 ps |
| CPU time | 14.86 seconds |
| Started | Oct 09 05:19:03 AM UTC 24 |
| Finished | Oct 09 05:19:19 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883007153 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.3883007153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.2450099723 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 12673560 ps |
| CPU time | 1.68 seconds |
| Started | Oct 09 05:19:03 AM UTC 24 |
| Finished | Oct 09 05:19:06 AM UTC 24 |
| Peak memory | 211136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450099723 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.2450099723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/44.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.190473032 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 454944747 ps |
| CPU time | 36.18 seconds |
| Started | Oct 09 05:19:11 AM UTC 24 |
| Finished | Oct 09 05:19:48 AM UTC 24 |
| Peak memory | 214152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190473032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.190473032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/44.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3128713241 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 608755211 ps |
| CPU time | 6.47 seconds |
| Started | Oct 09 05:19:11 AM UTC 24 |
| Finished | Oct 09 05:19:18 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128713241 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3128713241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/44.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.2301799460 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 199869847 ps |
| CPU time | 29.65 seconds |
| Started | Oct 09 05:19:11 AM UTC 24 |
| Finished | Oct 09 05:19:42 AM UTC 24 |
| Peak memory | 214160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301799460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.2301799460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2625802747 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 600427297 ps |
| CPU time | 80.09 seconds |
| Started | Oct 09 05:19:11 AM UTC 24 |
| Finished | Oct 09 05:20:33 AM UTC 24 |
| Peak memory | 216204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625802747 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.2625802747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.2698000061 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 570633564 ps |
| CPU time | 7.35 seconds |
| Started | Oct 09 05:19:11 AM UTC 24 |
| Finished | Oct 09 05:19:19 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698000061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2698000061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/44.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.481976806 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 1262163823 ps |
| CPU time | 13.84 seconds |
| Started | Oct 09 05:19:26 AM UTC 24 |
| Finished | Oct 09 05:19:41 AM UTC 24 |
| Peak memory | 212240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481976806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.481976806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/45.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.3666235002 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 30437326903 ps |
| CPU time | 127.77 seconds |
| Started | Oct 09 05:19:26 AM UTC 24 |
| Finished | Oct 09 05:21:36 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666235002 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.3666235002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.3030462200 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 19463080 ps |
| CPU time | 1.68 seconds |
| Started | Oct 09 05:19:26 AM UTC 24 |
| Finished | Oct 09 05:19:29 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030462200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.3030462200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.970091306 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 42020182 ps |
| CPU time | 2.38 seconds |
| Started | Oct 09 05:19:26 AM UTC 24 |
| Finished | Oct 09 05:19:29 AM UTC 24 |
| Peak memory | 212276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970091306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.970091306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/45.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random.2708482214 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 154471642 ps |
| CPU time | 10.5 seconds |
| Started | Oct 09 05:19:18 AM UTC 24 |
| Finished | Oct 09 05:19:30 AM UTC 24 |
| Peak memory | 212220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708482214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.2708482214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/45.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.1289494207 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 5591398633 ps |
| CPU time | 18.66 seconds |
| Started | Oct 09 05:19:18 AM UTC 24 |
| Finished | Oct 09 05:19:38 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289494207 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.1289494207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/45.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3973851368 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 71136206425 ps |
| CPU time | 95.9 seconds |
| Started | Oct 09 05:19:26 AM UTC 24 |
| Finished | Oct 09 05:21:04 AM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973851368 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3973851368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/45.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.133622559 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 41612961 ps |
| CPU time | 5.31 seconds |
| Started | Oct 09 05:19:18 AM UTC 24 |
| Finished | Oct 09 05:19:25 AM UTC 24 |
| Peak memory | 212428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133622559 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.133622559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/45.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.1753275875 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 2236170989 ps |
| CPU time | 10.1 seconds |
| Started | Oct 09 05:19:26 AM UTC 24 |
| Finished | Oct 09 05:19:37 AM UTC 24 |
| Peak memory | 212424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753275875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1753275875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/45.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.3149708793 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 187390946 ps |
| CPU time | 2.47 seconds |
| Started | Oct 09 05:19:11 AM UTC 24 |
| Finished | Oct 09 05:19:15 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149708793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.3149708793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/45.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.3471128881 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 3033223757 ps |
| CPU time | 11.83 seconds |
| Started | Oct 09 05:19:14 AM UTC 24 |
| Finished | Oct 09 05:19:27 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471128881 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.3471128881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/45.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.2025643483 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 1564553245 ps |
| CPU time | 15.46 seconds |
| Started | Oct 09 05:19:18 AM UTC 24 |
| Finished | Oct 09 05:19:35 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025643483 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.2025643483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.3728432123 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 14969227 ps |
| CPU time | 1.78 seconds |
| Started | Oct 09 05:19:14 AM UTC 24 |
| Finished | Oct 09 05:19:17 AM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728432123 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.3728432123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/45.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.731395731 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 520109270 ps |
| CPU time | 31.07 seconds |
| Started | Oct 09 05:19:26 AM UTC 24 |
| Finished | Oct 09 05:19:59 AM UTC 24 |
| Peak memory | 214156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731395731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.731395731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/45.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.1259299273 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 1028579935 ps |
| CPU time | 4.75 seconds |
| Started | Oct 09 05:19:26 AM UTC 24 |
| Finished | Oct 09 05:19:32 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259299273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1259299273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/45.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1739002264 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 235321072 ps |
| CPU time | 17.13 seconds |
| Started | Oct 09 05:19:26 AM UTC 24 |
| Finished | Oct 09 05:19:45 AM UTC 24 |
| Peak memory | 214164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739002264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.1739002264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.1430628694 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 423309420 ps |
| CPU time | 11.93 seconds |
| Started | Oct 09 05:19:26 AM UTC 24 |
| Finished | Oct 09 05:19:39 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430628694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.1430628694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/45.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.1357233535 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 110712725 ps |
| CPU time | 12.74 seconds |
| Started | Oct 09 05:19:34 AM UTC 24 |
| Finished | Oct 09 05:19:48 AM UTC 24 |
| Peak memory | 212436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357233535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.1357233535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/46.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.2076998622 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 44267678582 ps |
| CPU time | 341.13 seconds |
| Started | Oct 09 05:19:34 AM UTC 24 |
| Finished | Oct 09 05:25:20 AM UTC 24 |
| Peak memory | 217900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076998622 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.2076998622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.3526627876 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 400897040 ps |
| CPU time | 8.03 seconds |
| Started | Oct 09 05:19:37 AM UTC 24 |
| Finished | Oct 09 05:19:47 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526627876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.3526627876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.2550490697 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 269893321 ps |
| CPU time | 5.15 seconds |
| Started | Oct 09 05:19:37 AM UTC 24 |
| Finished | Oct 09 05:19:44 AM UTC 24 |
| Peak memory | 212348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550490697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2550490697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/46.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random.3309526506 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 127811171 ps |
| CPU time | 7.8 seconds |
| Started | Oct 09 05:19:34 AM UTC 24 |
| Finished | Oct 09 05:19:43 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309526506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.3309526506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/46.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.1163615478 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 31805037981 ps |
| CPU time | 95.1 seconds |
| Started | Oct 09 05:19:34 AM UTC 24 |
| Finished | Oct 09 05:21:11 AM UTC 24 |
| Peak memory | 212496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163615478 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1163615478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/46.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3636998810 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 9264165180 ps |
| CPU time | 64.84 seconds |
| Started | Oct 09 05:19:34 AM UTC 24 |
| Finished | Oct 09 05:20:41 AM UTC 24 |
| Peak memory | 212140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636998810 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.3636998810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/46.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.4096590768 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 77516256 ps |
| CPU time | 9.43 seconds |
| Started | Oct 09 05:19:34 AM UTC 24 |
| Finished | Oct 09 05:19:44 AM UTC 24 |
| Peak memory | 212024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096590768 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.4096590768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/46.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.712202153 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 19487447 ps |
| CPU time | 3.03 seconds |
| Started | Oct 09 05:19:34 AM UTC 24 |
| Finished | Oct 09 05:19:38 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712202153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.712202153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/46.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.1457786635 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 86014724 ps |
| CPU time | 2.44 seconds |
| Started | Oct 09 05:19:30 AM UTC 24 |
| Finished | Oct 09 05:19:34 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457786635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.1457786635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/46.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.3126900270 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 2024350532 ps |
| CPU time | 12.27 seconds |
| Started | Oct 09 05:19:30 AM UTC 24 |
| Finished | Oct 09 05:19:44 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126900270 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.3126900270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/46.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.4109830970 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 1031359012 ps |
| CPU time | 9.7 seconds |
| Started | Oct 09 05:19:30 AM UTC 24 |
| Finished | Oct 09 05:19:41 AM UTC 24 |
| Peak memory | 212352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109830970 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.4109830970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.2515660433 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 11233810 ps |
| CPU time | 1.49 seconds |
| Started | Oct 09 05:19:30 AM UTC 24 |
| Finished | Oct 09 05:19:33 AM UTC 24 |
| Peak memory | 211136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515660433 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.2515660433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/46.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.3570064235 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 702593583 ps |
| CPU time | 26.42 seconds |
| Started | Oct 09 05:19:37 AM UTC 24 |
| Finished | Oct 09 05:20:05 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570064235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.3570064235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/46.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1281435849 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 2078358554 ps |
| CPU time | 26.12 seconds |
| Started | Oct 09 05:19:42 AM UTC 24 |
| Finished | Oct 09 05:20:09 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281435849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1281435849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/46.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.3014857893 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 608645451 ps |
| CPU time | 83.76 seconds |
| Started | Oct 09 05:19:41 AM UTC 24 |
| Finished | Oct 09 05:21:07 AM UTC 24 |
| Peak memory | 216208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014857893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.3014857893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.4281043975 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 440599714 ps |
| CPU time | 34.02 seconds |
| Started | Oct 09 05:19:42 AM UTC 24 |
| Finished | Oct 09 05:20:17 AM UTC 24 |
| Peak memory | 214160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281043975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.4281043975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.4087650741 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 59834574 ps |
| CPU time | 5.75 seconds |
| Started | Oct 09 05:19:37 AM UTC 24 |
| Finished | Oct 09 05:19:44 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087650741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.4087650741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/46.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.2873972098 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 85381169509 ps |
| CPU time | 333.37 seconds |
| Started | Oct 09 05:19:47 AM UTC 24 |
| Finished | Oct 09 05:25:25 AM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873972098 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.2873972098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.4078452620 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 5423019177 ps |
| CPU time | 16.33 seconds |
| Started | Oct 09 05:19:47 AM UTC 24 |
| Finished | Oct 09 05:20:05 AM UTC 24 |
| Peak memory | 212152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078452620 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.4078452620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.1059709376 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 108244159 ps |
| CPU time | 1.72 seconds |
| Started | Oct 09 05:19:47 AM UTC 24 |
| Finished | Oct 09 05:19:50 AM UTC 24 |
| Peak memory | 211072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059709376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1059709376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/47.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random.1764451012 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 3983792729 ps |
| CPU time | 16.98 seconds |
| Started | Oct 09 05:19:47 AM UTC 24 |
| Finished | Oct 09 05:20:05 AM UTC 24 |
| Peak memory | 212148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764451012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.1764451012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/47.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.4158302434 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 13931534802 ps |
| CPU time | 53.81 seconds |
| Started | Oct 09 05:19:47 AM UTC 24 |
| Finished | Oct 09 05:20:42 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158302434 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.4158302434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/47.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1639758664 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 13816415801 ps |
| CPU time | 112.01 seconds |
| Started | Oct 09 05:19:47 AM UTC 24 |
| Finished | Oct 09 05:21:41 AM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639758664 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1639758664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/47.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.750507341 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 187205591 ps |
| CPU time | 6.09 seconds |
| Started | Oct 09 05:19:47 AM UTC 24 |
| Finished | Oct 09 05:19:54 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750507341 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.750507341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/47.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.826778156 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 49132248 ps |
| CPU time | 3.59 seconds |
| Started | Oct 09 05:19:47 AM UTC 24 |
| Finished | Oct 09 05:19:52 AM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826778156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.826778156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/47.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.2785381389 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 58265111 ps |
| CPU time | 2.33 seconds |
| Started | Oct 09 05:19:42 AM UTC 24 |
| Finished | Oct 09 05:19:45 AM UTC 24 |
| Peak memory | 212084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785381389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.2785381389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/47.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1725585 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 6473842175 ps |
| CPU time | 11.53 seconds |
| Started | Oct 09 05:19:42 AM UTC 24 |
| Finished | Oct 09 05:19:55 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725585 -assert nopostproc +UVM_TESTNAME=xbar_base_t est +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1725585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/47.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2336830533 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 447465932 ps |
| CPU time | 7.12 seconds |
| Started | Oct 09 05:19:47 AM UTC 24 |
| Finished | Oct 09 05:19:55 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336830533 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2336830533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.2196045269 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 10497615 ps |
| CPU time | 1.46 seconds |
| Started | Oct 09 05:19:42 AM UTC 24 |
| Finished | Oct 09 05:19:44 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196045269 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.2196045269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/47.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.676463962 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 14194634480 ps |
| CPU time | 49.22 seconds |
| Started | Oct 09 05:19:47 AM UTC 24 |
| Finished | Oct 09 05:20:38 AM UTC 24 |
| Peak memory | 214480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676463962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.676463962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/47.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3747399419 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 4111446121 ps |
| CPU time | 40.45 seconds |
| Started | Oct 09 05:19:47 AM UTC 24 |
| Finished | Oct 09 05:20:29 AM UTC 24 |
| Peak memory | 212432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747399419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3747399419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/47.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.3606804857 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 10507073150 ps |
| CPU time | 77.47 seconds |
| Started | Oct 09 05:19:47 AM UTC 24 |
| Finished | Oct 09 05:21:07 AM UTC 24 |
| Peak memory | 216404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606804857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.3606804857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.3075710107 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 176224262 ps |
| CPU time | 10 seconds |
| Started | Oct 09 05:19:47 AM UTC 24 |
| Finished | Oct 09 05:19:59 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075710107 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.3075710107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.2106452158 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 895350472 ps |
| CPU time | 5.36 seconds |
| Started | Oct 09 05:19:47 AM UTC 24 |
| Finished | Oct 09 05:19:54 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106452158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2106452158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/47.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.2109147584 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 2231033067 ps |
| CPU time | 21.7 seconds |
| Started | Oct 09 05:19:58 AM UTC 24 |
| Finished | Oct 09 05:20:21 AM UTC 24 |
| Peak memory | 212436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109147584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.2109147584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/48.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.576629195 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 200954430748 ps |
| CPU time | 402.71 seconds |
| Started | Oct 09 05:19:58 AM UTC 24 |
| Finished | Oct 09 05:26:46 AM UTC 24 |
| Peak memory | 218224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576629195 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.576629195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.94591647 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 155443387 ps |
| CPU time | 4.12 seconds |
| Started | Oct 09 05:19:58 AM UTC 24 |
| Finished | Oct 09 05:20:03 AM UTC 24 |
| Peak memory | 212184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94591647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.94591647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.3622070531 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 564552827 ps |
| CPU time | 10.69 seconds |
| Started | Oct 09 05:19:58 AM UTC 24 |
| Finished | Oct 09 05:20:10 AM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622070531 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3622070531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/48.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random.557574623 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 76415660 ps |
| CPU time | 2.27 seconds |
| Started | Oct 09 05:19:51 AM UTC 24 |
| Finished | Oct 09 05:19:55 AM UTC 24 |
| Peak memory | 212216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557574623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.557574623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/48.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.1607749049 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 79859912132 ps |
| CPU time | 95.4 seconds |
| Started | Oct 09 05:19:51 AM UTC 24 |
| Finished | Oct 09 05:21:29 AM UTC 24 |
| Peak memory | 212240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607749049 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1607749049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/48.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.17002786 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 9238986548 ps |
| CPU time | 78.18 seconds |
| Started | Oct 09 05:19:54 AM UTC 24 |
| Finished | Oct 09 05:21:14 AM UTC 24 |
| Peak memory | 212152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17002786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.17002786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/48.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.692982139 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 69068093 ps |
| CPU time | 8.39 seconds |
| Started | Oct 09 05:19:51 AM UTC 24 |
| Finished | Oct 09 05:20:01 AM UTC 24 |
| Peak memory | 212104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692982139 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.692982139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/48.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.179872826 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 209174232 ps |
| CPU time | 8.21 seconds |
| Started | Oct 09 05:19:58 AM UTC 24 |
| Finished | Oct 09 05:20:07 AM UTC 24 |
| Peak memory | 212352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179872826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.179872826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/48.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.1727197823 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 12454897 ps |
| CPU time | 1.55 seconds |
| Started | Oct 09 05:19:51 AM UTC 24 |
| Finished | Oct 09 05:19:54 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727197823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.1727197823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/48.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1158538940 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 2477997177 ps |
| CPU time | 12.81 seconds |
| Started | Oct 09 05:19:51 AM UTC 24 |
| Finished | Oct 09 05:20:05 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158538940 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.1158538940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/48.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.4166266350 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 2144681129 ps |
| CPU time | 7.88 seconds |
| Started | Oct 09 05:19:51 AM UTC 24 |
| Finished | Oct 09 05:20:00 AM UTC 24 |
| Peak memory | 212352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166266350 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.4166266350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.1870071036 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 11939034 ps |
| CPU time | 1.68 seconds |
| Started | Oct 09 05:19:51 AM UTC 24 |
| Finished | Oct 09 05:19:54 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870071036 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.1870071036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/48.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.712139021 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 310188253 ps |
| CPU time | 14.05 seconds |
| Started | Oct 09 05:19:58 AM UTC 24 |
| Finished | Oct 09 05:20:14 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712139021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.712139021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/48.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.2781552938 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 1191063311 ps |
| CPU time | 14.21 seconds |
| Started | Oct 09 05:19:58 AM UTC 24 |
| Finished | Oct 09 05:20:14 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781552938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2781552938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/48.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.1283486242 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 6732298 ps |
| CPU time | 2.29 seconds |
| Started | Oct 09 05:19:58 AM UTC 24 |
| Finished | Oct 09 05:20:02 AM UTC 24 |
| Peak memory | 212044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283486242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.1283486242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.636245304 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 4173701762 ps |
| CPU time | 66.59 seconds |
| Started | Oct 09 05:20:01 AM UTC 24 |
| Finished | Oct 09 05:21:10 AM UTC 24 |
| Peak memory | 214228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636245304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.636245304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.2182276980 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 69878809 ps |
| CPU time | 6.76 seconds |
| Started | Oct 09 05:19:58 AM UTC 24 |
| Finished | Oct 09 05:20:06 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182276980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2182276980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/48.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.1405441304 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 25811434 ps |
| CPU time | 2.8 seconds |
| Started | Oct 09 05:20:06 AM UTC 24 |
| Finished | Oct 09 05:20:10 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405441304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.1405441304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/49.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.1481187354 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 4269745095 ps |
| CPU time | 34.22 seconds |
| Started | Oct 09 05:20:06 AM UTC 24 |
| Finished | Oct 09 05:20:42 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481187354 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.1481187354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.3916509829 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 65795915 ps |
| CPU time | 2.23 seconds |
| Started | Oct 09 05:20:14 AM UTC 24 |
| Finished | Oct 09 05:20:17 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916509829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.3916509829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.4157980404 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 510103289 ps |
| CPU time | 4.85 seconds |
| Started | Oct 09 05:20:13 AM UTC 24 |
| Finished | Oct 09 05:20:19 AM UTC 24 |
| Peak memory | 212216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157980404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.4157980404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/49.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random.1727689879 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 52556495 ps |
| CPU time | 3.32 seconds |
| Started | Oct 09 05:20:06 AM UTC 24 |
| Finished | Oct 09 05:20:10 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727689879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.1727689879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/49.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.3777287973 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 18301160844 ps |
| CPU time | 66.83 seconds |
| Started | Oct 09 05:20:06 AM UTC 24 |
| Finished | Oct 09 05:21:15 AM UTC 24 |
| Peak memory | 212432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777287973 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.3777287973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/49.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.734939915 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 5110848026 ps |
| CPU time | 39.57 seconds |
| Started | Oct 09 05:20:06 AM UTC 24 |
| Finished | Oct 09 05:20:47 AM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734939915 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.734939915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/49.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.3287584403 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 95130396 ps |
| CPU time | 5.42 seconds |
| Started | Oct 09 05:20:06 AM UTC 24 |
| Finished | Oct 09 05:20:12 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287584403 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.3287584403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/49.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.2550592046 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 2976482781 ps |
| CPU time | 6.69 seconds |
| Started | Oct 09 05:20:13 AM UTC 24 |
| Finished | Oct 09 05:20:21 AM UTC 24 |
| Peak memory | 212168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550592046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2550592046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/49.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.1267281102 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 9847012 ps |
| CPU time | 1.44 seconds |
| Started | Oct 09 05:20:01 AM UTC 24 |
| Finished | Oct 09 05:20:04 AM UTC 24 |
| Peak memory | 211084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267281102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1267281102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/49.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3781981923 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 2336767690 ps |
| CPU time | 8.02 seconds |
| Started | Oct 09 05:20:02 AM UTC 24 |
| Finished | Oct 09 05:20:11 AM UTC 24 |
| Peak memory | 212168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781981923 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3781981923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/49.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1856276715 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 1402606503 ps |
| CPU time | 8.25 seconds |
| Started | Oct 09 05:20:06 AM UTC 24 |
| Finished | Oct 09 05:20:15 AM UTC 24 |
| Peak memory | 212352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856276715 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.1856276715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.925538524 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 11394631 ps |
| CPU time | 1.82 seconds |
| Started | Oct 09 05:20:02 AM UTC 24 |
| Finished | Oct 09 05:20:04 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925538524 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.925538524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/49.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.1161686804 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 14560136749 ps |
| CPU time | 88.69 seconds |
| Started | Oct 09 05:20:14 AM UTC 24 |
| Finished | Oct 09 05:21:44 AM UTC 24 |
| Peak memory | 216276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161686804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1161686804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/49.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2476709570 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 109325196 ps |
| CPU time | 9.74 seconds |
| Started | Oct 09 05:20:14 AM UTC 24 |
| Finished | Oct 09 05:20:25 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476709570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2476709570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/49.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.3058522700 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 652733697 ps |
| CPU time | 108.19 seconds |
| Started | Oct 09 05:20:14 AM UTC 24 |
| Finished | Oct 09 05:22:04 AM UTC 24 |
| Peak memory | 218256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058522700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.3058522700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.202094057 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 299611869 ps |
| CPU time | 46.47 seconds |
| Started | Oct 09 05:20:14 AM UTC 24 |
| Finished | Oct 09 05:21:02 AM UTC 24 |
| Peak memory | 214164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202094057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.202094057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.146563026 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 47997567 ps |
| CPU time | 4.29 seconds |
| Started | Oct 09 05:20:13 AM UTC 24 |
| Finished | Oct 09 05:20:19 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146563026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.146563026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/49.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device.4164440360 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 1480288521 ps |
| CPU time | 30.51 seconds |
| Started | Oct 09 05:10:34 AM UTC 24 |
| Finished | Oct 09 05:11:06 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164440360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.4164440360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/5.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.2049007939 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 39046803983 ps |
| CPU time | 326.88 seconds |
| Started | Oct 09 05:10:34 AM UTC 24 |
| Finished | Oct 09 05:16:06 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049007939 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.2049007939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.1180291651 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 100243943 ps |
| CPU time | 10.24 seconds |
| Started | Oct 09 05:10:43 AM UTC 24 |
| Finished | Oct 09 05:10:54 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180291651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1180291651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_error_random.2393136208 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 488610670 ps |
| CPU time | 10.04 seconds |
| Started | Oct 09 05:10:38 AM UTC 24 |
| Finished | Oct 09 05:10:50 AM UTC 24 |
| Peak memory | 212344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393136208 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.2393136208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/5.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random.4207206712 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 274605539 ps |
| CPU time | 3.87 seconds |
| Started | Oct 09 05:10:29 AM UTC 24 |
| Finished | Oct 09 05:10:34 AM UTC 24 |
| Peak memory | 212344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207206712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.4207206712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/5.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_large_delays.1028884208 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 10095802059 ps |
| CPU time | 32.32 seconds |
| Started | Oct 09 05:10:31 AM UTC 24 |
| Finished | Oct 09 05:11:05 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028884208 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1028884208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/5.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_slow_rsp.1248450096 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 16222735312 ps |
| CPU time | 41.87 seconds |
| Started | Oct 09 05:10:31 AM UTC 24 |
| Finished | Oct 09 05:11:15 AM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248450096 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.1248450096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/5.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_zero_delays.3578736731 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 36341017 ps |
| CPU time | 2.38 seconds |
| Started | Oct 09 05:10:30 AM UTC 24 |
| Finished | Oct 09 05:10:34 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578736731 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.3578736731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/5.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_same_source.2696095845 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 662778947 ps |
| CPU time | 6.33 seconds |
| Started | Oct 09 05:10:35 AM UTC 24 |
| Finished | Oct 09 05:10:42 AM UTC 24 |
| Peak memory | 212100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696095845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2696095845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/5.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke.2106126950 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 89531947 ps |
| CPU time | 2.37 seconds |
| Started | Oct 09 05:10:27 AM UTC 24 |
| Finished | Oct 09 05:10:30 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106126950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2106126950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/5.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_large_delays.764668124 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 2223461167 ps |
| CPU time | 18.1 seconds |
| Started | Oct 09 05:10:27 AM UTC 24 |
| Finished | Oct 09 05:10:46 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764668124 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.764668124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/5.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.3817963664 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 2246621811 ps |
| CPU time | 15.73 seconds |
| Started | Oct 09 05:10:28 AM UTC 24 |
| Finished | Oct 09 05:10:45 AM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817963664 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.3817963664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.2360584492 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 21736357 ps |
| CPU time | 1.56 seconds |
| Started | Oct 09 05:10:27 AM UTC 24 |
| Finished | Oct 09 05:10:29 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360584492 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.2360584492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/5.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all.3383261181 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 2647606525 ps |
| CPU time | 40.29 seconds |
| Started | Oct 09 05:10:43 AM UTC 24 |
| Finished | Oct 09 05:11:24 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383261181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3383261181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/5.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_error.2412372496 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 4728241181 ps |
| CPU time | 60.22 seconds |
| Started | Oct 09 05:10:44 AM UTC 24 |
| Finished | Oct 09 05:11:46 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412372496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2412372496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/5.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.423389147 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 259051550 ps |
| CPU time | 34.87 seconds |
| Started | Oct 09 05:10:43 AM UTC 24 |
| Finished | Oct 09 05:11:19 AM UTC 24 |
| Peak memory | 214156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423389147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.423389147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.3442740147 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 7347517 ps |
| CPU time | 3.57 seconds |
| Started | Oct 09 05:10:46 AM UTC 24 |
| Finished | Oct 09 05:10:50 AM UTC 24 |
| Peak memory | 212300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442740147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.3442740147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_unmapped_addr.3506158287 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 396291383 ps |
| CPU time | 3.21 seconds |
| Started | Oct 09 05:10:42 AM UTC 24 |
| Finished | Oct 09 05:10:47 AM UTC 24 |
| Peak memory | 212368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506158287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.3506158287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/5.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device.2029924826 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 685244192 ps |
| CPU time | 17.56 seconds |
| Started | Oct 09 05:10:56 AM UTC 24 |
| Finished | Oct 09 05:11:15 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029924826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2029924826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/6.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.3827921071 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 4322552088 ps |
| CPU time | 24.6 seconds |
| Started | Oct 09 05:10:57 AM UTC 24 |
| Finished | Oct 09 05:11:23 AM UTC 24 |
| Peak memory | 212436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827921071 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.3827921071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.3955999086 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 1057601834 ps |
| CPU time | 6.45 seconds |
| Started | Oct 09 05:11:02 AM UTC 24 |
| Finished | Oct 09 05:11:09 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955999086 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.3955999086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_error_random.2691510020 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 111042431 ps |
| CPU time | 7.61 seconds |
| Started | Oct 09 05:11:00 AM UTC 24 |
| Finished | Oct 09 05:11:09 AM UTC 24 |
| Peak memory | 212084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691510020 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2691510020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/6.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random.849166369 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 774421427 ps |
| CPU time | 19.32 seconds |
| Started | Oct 09 05:10:50 AM UTC 24 |
| Finished | Oct 09 05:11:11 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849166369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.849166369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/6.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_large_delays.3095915469 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 46784966197 ps |
| CPU time | 139.39 seconds |
| Started | Oct 09 05:10:52 AM UTC 24 |
| Finished | Oct 09 05:13:14 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095915469 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.3095915469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/6.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_slow_rsp.3299651481 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 21895680867 ps |
| CPU time | 50.31 seconds |
| Started | Oct 09 05:10:55 AM UTC 24 |
| Finished | Oct 09 05:11:47 AM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299651481 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3299651481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/6.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_zero_delays.3690455429 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 86984070 ps |
| CPU time | 6.03 seconds |
| Started | Oct 09 05:10:52 AM UTC 24 |
| Finished | Oct 09 05:10:59 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690455429 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.3690455429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/6.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_same_source.204691360 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 18773202 ps |
| CPU time | 1.86 seconds |
| Started | Oct 09 05:11:00 AM UTC 24 |
| Finished | Oct 09 05:11:03 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204691360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.204691360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/6.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke.4269812795 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 57643783 ps |
| CPU time | 2.12 seconds |
| Started | Oct 09 05:10:47 AM UTC 24 |
| Finished | Oct 09 05:10:50 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269812795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.4269812795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/6.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_large_delays.2139065062 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1791575580 ps |
| CPU time | 16.88 seconds |
| Started | Oct 09 05:10:47 AM UTC 24 |
| Finished | Oct 09 05:11:05 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139065062 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.2139065062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/6.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.3669114490 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 4449099736 ps |
| CPU time | 18.2 seconds |
| Started | Oct 09 05:10:50 AM UTC 24 |
| Finished | Oct 09 05:11:10 AM UTC 24 |
| Peak memory | 212480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669114490 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3669114490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.2633283934 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 15716003 ps |
| CPU time | 1.57 seconds |
| Started | Oct 09 05:10:47 AM UTC 24 |
| Finished | Oct 09 05:10:50 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633283934 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.2633283934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/6.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all.3410414511 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 1977992811 ps |
| CPU time | 23.47 seconds |
| Started | Oct 09 05:11:04 AM UTC 24 |
| Finished | Oct 09 05:11:28 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410414511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.3410414511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/6.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_error.2768152584 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 168788940 ps |
| CPU time | 15.07 seconds |
| Started | Oct 09 05:11:06 AM UTC 24 |
| Finished | Oct 09 05:11:22 AM UTC 24 |
| Peak memory | 212240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768152584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.2768152584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/6.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.4194454225 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 1933762976 ps |
| CPU time | 107.37 seconds |
| Started | Oct 09 05:11:06 AM UTC 24 |
| Finished | Oct 09 05:12:55 AM UTC 24 |
| Peak memory | 216204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194454225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.4194454225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.4194633684 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 3923497303 ps |
| CPU time | 50.69 seconds |
| Started | Oct 09 05:11:07 AM UTC 24 |
| Finished | Oct 09 05:11:59 AM UTC 24 |
| Peak memory | 214228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194633684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.4194633684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_unmapped_addr.3426730960 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 33660024 ps |
| CPU time | 5.34 seconds |
| Started | Oct 09 05:11:01 AM UTC 24 |
| Finished | Oct 09 05:11:08 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426730960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3426730960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/6.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device.634828753 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1698668391 ps |
| CPU time | 12.58 seconds |
| Started | Oct 09 05:11:11 AM UTC 24 |
| Finished | Oct 09 05:11:25 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634828753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.634828753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/7.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.41687175 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 502810434211 ps |
| CPU time | 438.24 seconds |
| Started | Oct 09 05:11:12 AM UTC 24 |
| Finished | Oct 09 05:18:36 AM UTC 24 |
| Peak memory | 220204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41687175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.41687175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.2283202795 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 713832665 ps |
| CPU time | 8.23 seconds |
| Started | Oct 09 05:11:16 AM UTC 24 |
| Finished | Oct 09 05:11:25 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283202795 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.2283202795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_error_random.4274542869 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 209491211 ps |
| CPU time | 6.37 seconds |
| Started | Oct 09 05:11:12 AM UTC 24 |
| Finished | Oct 09 05:11:20 AM UTC 24 |
| Peak memory | 212344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274542869 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.4274542869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/7.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random.3936028784 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 119313797 ps |
| CPU time | 3.99 seconds |
| Started | Oct 09 05:11:11 AM UTC 24 |
| Finished | Oct 09 05:11:16 AM UTC 24 |
| Peak memory | 212152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936028784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.3936028784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/7.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_large_delays.2411245131 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 55709091172 ps |
| CPU time | 142.81 seconds |
| Started | Oct 09 05:11:11 AM UTC 24 |
| Finished | Oct 09 05:13:36 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411245131 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2411245131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/7.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_slow_rsp.3213777377 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 10099874900 ps |
| CPU time | 62.11 seconds |
| Started | Oct 09 05:11:11 AM UTC 24 |
| Finished | Oct 09 05:12:15 AM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213777377 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.3213777377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/7.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_zero_delays.398043786 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 31462694 ps |
| CPU time | 5.03 seconds |
| Started | Oct 09 05:11:11 AM UTC 24 |
| Finished | Oct 09 05:11:17 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398043786 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.398043786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/7.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_same_source.1668056632 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 118448134 ps |
| CPU time | 4.94 seconds |
| Started | Oct 09 05:11:12 AM UTC 24 |
| Finished | Oct 09 05:11:18 AM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668056632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.1668056632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/7.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke.1358576555 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 13985443 ps |
| CPU time | 1.64 seconds |
| Started | Oct 09 05:11:09 AM UTC 24 |
| Finished | Oct 09 05:11:11 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358576555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.1358576555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/7.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_large_delays.3662581535 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 4175498824 ps |
| CPU time | 7.34 seconds |
| Started | Oct 09 05:11:09 AM UTC 24 |
| Finished | Oct 09 05:11:17 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662581535 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3662581535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/7.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.4284064999 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 814766258 ps |
| CPU time | 8.79 seconds |
| Started | Oct 09 05:11:11 AM UTC 24 |
| Finished | Oct 09 05:11:20 AM UTC 24 |
| Peak memory | 212352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284064999 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.4284064999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.141956320 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 7962607 ps |
| CPU time | 1.7 seconds |
| Started | Oct 09 05:11:09 AM UTC 24 |
| Finished | Oct 09 05:11:11 AM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141956320 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.141956320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/7.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_error.2514717709 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 534540203 ps |
| CPU time | 38.06 seconds |
| Started | Oct 09 05:11:18 AM UTC 24 |
| Finished | Oct 09 05:11:57 AM UTC 24 |
| Peak memory | 211720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514717709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2514717709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/7.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.2505968849 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 2826773824 ps |
| CPU time | 102.46 seconds |
| Started | Oct 09 05:11:17 AM UTC 24 |
| Finished | Oct 09 05:13:01 AM UTC 24 |
| Peak memory | 216272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505968849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.2505968849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.2121995647 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 102812284 ps |
| CPU time | 9.13 seconds |
| Started | Oct 09 05:11:18 AM UTC 24 |
| Finished | Oct 09 05:11:28 AM UTC 24 |
| Peak memory | 211680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121995647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.2121995647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_unmapped_addr.2069616081 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 571297568 ps |
| CPU time | 15 seconds |
| Started | Oct 09 05:11:15 AM UTC 24 |
| Finished | Oct 09 05:11:32 AM UTC 24 |
| Peak memory | 212368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069616081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2069616081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/7.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device.4096884227 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 334159743 ps |
| CPU time | 8.5 seconds |
| Started | Oct 09 05:11:25 AM UTC 24 |
| Finished | Oct 09 05:11:35 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096884227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.4096884227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/8.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.1213094700 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 5282835989 ps |
| CPU time | 35.51 seconds |
| Started | Oct 09 05:11:25 AM UTC 24 |
| Finished | Oct 09 05:12:02 AM UTC 24 |
| Peak memory | 212180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213094700 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.1213094700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.441154932 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 326698034 ps |
| CPU time | 4.03 seconds |
| Started | Oct 09 05:11:27 AM UTC 24 |
| Finished | Oct 09 05:11:32 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441154932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.441154932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_error_random.3195391232 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 24830720 ps |
| CPU time | 3.93 seconds |
| Started | Oct 09 05:11:26 AM UTC 24 |
| Finished | Oct 09 05:11:31 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195391232 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.3195391232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/8.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random.68830386 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 44849032 ps |
| CPU time | 5.31 seconds |
| Started | Oct 09 05:11:22 AM UTC 24 |
| Finished | Oct 09 05:11:29 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68830386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.68830386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/8.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_large_delays.1876387753 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 19798170387 ps |
| CPU time | 51.12 seconds |
| Started | Oct 09 05:11:24 AM UTC 24 |
| Finished | Oct 09 05:12:16 AM UTC 24 |
| Peak memory | 212492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876387753 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1876387753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/8.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_slow_rsp.1375062042 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 73681795576 ps |
| CPU time | 194.12 seconds |
| Started | Oct 09 05:11:24 AM UTC 24 |
| Finished | Oct 09 05:14:41 AM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375062042 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1375062042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/8.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_zero_delays.1407013636 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 21668289 ps |
| CPU time | 1.94 seconds |
| Started | Oct 09 05:11:24 AM UTC 24 |
| Finished | Oct 09 05:11:27 AM UTC 24 |
| Peak memory | 211080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407013636 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.1407013636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/8.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_same_source.2451842544 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 2965663304 ps |
| CPU time | 14.46 seconds |
| Started | Oct 09 05:11:26 AM UTC 24 |
| Finished | Oct 09 05:11:41 AM UTC 24 |
| Peak memory | 212496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451842544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2451842544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/8.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke.1751212334 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 65103673 ps |
| CPU time | 2.94 seconds |
| Started | Oct 09 05:11:19 AM UTC 24 |
| Finished | Oct 09 05:11:23 AM UTC 24 |
| Peak memory | 212108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751212334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1751212334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/8.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_large_delays.898703017 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 3488526083 ps |
| CPU time | 18.43 seconds |
| Started | Oct 09 05:11:20 AM UTC 24 |
| Finished | Oct 09 05:11:40 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898703017 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.898703017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/8.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.4142447308 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 1280302998 ps |
| CPU time | 10.72 seconds |
| Started | Oct 09 05:11:21 AM UTC 24 |
| Finished | Oct 09 05:11:33 AM UTC 24 |
| Peak memory | 212352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142447308 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.4142447308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.2337433884 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 8260126 ps |
| CPU time | 1.35 seconds |
| Started | Oct 09 05:11:20 AM UTC 24 |
| Finished | Oct 09 05:11:23 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337433884 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.2337433884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/8.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all.2728450412 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 5317501253 ps |
| CPU time | 54.24 seconds |
| Started | Oct 09 05:11:28 AM UTC 24 |
| Finished | Oct 09 05:12:24 AM UTC 24 |
| Peak memory | 214480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728450412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.2728450412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/8.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_error.928118333 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 9878864893 ps |
| CPU time | 118.54 seconds |
| Started | Oct 09 05:11:29 AM UTC 24 |
| Finished | Oct 09 05:13:31 AM UTC 24 |
| Peak memory | 212176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928118333 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.928118333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/8.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.2714585546 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 384654128 ps |
| CPU time | 45.77 seconds |
| Started | Oct 09 05:11:29 AM UTC 24 |
| Finished | Oct 09 05:12:17 AM UTC 24 |
| Peak memory | 216212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714585546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.2714585546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.1473608496 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 179391001 ps |
| CPU time | 24.37 seconds |
| Started | Oct 09 05:11:30 AM UTC 24 |
| Finished | Oct 09 05:11:56 AM UTC 24 |
| Peak memory | 214160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473608496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.1473608496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_unmapped_addr.666630506 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 27644564 ps |
| CPU time | 2.61 seconds |
| Started | Oct 09 05:11:26 AM UTC 24 |
| Finished | Oct 09 05:11:29 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666630506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.666630506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/8.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device.2337063365 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 1927649879 ps |
| CPU time | 27.59 seconds |
| Started | Oct 09 05:11:36 AM UTC 24 |
| Finished | Oct 09 05:12:05 AM UTC 24 |
| Peak memory | 212368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337063365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.2337063365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/9.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.342239054 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 16806097359 ps |
| CPU time | 146.09 seconds |
| Started | Oct 09 05:11:36 AM UTC 24 |
| Finished | Oct 09 05:14:05 AM UTC 24 |
| Peak memory | 212432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342239054 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.342239054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1212103429 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 710080596 ps |
| CPU time | 11.44 seconds |
| Started | Oct 09 05:11:38 AM UTC 24 |
| Finished | Oct 09 05:11:51 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212103429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.1212103429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_error_random.3516128237 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 59990885 ps |
| CPU time | 7.14 seconds |
| Started | Oct 09 05:11:38 AM UTC 24 |
| Finished | Oct 09 05:11:47 AM UTC 24 |
| Peak memory | 212084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516128237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.3516128237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/9.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random.1101117837 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1840734721 ps |
| CPU time | 20.47 seconds |
| Started | Oct 09 05:11:32 AM UTC 24 |
| Finished | Oct 09 05:11:54 AM UTC 24 |
| Peak memory | 212084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101117837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.1101117837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/9.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_large_delays.1514390095 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 15669116277 ps |
| CPU time | 50.17 seconds |
| Started | Oct 09 05:11:35 AM UTC 24 |
| Finished | Oct 09 05:12:27 AM UTC 24 |
| Peak memory | 212428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514390095 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1514390095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/9.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_slow_rsp.3840310234 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 3764095875 ps |
| CPU time | 10.6 seconds |
| Started | Oct 09 05:11:35 AM UTC 24 |
| Finished | Oct 09 05:11:47 AM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840310234 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.3840310234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/9.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_zero_delays.1434469138 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 54310393 ps |
| CPU time | 8.53 seconds |
| Started | Oct 09 05:11:33 AM UTC 24 |
| Finished | Oct 09 05:11:44 AM UTC 24 |
| Peak memory | 212236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434469138 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.1434469138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/9.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_same_source.2932777887 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 898282965 ps |
| CPU time | 8.2 seconds |
| Started | Oct 09 05:11:38 AM UTC 24 |
| Finished | Oct 09 05:11:48 AM UTC 24 |
| Peak memory | 212232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932777887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.2932777887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/9.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke.3696821301 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 13065115 ps |
| CPU time | 1.88 seconds |
| Started | Oct 09 05:11:30 AM UTC 24 |
| Finished | Oct 09 05:11:33 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696821301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3696821301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/9.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_large_delays.1675266482 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 3743201761 ps |
| CPU time | 16.92 seconds |
| Started | Oct 09 05:11:32 AM UTC 24 |
| Finished | Oct 09 05:11:50 AM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675266482 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.1675266482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/9.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.505782307 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 706387366 ps |
| CPU time | 5.21 seconds |
| Started | Oct 09 05:11:32 AM UTC 24 |
| Finished | Oct 09 05:11:39 AM UTC 24 |
| Peak memory | 212368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505782307 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.505782307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.2131342866 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 12455902 ps |
| CPU time | 1.86 seconds |
| Started | Oct 09 05:11:32 AM UTC 24 |
| Finished | Oct 09 05:11:35 AM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131342866 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.2131342866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/9.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all.4285567941 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 330612978 ps |
| CPU time | 5.38 seconds |
| Started | Oct 09 05:11:39 AM UTC 24 |
| Finished | Oct 09 05:11:46 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285567941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.4285567941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/9.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_error.702346241 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 625938283 ps |
| CPU time | 27.92 seconds |
| Started | Oct 09 05:11:42 AM UTC 24 |
| Finished | Oct 09 05:12:11 AM UTC 24 |
| Peak memory | 212368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702346241 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.702346241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/9.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.1126033633 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 463607608 ps |
| CPU time | 54.54 seconds |
| Started | Oct 09 05:11:41 AM UTC 24 |
| Finished | Oct 09 05:12:37 AM UTC 24 |
| Peak memory | 214420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126033633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.1126033633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.1969801203 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 239541392 ps |
| CPU time | 42.01 seconds |
| Started | Oct 09 05:11:43 AM UTC 24 |
| Finished | Oct 09 05:12:26 AM UTC 24 |
| Peak memory | 214164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969801203 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.1969801203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_unmapped_addr.3413852376 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 4030776428 ps |
| CPU time | 11.88 seconds |
| Started | Oct 09 05:11:38 AM UTC 24 |
| Finished | Oct 09 05:11:51 AM UTC 24 |
| Peak memory | 212432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413852376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3413852376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/9.xbar_unmapped_addr/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |