Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	472	1			T220	1		T35	1		T131	1
all_values[1]	475	1			T17	1		T35	1		T45	1
all_values[2]	493	1			T45	1		T57	1		T231	1
all_values[3]	449	1			T27	2		T220	1		T63	2
all_values[4]	504	1			T27	2		T220	1		T35	3
all_values[5]	449	1			T45	1		T131	1		T53	1
all_values[6]	470	1			T17	1		T220	1		T35	1
all_values[7]	459	1			T45	2		T132	1		T53	1
all_values[8]	495	1			T220	1		T35	2		T53	2
all_values[9]	512	1			T27	1		T45	2		T132	3
all_values[10]	493	1			T17	1		T45	1		T131	1
all_values[11]	500	1			T35	2		T45	1		T132	3
all_values[12]	505	1			T27	1		T35	1		T45	2
all_values[13]	501	1			T17	1		T220	1		T35	1
all_values[14]	497	1			T220	1		T45	1		T63	4
all_values[15]	510	1			T17	1		T220	1		T131	1
all_values[16]	456	1			T220	1		T35	3		T131	1
all_values[17]	504	1			T220	3		T35	1		T45	4
all_values[18]	480	1			T220	1		T45	1		T131	1
all_values[19]	482	1			T45	1		T131	1		T132	3
all_values[20]	475	1			T27	1		T220	2		T45	2
all_values[21]	511	1			T17	1		T220	2		T63	1
all_values[22]	483	1			T27	1		T35	2		T132	1
all_values[23]	476	1			T220	1		T63	2		T55	2
all_values[24]	480	1			T17	1		T220	1		T35	1
all_values[25]	479	1			T220	4		T45	1		T53	1
all_values[26]	456	1			T220	1		T45	1		T132	1