| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.24 | 100.00 | 95.80 | 100.00 | 100.00 | 100.00 | 99.64 |
| T774 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.785110625 | Oct 12 03:02:55 PM UTC 24 | Oct 12 03:03:59 PM UTC 24 | 595676850 ps | ||
| T775 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.3391490965 | Oct 12 03:03:48 PM UTC 24 | Oct 12 03:03:59 PM UTC 24 | 61276792 ps | ||
| T259 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.1813046659 | Oct 12 03:03:32 PM UTC 24 | Oct 12 03:04:00 PM UTC 24 | 3064809006 ps | ||
| T776 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.28299287 | Oct 12 03:03:46 PM UTC 24 | Oct 12 03:04:02 PM UTC 24 | 1532766695 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.2857335280 | Oct 12 03:02:33 PM UTC 24 | Oct 12 03:04:02 PM UTC 24 | 20233992885 ps | ||
| T777 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.959243667 | Oct 12 03:03:58 PM UTC 24 | Oct 12 03:04:03 PM UTC 24 | 142517987 ps | ||
| T778 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.3819638472 | Oct 12 03:03:54 PM UTC 24 | Oct 12 03:04:03 PM UTC 24 | 1031992833 ps | ||
| T779 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1936125313 | Oct 12 03:04:02 PM UTC 24 | Oct 12 03:04:04 PM UTC 24 | 5962891 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.1207695243 | Oct 12 03:02:59 PM UTC 24 | Oct 12 03:04:05 PM UTC 24 | 21730113823 ps | ||
| T780 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.280961969 | Oct 12 03:00:51 PM UTC 24 | Oct 12 03:04:05 PM UTC 24 | 1524291316 ps | ||
| T781 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1401170308 | Oct 12 03:02:59 PM UTC 24 | Oct 12 03:04:06 PM UTC 24 | 23485379949 ps | ||
| T782 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.2961499557 | Oct 12 03:03:59 PM UTC 24 | Oct 12 03:04:06 PM UTC 24 | 63746259 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.1629111799 | Oct 12 03:03:54 PM UTC 24 | Oct 12 03:04:07 PM UTC 24 | 2607966391 ps | ||
| T783 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.1410575398 | Oct 12 03:04:06 PM UTC 24 | Oct 12 03:04:08 PM UTC 24 | 13915552 ps | ||
| T784 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3078229252 | Oct 12 03:03:50 PM UTC 24 | Oct 12 03:04:09 PM UTC 24 | 3281762265 ps | ||
| T785 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.1155000384 | Oct 12 03:03:17 PM UTC 24 | Oct 12 03:04:09 PM UTC 24 | 10100654749 ps | ||
| T786 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.4073053082 | Oct 12 03:04:06 PM UTC 24 | Oct 12 03:04:09 PM UTC 24 | 10164120 ps | ||
| T787 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.2558536303 | Oct 12 03:03:54 PM UTC 24 | Oct 12 03:04:11 PM UTC 24 | 1421103437 ps | ||
| T788 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.1087538761 | Oct 12 03:03:39 PM UTC 24 | Oct 12 03:04:14 PM UTC 24 | 1250582726 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.3480638899 | Oct 12 03:04:06 PM UTC 24 | Oct 12 03:04:14 PM UTC 24 | 2863437085 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.4127137343 | Oct 12 03:03:11 PM UTC 24 | Oct 12 03:04:14 PM UTC 24 | 315864474 ps | ||
| T789 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.2638370702 | Oct 12 03:03:30 PM UTC 24 | Oct 12 03:04:14 PM UTC 24 | 12652853567 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.3195913097 | Oct 12 03:01:15 PM UTC 24 | Oct 12 03:04:15 PM UTC 24 | 41705607867 ps | ||
| T790 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.204912796 | Oct 12 03:03:50 PM UTC 24 | Oct 12 03:04:16 PM UTC 24 | 5182476391 ps | ||
| T791 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.904782095 | Oct 12 03:04:06 PM UTC 24 | Oct 12 03:04:16 PM UTC 24 | 3220061872 ps | ||
| T792 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.1750525154 | Oct 12 03:04:11 PM UTC 24 | Oct 12 03:04:17 PM UTC 24 | 175690121 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.3652247938 | Oct 12 03:03:32 PM UTC 24 | Oct 12 03:04:17 PM UTC 24 | 13105409481 ps | ||
| T793 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.490941119 | Oct 12 03:04:11 PM UTC 24 | Oct 12 03:04:18 PM UTC 24 | 37593070 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.1387397078 | Oct 12 03:04:11 PM UTC 24 | Oct 12 03:04:18 PM UTC 24 | 121122552 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.1436074251 | Oct 12 03:04:14 PM UTC 24 | Oct 12 03:04:20 PM UTC 24 | 84581882 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random.2552174881 | Oct 12 03:04:06 PM UTC 24 | Oct 12 03:04:22 PM UTC 24 | 851434372 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.3301645574 | Oct 12 03:04:20 PM UTC 24 | Oct 12 03:04:23 PM UTC 24 | 10834673 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.3266774541 | Oct 12 03:04:20 PM UTC 24 | Oct 12 03:04:23 PM UTC 24 | 15641758 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.715898832 | Oct 12 03:04:20 PM UTC 24 | Oct 12 03:04:23 PM UTC 24 | 70825113 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.3121982534 | Oct 12 03:04:11 PM UTC 24 | Oct 12 03:04:24 PM UTC 24 | 548888702 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.1040015999 | Oct 12 03:04:14 PM UTC 24 | Oct 12 03:04:24 PM UTC 24 | 1242872072 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.733933663 | Oct 12 03:02:43 PM UTC 24 | Oct 12 03:04:25 PM UTC 24 | 6003869719 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.2818464632 | Oct 12 03:04:11 PM UTC 24 | Oct 12 03:04:29 PM UTC 24 | 4797316875 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.1358061816 | Oct 12 03:04:11 PM UTC 24 | Oct 12 03:04:30 PM UTC 24 | 6232625070 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.635564417 | Oct 12 03:03:23 PM UTC 24 | Oct 12 03:04:30 PM UTC 24 | 5545275827 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random.3860686373 | Oct 12 03:04:20 PM UTC 24 | Oct 12 03:04:31 PM UTC 24 | 95008318 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.2296041390 | Oct 12 03:04:20 PM UTC 24 | Oct 12 03:04:32 PM UTC 24 | 2503137849 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.615235575 | Oct 12 03:04:26 PM UTC 24 | Oct 12 03:04:32 PM UTC 24 | 39471241 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.3201367170 | Oct 12 03:04:29 PM UTC 24 | Oct 12 03:04:35 PM UTC 24 | 605340333 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.2142465354 | Oct 12 03:04:26 PM UTC 24 | Oct 12 03:04:35 PM UTC 24 | 70762793 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.1709932072 | Oct 12 03:04:34 PM UTC 24 | Oct 12 03:04:36 PM UTC 24 | 15146181 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.902289535 | Oct 12 03:02:25 PM UTC 24 | Oct 12 03:04:36 PM UTC 24 | 4605221543 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.469809435 | Oct 12 03:04:34 PM UTC 24 | Oct 12 03:04:36 PM UTC 24 | 9165002 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.1151039802 | Oct 12 03:04:26 PM UTC 24 | Oct 12 03:04:37 PM UTC 24 | 1695717542 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.3571408195 | Oct 12 03:04:20 PM UTC 24 | Oct 12 03:04:37 PM UTC 24 | 11134269113 ps | ||
| T230 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.800835605 | Oct 12 03:03:19 PM UTC 24 | Oct 12 03:04:40 PM UTC 24 | 37897075385 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.687237894 | Oct 12 03:04:23 PM UTC 24 | Oct 12 03:04:40 PM UTC 24 | 54056693 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1105517239 | Oct 12 03:02:07 PM UTC 24 | Oct 12 03:04:40 PM UTC 24 | 3416669111 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.4041847326 | Oct 12 03:03:42 PM UTC 24 | Oct 12 03:04:42 PM UTC 24 | 23011393155 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.3703890663 | Oct 12 03:04:34 PM UTC 24 | Oct 12 03:04:42 PM UTC 24 | 6584040946 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.3266233836 | Oct 12 03:04:38 PM UTC 24 | Oct 12 03:04:45 PM UTC 24 | 40823263 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random.3252078084 | Oct 12 03:04:38 PM UTC 24 | Oct 12 03:04:47 PM UTC 24 | 419164215 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.155752048 | Oct 12 03:04:41 PM UTC 24 | Oct 12 03:04:47 PM UTC 24 | 914174887 ps | ||
| T252 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.2500666714 | Oct 12 03:01:31 PM UTC 24 | Oct 12 03:04:49 PM UTC 24 | 51704393964 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.211095490 | Oct 12 03:04:42 PM UTC 24 | Oct 12 03:04:50 PM UTC 24 | 370848902 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.2942753186 | Oct 12 03:04:42 PM UTC 24 | Oct 12 03:04:50 PM UTC 24 | 103068899 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.3405134627 | Oct 12 03:04:45 PM UTC 24 | Oct 12 03:04:51 PM UTC 24 | 242683769 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.331492819 | Oct 12 03:04:29 PM UTC 24 | Oct 12 03:04:51 PM UTC 24 | 235985072 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.2652353438 | Oct 12 03:04:49 PM UTC 24 | Oct 12 03:04:52 PM UTC 24 | 13290853 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.1146359696 | Oct 12 03:04:45 PM UTC 24 | Oct 12 03:04:53 PM UTC 24 | 692173216 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.538492793 | Oct 12 03:03:08 PM UTC 24 | Oct 12 03:04:53 PM UTC 24 | 1070807855 ps | ||
| T201 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.3277310321 | Oct 12 03:03:17 PM UTC 24 | Oct 12 03:04:55 PM UTC 24 | 19348683400 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1065345703 | Oct 12 03:04:53 PM UTC 24 | Oct 12 03:04:56 PM UTC 24 | 15863742 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.4000583784 | Oct 12 03:04:14 PM UTC 24 | Oct 12 03:04:59 PM UTC 24 | 2139866992 ps | ||
| T832 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.3704011541 | Oct 12 03:04:35 PM UTC 24 | Oct 12 03:05:00 PM UTC 24 | 2590618991 ps | ||
| T833 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.2065967308 | Oct 12 03:04:11 PM UTC 24 | Oct 12 03:05:00 PM UTC 24 | 5800076513 ps | ||
| T834 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.2563146201 | Oct 12 03:04:53 PM UTC 24 | Oct 12 03:05:02 PM UTC 24 | 51458492 ps | ||
| T835 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.2641084006 | Oct 12 03:04:58 PM UTC 24 | Oct 12 03:05:02 PM UTC 24 | 34834320 ps | ||
| T836 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.4139527750 | Oct 12 03:04:56 PM UTC 24 | Oct 12 03:05:03 PM UTC 24 | 54869380 ps | ||
| T837 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random.2926974453 | Oct 12 03:04:53 PM UTC 24 | Oct 12 03:05:04 PM UTC 24 | 921873959 ps | ||
| T838 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.4141784720 | Oct 12 03:04:23 PM UTC 24 | Oct 12 03:05:04 PM UTC 24 | 8938335670 ps | ||
| T839 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.1447257146 | Oct 12 03:05:01 PM UTC 24 | Oct 12 03:05:05 PM UTC 24 | 88268305 ps | ||
| T840 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3671972888 | Oct 12 03:04:53 PM UTC 24 | Oct 12 03:05:06 PM UTC 24 | 1105089525 ps | ||
| T841 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2352734540 | Oct 12 03:04:53 PM UTC 24 | Oct 12 03:05:07 PM UTC 24 | 6595100249 ps | ||
| T842 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2433204705 | Oct 12 03:05:08 PM UTC 24 | Oct 12 03:05:10 PM UTC 24 | 9018779 ps | ||
| T843 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.2950471216 | Oct 12 03:05:01 PM UTC 24 | Oct 12 03:05:11 PM UTC 24 | 1195194742 ps | ||
| T844 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.1020988730 | Oct 12 03:05:08 PM UTC 24 | Oct 12 03:05:11 PM UTC 24 | 80484357 ps | ||
| T845 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1043588498 | Oct 12 03:04:56 PM UTC 24 | Oct 12 03:05:12 PM UTC 24 | 2246256144 ps | ||
| T846 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.1455206983 | Oct 12 03:05:05 PM UTC 24 | Oct 12 03:05:13 PM UTC 24 | 1359186542 ps | ||
| T847 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.458172597 | Oct 12 03:03:54 PM UTC 24 | Oct 12 03:05:15 PM UTC 24 | 13304910944 ps | ||
| T848 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.3967174339 | Oct 12 03:05:10 PM UTC 24 | Oct 12 03:05:17 PM UTC 24 | 1022438275 ps | ||
| T849 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random.513248645 | Oct 12 03:05:13 PM UTC 24 | Oct 12 03:05:17 PM UTC 24 | 27061681 ps | ||
| T850 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.618926358 | Oct 12 03:05:13 PM UTC 24 | Oct 12 03:05:18 PM UTC 24 | 30451735 ps | ||
| T851 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2839781790 | Oct 12 03:05:05 PM UTC 24 | Oct 12 03:05:21 PM UTC 24 | 685750994 ps | ||
| T852 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1034366893 | Oct 12 03:04:41 PM UTC 24 | Oct 12 03:05:23 PM UTC 24 | 6802235898 ps | ||
| T853 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.3174721000 | Oct 12 03:04:23 PM UTC 24 | Oct 12 03:05:23 PM UTC 24 | 37726427604 ps | ||
| T854 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.2635755123 | Oct 12 03:05:16 PM UTC 24 | Oct 12 03:05:24 PM UTC 24 | 121358350 ps | ||
| T855 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.2782914272 | Oct 12 03:05:19 PM UTC 24 | Oct 12 03:05:24 PM UTC 24 | 717777190 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.4224262804 | Oct 12 03:03:39 PM UTC 24 | Oct 12 03:05:25 PM UTC 24 | 8648208533 ps | ||
| T856 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.4079673587 | Oct 12 03:04:02 PM UTC 24 | Oct 12 03:05:27 PM UTC 24 | 3806081857 ps | ||
| T857 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2176840505 | Oct 12 03:04:20 PM UTC 24 | Oct 12 03:05:29 PM UTC 24 | 5132356613 ps | ||
| T858 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.498357480 | Oct 12 03:05:28 PM UTC 24 | Oct 12 03:05:30 PM UTC 24 | 14091866 ps | ||
| T859 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.3436194945 | Oct 12 03:04:47 PM UTC 24 | Oct 12 03:05:31 PM UTC 24 | 487420840 ps | ||
| T860 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.2073027959 | Oct 12 03:04:38 PM UTC 24 | Oct 12 03:05:32 PM UTC 24 | 10920091891 ps | ||
| T861 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.4245486193 | Oct 12 03:05:30 PM UTC 24 | Oct 12 03:05:32 PM UTC 24 | 9578206 ps | ||
| T862 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.190990325 | Oct 12 03:03:42 PM UTC 24 | Oct 12 03:05:32 PM UTC 24 | 4948702498 ps | ||
| T863 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1530637483 | Oct 12 03:05:10 PM UTC 24 | Oct 12 03:05:34 PM UTC 24 | 3157114251 ps | ||
| T864 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.658185360 | Oct 12 03:05:19 PM UTC 24 | Oct 12 03:05:34 PM UTC 24 | 802102000 ps | ||
| T865 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.3966880185 | Oct 12 03:05:21 PM UTC 24 | Oct 12 03:05:37 PM UTC 24 | 3033628025 ps | ||
| T257 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.343543460 | Oct 12 03:02:59 PM UTC 24 | Oct 12 03:05:37 PM UTC 24 | 17488558126 ps | ||
| T866 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.481466910 | Oct 12 03:05:22 PM UTC 24 | Oct 12 03:05:38 PM UTC 24 | 689474760 ps | ||
| T867 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.3676182418 | Oct 12 03:05:35 PM UTC 24 | Oct 12 03:05:43 PM UTC 24 | 88114138 ps | ||
| T868 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random.3108733641 | Oct 12 03:05:35 PM UTC 24 | Oct 12 03:05:44 PM UTC 24 | 392416526 ps | ||
| T869 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.3037818299 | Oct 12 03:05:41 PM UTC 24 | Oct 12 03:05:45 PM UTC 24 | 97462127 ps | ||
| T870 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.2666162115 | Oct 12 03:05:31 PM UTC 24 | Oct 12 03:05:45 PM UTC 24 | 2744744654 ps | ||
| T871 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.648362499 | Oct 12 03:04:45 PM UTC 24 | Oct 12 03:05:47 PM UTC 24 | 557429205 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.1230827557 | Oct 12 03:05:30 PM UTC 24 | Oct 12 03:05:47 PM UTC 24 | 2136932807 ps | ||
| T872 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.4069303278 | Oct 12 03:05:38 PM UTC 24 | Oct 12 03:05:47 PM UTC 24 | 411761629 ps | ||
| T873 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.3550760544 | Oct 12 03:05:38 PM UTC 24 | Oct 12 03:05:49 PM UTC 24 | 180484305 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1236896050 | Oct 12 03:03:23 PM UTC 24 | Oct 12 03:05:50 PM UTC 24 | 4561478655 ps | ||
| T874 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.2584858130 | Oct 12 03:04:20 PM UTC 24 | Oct 12 03:05:51 PM UTC 24 | 1075137555 ps | ||
| T875 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.3264512566 | Oct 12 03:05:26 PM UTC 24 | Oct 12 03:05:52 PM UTC 24 | 349424094 ps | ||
| T876 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2875220431 | Oct 12 03:05:45 PM UTC 24 | Oct 12 03:05:52 PM UTC 24 | 503734879 ps | ||
| T877 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.3558966413 | Oct 12 03:05:41 PM UTC 24 | Oct 12 03:05:53 PM UTC 24 | 4517742230 ps | ||
| T878 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.2057141312 | Oct 12 03:05:26 PM UTC 24 | Oct 12 03:05:53 PM UTC 24 | 981005539 ps | ||
| T879 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.1117688780 | Oct 12 03:04:38 PM UTC 24 | Oct 12 03:05:54 PM UTC 24 | 65151421450 ps | ||
| T880 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.838252245 | Oct 12 03:05:26 PM UTC 24 | Oct 12 03:06:03 PM UTC 24 | 6518639872 ps | ||
| T881 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3278928986 | Oct 12 03:05:16 PM UTC 24 | Oct 12 03:06:04 PM UTC 24 | 14285642261 ps | ||
| T882 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.648155901 | Oct 12 03:04:02 PM UTC 24 | Oct 12 03:06:09 PM UTC 24 | 5638016375 ps | ||
| T225 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3149861729 | Oct 12 03:02:47 PM UTC 24 | Oct 12 03:06:12 PM UTC 24 | 41275838555 ps | ||
| T883 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.811493224 | Oct 12 03:04:31 PM UTC 24 | Oct 12 03:06:12 PM UTC 24 | 7183486787 ps | ||
| T884 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.3485374492 | Oct 12 03:04:29 PM UTC 24 | Oct 12 03:06:16 PM UTC 24 | 15156744710 ps | ||
| T885 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.4056950138 | Oct 12 03:05:51 PM UTC 24 | Oct 12 03:06:17 PM UTC 24 | 190014929 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.37288824 | Oct 12 03:05:05 PM UTC 24 | Oct 12 03:06:23 PM UTC 24 | 6793180483 ps | ||
| T886 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2871853325 | Oct 12 03:05:05 PM UTC 24 | Oct 12 03:06:25 PM UTC 24 | 449696387 ps | ||
| T887 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.606188190 | Oct 12 03:04:31 PM UTC 24 | Oct 12 03:06:25 PM UTC 24 | 1117900132 ps | ||
| T888 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.2025483706 | Oct 12 03:04:56 PM UTC 24 | Oct 12 03:06:25 PM UTC 24 | 26081254059 ps | ||
| T889 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.1507446436 | Oct 12 03:05:13 PM UTC 24 | Oct 12 03:06:25 PM UTC 24 | 24847679646 ps | ||
| T890 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.1999302634 | Oct 12 03:05:38 PM UTC 24 | Oct 12 03:06:28 PM UTC 24 | 5555237146 ps | ||
| T891 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.889223501 | Oct 12 03:02:52 PM UTC 24 | Oct 12 03:06:28 PM UTC 24 | 14180026840 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.1141029014 | Oct 12 03:05:26 PM UTC 24 | Oct 12 03:06:29 PM UTC 24 | 6765573203 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.3460004793 | Oct 12 03:04:26 PM UTC 24 | Oct 12 03:06:31 PM UTC 24 | 24746051313 ps | ||
| T892 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.3704965347 | Oct 12 03:05:47 PM UTC 24 | Oct 12 03:06:37 PM UTC 24 | 5129297601 ps | ||
| T893 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.3819280211 | Oct 12 03:05:47 PM UTC 24 | Oct 12 03:06:44 PM UTC 24 | 475716769 ps | ||
| T894 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.743299542 | Oct 12 03:03:25 PM UTC 24 | Oct 12 03:06:45 PM UTC 24 | 8536537124 ps | ||
| T895 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.4010208735 | Oct 12 03:05:35 PM UTC 24 | Oct 12 03:06:47 PM UTC 24 | 27461234390 ps | ||
| T896 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.1013268176 | Oct 12 03:04:49 PM UTC 24 | Oct 12 03:06:50 PM UTC 24 | 11536929981 ps | ||
| T897 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.3809400812 | Oct 12 03:05:47 PM UTC 24 | Oct 12 03:06:50 PM UTC 24 | 7207151352 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.577985137 | Oct 12 03:04:45 PM UTC 24 | Oct 12 03:06:52 PM UTC 24 | 22509464316 ps | ||
| T247 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.1497163405 | Oct 12 03:04:58 PM UTC 24 | Oct 12 03:06:58 PM UTC 24 | 15881917501 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.1657896705 | Oct 12 03:04:20 PM UTC 24 | Oct 12 03:07:05 PM UTC 24 | 739191966 ps | ||
| T898 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.1589523091 | Oct 12 03:05:19 PM UTC 24 | Oct 12 03:07:06 PM UTC 24 | 50992539208 ps | ||
| T899 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.269069584 | Oct 12 03:05:07 PM UTC 24 | Oct 12 03:07:14 PM UTC 24 | 872676653 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.4119700662 | Oct 12 03:02:39 PM UTC 24 | Oct 12 03:07:18 PM UTC 24 | 20815953883 ps | ||
| T900 | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.770811689 | Oct 12 03:05:38 PM UTC 24 | Oct 12 03:08:08 PM UTC 24 | 89233256717 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_error_random.3512715581 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 264433873 ps |
| CPU time | 4.61 seconds |
| Started | Oct 12 02:52:19 PM UTC 24 |
| Finished | Oct 12 02:52:25 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512715581 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.3512715581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/0.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.660163962 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 20647062841 ps |
| CPU time | 177.61 seconds |
| Started | Oct 12 02:53:47 PM UTC 24 |
| Finished | Oct 12 02:56:47 PM UTC 24 |
| Peak memory | 213036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660163962 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.660163962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.2500666714 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 51704393964 ps |
| CPU time | 194.88 seconds |
| Started | Oct 12 03:01:31 PM UTC 24 |
| Finished | Oct 12 03:04:49 PM UTC 24 |
| Peak memory | 214496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500666714 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.2500666714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.2586925138 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 18601347003 ps |
| CPU time | 199.46 seconds |
| Started | Oct 12 02:52:31 PM UTC 24 |
| Finished | Oct 12 02:55:54 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586925138 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.2586925138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.186795556 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 23449742405 ps |
| CPU time | 119.36 seconds |
| Started | Oct 12 02:55:40 PM UTC 24 |
| Finished | Oct 12 02:57:41 PM UTC 24 |
| Peak memory | 213100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186795556 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.186795556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.3169696541 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 44029961520 ps |
| CPU time | 151.73 seconds |
| Started | Oct 12 02:57:02 PM UTC 24 |
| Finished | Oct 12 02:59:36 PM UTC 24 |
| Peak memory | 213016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169696541 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.3169696541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_unmapped_addr.3712920314 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 733555812 ps |
| CPU time | 7.36 seconds |
| Started | Oct 12 02:52:22 PM UTC 24 |
| Finished | Oct 12 02:52:30 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712920314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3712920314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/0.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.3213484531 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 15182030285 ps |
| CPU time | 111.96 seconds |
| Started | Oct 12 03:00:15 PM UTC 24 |
| Finished | Oct 12 03:02:09 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213484531 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.3213484531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all.3109887347 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 3503612905 ps |
| CPU time | 67.63 seconds |
| Started | Oct 12 02:52:22 PM UTC 24 |
| Finished | Oct 12 02:53:31 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109887347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3109887347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/0.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.3242849803 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 293361830 ps |
| CPU time | 37.03 seconds |
| Started | Oct 12 02:52:22 PM UTC 24 |
| Finished | Oct 12 02:53:00 PM UTC 24 |
| Peak memory | 213040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242849803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.3242849803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.2527514311 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 21768985679 ps |
| CPU time | 175.29 seconds |
| Started | Oct 12 02:56:32 PM UTC 24 |
| Finished | Oct 12 02:59:30 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527514311 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.2527514311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.1508986221 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 42646482561 ps |
| CPU time | 101.67 seconds |
| Started | Oct 12 02:54:44 PM UTC 24 |
| Finished | Oct 12 02:56:28 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508986221 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.1508986221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_zero_delays.3690192292 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 30208335 ps |
| CPU time | 2.71 seconds |
| Started | Oct 12 02:52:16 PM UTC 24 |
| Finished | Oct 12 02:52:20 PM UTC 24 |
| Peak memory | 212956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690192292 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.3690192292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/0.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.637260236 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 12127286286 ps |
| CPU time | 81.24 seconds |
| Started | Oct 12 02:52:18 PM UTC 24 |
| Finished | Oct 12 02:53:41 PM UTC 24 |
| Peak memory | 213092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637260236 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.637260236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_large_delays.3344420879 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 25280957395 ps |
| CPU time | 56.1 seconds |
| Started | Oct 12 02:52:16 PM UTC 24 |
| Finished | Oct 12 02:53:14 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344420879 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3344420879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/0.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.2077323666 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 9505474423 ps |
| CPU time | 184.17 seconds |
| Started | Oct 12 02:57:08 PM UTC 24 |
| Finished | Oct 12 03:00:15 PM UTC 24 |
| Peak memory | 217124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077323666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.2077323666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.2961651418 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 717928999 ps |
| CPU time | 115.26 seconds |
| Started | Oct 12 02:54:32 PM UTC 24 |
| Finished | Oct 12 02:56:31 PM UTC 24 |
| Peak memory | 215000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961651418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.2961651418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.1244459711 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 4846372398 ps |
| CPU time | 88.13 seconds |
| Started | Oct 12 02:52:44 PM UTC 24 |
| Finished | Oct 12 02:54:15 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244459711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.1244459711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.1289571762 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5028171687 ps |
| CPU time | 132.03 seconds |
| Started | Oct 12 02:55:49 PM UTC 24 |
| Finished | Oct 12 02:58:03 PM UTC 24 |
| Peak memory | 217136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289571762 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.1289571762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.2535790019 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 66840846598 ps |
| CPU time | 160.24 seconds |
| Started | Oct 12 02:58:20 PM UTC 24 |
| Finished | Oct 12 03:01:03 PM UTC 24 |
| Peak memory | 214560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535790019 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.2535790019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_slow_rsp.2281868516 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 92388377585 ps |
| CPU time | 84.49 seconds |
| Started | Oct 12 02:52:18 PM UTC 24 |
| Finished | Oct 12 02:53:44 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281868516 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.2281868516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/0.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_error.3512597316 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3231811657 ps |
| CPU time | 48.8 seconds |
| Started | Oct 12 03:00:34 PM UTC 24 |
| Finished | Oct 12 03:01:25 PM UTC 24 |
| Peak memory | 213080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512597316 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3512597316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/30.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.1629111799 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 2607966391 ps |
| CPU time | 12.28 seconds |
| Started | Oct 12 03:03:54 PM UTC 24 |
| Finished | Oct 12 03:04:07 PM UTC 24 |
| Peak memory | 212988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629111799 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.1629111799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/43.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device.1408156484 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 2960501907 ps |
| CPU time | 30.23 seconds |
| Started | Oct 12 02:52:49 PM UTC 24 |
| Finished | Oct 12 02:53:21 PM UTC 24 |
| Peak memory | 210952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408156484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.1408156484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/2.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all.1767885738 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 5720983366 ps |
| CPU time | 81.85 seconds |
| Started | Oct 12 03:01:21 PM UTC 24 |
| Finished | Oct 12 03:02:44 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767885738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.1767885738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/33.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.127213028 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 16103049378 ps |
| CPU time | 92.06 seconds |
| Started | Oct 12 03:00:27 PM UTC 24 |
| Finished | Oct 12 03:02:01 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127213028 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.127213028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.3273876152 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 19033265100 ps |
| CPU time | 151.41 seconds |
| Started | Oct 12 02:57:35 PM UTC 24 |
| Finished | Oct 12 03:00:09 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273876152 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.3273876152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_error.778752606 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 3460453960 ps |
| CPU time | 47.16 seconds |
| Started | Oct 12 02:52:22 PM UTC 24 |
| Finished | Oct 12 02:53:11 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778752606 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.778752606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/0.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.1354919561 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 1847263234 ps |
| CPU time | 87.42 seconds |
| Started | Oct 12 02:56:07 PM UTC 24 |
| Finished | Oct 12 02:57:36 PM UTC 24 |
| Peak memory | 215024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354919561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.1354919561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device.2197483745 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 551443327 ps |
| CPU time | 7.96 seconds |
| Started | Oct 12 02:52:18 PM UTC 24 |
| Finished | Oct 12 02:52:27 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197483745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.2197483745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/0.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3898606478 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 45023119181 ps |
| CPU time | 142.67 seconds |
| Started | Oct 12 02:58:07 PM UTC 24 |
| Finished | Oct 12 03:00:32 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898606478 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.3898606478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1294539525 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 496911180 ps |
| CPU time | 63.61 seconds |
| Started | Oct 12 02:52:22 PM UTC 24 |
| Finished | Oct 12 02:53:27 PM UTC 24 |
| Peak memory | 215000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294539525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.1294539525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.1433658457 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 22494160688 ps |
| CPU time | 183.68 seconds |
| Started | Oct 12 03:00:44 PM UTC 24 |
| Finished | Oct 12 03:03:51 PM UTC 24 |
| Peak memory | 214564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433658457 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.1433658457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.1271811895 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 3863063510 ps |
| CPU time | 94.63 seconds |
| Started | Oct 12 02:59:21 PM UTC 24 |
| Finished | Oct 12 03:00:58 PM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271811895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.1271811895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3882868988 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 14526423248 ps |
| CPU time | 207.45 seconds |
| Started | Oct 12 02:56:51 PM UTC 24 |
| Finished | Oct 12 03:00:22 PM UTC 24 |
| Peak memory | 218628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882868988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.3882868988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.2935586691 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 6175220423 ps |
| CPU time | 80.54 seconds |
| Started | Oct 12 02:57:10 PM UTC 24 |
| Finished | Oct 12 02:58:32 PM UTC 24 |
| Peak memory | 217200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935586691 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.2935586691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.3063266871 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 56238356 ps |
| CPU time | 5.89 seconds |
| Started | Oct 12 02:52:22 PM UTC 24 |
| Finished | Oct 12 02:52:29 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063266871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.3063266871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random.157365156 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 657030130 ps |
| CPU time | 3.71 seconds |
| Started | Oct 12 02:52:16 PM UTC 24 |
| Finished | Oct 12 02:52:21 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157365156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.157365156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/0.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_same_source.3799317230 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 2895543608 ps |
| CPU time | 13.72 seconds |
| Started | Oct 12 02:52:19 PM UTC 24 |
| Finished | Oct 12 02:52:34 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799317230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.3799317230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/0.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke.4223952471 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 9231718 ps |
| CPU time | 1.74 seconds |
| Started | Oct 12 02:52:13 PM UTC 24 |
| Finished | Oct 12 02:52:15 PM UTC 24 |
| Peak memory | 210396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223952471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.4223952471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/0.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_large_delays.4068835929 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 1205012848 ps |
| CPU time | 10.21 seconds |
| Started | Oct 12 02:52:14 PM UTC 24 |
| Finished | Oct 12 02:52:25 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068835929 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.4068835929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/0.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.1234847020 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3833538864 ps |
| CPU time | 12.83 seconds |
| Started | Oct 12 02:52:15 PM UTC 24 |
| Finished | Oct 12 02:52:29 PM UTC 24 |
| Peak memory | 211024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234847020 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1234847020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.572631348 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 9110084 ps |
| CPU time | 1.68 seconds |
| Started | Oct 12 02:52:14 PM UTC 24 |
| Finished | Oct 12 02:52:17 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572631348 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.572631348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/0.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device.2630029547 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1245885548 ps |
| CPU time | 11.52 seconds |
| Started | Oct 12 02:52:30 PM UTC 24 |
| Finished | Oct 12 02:52:43 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630029547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.2630029547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/1.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.2760953973 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 88951868 ps |
| CPU time | 6.63 seconds |
| Started | Oct 12 02:52:37 PM UTC 24 |
| Finished | Oct 12 02:52:45 PM UTC 24 |
| Peak memory | 212972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760953973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.2760953973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_error_random.2908874689 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1344044231 ps |
| CPU time | 10.35 seconds |
| Started | Oct 12 02:52:33 PM UTC 24 |
| Finished | Oct 12 02:52:45 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908874689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2908874689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/1.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random.2656499580 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2397698659 ps |
| CPU time | 11.98 seconds |
| Started | Oct 12 02:52:28 PM UTC 24 |
| Finished | Oct 12 02:52:41 PM UTC 24 |
| Peak memory | 213004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656499580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.2656499580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/1.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_large_delays.1151939654 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 4385288680 ps |
| CPU time | 14.41 seconds |
| Started | Oct 12 02:52:29 PM UTC 24 |
| Finished | Oct 12 02:52:44 PM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151939654 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.1151939654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/1.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_slow_rsp.4280634635 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 23721941344 ps |
| CPU time | 77.88 seconds |
| Started | Oct 12 02:52:30 PM UTC 24 |
| Finished | Oct 12 02:53:50 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280634635 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.4280634635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/1.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_zero_delays.1465078580 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 20414264 ps |
| CPU time | 3.15 seconds |
| Started | Oct 12 02:52:28 PM UTC 24 |
| Finished | Oct 12 02:52:32 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465078580 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.1465078580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/1.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_same_source.3515999364 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2224957527 ps |
| CPU time | 11.74 seconds |
| Started | Oct 12 02:52:32 PM UTC 24 |
| Finished | Oct 12 02:52:45 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515999364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.3515999364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/1.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke.418940609 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 101194356 ps |
| CPU time | 1.61 seconds |
| Started | Oct 12 02:52:23 PM UTC 24 |
| Finished | Oct 12 02:52:26 PM UTC 24 |
| Peak memory | 211972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418940609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.418940609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/1.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_large_delays.3036483824 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 4240375434 ps |
| CPU time | 17.54 seconds |
| Started | Oct 12 02:52:26 PM UTC 24 |
| Finished | Oct 12 02:52:45 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036483824 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3036483824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/1.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.1010943529 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 2618466662 ps |
| CPU time | 15.34 seconds |
| Started | Oct 12 02:52:26 PM UTC 24 |
| Finished | Oct 12 02:52:43 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010943529 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1010943529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.3576275225 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 8629091 ps |
| CPU time | 1.7 seconds |
| Started | Oct 12 02:52:25 PM UTC 24 |
| Finished | Oct 12 02:52:28 PM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576275225 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.3576275225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/1.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all.974637126 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2942642498 ps |
| CPU time | 22.27 seconds |
| Started | Oct 12 02:52:38 PM UTC 24 |
| Finished | Oct 12 02:53:01 PM UTC 24 |
| Peak memory | 212992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974637126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.974637126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/1.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_error.2160563606 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 550323284 ps |
| CPU time | 31.84 seconds |
| Started | Oct 12 02:52:43 PM UTC 24 |
| Finished | Oct 12 02:53:17 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160563606 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.2160563606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/1.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.3779881261 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1690653806 ps |
| CPU time | 21.19 seconds |
| Started | Oct 12 02:52:42 PM UTC 24 |
| Finished | Oct 12 02:53:05 PM UTC 24 |
| Peak memory | 212936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779881261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.3779881261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_unmapped_addr.431585838 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 102757145 ps |
| CPU time | 9.27 seconds |
| Started | Oct 12 02:52:34 PM UTC 24 |
| Finished | Oct 12 02:52:45 PM UTC 24 |
| Peak memory | 212920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431585838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.431585838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/1.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device.3492770756 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 851861281 ps |
| CPU time | 14.49 seconds |
| Started | Oct 12 02:55:09 PM UTC 24 |
| Finished | Oct 12 02:55:25 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492770756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.3492770756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/10.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.4163185740 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 9425226422 ps |
| CPU time | 77.25 seconds |
| Started | Oct 12 02:55:10 PM UTC 24 |
| Finished | Oct 12 02:56:28 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163185740 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.4163185740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.2466672028 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 58187696 ps |
| CPU time | 4.78 seconds |
| Started | Oct 12 02:55:16 PM UTC 24 |
| Finished | Oct 12 02:55:22 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466672028 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2466672028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_error_random.10111586 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 250562772 ps |
| CPU time | 5.49 seconds |
| Started | Oct 12 02:55:13 PM UTC 24 |
| Finished | Oct 12 02:55:19 PM UTC 24 |
| Peak memory | 210888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10111586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.10111586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/10.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random.1937337685 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 142900809 ps |
| CPU time | 2.92 seconds |
| Started | Oct 12 02:55:07 PM UTC 24 |
| Finished | Oct 12 02:55:11 PM UTC 24 |
| Peak memory | 212912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937337685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.1937337685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/10.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_large_delays.1876568353 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 13279355180 ps |
| CPU time | 55.59 seconds |
| Started | Oct 12 02:55:08 PM UTC 24 |
| Finished | Oct 12 02:56:05 PM UTC 24 |
| Peak memory | 211040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876568353 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1876568353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/10.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_slow_rsp.3131314110 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 3838299655 ps |
| CPU time | 32.14 seconds |
| Started | Oct 12 02:55:09 PM UTC 24 |
| Finished | Oct 12 02:55:43 PM UTC 24 |
| Peak memory | 213016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131314110 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3131314110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/10.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_zero_delays.1051563725 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 66689782 ps |
| CPU time | 9.08 seconds |
| Started | Oct 12 02:55:08 PM UTC 24 |
| Finished | Oct 12 02:55:18 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051563725 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.1051563725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/10.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_same_source.90197125 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 23373503 ps |
| CPU time | 2.46 seconds |
| Started | Oct 12 02:55:12 PM UTC 24 |
| Finished | Oct 12 02:55:15 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90197125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.90197125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/10.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke.1884299194 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 76999841 ps |
| CPU time | 2.25 seconds |
| Started | Oct 12 02:55:05 PM UTC 24 |
| Finished | Oct 12 02:55:08 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884299194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.1884299194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/10.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3275872690 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1791401901 ps |
| CPU time | 9.09 seconds |
| Started | Oct 12 02:55:05 PM UTC 24 |
| Finished | Oct 12 02:55:15 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275872690 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3275872690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/10.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.670464967 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 1241277414 ps |
| CPU time | 9.8 seconds |
| Started | Oct 12 02:55:07 PM UTC 24 |
| Finished | Oct 12 02:55:18 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670464967 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.670464967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.2956113815 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 24107743 ps |
| CPU time | 1.7 seconds |
| Started | Oct 12 02:55:05 PM UTC 24 |
| Finished | Oct 12 02:55:08 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956113815 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.2956113815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/10.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all.2382810995 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 5898391905 ps |
| CPU time | 35.7 seconds |
| Started | Oct 12 02:55:16 PM UTC 24 |
| Finished | Oct 12 02:55:53 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382810995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.2382810995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/10.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_error.3458988797 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 2417955156 ps |
| CPU time | 38.39 seconds |
| Started | Oct 12 02:55:17 PM UTC 24 |
| Finished | Oct 12 02:55:57 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458988797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.3458988797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/10.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.241045053 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 12288459736 ps |
| CPU time | 246.02 seconds |
| Started | Oct 12 02:55:17 PM UTC 24 |
| Finished | Oct 12 02:59:27 PM UTC 24 |
| Peak memory | 218700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241045053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.241045053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.3710054875 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 106896293 ps |
| CPU time | 12.52 seconds |
| Started | Oct 12 02:55:17 PM UTC 24 |
| Finished | Oct 12 02:55:31 PM UTC 24 |
| Peak memory | 213040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710054875 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.3710054875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_unmapped_addr.3912986673 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 138001184 ps |
| CPU time | 2.75 seconds |
| Started | Oct 12 02:55:15 PM UTC 24 |
| Finished | Oct 12 02:55:19 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912986673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.3912986673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/10.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device.778698486 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 222198921 ps |
| CPU time | 11.62 seconds |
| Started | Oct 12 02:55:23 PM UTC 24 |
| Finished | Oct 12 02:55:36 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778698486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.778698486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/11.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.4165600032 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 52768375232 ps |
| CPU time | 147.95 seconds |
| Started | Oct 12 02:55:23 PM UTC 24 |
| Finished | Oct 12 02:57:53 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165600032 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.4165600032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.132860387 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 495378226 ps |
| CPU time | 8.54 seconds |
| Started | Oct 12 02:55:27 PM UTC 24 |
| Finished | Oct 12 02:55:37 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132860387 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.132860387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_error_random.181424159 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 698026794 ps |
| CPU time | 3.18 seconds |
| Started | Oct 12 02:55:24 PM UTC 24 |
| Finished | Oct 12 02:55:28 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181424159 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.181424159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/11.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random.2468088973 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 238978250 ps |
| CPU time | 6.34 seconds |
| Started | Oct 12 02:55:19 PM UTC 24 |
| Finished | Oct 12 02:55:27 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468088973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.2468088973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/11.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_large_delays.540447578 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 20675218493 ps |
| CPU time | 94.33 seconds |
| Started | Oct 12 02:55:21 PM UTC 24 |
| Finished | Oct 12 02:56:57 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540447578 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.540447578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/11.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_slow_rsp.3644449822 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 38743380346 ps |
| CPU time | 71.02 seconds |
| Started | Oct 12 02:55:21 PM UTC 24 |
| Finished | Oct 12 02:56:33 PM UTC 24 |
| Peak memory | 211032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644449822 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3644449822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/11.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_zero_delays.677476981 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 40606652 ps |
| CPU time | 6.32 seconds |
| Started | Oct 12 02:55:19 PM UTC 24 |
| Finished | Oct 12 02:55:27 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677476981 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.677476981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/11.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_same_source.3947853472 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 2407908249 ps |
| CPU time | 15.86 seconds |
| Started | Oct 12 02:55:24 PM UTC 24 |
| Finished | Oct 12 02:55:41 PM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947853472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3947853472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/11.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke.1649453598 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 128539312 ps |
| CPU time | 2.56 seconds |
| Started | Oct 12 02:55:19 PM UTC 24 |
| Finished | Oct 12 02:55:23 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649453598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.1649453598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/11.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_large_delays.1497643421 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1766926678 ps |
| CPU time | 13.75 seconds |
| Started | Oct 12 02:55:19 PM UTC 24 |
| Finished | Oct 12 02:55:34 PM UTC 24 |
| Peak memory | 213016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497643421 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.1497643421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/11.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.3285932868 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1155424610 ps |
| CPU time | 12.33 seconds |
| Started | Oct 12 02:55:19 PM UTC 24 |
| Finished | Oct 12 02:55:33 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285932868 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3285932868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.675117359 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 8711411 ps |
| CPU time | 1.61 seconds |
| Started | Oct 12 02:55:19 PM UTC 24 |
| Finished | Oct 12 02:55:22 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675117359 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.675117359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/11.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all.942222762 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 5875420081 ps |
| CPU time | 89.2 seconds |
| Started | Oct 12 02:55:27 PM UTC 24 |
| Finished | Oct 12 02:56:59 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942222762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.942222762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/11.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_error.3118392374 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 409438176 ps |
| CPU time | 27.83 seconds |
| Started | Oct 12 02:55:30 PM UTC 24 |
| Finished | Oct 12 02:55:59 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118392374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.3118392374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/11.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.3167426715 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 270100949 ps |
| CPU time | 46.98 seconds |
| Started | Oct 12 02:55:30 PM UTC 24 |
| Finished | Oct 12 02:56:18 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167426715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.3167426715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.547381852 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 542453843 ps |
| CPU time | 94.95 seconds |
| Started | Oct 12 02:55:31 PM UTC 24 |
| Finished | Oct 12 02:57:08 PM UTC 24 |
| Peak memory | 217064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547381852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.547381852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_unmapped_addr.1408847067 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 482379597 ps |
| CPU time | 11.33 seconds |
| Started | Oct 12 02:55:26 PM UTC 24 |
| Finished | Oct 12 02:55:39 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408847067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1408847067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/11.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device.3894350208 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1552874472 ps |
| CPU time | 12.81 seconds |
| Started | Oct 12 02:55:40 PM UTC 24 |
| Finished | Oct 12 02:55:54 PM UTC 24 |
| Peak memory | 212956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894350208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.3894350208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/12.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.4146647259 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1139883361 ps |
| CPU time | 4.27 seconds |
| Started | Oct 12 02:55:44 PM UTC 24 |
| Finished | Oct 12 02:55:49 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146647259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.4146647259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_error_random.4074491344 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 1100528932 ps |
| CPU time | 11.27 seconds |
| Started | Oct 12 02:55:43 PM UTC 24 |
| Finished | Oct 12 02:55:55 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074491344 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.4074491344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/12.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random.1368812557 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 325445732 ps |
| CPU time | 7.95 seconds |
| Started | Oct 12 02:55:36 PM UTC 24 |
| Finished | Oct 12 02:55:45 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368812557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.1368812557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/12.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_large_delays.4179437513 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 8836149792 ps |
| CPU time | 51.47 seconds |
| Started | Oct 12 02:55:36 PM UTC 24 |
| Finished | Oct 12 02:56:29 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179437513 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.4179437513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/12.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_slow_rsp.4029280061 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 1307798179 ps |
| CPU time | 12.72 seconds |
| Started | Oct 12 02:55:37 PM UTC 24 |
| Finished | Oct 12 02:55:51 PM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029280061 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.4029280061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/12.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_zero_delays.3468333782 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 67241292 ps |
| CPU time | 4.82 seconds |
| Started | Oct 12 02:55:36 PM UTC 24 |
| Finished | Oct 12 02:55:42 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468333782 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.3468333782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/12.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_same_source.894839242 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 2116656975 ps |
| CPU time | 18.34 seconds |
| Started | Oct 12 02:55:42 PM UTC 24 |
| Finished | Oct 12 02:56:01 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894839242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.894839242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/12.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke.3645473251 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 109116500 ps |
| CPU time | 1.99 seconds |
| Started | Oct 12 02:55:32 PM UTC 24 |
| Finished | Oct 12 02:55:35 PM UTC 24 |
| Peak memory | 211952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645473251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.3645473251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/12.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_large_delays.1874888131 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 2340402282 ps |
| CPU time | 13.03 seconds |
| Started | Oct 12 02:55:34 PM UTC 24 |
| Finished | Oct 12 02:55:48 PM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874888131 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.1874888131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/12.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.3304275905 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 5193494335 ps |
| CPU time | 11.74 seconds |
| Started | Oct 12 02:55:35 PM UTC 24 |
| Finished | Oct 12 02:55:48 PM UTC 24 |
| Peak memory | 213000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304275905 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.3304275905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.3584119020 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 11317161 ps |
| CPU time | 1.63 seconds |
| Started | Oct 12 02:55:33 PM UTC 24 |
| Finished | Oct 12 02:55:36 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584119020 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.3584119020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/12.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all.2297540019 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 355817344 ps |
| CPU time | 35.09 seconds |
| Started | Oct 12 02:55:46 PM UTC 24 |
| Finished | Oct 12 02:56:23 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297540019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2297540019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/12.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_error.2314212972 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 10646630476 ps |
| CPU time | 62.52 seconds |
| Started | Oct 12 02:55:47 PM UTC 24 |
| Finished | Oct 12 02:56:52 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314212972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.2314212972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/12.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.1630405520 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 184486902 ps |
| CPU time | 40.56 seconds |
| Started | Oct 12 02:55:46 PM UTC 24 |
| Finished | Oct 12 02:56:28 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630405520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.1630405520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_unmapped_addr.3128798516 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 12628330 ps |
| CPU time | 1.72 seconds |
| Started | Oct 12 02:55:44 PM UTC 24 |
| Finished | Oct 12 02:55:47 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128798516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.3128798516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/12.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device.3543456261 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 1254681177 ps |
| CPU time | 31.21 seconds |
| Started | Oct 12 02:55:56 PM UTC 24 |
| Finished | Oct 12 02:56:28 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543456261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.3543456261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/13.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.1738345718 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 15340639778 ps |
| CPU time | 82.78 seconds |
| Started | Oct 12 02:55:58 PM UTC 24 |
| Finished | Oct 12 02:57:23 PM UTC 24 |
| Peak memory | 213152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738345718 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.1738345718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.65820114 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 98146735 ps |
| CPU time | 6.46 seconds |
| Started | Oct 12 02:56:02 PM UTC 24 |
| Finished | Oct 12 02:56:09 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65820114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.65820114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_error_random.3881981273 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 3344920208 ps |
| CPU time | 16.7 seconds |
| Started | Oct 12 02:56:00 PM UTC 24 |
| Finished | Oct 12 02:56:18 PM UTC 24 |
| Peak memory | 210956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881981273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3881981273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/13.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random.854580955 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 259537954 ps |
| CPU time | 6.51 seconds |
| Started | Oct 12 02:55:53 PM UTC 24 |
| Finished | Oct 12 02:56:01 PM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854580955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.854580955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/13.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_large_delays.4113870764 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 8065824805 ps |
| CPU time | 16.81 seconds |
| Started | Oct 12 02:55:55 PM UTC 24 |
| Finished | Oct 12 02:56:12 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113870764 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.4113870764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/13.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_slow_rsp.3092979941 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 6009626102 ps |
| CPU time | 45.48 seconds |
| Started | Oct 12 02:55:55 PM UTC 24 |
| Finished | Oct 12 02:56:41 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092979941 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.3092979941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/13.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_zero_delays.68333486 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 35264131 ps |
| CPU time | 3.18 seconds |
| Started | Oct 12 02:55:54 PM UTC 24 |
| Finished | Oct 12 02:55:59 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68333486 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.68333486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/13.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_same_source.3226049367 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 96832367 ps |
| CPU time | 3.8 seconds |
| Started | Oct 12 02:56:00 PM UTC 24 |
| Finished | Oct 12 02:56:05 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226049367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.3226049367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/13.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke.127162521 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 93828710 ps |
| CPU time | 2.6 seconds |
| Started | Oct 12 02:55:49 PM UTC 24 |
| Finished | Oct 12 02:55:52 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127162521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.127162521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/13.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_large_delays.3767171933 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 2348269478 ps |
| CPU time | 12.35 seconds |
| Started | Oct 12 02:55:52 PM UTC 24 |
| Finished | Oct 12 02:56:05 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767171933 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.3767171933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/13.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.2241471590 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 1562974826 ps |
| CPU time | 8.68 seconds |
| Started | Oct 12 02:55:53 PM UTC 24 |
| Finished | Oct 12 02:56:03 PM UTC 24 |
| Peak memory | 212920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241471590 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2241471590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.1239274240 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 9095815 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 02:55:50 PM UTC 24 |
| Finished | Oct 12 02:55:52 PM UTC 24 |
| Peak memory | 211960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239274240 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.1239274240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/13.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all.1359102794 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 3651220509 ps |
| CPU time | 84.91 seconds |
| Started | Oct 12 02:56:03 PM UTC 24 |
| Finished | Oct 12 02:57:30 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359102794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1359102794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/13.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_error.1041458306 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 5765853733 ps |
| CPU time | 56.77 seconds |
| Started | Oct 12 02:56:04 PM UTC 24 |
| Finished | Oct 12 02:57:03 PM UTC 24 |
| Peak memory | 213080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041458306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.1041458306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/13.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.2818420924 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 7845588 ps |
| CPU time | 4.82 seconds |
| Started | Oct 12 02:56:03 PM UTC 24 |
| Finished | Oct 12 02:56:09 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818420924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.2818420924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_unmapped_addr.1726048929 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 148089755 ps |
| CPU time | 4.62 seconds |
| Started | Oct 12 02:56:00 PM UTC 24 |
| Finished | Oct 12 02:56:06 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726048929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.1726048929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/13.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device.2851698783 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 2920920485 ps |
| CPU time | 21.86 seconds |
| Started | Oct 12 02:56:13 PM UTC 24 |
| Finished | Oct 12 02:56:36 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851698783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.2851698783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/14.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.1993822092 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 14262506379 ps |
| CPU time | 49.09 seconds |
| Started | Oct 12 02:56:15 PM UTC 24 |
| Finished | Oct 12 02:57:06 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993822092 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.1993822092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.2072941175 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 745475914 ps |
| CPU time | 8.1 seconds |
| Started | Oct 12 02:56:21 PM UTC 24 |
| Finished | Oct 12 02:56:30 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072941175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.2072941175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_error_random.2082700615 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 2545158434 ps |
| CPU time | 16.88 seconds |
| Started | Oct 12 02:56:20 PM UTC 24 |
| Finished | Oct 12 02:56:38 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082700615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2082700615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/14.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random.3304978232 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 56522576 ps |
| CPU time | 8.1 seconds |
| Started | Oct 12 02:56:11 PM UTC 24 |
| Finished | Oct 12 02:56:20 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304978232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.3304978232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/14.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_large_delays.1483544268 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 16419993378 ps |
| CPU time | 68.1 seconds |
| Started | Oct 12 02:56:11 PM UTC 24 |
| Finished | Oct 12 02:57:21 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483544268 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.1483544268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/14.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_slow_rsp.3722511183 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 37242741131 ps |
| CPU time | 43.35 seconds |
| Started | Oct 12 02:56:11 PM UTC 24 |
| Finished | Oct 12 02:56:56 PM UTC 24 |
| Peak memory | 213012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722511183 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3722511183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/14.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_zero_delays.2526840665 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 81537802 ps |
| CPU time | 7.91 seconds |
| Started | Oct 12 02:56:11 PM UTC 24 |
| Finished | Oct 12 02:56:20 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526840665 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2526840665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/14.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_same_source.2345341610 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 34382707 ps |
| CPU time | 5.45 seconds |
| Started | Oct 12 02:56:18 PM UTC 24 |
| Finished | Oct 12 02:56:25 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345341610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.2345341610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/14.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke.2758448044 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 9611237 ps |
| CPU time | 1.79 seconds |
| Started | Oct 12 02:56:07 PM UTC 24 |
| Finished | Oct 12 02:56:09 PM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758448044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.2758448044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/14.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_large_delays.715013124 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 3078554446 ps |
| CPU time | 15.22 seconds |
| Started | Oct 12 02:56:07 PM UTC 24 |
| Finished | Oct 12 02:56:23 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715013124 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.715013124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/14.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2240245212 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 1486285182 ps |
| CPU time | 8.3 seconds |
| Started | Oct 12 02:56:08 PM UTC 24 |
| Finished | Oct 12 02:56:17 PM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240245212 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2240245212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.804045261 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 35503853 ps |
| CPU time | 1.64 seconds |
| Started | Oct 12 02:56:07 PM UTC 24 |
| Finished | Oct 12 02:56:09 PM UTC 24 |
| Peak memory | 211960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804045261 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.804045261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/14.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all.1238454862 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 6701343696 ps |
| CPU time | 55.15 seconds |
| Started | Oct 12 02:56:21 PM UTC 24 |
| Finished | Oct 12 02:57:18 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238454862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.1238454862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/14.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_error.3266323388 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 732701079 ps |
| CPU time | 28.78 seconds |
| Started | Oct 12 02:56:25 PM UTC 24 |
| Finished | Oct 12 02:56:55 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266323388 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.3266323388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/14.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.1347381166 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 2366242850 ps |
| CPU time | 101.91 seconds |
| Started | Oct 12 02:56:23 PM UTC 24 |
| Finished | Oct 12 02:58:07 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347381166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.1347381166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.1436627963 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 7730210887 ps |
| CPU time | 100.87 seconds |
| Started | Oct 12 02:56:25 PM UTC 24 |
| Finished | Oct 12 02:58:08 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436627963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.1436627963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_unmapped_addr.3743614443 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 478629327 ps |
| CPU time | 14.52 seconds |
| Started | Oct 12 02:56:20 PM UTC 24 |
| Finished | Oct 12 02:56:36 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743614443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.3743614443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/14.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device.1926039763 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 120926547 ps |
| CPU time | 2.26 seconds |
| Started | Oct 12 02:56:31 PM UTC 24 |
| Finished | Oct 12 02:56:34 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926039763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.1926039763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/15.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.3919486227 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 272127722 ps |
| CPU time | 7.68 seconds |
| Started | Oct 12 02:56:35 PM UTC 24 |
| Finished | Oct 12 02:56:44 PM UTC 24 |
| Peak memory | 213100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919486227 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.3919486227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_error_random.2319752961 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 222744333 ps |
| CPU time | 3.97 seconds |
| Started | Oct 12 02:56:34 PM UTC 24 |
| Finished | Oct 12 02:56:39 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319752961 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2319752961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/15.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random.2149371804 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 1941517580 ps |
| CPU time | 5.95 seconds |
| Started | Oct 12 02:56:29 PM UTC 24 |
| Finished | Oct 12 02:56:37 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149371804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2149371804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/15.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_large_delays.4202877598 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 53980087622 ps |
| CPU time | 70.91 seconds |
| Started | Oct 12 02:56:31 PM UTC 24 |
| Finished | Oct 12 02:57:44 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202877598 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.4202877598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/15.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_slow_rsp.1492605106 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 7673518097 ps |
| CPU time | 64.9 seconds |
| Started | Oct 12 02:56:31 PM UTC 24 |
| Finished | Oct 12 02:57:38 PM UTC 24 |
| Peak memory | 213012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492605106 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1492605106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/15.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_zero_delays.1541993608 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 28756915 ps |
| CPU time | 2.84 seconds |
| Started | Oct 12 02:56:29 PM UTC 24 |
| Finished | Oct 12 02:56:33 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541993608 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.1541993608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/15.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_same_source.1762551412 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 70063912 ps |
| CPU time | 4.84 seconds |
| Started | Oct 12 02:56:33 PM UTC 24 |
| Finished | Oct 12 02:56:39 PM UTC 24 |
| Peak memory | 212928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762551412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1762551412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/15.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke.1255063054 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 55599050 ps |
| CPU time | 1.94 seconds |
| Started | Oct 12 02:56:27 PM UTC 24 |
| Finished | Oct 12 02:56:30 PM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255063054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.1255063054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/15.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_large_delays.217958726 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 3376877067 ps |
| CPU time | 12.41 seconds |
| Started | Oct 12 02:56:29 PM UTC 24 |
| Finished | Oct 12 02:56:43 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217958726 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.217958726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/15.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.1641936610 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 2021828709 ps |
| CPU time | 18.62 seconds |
| Started | Oct 12 02:56:29 PM UTC 24 |
| Finished | Oct 12 02:56:49 PM UTC 24 |
| Peak memory | 213000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641936610 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.1641936610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.3066451920 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 21670416 ps |
| CPU time | 1.6 seconds |
| Started | Oct 12 02:56:27 PM UTC 24 |
| Finished | Oct 12 02:56:29 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066451920 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.3066451920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/15.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all.2198617977 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 107502803 ps |
| CPU time | 9.94 seconds |
| Started | Oct 12 02:56:36 PM UTC 24 |
| Finished | Oct 12 02:56:47 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198617977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.2198617977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/15.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_error.2658539263 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 3933765512 ps |
| CPU time | 62.51 seconds |
| Started | Oct 12 02:56:37 PM UTC 24 |
| Finished | Oct 12 02:57:42 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658539263 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2658539263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/15.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3213762916 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 345914307 ps |
| CPU time | 50.77 seconds |
| Started | Oct 12 02:56:37 PM UTC 24 |
| Finished | Oct 12 02:57:30 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213762916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.3213762916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.720015847 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 1000420824 ps |
| CPU time | 86.12 seconds |
| Started | Oct 12 02:56:39 PM UTC 24 |
| Finished | Oct 12 02:58:07 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720015847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.720015847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_unmapped_addr.3492048861 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 229395908 ps |
| CPU time | 3.26 seconds |
| Started | Oct 12 02:56:35 PM UTC 24 |
| Finished | Oct 12 02:56:39 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492048861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3492048861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/15.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device.3515677401 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1505975421 ps |
| CPU time | 21.29 seconds |
| Started | Oct 12 02:56:45 PM UTC 24 |
| Finished | Oct 12 02:57:08 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515677401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.3515677401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/16.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.1466934893 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 22192877568 ps |
| CPU time | 117.36 seconds |
| Started | Oct 12 02:56:48 PM UTC 24 |
| Finished | Oct 12 02:58:47 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466934893 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.1466934893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.2229205127 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 26116833 ps |
| CPU time | 1.75 seconds |
| Started | Oct 12 02:56:50 PM UTC 24 |
| Finished | Oct 12 02:56:53 PM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229205127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.2229205127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_error_random.1052934262 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 727581619 ps |
| CPU time | 13.95 seconds |
| Started | Oct 12 02:56:49 PM UTC 24 |
| Finished | Oct 12 02:57:04 PM UTC 24 |
| Peak memory | 213000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052934262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1052934262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/16.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random.2724755115 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 61635292 ps |
| CPU time | 2.58 seconds |
| Started | Oct 12 02:56:44 PM UTC 24 |
| Finished | Oct 12 02:56:47 PM UTC 24 |
| Peak memory | 212932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724755115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.2724755115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/16.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_large_delays.1265761710 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 21030120053 ps |
| CPU time | 48.19 seconds |
| Started | Oct 12 02:56:44 PM UTC 24 |
| Finished | Oct 12 02:57:33 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265761710 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.1265761710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/16.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_slow_rsp.3718844122 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 19862855653 ps |
| CPU time | 107.56 seconds |
| Started | Oct 12 02:56:45 PM UTC 24 |
| Finished | Oct 12 02:58:35 PM UTC 24 |
| Peak memory | 211032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718844122 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.3718844122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/16.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_zero_delays.1791703864 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 165621081 ps |
| CPU time | 5.73 seconds |
| Started | Oct 12 02:56:44 PM UTC 24 |
| Finished | Oct 12 02:56:50 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791703864 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.1791703864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/16.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_same_source.4020947539 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 28396606 ps |
| CPU time | 2.48 seconds |
| Started | Oct 12 02:56:49 PM UTC 24 |
| Finished | Oct 12 02:56:52 PM UTC 24 |
| Peak memory | 212932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020947539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.4020947539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/16.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke.2891584656 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 14110575 ps |
| CPU time | 1.67 seconds |
| Started | Oct 12 02:56:40 PM UTC 24 |
| Finished | Oct 12 02:56:43 PM UTC 24 |
| Peak memory | 211952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891584656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.2891584656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/16.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_large_delays.916824297 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 1392640572 ps |
| CPU time | 7.82 seconds |
| Started | Oct 12 02:56:40 PM UTC 24 |
| Finished | Oct 12 02:56:49 PM UTC 24 |
| Peak memory | 212984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916824297 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.916824297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/16.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.1680696702 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 594623389 ps |
| CPU time | 6.56 seconds |
| Started | Oct 12 02:56:42 PM UTC 24 |
| Finished | Oct 12 02:56:50 PM UTC 24 |
| Peak memory | 212944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680696702 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1680696702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.3796547218 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 8976911 ps |
| CPU time | 1.59 seconds |
| Started | Oct 12 02:56:40 PM UTC 24 |
| Finished | Oct 12 02:56:43 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796547218 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.3796547218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/16.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all.1199050359 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 37430062406 ps |
| CPU time | 72.67 seconds |
| Started | Oct 12 02:56:51 PM UTC 24 |
| Finished | Oct 12 02:58:06 PM UTC 24 |
| Peak memory | 215072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199050359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.1199050359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/16.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_error.1273916692 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 274142334 ps |
| CPU time | 16.1 seconds |
| Started | Oct 12 02:56:53 PM UTC 24 |
| Finished | Oct 12 02:57:10 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273916692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1273916692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/16.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.2394019012 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 540161237 ps |
| CPU time | 46.41 seconds |
| Started | Oct 12 02:56:53 PM UTC 24 |
| Finished | Oct 12 02:57:41 PM UTC 24 |
| Peak memory | 212972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394019012 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.2394019012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_unmapped_addr.2509865239 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 83430438 ps |
| CPU time | 3.2 seconds |
| Started | Oct 12 02:56:50 PM UTC 24 |
| Finished | Oct 12 02:56:54 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509865239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.2509865239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/16.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device.3294498534 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 359769344 ps |
| CPU time | 2.55 seconds |
| Started | Oct 12 02:57:00 PM UTC 24 |
| Finished | Oct 12 02:57:03 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294498534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.3294498534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/17.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.1299556002 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 43829448 ps |
| CPU time | 4.99 seconds |
| Started | Oct 12 02:57:06 PM UTC 24 |
| Finished | Oct 12 02:57:12 PM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299556002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.1299556002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_error_random.3045897520 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 46219252 ps |
| CPU time | 5.3 seconds |
| Started | Oct 12 02:57:04 PM UTC 24 |
| Finished | Oct 12 02:57:11 PM UTC 24 |
| Peak memory | 213012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045897520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3045897520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/17.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random.408371098 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 272798438 ps |
| CPU time | 3.99 seconds |
| Started | Oct 12 02:56:57 PM UTC 24 |
| Finished | Oct 12 02:57:02 PM UTC 24 |
| Peak memory | 210948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408371098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.408371098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/17.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_large_delays.551777315 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 30418786278 ps |
| CPU time | 92.82 seconds |
| Started | Oct 12 02:56:58 PM UTC 24 |
| Finished | Oct 12 02:58:33 PM UTC 24 |
| Peak memory | 212988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551777315 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.551777315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/17.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_slow_rsp.867130303 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 29606880723 ps |
| CPU time | 62.75 seconds |
| Started | Oct 12 02:57:00 PM UTC 24 |
| Finished | Oct 12 02:58:04 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867130303 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.867130303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/17.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_zero_delays.1639153653 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 82436452 ps |
| CPU time | 3.02 seconds |
| Started | Oct 12 02:56:57 PM UTC 24 |
| Finished | Oct 12 02:57:01 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639153653 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.1639153653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/17.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_same_source.1975522427 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 25129327 ps |
| CPU time | 2.68 seconds |
| Started | Oct 12 02:57:03 PM UTC 24 |
| Finished | Oct 12 02:57:07 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975522427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.1975522427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/17.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke.3752128629 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 10042679 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:56:54 PM UTC 24 |
| Finished | Oct 12 02:56:56 PM UTC 24 |
| Peak memory | 209864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752128629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3752128629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/17.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_large_delays.4088619391 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 4303599763 ps |
| CPU time | 14.45 seconds |
| Started | Oct 12 02:56:56 PM UTC 24 |
| Finished | Oct 12 02:57:11 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088619391 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.4088619391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/17.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.2704901964 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 2149390516 ps |
| CPU time | 16.34 seconds |
| Started | Oct 12 02:56:56 PM UTC 24 |
| Finished | Oct 12 02:57:13 PM UTC 24 |
| Peak memory | 213060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704901964 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2704901964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.1368469775 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 9665753 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 02:56:56 PM UTC 24 |
| Finished | Oct 12 02:56:58 PM UTC 24 |
| Peak memory | 211968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368469775 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.1368469775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/17.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all.3034135806 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2629392414 ps |
| CPU time | 16.31 seconds |
| Started | Oct 12 02:57:08 PM UTC 24 |
| Finished | Oct 12 02:57:25 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034135806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3034135806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/17.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_error.3532117785 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 2635680058 ps |
| CPU time | 47.47 seconds |
| Started | Oct 12 02:57:09 PM UTC 24 |
| Finished | Oct 12 02:57:59 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532117785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3532117785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/17.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_unmapped_addr.2743000649 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 49691653 ps |
| CPU time | 3.28 seconds |
| Started | Oct 12 02:57:04 PM UTC 24 |
| Finished | Oct 12 02:57:09 PM UTC 24 |
| Peak memory | 212920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743000649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2743000649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/17.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device.179649266 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 300461037 ps |
| CPU time | 9.06 seconds |
| Started | Oct 12 02:57:19 PM UTC 24 |
| Finished | Oct 12 02:57:29 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179649266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.179649266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/18.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.3650608289 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 5648879147 ps |
| CPU time | 24.73 seconds |
| Started | Oct 12 02:57:20 PM UTC 24 |
| Finished | Oct 12 02:57:46 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650608289 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.3650608289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.1484815609 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 75820870 ps |
| CPU time | 1.69 seconds |
| Started | Oct 12 02:57:26 PM UTC 24 |
| Finished | Oct 12 02:57:29 PM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484815609 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.1484815609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_error_random.2935679390 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 9736037 ps |
| CPU time | 1.72 seconds |
| Started | Oct 12 02:57:24 PM UTC 24 |
| Finished | Oct 12 02:57:26 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935679390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.2935679390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/18.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random.768785353 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 690172671 ps |
| CPU time | 5.4 seconds |
| Started | Oct 12 02:57:12 PM UTC 24 |
| Finished | Oct 12 02:57:19 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768785353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.768785353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/18.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_large_delays.1582420379 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 9833008483 ps |
| CPU time | 46.69 seconds |
| Started | Oct 12 02:57:14 PM UTC 24 |
| Finished | Oct 12 02:58:02 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582420379 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.1582420379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/18.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_slow_rsp.965764215 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1098572153 ps |
| CPU time | 16.09 seconds |
| Started | Oct 12 02:57:15 PM UTC 24 |
| Finished | Oct 12 02:57:32 PM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965764215 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.965764215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/18.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_zero_delays.2891442334 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 266447320 ps |
| CPU time | 8.82 seconds |
| Started | Oct 12 02:57:12 PM UTC 24 |
| Finished | Oct 12 02:57:22 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891442334 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.2891442334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/18.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_same_source.2357913908 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 70135695 ps |
| CPU time | 4.81 seconds |
| Started | Oct 12 02:57:21 PM UTC 24 |
| Finished | Oct 12 02:57:27 PM UTC 24 |
| Peak memory | 212988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357913908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2357913908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/18.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke.2069363137 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 9516185 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 02:57:10 PM UTC 24 |
| Finished | Oct 12 02:57:12 PM UTC 24 |
| Peak memory | 209864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069363137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.2069363137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/18.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_large_delays.2462491645 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1760974472 ps |
| CPU time | 16.02 seconds |
| Started | Oct 12 02:57:12 PM UTC 24 |
| Finished | Oct 12 02:57:29 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462491645 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.2462491645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/18.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.2858564779 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 6737508350 ps |
| CPU time | 12.85 seconds |
| Started | Oct 12 02:57:12 PM UTC 24 |
| Finished | Oct 12 02:57:26 PM UTC 24 |
| Peak memory | 212992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858564779 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2858564779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.3892443495 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 8063871 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 02:57:11 PM UTC 24 |
| Finished | Oct 12 02:57:13 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892443495 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.3892443495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/18.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all.1830438308 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 10509533682 ps |
| CPU time | 55.49 seconds |
| Started | Oct 12 02:57:27 PM UTC 24 |
| Finished | Oct 12 02:58:24 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830438308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.1830438308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/18.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1044570562 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 819265948 ps |
| CPU time | 63.12 seconds |
| Started | Oct 12 02:57:29 PM UTC 24 |
| Finished | Oct 12 02:58:33 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044570562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1044570562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/18.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.2995024313 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 732213843 ps |
| CPU time | 48.38 seconds |
| Started | Oct 12 02:57:27 PM UTC 24 |
| Finished | Oct 12 02:58:17 PM UTC 24 |
| Peak memory | 215012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995024313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.2995024313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.1664364780 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 5080460971 ps |
| CPU time | 134.3 seconds |
| Started | Oct 12 02:57:30 PM UTC 24 |
| Finished | Oct 12 02:59:47 PM UTC 24 |
| Peak memory | 217136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664364780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.1664364780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_unmapped_addr.3308705183 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 80043806 ps |
| CPU time | 8.06 seconds |
| Started | Oct 12 02:57:24 PM UTC 24 |
| Finished | Oct 12 02:57:33 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308705183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3308705183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/18.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device.2034546969 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 5478702490 ps |
| CPU time | 19.74 seconds |
| Started | Oct 12 02:57:35 PM UTC 24 |
| Finished | Oct 12 02:57:56 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034546969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.2034546969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/19.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.905382210 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 23700652 ps |
| CPU time | 2.59 seconds |
| Started | Oct 12 02:57:41 PM UTC 24 |
| Finished | Oct 12 02:57:45 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905382210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.905382210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_error_random.1625078781 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 132405445 ps |
| CPU time | 9.08 seconds |
| Started | Oct 12 02:57:39 PM UTC 24 |
| Finished | Oct 12 02:57:49 PM UTC 24 |
| Peak memory | 213000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625078781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1625078781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/19.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random.1020458194 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 815285689 ps |
| CPU time | 14.5 seconds |
| Started | Oct 12 02:57:34 PM UTC 24 |
| Finished | Oct 12 02:57:49 PM UTC 24 |
| Peak memory | 212896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020458194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.1020458194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/19.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_large_delays.1489621342 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 19782941102 ps |
| CPU time | 98.17 seconds |
| Started | Oct 12 02:57:34 PM UTC 24 |
| Finished | Oct 12 02:59:14 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489621342 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1489621342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/19.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_slow_rsp.3488864399 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 2369063583 ps |
| CPU time | 13.22 seconds |
| Started | Oct 12 02:57:34 PM UTC 24 |
| Finished | Oct 12 02:57:48 PM UTC 24 |
| Peak memory | 213016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488864399 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.3488864399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/19.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_zero_delays.4198361663 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 36692211 ps |
| CPU time | 3.08 seconds |
| Started | Oct 12 02:57:34 PM UTC 24 |
| Finished | Oct 12 02:57:38 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198361663 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.4198361663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/19.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_same_source.3910516961 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 98058313 ps |
| CPU time | 5.25 seconds |
| Started | Oct 12 02:57:38 PM UTC 24 |
| Finished | Oct 12 02:57:44 PM UTC 24 |
| Peak memory | 213000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910516961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3910516961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/19.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke.4264021374 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 41417739 ps |
| CPU time | 1.86 seconds |
| Started | Oct 12 02:57:30 PM UTC 24 |
| Finished | Oct 12 02:57:33 PM UTC 24 |
| Peak memory | 209864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264021374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.4264021374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/19.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_large_delays.1057924017 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 3133097594 ps |
| CPU time | 8.87 seconds |
| Started | Oct 12 02:57:32 PM UTC 24 |
| Finished | Oct 12 02:57:42 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057924017 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.1057924017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/19.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.1926800163 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 1010985101 ps |
| CPU time | 8.76 seconds |
| Started | Oct 12 02:57:32 PM UTC 24 |
| Finished | Oct 12 02:57:42 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926800163 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1926800163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.3453150089 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 8164379 ps |
| CPU time | 1.57 seconds |
| Started | Oct 12 02:57:32 PM UTC 24 |
| Finished | Oct 12 02:57:34 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453150089 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.3453150089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/19.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all.215936877 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 214516763 ps |
| CPU time | 16.27 seconds |
| Started | Oct 12 02:57:43 PM UTC 24 |
| Finished | Oct 12 02:58:01 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215936877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.215936877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/19.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_error.3795330119 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 274440579 ps |
| CPU time | 7.1 seconds |
| Started | Oct 12 02:57:43 PM UTC 24 |
| Finished | Oct 12 02:57:52 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795330119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3795330119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/19.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.3562582157 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 326340836 ps |
| CPU time | 41.14 seconds |
| Started | Oct 12 02:57:43 PM UTC 24 |
| Finished | Oct 12 02:58:26 PM UTC 24 |
| Peak memory | 215016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562582157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.3562582157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.3258361281 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 443950647 ps |
| CPU time | 62.71 seconds |
| Started | Oct 12 02:57:43 PM UTC 24 |
| Finished | Oct 12 02:58:48 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258361281 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.3258361281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_unmapped_addr.2334546445 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 127281196 ps |
| CPU time | 6.49 seconds |
| Started | Oct 12 02:57:39 PM UTC 24 |
| Finished | Oct 12 02:57:47 PM UTC 24 |
| Peak memory | 212952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334546445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.2334546445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/19.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.2139716015 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 78710401826 ps |
| CPU time | 86.22 seconds |
| Started | Oct 12 02:52:49 PM UTC 24 |
| Finished | Oct 12 02:54:17 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139716015 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.2139716015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.1264598951 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 58660299 ps |
| CPU time | 3.32 seconds |
| Started | Oct 12 02:53:01 PM UTC 24 |
| Finished | Oct 12 02:53:05 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264598951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.1264598951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_error_random.3312363176 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 8635196 ps |
| CPU time | 1.69 seconds |
| Started | Oct 12 02:52:57 PM UTC 24 |
| Finished | Oct 12 02:53:00 PM UTC 24 |
| Peak memory | 211956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312363176 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3312363176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/2.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random.1309159169 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 681039920 ps |
| CPU time | 13.98 seconds |
| Started | Oct 12 02:52:46 PM UTC 24 |
| Finished | Oct 12 02:53:01 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309159169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.1309159169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/2.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_large_delays.2195155409 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 13965574576 ps |
| CPU time | 48.77 seconds |
| Started | Oct 12 02:52:47 PM UTC 24 |
| Finished | Oct 12 02:53:37 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195155409 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2195155409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/2.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_slow_rsp.201380248 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 16539200612 ps |
| CPU time | 32.29 seconds |
| Started | Oct 12 02:52:48 PM UTC 24 |
| Finished | Oct 12 02:53:22 PM UTC 24 |
| Peak memory | 213012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201380248 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.201380248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/2.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_zero_delays.3666048000 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 47754411 ps |
| CPU time | 7.04 seconds |
| Started | Oct 12 02:52:47 PM UTC 24 |
| Finished | Oct 12 02:52:55 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666048000 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.3666048000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/2.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_same_source.3531142952 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 49809631 ps |
| CPU time | 8.11 seconds |
| Started | Oct 12 02:52:55 PM UTC 24 |
| Finished | Oct 12 02:53:05 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531142952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3531142952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/2.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke.449750845 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 117801496 ps |
| CPU time | 2.45 seconds |
| Started | Oct 12 02:52:44 PM UTC 24 |
| Finished | Oct 12 02:52:48 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449750845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.449750845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/2.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_large_delays.2319693801 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 13911683854 ps |
| CPU time | 22.75 seconds |
| Started | Oct 12 02:52:46 PM UTC 24 |
| Finished | Oct 12 02:53:10 PM UTC 24 |
| Peak memory | 212996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319693801 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.2319693801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/2.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.1920415528 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 3112213654 ps |
| CPU time | 17.54 seconds |
| Started | Oct 12 02:52:46 PM UTC 24 |
| Finished | Oct 12 02:53:05 PM UTC 24 |
| Peak memory | 213060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920415528 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.1920415528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.3482320289 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 16405968 ps |
| CPU time | 1.51 seconds |
| Started | Oct 12 02:52:46 PM UTC 24 |
| Finished | Oct 12 02:52:48 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482320289 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.3482320289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/2.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all.1696874476 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 883466031 ps |
| CPU time | 36.67 seconds |
| Started | Oct 12 02:53:02 PM UTC 24 |
| Finished | Oct 12 02:53:40 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696874476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.1696874476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/2.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3153638893 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 4174383554 ps |
| CPU time | 34.46 seconds |
| Started | Oct 12 02:53:05 PM UTC 24 |
| Finished | Oct 12 02:53:41 PM UTC 24 |
| Peak memory | 213036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153638893 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3153638893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/2.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.2773613740 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2917658357 ps |
| CPU time | 67.47 seconds |
| Started | Oct 12 02:53:02 PM UTC 24 |
| Finished | Oct 12 02:54:11 PM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773613740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.2773613740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.277732953 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 5383210848 ps |
| CPU time | 97.73 seconds |
| Started | Oct 12 02:53:05 PM UTC 24 |
| Finished | Oct 12 02:54:45 PM UTC 24 |
| Peak memory | 217132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277732953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.277732953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_unmapped_addr.2809903830 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1877776781 ps |
| CPU time | 9.33 seconds |
| Started | Oct 12 02:53:01 PM UTC 24 |
| Finished | Oct 12 02:53:11 PM UTC 24 |
| Peak memory | 212920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809903830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2809903830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/2.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device.87047524 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 67913629 ps |
| CPU time | 9.82 seconds |
| Started | Oct 12 02:57:51 PM UTC 24 |
| Finished | Oct 12 02:58:02 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87047524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.87047524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/20.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.133076730 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 15519066125 ps |
| CPU time | 111.18 seconds |
| Started | Oct 12 02:57:51 PM UTC 24 |
| Finished | Oct 12 02:59:44 PM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133076730 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.133076730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.2016197416 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 51177866 ps |
| CPU time | 5.07 seconds |
| Started | Oct 12 02:57:59 PM UTC 24 |
| Finished | Oct 12 02:58:05 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016197416 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.2016197416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_error_random.3870963571 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1193930797 ps |
| CPU time | 15.9 seconds |
| Started | Oct 12 02:57:54 PM UTC 24 |
| Finished | Oct 12 02:58:12 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870963571 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3870963571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/20.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random.839191219 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 375271977 ps |
| CPU time | 8.51 seconds |
| Started | Oct 12 02:57:48 PM UTC 24 |
| Finished | Oct 12 02:57:58 PM UTC 24 |
| Peak memory | 212936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839191219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.839191219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/20.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_large_delays.4225732972 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 8611973506 ps |
| CPU time | 40.92 seconds |
| Started | Oct 12 02:57:49 PM UTC 24 |
| Finished | Oct 12 02:58:32 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225732972 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.4225732972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/20.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_slow_rsp.3118411089 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 1836744280 ps |
| CPU time | 11.58 seconds |
| Started | Oct 12 02:57:49 PM UTC 24 |
| Finished | Oct 12 02:58:02 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118411089 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3118411089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/20.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_zero_delays.207133598 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 100431579 ps |
| CPU time | 9.58 seconds |
| Started | Oct 12 02:57:48 PM UTC 24 |
| Finished | Oct 12 02:57:59 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207133598 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.207133598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/20.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_same_source.1826705567 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 30983153 ps |
| CPU time | 4.15 seconds |
| Started | Oct 12 02:57:52 PM UTC 24 |
| Finished | Oct 12 02:57:58 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826705567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1826705567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/20.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke.4064277862 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 58664122 ps |
| CPU time | 2.74 seconds |
| Started | Oct 12 02:57:45 PM UTC 24 |
| Finished | Oct 12 02:57:49 PM UTC 24 |
| Peak memory | 212940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064277862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.4064277862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/20.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_large_delays.3020202737 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 3357699220 ps |
| CPU time | 12.67 seconds |
| Started | Oct 12 02:57:46 PM UTC 24 |
| Finished | Oct 12 02:58:00 PM UTC 24 |
| Peak memory | 213016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020202737 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.3020202737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/20.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.1113614559 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1374467362 ps |
| CPU time | 13.37 seconds |
| Started | Oct 12 02:57:48 PM UTC 24 |
| Finished | Oct 12 02:58:02 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113614559 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.1113614559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.788122948 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 8856200 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:57:45 PM UTC 24 |
| Finished | Oct 12 02:57:47 PM UTC 24 |
| Peak memory | 211968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788122948 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.788122948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/20.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all.3595429882 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 249634942 ps |
| CPU time | 3.82 seconds |
| Started | Oct 12 02:57:59 PM UTC 24 |
| Finished | Oct 12 02:58:04 PM UTC 24 |
| Peak memory | 212928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595429882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3595429882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/20.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_error.676197206 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 2092854326 ps |
| CPU time | 32.31 seconds |
| Started | Oct 12 02:58:01 PM UTC 24 |
| Finished | Oct 12 02:58:35 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676197206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.676197206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/20.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.1037359945 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 5630843131 ps |
| CPU time | 147.22 seconds |
| Started | Oct 12 02:58:01 PM UTC 24 |
| Finished | Oct 12 03:00:31 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037359945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.1037359945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.3078990451 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 900741976 ps |
| CPU time | 106.5 seconds |
| Started | Oct 12 02:58:01 PM UTC 24 |
| Finished | Oct 12 02:59:50 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078990451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.3078990451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_unmapped_addr.1943884400 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 137401971 ps |
| CPU time | 3.95 seconds |
| Started | Oct 12 02:57:58 PM UTC 24 |
| Finished | Oct 12 02:58:03 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943884400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1943884400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/20.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device.1733028721 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 1686887826 ps |
| CPU time | 18.38 seconds |
| Started | Oct 12 02:58:07 PM UTC 24 |
| Finished | Oct 12 02:58:27 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733028721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.1733028721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/21.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.344408824 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 89585984 ps |
| CPU time | 5.98 seconds |
| Started | Oct 12 02:58:09 PM UTC 24 |
| Finished | Oct 12 02:58:16 PM UTC 24 |
| Peak memory | 212968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344408824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.344408824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_error_random.2939572510 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 359124064 ps |
| CPU time | 3.18 seconds |
| Started | Oct 12 02:58:07 PM UTC 24 |
| Finished | Oct 12 02:58:11 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939572510 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2939572510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/21.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random.263763848 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 371737132 ps |
| CPU time | 5.57 seconds |
| Started | Oct 12 02:58:05 PM UTC 24 |
| Finished | Oct 12 02:58:12 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263763848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.263763848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/21.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_large_delays.950658353 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 37713058594 ps |
| CPU time | 90.06 seconds |
| Started | Oct 12 02:58:05 PM UTC 24 |
| Finished | Oct 12 02:59:37 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950658353 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.950658353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/21.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_slow_rsp.3006809767 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 19116966509 ps |
| CPU time | 99.01 seconds |
| Started | Oct 12 02:58:05 PM UTC 24 |
| Finished | Oct 12 02:59:46 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006809767 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3006809767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/21.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_zero_delays.1405698322 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 59545958 ps |
| CPU time | 7.88 seconds |
| Started | Oct 12 02:58:05 PM UTC 24 |
| Finished | Oct 12 02:58:14 PM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405698322 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.1405698322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/21.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_same_source.533882519 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 148474522 ps |
| CPU time | 2.84 seconds |
| Started | Oct 12 02:58:07 PM UTC 24 |
| Finished | Oct 12 02:58:11 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533882519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.533882519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/21.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke.4080624778 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 94823086 ps |
| CPU time | 1.9 seconds |
| Started | Oct 12 02:58:03 PM UTC 24 |
| Finished | Oct 12 02:58:05 PM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080624778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.4080624778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/21.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_large_delays.3432897538 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 12017291203 ps |
| CPU time | 12.01 seconds |
| Started | Oct 12 02:58:05 PM UTC 24 |
| Finished | Oct 12 02:58:18 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432897538 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.3432897538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/21.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.968941986 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 2555156354 ps |
| CPU time | 23.09 seconds |
| Started | Oct 12 02:58:05 PM UTC 24 |
| Finished | Oct 12 02:58:29 PM UTC 24 |
| Peak memory | 211028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968941986 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.968941986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.2338082310 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 18388795 ps |
| CPU time | 1.49 seconds |
| Started | Oct 12 02:58:03 PM UTC 24 |
| Finished | Oct 12 02:58:05 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338082310 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.2338082310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/21.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all.1768811348 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 4714682640 ps |
| CPU time | 66.36 seconds |
| Started | Oct 12 02:58:09 PM UTC 24 |
| Finished | Oct 12 02:59:17 PM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768811348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1768811348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/21.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_error.2972353437 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 2981847476 ps |
| CPU time | 35.78 seconds |
| Started | Oct 12 02:58:13 PM UTC 24 |
| Finished | Oct 12 02:58:50 PM UTC 24 |
| Peak memory | 213084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972353437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.2972353437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/21.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.1183365856 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 291772763 ps |
| CPU time | 47.75 seconds |
| Started | Oct 12 02:58:09 PM UTC 24 |
| Finished | Oct 12 02:58:58 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183365856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.1183365856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.2653228342 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 2066034513 ps |
| CPU time | 74.51 seconds |
| Started | Oct 12 02:58:13 PM UTC 24 |
| Finished | Oct 12 02:59:29 PM UTC 24 |
| Peak memory | 212972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653228342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.2653228342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_unmapped_addr.252277804 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 244339516 ps |
| CPU time | 5.33 seconds |
| Started | Oct 12 02:58:09 PM UTC 24 |
| Finished | Oct 12 02:58:16 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252277804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.252277804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/21.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device.3291434111 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 175324795 ps |
| CPU time | 2.48 seconds |
| Started | Oct 12 02:58:19 PM UTC 24 |
| Finished | Oct 12 02:58:23 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291434111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.3291434111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/22.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.3831710401 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 119894917 ps |
| CPU time | 5.01 seconds |
| Started | Oct 12 02:58:26 PM UTC 24 |
| Finished | Oct 12 02:58:32 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831710401 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.3831710401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_error_random.2018654156 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 1164276378 ps |
| CPU time | 11.33 seconds |
| Started | Oct 12 02:58:24 PM UTC 24 |
| Finished | Oct 12 02:58:36 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018654156 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2018654156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/22.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random.2332146860 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 68262843 ps |
| CPU time | 5.1 seconds |
| Started | Oct 12 02:58:17 PM UTC 24 |
| Finished | Oct 12 02:58:23 PM UTC 24 |
| Peak memory | 212936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332146860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.2332146860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/22.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_large_delays.2857413718 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 13363903872 ps |
| CPU time | 75 seconds |
| Started | Oct 12 02:58:19 PM UTC 24 |
| Finished | Oct 12 02:59:36 PM UTC 24 |
| Peak memory | 213080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857413718 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2857413718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/22.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_slow_rsp.1036031255 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 4598559041 ps |
| CPU time | 36.95 seconds |
| Started | Oct 12 02:58:19 PM UTC 24 |
| Finished | Oct 12 02:58:57 PM UTC 24 |
| Peak memory | 213000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036031255 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1036031255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/22.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_zero_delays.4106309896 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 78368146 ps |
| CPU time | 5.68 seconds |
| Started | Oct 12 02:58:19 PM UTC 24 |
| Finished | Oct 12 02:58:26 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106309896 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.4106309896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/22.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_same_source.1158397861 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 21979628 ps |
| CPU time | 2.24 seconds |
| Started | Oct 12 02:58:24 PM UTC 24 |
| Finished | Oct 12 02:58:27 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158397861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1158397861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/22.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke.3445626544 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 224974603 ps |
| CPU time | 1.8 seconds |
| Started | Oct 12 02:58:13 PM UTC 24 |
| Finished | Oct 12 02:58:16 PM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445626544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.3445626544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/22.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_large_delays.2589178780 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 3271407219 ps |
| CPU time | 15.32 seconds |
| Started | Oct 12 02:58:15 PM UTC 24 |
| Finished | Oct 12 02:58:32 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589178780 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.2589178780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/22.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.863608451 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 1940592015 ps |
| CPU time | 10.43 seconds |
| Started | Oct 12 02:58:17 PM UTC 24 |
| Finished | Oct 12 02:58:28 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863608451 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.863608451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.165017350 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 19484519 ps |
| CPU time | 1.83 seconds |
| Started | Oct 12 02:58:14 PM UTC 24 |
| Finished | Oct 12 02:58:17 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165017350 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.165017350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/22.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all.1133014928 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 2975323352 ps |
| CPU time | 31.65 seconds |
| Started | Oct 12 02:58:28 PM UTC 24 |
| Finished | Oct 12 02:59:01 PM UTC 24 |
| Peak memory | 213004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133014928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.1133014928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/22.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_error.529442289 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 351017164 ps |
| CPU time | 2 seconds |
| Started | Oct 12 02:58:28 PM UTC 24 |
| Finished | Oct 12 02:58:31 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529442289 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.529442289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/22.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.395635242 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 1006794396 ps |
| CPU time | 55.21 seconds |
| Started | Oct 12 02:58:28 PM UTC 24 |
| Finished | Oct 12 02:59:25 PM UTC 24 |
| Peak memory | 215016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395635242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.395635242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.1788015729 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 3078408807 ps |
| CPU time | 45.32 seconds |
| Started | Oct 12 02:58:29 PM UTC 24 |
| Finished | Oct 12 02:59:16 PM UTC 24 |
| Peak memory | 213104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788015729 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.1788015729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_unmapped_addr.1665806042 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 251939847 ps |
| CPU time | 6.59 seconds |
| Started | Oct 12 02:58:25 PM UTC 24 |
| Finished | Oct 12 02:58:33 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665806042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.1665806042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/22.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device.3798810987 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 55490688 ps |
| CPU time | 13.87 seconds |
| Started | Oct 12 02:58:36 PM UTC 24 |
| Finished | Oct 12 02:58:51 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798810987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.3798810987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/23.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.3904562610 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 15194589042 ps |
| CPU time | 108.46 seconds |
| Started | Oct 12 02:58:36 PM UTC 24 |
| Finished | Oct 12 03:00:27 PM UTC 24 |
| Peak memory | 213016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904562610 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.3904562610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.3770029280 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 190017109 ps |
| CPU time | 1.71 seconds |
| Started | Oct 12 02:58:38 PM UTC 24 |
| Finished | Oct 12 02:58:41 PM UTC 24 |
| Peak memory | 211972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770029280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.3770029280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_error_random.975987604 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 1595066227 ps |
| CPU time | 8.14 seconds |
| Started | Oct 12 02:58:36 PM UTC 24 |
| Finished | Oct 12 02:58:45 PM UTC 24 |
| Peak memory | 212928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975987604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.975987604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/23.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random.2879829585 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 23917224 ps |
| CPU time | 2.93 seconds |
| Started | Oct 12 02:58:34 PM UTC 24 |
| Finished | Oct 12 02:58:38 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879829585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.2879829585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/23.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_large_delays.714466611 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 70616973868 ps |
| CPU time | 140.7 seconds |
| Started | Oct 12 02:58:34 PM UTC 24 |
| Finished | Oct 12 03:00:57 PM UTC 24 |
| Peak memory | 213020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714466611 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.714466611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/23.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_slow_rsp.3302437849 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 1283796856 ps |
| CPU time | 11.43 seconds |
| Started | Oct 12 02:58:34 PM UTC 24 |
| Finished | Oct 12 02:58:47 PM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302437849 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3302437849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/23.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_zero_delays.3159809339 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 60994772 ps |
| CPU time | 9.8 seconds |
| Started | Oct 12 02:58:34 PM UTC 24 |
| Finished | Oct 12 02:58:45 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159809339 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.3159809339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/23.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_same_source.3735109875 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 20947855 ps |
| CPU time | 2.02 seconds |
| Started | Oct 12 02:58:36 PM UTC 24 |
| Finished | Oct 12 02:58:39 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735109875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3735109875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/23.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke.3023848490 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 27369636 ps |
| CPU time | 1.75 seconds |
| Started | Oct 12 02:58:30 PM UTC 24 |
| Finished | Oct 12 02:58:33 PM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023848490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.3023848490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/23.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_large_delays.1447231863 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 6687852827 ps |
| CPU time | 15.91 seconds |
| Started | Oct 12 02:58:34 PM UTC 24 |
| Finished | Oct 12 02:58:51 PM UTC 24 |
| Peak memory | 212992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447231863 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.1447231863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/23.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.1839691121 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 5449564131 ps |
| CPU time | 13.66 seconds |
| Started | Oct 12 02:58:34 PM UTC 24 |
| Finished | Oct 12 02:58:49 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839691121 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.1839691121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.1305981937 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 18744003 ps |
| CPU time | 1.79 seconds |
| Started | Oct 12 02:58:32 PM UTC 24 |
| Finished | Oct 12 02:58:34 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305981937 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.1305981937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/23.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all.1989200179 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 1303848361 ps |
| CPU time | 19.15 seconds |
| Started | Oct 12 02:58:38 PM UTC 24 |
| Finished | Oct 12 02:58:58 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989200179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1989200179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/23.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_error.4162324561 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 3077264172 ps |
| CPU time | 44.58 seconds |
| Started | Oct 12 02:58:40 PM UTC 24 |
| Finished | Oct 12 02:59:27 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162324561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.4162324561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/23.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.3719848022 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 527441396 ps |
| CPU time | 65.34 seconds |
| Started | Oct 12 02:58:39 PM UTC 24 |
| Finished | Oct 12 02:59:46 PM UTC 24 |
| Peak memory | 215008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719848022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.3719848022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.452088394 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 439966262 ps |
| CPU time | 44.99 seconds |
| Started | Oct 12 02:58:42 PM UTC 24 |
| Finished | Oct 12 02:59:28 PM UTC 24 |
| Peak memory | 212968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452088394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.452088394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_unmapped_addr.3258497459 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 771001817 ps |
| CPU time | 11.36 seconds |
| Started | Oct 12 02:58:36 PM UTC 24 |
| Finished | Oct 12 02:58:49 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258497459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.3258497459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/23.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device.2220102239 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 4551870692 ps |
| CPU time | 15.65 seconds |
| Started | Oct 12 02:58:51 PM UTC 24 |
| Finished | Oct 12 02:59:08 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220102239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.2220102239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/24.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.3768006419 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 15190574597 ps |
| CPU time | 49.95 seconds |
| Started | Oct 12 02:58:52 PM UTC 24 |
| Finished | Oct 12 02:59:44 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768006419 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.3768006419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.2029452688 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 289956752 ps |
| CPU time | 8.92 seconds |
| Started | Oct 12 02:58:58 PM UTC 24 |
| Finished | Oct 12 02:59:08 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029452688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.2029452688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_error_random.3833100857 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 48927802 ps |
| CPU time | 5.26 seconds |
| Started | Oct 12 02:58:53 PM UTC 24 |
| Finished | Oct 12 02:58:59 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833100857 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3833100857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/24.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random.1012859719 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 86089945 ps |
| CPU time | 7.1 seconds |
| Started | Oct 12 02:58:49 PM UTC 24 |
| Finished | Oct 12 02:58:57 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012859719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.1012859719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/24.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_large_delays.1633327763 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 27739149786 ps |
| CPU time | 81.31 seconds |
| Started | Oct 12 02:58:51 PM UTC 24 |
| Finished | Oct 12 03:00:14 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633327763 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1633327763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/24.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_slow_rsp.2508378310 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 9471323912 ps |
| CPU time | 69.01 seconds |
| Started | Oct 12 02:58:51 PM UTC 24 |
| Finished | Oct 12 03:00:02 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508378310 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2508378310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/24.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_zero_delays.2376068860 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 127812509 ps |
| CPU time | 3.94 seconds |
| Started | Oct 12 02:58:51 PM UTC 24 |
| Finished | Oct 12 02:58:56 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376068860 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.2376068860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/24.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_same_source.3046304154 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 6487361213 ps |
| CPU time | 17.64 seconds |
| Started | Oct 12 02:58:53 PM UTC 24 |
| Finished | Oct 12 02:59:11 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046304154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3046304154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/24.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke.3389883553 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 84087671 ps |
| CPU time | 1.9 seconds |
| Started | Oct 12 02:58:46 PM UTC 24 |
| Finished | Oct 12 02:58:49 PM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389883553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3389883553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/24.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_large_delays.2810152370 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 5239289598 ps |
| CPU time | 24.75 seconds |
| Started | Oct 12 02:58:48 PM UTC 24 |
| Finished | Oct 12 02:59:14 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810152370 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.2810152370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/24.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.142689360 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 1216623103 ps |
| CPU time | 12.73 seconds |
| Started | Oct 12 02:58:49 PM UTC 24 |
| Finished | Oct 12 02:59:03 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142689360 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.142689360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.292867147 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 9054048 ps |
| CPU time | 1.69 seconds |
| Started | Oct 12 02:58:46 PM UTC 24 |
| Finished | Oct 12 02:58:49 PM UTC 24 |
| Peak memory | 211960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292867147 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.292867147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/24.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all.65415300 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 5951257384 ps |
| CPU time | 67.88 seconds |
| Started | Oct 12 02:58:58 PM UTC 24 |
| Finished | Oct 12 03:00:08 PM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65415300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-si m-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.65415300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/24.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_error.2256816177 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 7160400457 ps |
| CPU time | 63.63 seconds |
| Started | Oct 12 02:59:00 PM UTC 24 |
| Finished | Oct 12 03:00:05 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256816177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2256816177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/24.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.974452280 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 477199554 ps |
| CPU time | 73.22 seconds |
| Started | Oct 12 02:59:00 PM UTC 24 |
| Finished | Oct 12 03:00:15 PM UTC 24 |
| Peak memory | 215016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974452280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.974452280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.140249455 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 955996497 ps |
| CPU time | 83.51 seconds |
| Started | Oct 12 02:59:00 PM UTC 24 |
| Finished | Oct 12 03:00:25 PM UTC 24 |
| Peak memory | 212956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140249455 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.140249455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_unmapped_addr.200535182 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 719004788 ps |
| CPU time | 9.56 seconds |
| Started | Oct 12 02:58:57 PM UTC 24 |
| Finished | Oct 12 02:59:07 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200535182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.200535182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/24.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device.1874489488 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 78555858 ps |
| CPU time | 7.18 seconds |
| Started | Oct 12 02:59:14 PM UTC 24 |
| Finished | Oct 12 02:59:22 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874489488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.1874489488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/25.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.3161683208 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 16119124635 ps |
| CPU time | 126.55 seconds |
| Started | Oct 12 02:59:15 PM UTC 24 |
| Finished | Oct 12 03:01:24 PM UTC 24 |
| Peak memory | 214564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161683208 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.3161683208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.2791111231 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 562060441 ps |
| CPU time | 8.15 seconds |
| Started | Oct 12 02:59:18 PM UTC 24 |
| Finished | Oct 12 02:59:28 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791111231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.2791111231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_error_random.1382780008 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 9317746 ps |
| CPU time | 1.75 seconds |
| Started | Oct 12 02:59:18 PM UTC 24 |
| Finished | Oct 12 02:59:21 PM UTC 24 |
| Peak memory | 211948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382780008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.1382780008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/25.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random.3540127731 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 91068998 ps |
| CPU time | 7.35 seconds |
| Started | Oct 12 02:59:08 PM UTC 24 |
| Finished | Oct 12 02:59:17 PM UTC 24 |
| Peak memory | 210888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540127731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.3540127731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/25.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_large_delays.3953954271 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 8445012545 ps |
| CPU time | 17.88 seconds |
| Started | Oct 12 02:59:10 PM UTC 24 |
| Finished | Oct 12 02:59:29 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953954271 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.3953954271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/25.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_slow_rsp.699649400 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 32618240656 ps |
| CPU time | 35.27 seconds |
| Started | Oct 12 02:59:12 PM UTC 24 |
| Finished | Oct 12 02:59:49 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699649400 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.699649400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/25.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_zero_delays.3221566524 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 63374239 ps |
| CPU time | 6.87 seconds |
| Started | Oct 12 02:59:10 PM UTC 24 |
| Finished | Oct 12 02:59:18 PM UTC 24 |
| Peak memory | 212956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221566524 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.3221566524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/25.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_same_source.3352279539 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 137484852 ps |
| CPU time | 8.03 seconds |
| Started | Oct 12 02:59:17 PM UTC 24 |
| Finished | Oct 12 02:59:26 PM UTC 24 |
| Peak memory | 212944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352279539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3352279539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/25.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke.2792806985 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 64327908 ps |
| CPU time | 2.58 seconds |
| Started | Oct 12 02:59:02 PM UTC 24 |
| Finished | Oct 12 02:59:06 PM UTC 24 |
| Peak memory | 212916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792806985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.2792806985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/25.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_large_delays.137926690 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 1241367184 ps |
| CPU time | 11.34 seconds |
| Started | Oct 12 02:59:07 PM UTC 24 |
| Finished | Oct 12 02:59:19 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137926690 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.137926690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/25.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.1319387030 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 654798710 ps |
| CPU time | 9.8 seconds |
| Started | Oct 12 02:59:07 PM UTC 24 |
| Finished | Oct 12 02:59:18 PM UTC 24 |
| Peak memory | 212932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319387030 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.1319387030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.1686478566 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 13261011 ps |
| CPU time | 1.73 seconds |
| Started | Oct 12 02:59:03 PM UTC 24 |
| Finished | Oct 12 02:59:06 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686478566 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.1686478566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/25.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all.3374160133 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 1016756870 ps |
| CPU time | 16.42 seconds |
| Started | Oct 12 02:59:20 PM UTC 24 |
| Finished | Oct 12 02:59:37 PM UTC 24 |
| Peak memory | 212944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374160133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.3374160133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/25.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_error.3951699474 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 3537040889 ps |
| CPU time | 29.28 seconds |
| Started | Oct 12 02:59:22 PM UTC 24 |
| Finished | Oct 12 02:59:53 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951699474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.3951699474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/25.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.1682625757 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 12057864726 ps |
| CPU time | 107.69 seconds |
| Started | Oct 12 02:59:23 PM UTC 24 |
| Finished | Oct 12 03:01:13 PM UTC 24 |
| Peak memory | 217200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682625757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.1682625757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_unmapped_addr.3395945729 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 40175726 ps |
| CPU time | 4.31 seconds |
| Started | Oct 12 02:59:18 PM UTC 24 |
| Finished | Oct 12 02:59:24 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395945729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3395945729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/25.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device.3466052580 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 807774552 ps |
| CPU time | 16.39 seconds |
| Started | Oct 12 02:59:30 PM UTC 24 |
| Finished | Oct 12 02:59:47 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466052580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.3466052580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/26.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.2765571752 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 15225222004 ps |
| CPU time | 66.81 seconds |
| Started | Oct 12 02:59:32 PM UTC 24 |
| Finished | Oct 12 03:00:40 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765571752 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.2765571752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.2739381473 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 130899715 ps |
| CPU time | 4.24 seconds |
| Started | Oct 12 02:59:36 PM UTC 24 |
| Finished | Oct 12 02:59:42 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739381473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.2739381473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_error_random.3794717304 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 498721511 ps |
| CPU time | 8.41 seconds |
| Started | Oct 12 02:59:32 PM UTC 24 |
| Finished | Oct 12 02:59:41 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794717304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3794717304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/26.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random.3115955756 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 55081527 ps |
| CPU time | 7.5 seconds |
| Started | Oct 12 02:59:30 PM UTC 24 |
| Finished | Oct 12 02:59:38 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115955756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.3115955756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/26.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_large_delays.3118283745 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 33860698765 ps |
| CPU time | 116.54 seconds |
| Started | Oct 12 02:59:30 PM UTC 24 |
| Finished | Oct 12 03:01:28 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118283745 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.3118283745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/26.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_slow_rsp.372579056 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 10991609790 ps |
| CPU time | 24.88 seconds |
| Started | Oct 12 02:59:30 PM UTC 24 |
| Finished | Oct 12 02:59:56 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372579056 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.372579056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/26.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_zero_delays.1770453140 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 69327847 ps |
| CPU time | 3.81 seconds |
| Started | Oct 12 02:59:30 PM UTC 24 |
| Finished | Oct 12 02:59:35 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770453140 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.1770453140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/26.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_same_source.551987646 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 16718064 ps |
| CPU time | 2.82 seconds |
| Started | Oct 12 02:59:32 PM UTC 24 |
| Finished | Oct 12 02:59:36 PM UTC 24 |
| Peak memory | 212980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551987646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.551987646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/26.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke.3554709613 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 71642527 ps |
| CPU time | 2.38 seconds |
| Started | Oct 12 02:59:25 PM UTC 24 |
| Finished | Oct 12 02:59:28 PM UTC 24 |
| Peak memory | 212996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554709613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.3554709613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/26.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_large_delays.3919565986 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 4585533219 ps |
| CPU time | 10.86 seconds |
| Started | Oct 12 02:59:27 PM UTC 24 |
| Finished | Oct 12 02:59:40 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919565986 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3919565986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/26.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.2349160693 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 5016651997 ps |
| CPU time | 6.77 seconds |
| Started | Oct 12 02:59:27 PM UTC 24 |
| Finished | Oct 12 02:59:36 PM UTC 24 |
| Peak memory | 210956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349160693 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.2349160693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.1260129022 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 19988750 ps |
| CPU time | 1.77 seconds |
| Started | Oct 12 02:59:26 PM UTC 24 |
| Finished | Oct 12 02:59:29 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260129022 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.1260129022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/26.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all.2327301197 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 1159139061 ps |
| CPU time | 27.28 seconds |
| Started | Oct 12 02:59:39 PM UTC 24 |
| Finished | Oct 12 03:00:08 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327301197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2327301197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/26.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_error.3152828886 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 1115885468 ps |
| CPU time | 32.98 seconds |
| Started | Oct 12 02:59:39 PM UTC 24 |
| Finished | Oct 12 03:00:14 PM UTC 24 |
| Peak memory | 213012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152828886 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.3152828886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/26.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.322973973 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 97817218 ps |
| CPU time | 21.88 seconds |
| Started | Oct 12 02:59:39 PM UTC 24 |
| Finished | Oct 12 03:00:02 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322973973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.322973973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.863862286 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 1446769471 ps |
| CPU time | 75.83 seconds |
| Started | Oct 12 02:59:39 PM UTC 24 |
| Finished | Oct 12 03:00:57 PM UTC 24 |
| Peak memory | 217064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863862286 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.863862286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_unmapped_addr.2867207244 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 918584689 ps |
| CPU time | 10.98 seconds |
| Started | Oct 12 02:59:36 PM UTC 24 |
| Finished | Oct 12 02:59:49 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867207244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2867207244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/26.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device.2943990494 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 55813760 ps |
| CPU time | 11.37 seconds |
| Started | Oct 12 02:59:45 PM UTC 24 |
| Finished | Oct 12 02:59:58 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943990494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.2943990494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/27.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.888449607 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 8261037567 ps |
| CPU time | 60.03 seconds |
| Started | Oct 12 02:59:48 PM UTC 24 |
| Finished | Oct 12 03:00:50 PM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888449607 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.888449607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.3111546884 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 1312663423 ps |
| CPU time | 8.52 seconds |
| Started | Oct 12 02:59:49 PM UTC 24 |
| Finished | Oct 12 02:59:58 PM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111546884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.3111546884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_error_random.2125552029 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 15211647 ps |
| CPU time | 2.4 seconds |
| Started | Oct 12 02:59:48 PM UTC 24 |
| Finished | Oct 12 02:59:52 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125552029 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2125552029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/27.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random.975000663 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 235306349 ps |
| CPU time | 2.77 seconds |
| Started | Oct 12 02:59:44 PM UTC 24 |
| Finished | Oct 12 02:59:48 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975000663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.975000663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/27.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_large_delays.3150747509 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 58920147918 ps |
| CPU time | 87.74 seconds |
| Started | Oct 12 02:59:44 PM UTC 24 |
| Finished | Oct 12 03:01:14 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150747509 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.3150747509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/27.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_slow_rsp.3845671198 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 8894880361 ps |
| CPU time | 65.78 seconds |
| Started | Oct 12 02:59:45 PM UTC 24 |
| Finished | Oct 12 03:00:53 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845671198 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3845671198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/27.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_zero_delays.3074209566 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 93346375 ps |
| CPU time | 8.46 seconds |
| Started | Oct 12 02:59:44 PM UTC 24 |
| Finished | Oct 12 02:59:54 PM UTC 24 |
| Peak memory | 213048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074209566 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.3074209566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/27.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_same_source.1161173922 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 903649542 ps |
| CPU time | 13.32 seconds |
| Started | Oct 12 02:59:48 PM UTC 24 |
| Finished | Oct 12 03:00:03 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161173922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1161173922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/27.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke.779131812 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 22290230 ps |
| CPU time | 1.71 seconds |
| Started | Oct 12 02:59:39 PM UTC 24 |
| Finished | Oct 12 02:59:42 PM UTC 24 |
| Peak memory | 211960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779131812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.779131812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/27.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_large_delays.758913948 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1965052007 ps |
| CPU time | 14.27 seconds |
| Started | Oct 12 02:59:41 PM UTC 24 |
| Finished | Oct 12 02:59:56 PM UTC 24 |
| Peak memory | 212952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758913948 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.758913948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/27.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.1124626407 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 7547759562 ps |
| CPU time | 9.18 seconds |
| Started | Oct 12 02:59:42 PM UTC 24 |
| Finished | Oct 12 02:59:52 PM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124626407 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.1124626407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.421323109 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 9382938 ps |
| CPU time | 1.74 seconds |
| Started | Oct 12 02:59:39 PM UTC 24 |
| Finished | Oct 12 02:59:42 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421323109 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.421323109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/27.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all.2183666380 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 38200169064 ps |
| CPU time | 81.84 seconds |
| Started | Oct 12 02:59:50 PM UTC 24 |
| Finished | Oct 12 03:01:14 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183666380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2183666380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/27.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_error.3573544783 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 1827597793 ps |
| CPU time | 30.11 seconds |
| Started | Oct 12 02:59:52 PM UTC 24 |
| Finished | Oct 12 03:00:23 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573544783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3573544783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/27.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.3398742209 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 675188337 ps |
| CPU time | 143.58 seconds |
| Started | Oct 12 02:59:50 PM UTC 24 |
| Finished | Oct 12 03:02:16 PM UTC 24 |
| Peak memory | 218600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398742209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.3398742209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.2694518739 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 88943107 ps |
| CPU time | 8.92 seconds |
| Started | Oct 12 02:59:53 PM UTC 24 |
| Finished | Oct 12 03:00:03 PM UTC 24 |
| Peak memory | 210928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694518739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.2694518739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_unmapped_addr.3688689966 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 1006456331 ps |
| CPU time | 8.36 seconds |
| Started | Oct 12 02:59:49 PM UTC 24 |
| Finished | Oct 12 02:59:58 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688689966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3688689966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/27.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device.3985910012 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 178587184 ps |
| CPU time | 10.85 seconds |
| Started | Oct 12 03:00:00 PM UTC 24 |
| Finished | Oct 12 03:00:12 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985910012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.3985910012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/28.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2299897036 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 13325496980 ps |
| CPU time | 65.44 seconds |
| Started | Oct 12 03:00:00 PM UTC 24 |
| Finished | Oct 12 03:01:07 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299897036 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.2299897036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.2333861573 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 46722204 ps |
| CPU time | 2.81 seconds |
| Started | Oct 12 03:00:08 PM UTC 24 |
| Finished | Oct 12 03:00:12 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333861573 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.2333861573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_error_random.1974989942 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 3650595395 ps |
| CPU time | 11.73 seconds |
| Started | Oct 12 03:00:08 PM UTC 24 |
| Finished | Oct 12 03:00:21 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974989942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.1974989942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/28.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random.4164564079 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 279775676 ps |
| CPU time | 3.79 seconds |
| Started | Oct 12 02:59:58 PM UTC 24 |
| Finished | Oct 12 03:00:03 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164564079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.4164564079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/28.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_large_delays.3944239841 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 21807311178 ps |
| CPU time | 108.73 seconds |
| Started | Oct 12 02:59:58 PM UTC 24 |
| Finished | Oct 12 03:01:49 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944239841 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.3944239841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/28.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_slow_rsp.4074039870 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 2480008499 ps |
| CPU time | 6.91 seconds |
| Started | Oct 12 03:00:00 PM UTC 24 |
| Finished | Oct 12 03:00:08 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074039870 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.4074039870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/28.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_zero_delays.1590806484 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 211859601 ps |
| CPU time | 5.71 seconds |
| Started | Oct 12 02:59:58 PM UTC 24 |
| Finished | Oct 12 03:00:05 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590806484 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.1590806484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/28.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_same_source.1654680688 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 44733622 ps |
| CPU time | 4.36 seconds |
| Started | Oct 12 03:00:02 PM UTC 24 |
| Finished | Oct 12 03:00:11 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654680688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1654680688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/28.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke.2197951712 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 19038581 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 02:59:53 PM UTC 24 |
| Finished | Oct 12 02:59:55 PM UTC 24 |
| Peak memory | 209864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197951712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.2197951712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/28.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_large_delays.3554662288 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 2535310872 ps |
| CPU time | 13.17 seconds |
| Started | Oct 12 02:59:55 PM UTC 24 |
| Finished | Oct 12 03:00:09 PM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554662288 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.3554662288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/28.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.2089548644 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 756192706 ps |
| CPU time | 12.19 seconds |
| Started | Oct 12 02:59:56 PM UTC 24 |
| Finished | Oct 12 03:00:09 PM UTC 24 |
| Peak memory | 213020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089548644 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.2089548644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.1003395059 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 9119434 ps |
| CPU time | 1.61 seconds |
| Started | Oct 12 02:59:55 PM UTC 24 |
| Finished | Oct 12 02:59:57 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003395059 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.1003395059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/28.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all.4161065927 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 11910715622 ps |
| CPU time | 49.4 seconds |
| Started | Oct 12 03:00:08 PM UTC 24 |
| Finished | Oct 12 03:00:59 PM UTC 24 |
| Peak memory | 213112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161065927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.4161065927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/28.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_error.1292763764 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 3709562717 ps |
| CPU time | 67.79 seconds |
| Started | Oct 12 03:00:08 PM UTC 24 |
| Finished | Oct 12 03:01:18 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292763764 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.1292763764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/28.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.1392023240 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 2017655874 ps |
| CPU time | 74.76 seconds |
| Started | Oct 12 03:00:08 PM UTC 24 |
| Finished | Oct 12 03:01:25 PM UTC 24 |
| Peak memory | 215016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392023240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.1392023240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.115953907 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 278362347 ps |
| CPU time | 28.35 seconds |
| Started | Oct 12 03:00:10 PM UTC 24 |
| Finished | Oct 12 03:00:40 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115953907 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.115953907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_unmapped_addr.2935719094 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 33997315 ps |
| CPU time | 2.84 seconds |
| Started | Oct 12 03:00:08 PM UTC 24 |
| Finished | Oct 12 03:00:12 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935719094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.2935719094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/28.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device.3027973908 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 826264840 ps |
| CPU time | 17.65 seconds |
| Started | Oct 12 03:00:15 PM UTC 24 |
| Finished | Oct 12 03:00:33 PM UTC 24 |
| Peak memory | 212956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027973908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.3027973908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/29.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.2648365377 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 733405641 ps |
| CPU time | 5.08 seconds |
| Started | Oct 12 03:00:16 PM UTC 24 |
| Finished | Oct 12 03:00:23 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648365377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.2648365377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_error_random.1785186535 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 18660469 ps |
| CPU time | 1.86 seconds |
| Started | Oct 12 03:00:16 PM UTC 24 |
| Finished | Oct 12 03:00:19 PM UTC 24 |
| Peak memory | 211948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785186535 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.1785186535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/29.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random.2834372530 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 18323513 ps |
| CPU time | 2.68 seconds |
| Started | Oct 12 03:00:12 PM UTC 24 |
| Finished | Oct 12 03:00:16 PM UTC 24 |
| Peak memory | 211024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834372530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.2834372530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/29.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_large_delays.2717176970 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 5095628726 ps |
| CPU time | 32.8 seconds |
| Started | Oct 12 03:00:13 PM UTC 24 |
| Finished | Oct 12 03:00:47 PM UTC 24 |
| Peak memory | 212992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717176970 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2717176970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/29.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_slow_rsp.280207985 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 10147423420 ps |
| CPU time | 86.56 seconds |
| Started | Oct 12 03:00:13 PM UTC 24 |
| Finished | Oct 12 03:01:41 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280207985 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.280207985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/29.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_zero_delays.3501795775 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 70087283 ps |
| CPU time | 5.07 seconds |
| Started | Oct 12 03:00:13 PM UTC 24 |
| Finished | Oct 12 03:00:19 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501795775 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.3501795775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/29.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_same_source.736120272 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 411291439 ps |
| CPU time | 3.02 seconds |
| Started | Oct 12 03:00:15 PM UTC 24 |
| Finished | Oct 12 03:00:19 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736120272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.736120272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/29.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke.2827819019 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 26490717 ps |
| CPU time | 1.5 seconds |
| Started | Oct 12 03:00:11 PM UTC 24 |
| Finished | Oct 12 03:00:13 PM UTC 24 |
| Peak memory | 209864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827819019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2827819019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/29.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_large_delays.40924715 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 1996848604 ps |
| CPU time | 15.85 seconds |
| Started | Oct 12 03:00:11 PM UTC 24 |
| Finished | Oct 12 03:00:28 PM UTC 24 |
| Peak memory | 212968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40924715 -assert nopostproc +UVM_TESTNAME=xbar_base_ test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.40924715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/29.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.1995027506 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 686940891 ps |
| CPU time | 5.1 seconds |
| Started | Oct 12 03:00:11 PM UTC 24 |
| Finished | Oct 12 03:00:17 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995027506 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1995027506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.2035283515 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 8167814 ps |
| CPU time | 1.63 seconds |
| Started | Oct 12 03:00:11 PM UTC 24 |
| Finished | Oct 12 03:00:13 PM UTC 24 |
| Peak memory | 211968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035283515 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.2035283515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/29.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all.352218540 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 5211007581 ps |
| CPU time | 71.14 seconds |
| Started | Oct 12 03:00:16 PM UTC 24 |
| Finished | Oct 12 03:01:29 PM UTC 24 |
| Peak memory | 213096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352218540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.352218540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/29.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_error.1078752282 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 7635094133 ps |
| CPU time | 61.78 seconds |
| Started | Oct 12 03:00:18 PM UTC 24 |
| Finished | Oct 12 03:01:21 PM UTC 24 |
| Peak memory | 213008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078752282 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1078752282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/29.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.999081474 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 1228357980 ps |
| CPU time | 95.83 seconds |
| Started | Oct 12 03:00:18 PM UTC 24 |
| Finished | Oct 12 03:01:56 PM UTC 24 |
| Peak memory | 215008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999081474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.999081474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.2764335264 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 80284045 ps |
| CPU time | 2.86 seconds |
| Started | Oct 12 03:00:20 PM UTC 24 |
| Finished | Oct 12 03:00:23 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764335264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.2764335264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_unmapped_addr.1940278551 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1192856685 ps |
| CPU time | 12.28 seconds |
| Started | Oct 12 03:00:16 PM UTC 24 |
| Finished | Oct 12 03:00:30 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940278551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.1940278551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/29.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device.664653551 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 194500513 ps |
| CPU time | 13.76 seconds |
| Started | Oct 12 02:53:13 PM UTC 24 |
| Finished | Oct 12 02:53:28 PM UTC 24 |
| Peak memory | 212968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664653551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.664653551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/3.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.1620530042 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 5867072575 ps |
| CPU time | 45.58 seconds |
| Started | Oct 12 02:53:15 PM UTC 24 |
| Finished | Oct 12 02:54:02 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620530042 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.1620530042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.3379004291 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 43139673 ps |
| CPU time | 3.1 seconds |
| Started | Oct 12 02:53:21 PM UTC 24 |
| Finished | Oct 12 02:53:25 PM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379004291 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.3379004291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_error_random.658997467 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 617875377 ps |
| CPU time | 9.51 seconds |
| Started | Oct 12 02:53:18 PM UTC 24 |
| Finished | Oct 12 02:53:29 PM UTC 24 |
| Peak memory | 211028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658997467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.658997467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/3.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random.3806075980 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1801594404 ps |
| CPU time | 9.31 seconds |
| Started | Oct 12 02:53:09 PM UTC 24 |
| Finished | Oct 12 02:53:20 PM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806075980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.3806075980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/3.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_large_delays.1474547917 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 12382888359 ps |
| CPU time | 81.53 seconds |
| Started | Oct 12 02:53:11 PM UTC 24 |
| Finished | Oct 12 02:54:34 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474547917 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1474547917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/3.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_slow_rsp.132238796 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 15010428060 ps |
| CPU time | 95.22 seconds |
| Started | Oct 12 02:53:12 PM UTC 24 |
| Finished | Oct 12 02:54:49 PM UTC 24 |
| Peak memory | 213012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132238796 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.132238796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/3.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_zero_delays.14740314 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 68250889 ps |
| CPU time | 6.25 seconds |
| Started | Oct 12 02:53:10 PM UTC 24 |
| Finished | Oct 12 02:53:18 PM UTC 24 |
| Peak memory | 212996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14740314 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.14740314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/3.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_same_source.795998575 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 982782806 ps |
| CPU time | 6.92 seconds |
| Started | Oct 12 02:53:17 PM UTC 24 |
| Finished | Oct 12 02:53:25 PM UTC 24 |
| Peak memory | 213004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795998575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.795998575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/3.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke.3393910890 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 14007194 ps |
| CPU time | 1.58 seconds |
| Started | Oct 12 02:53:05 PM UTC 24 |
| Finished | Oct 12 02:53:08 PM UTC 24 |
| Peak memory | 211968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393910890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3393910890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/3.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_large_delays.1054021000 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1378008789 ps |
| CPU time | 11.56 seconds |
| Started | Oct 12 02:53:07 PM UTC 24 |
| Finished | Oct 12 02:53:20 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054021000 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.1054021000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/3.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.2932296701 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 3165912976 ps |
| CPU time | 17.37 seconds |
| Started | Oct 12 02:53:07 PM UTC 24 |
| Finished | Oct 12 02:53:26 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932296701 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.2932296701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.1114398707 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 9196457 ps |
| CPU time | 1.61 seconds |
| Started | Oct 12 02:53:07 PM UTC 24 |
| Finished | Oct 12 02:53:10 PM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114398707 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.1114398707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/3.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all.4135807683 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 360486868 ps |
| CPU time | 26.79 seconds |
| Started | Oct 12 02:53:21 PM UTC 24 |
| Finished | Oct 12 02:53:49 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135807683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.4135807683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/3.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_error.1690104754 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 2046785629 ps |
| CPU time | 42.45 seconds |
| Started | Oct 12 02:53:22 PM UTC 24 |
| Finished | Oct 12 02:54:06 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690104754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.1690104754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/3.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.4144981249 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 253265865 ps |
| CPU time | 35.91 seconds |
| Started | Oct 12 02:53:21 PM UTC 24 |
| Finished | Oct 12 02:53:58 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144981249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.4144981249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.4105723767 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 194922896 ps |
| CPU time | 23.56 seconds |
| Started | Oct 12 02:53:23 PM UTC 24 |
| Finished | Oct 12 02:53:48 PM UTC 24 |
| Peak memory | 213040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105723767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.4105723767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_unmapped_addr.1403591666 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 55750659 ps |
| CPU time | 5.89 seconds |
| Started | Oct 12 02:53:18 PM UTC 24 |
| Finished | Oct 12 02:53:25 PM UTC 24 |
| Peak memory | 211040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403591666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.1403591666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/3.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device.360494014 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 2829595705 ps |
| CPU time | 21.96 seconds |
| Started | Oct 12 03:00:26 PM UTC 24 |
| Finished | Oct 12 03:00:49 PM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360494014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.360494014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/30.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.2377256050 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 96569900 ps |
| CPU time | 2.11 seconds |
| Started | Oct 12 03:00:31 PM UTC 24 |
| Finished | Oct 12 03:00:35 PM UTC 24 |
| Peak memory | 212948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377256050 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.2377256050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_error_random.282265919 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 51479641 ps |
| CPU time | 6.18 seconds |
| Started | Oct 12 03:00:29 PM UTC 24 |
| Finished | Oct 12 03:00:36 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282265919 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.282265919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/30.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random.1791224352 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 19101871 ps |
| CPU time | 2.27 seconds |
| Started | Oct 12 03:00:25 PM UTC 24 |
| Finished | Oct 12 03:00:29 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791224352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.1791224352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/30.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.1389593081 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 6760455877 ps |
| CPU time | 32.43 seconds |
| Started | Oct 12 03:00:25 PM UTC 24 |
| Finished | Oct 12 03:00:59 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389593081 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1389593081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/30.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_slow_rsp.2851905974 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 6417863961 ps |
| CPU time | 74.75 seconds |
| Started | Oct 12 03:00:25 PM UTC 24 |
| Finished | Oct 12 03:01:42 PM UTC 24 |
| Peak memory | 211032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851905974 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.2851905974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/30.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_zero_delays.2891194545 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 57363111 ps |
| CPU time | 6.38 seconds |
| Started | Oct 12 03:00:25 PM UTC 24 |
| Finished | Oct 12 03:00:33 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891194545 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.2891194545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/30.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_same_source.1367117923 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 653600009 ps |
| CPU time | 6.27 seconds |
| Started | Oct 12 03:00:29 PM UTC 24 |
| Finished | Oct 12 03:00:36 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367117923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.1367117923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/30.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke.4243686626 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 8707566 ps |
| CPU time | 1.62 seconds |
| Started | Oct 12 03:00:20 PM UTC 24 |
| Finished | Oct 12 03:00:22 PM UTC 24 |
| Peak memory | 211952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243686626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.4243686626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/30.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_large_delays.234899692 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 4727286793 ps |
| CPU time | 16.56 seconds |
| Started | Oct 12 03:00:22 PM UTC 24 |
| Finished | Oct 12 03:00:40 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234899692 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.234899692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/30.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.962045562 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 1367475957 ps |
| CPU time | 7.06 seconds |
| Started | Oct 12 03:00:25 PM UTC 24 |
| Finished | Oct 12 03:00:33 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962045562 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.962045562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.2422557613 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 9541467 ps |
| CPU time | 1.83 seconds |
| Started | Oct 12 03:00:21 PM UTC 24 |
| Finished | Oct 12 03:00:24 PM UTC 24 |
| Peak memory | 211960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422557613 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2422557613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/30.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all.336287619 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 203073917 ps |
| CPU time | 21.57 seconds |
| Started | Oct 12 03:00:34 PM UTC 24 |
| Finished | Oct 12 03:00:57 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336287619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.336287619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/30.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2279207520 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 3370161669 ps |
| CPU time | 157.55 seconds |
| Started | Oct 12 03:00:34 PM UTC 24 |
| Finished | Oct 12 03:03:14 PM UTC 24 |
| Peak memory | 218804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279207520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.2279207520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.2215775256 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 1261586776 ps |
| CPU time | 50.58 seconds |
| Started | Oct 12 03:00:36 PM UTC 24 |
| Finished | Oct 12 03:01:28 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215775256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.2215775256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_unmapped_addr.284386297 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 111686783 ps |
| CPU time | 8.71 seconds |
| Started | Oct 12 03:00:30 PM UTC 24 |
| Finished | Oct 12 03:00:40 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284386297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.284386297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/30.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device.2789246989 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 78996773 ps |
| CPU time | 11.51 seconds |
| Started | Oct 12 03:00:44 PM UTC 24 |
| Finished | Oct 12 03:00:57 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789246989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.2789246989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/31.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.3424572926 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 4949274079 ps |
| CPU time | 14.91 seconds |
| Started | Oct 12 03:00:51 PM UTC 24 |
| Finished | Oct 12 03:01:07 PM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424572926 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.3424572926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_error_random.4289845689 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 3131503291 ps |
| CPU time | 10.95 seconds |
| Started | Oct 12 03:00:49 PM UTC 24 |
| Finished | Oct 12 03:01:01 PM UTC 24 |
| Peak memory | 212976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289845689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.4289845689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/31.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random.4041442409 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 561485959 ps |
| CPU time | 4.68 seconds |
| Started | Oct 12 03:00:41 PM UTC 24 |
| Finished | Oct 12 03:00:46 PM UTC 24 |
| Peak memory | 212940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041442409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.4041442409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/31.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_large_delays.1754267449 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 32450185588 ps |
| CPU time | 95.51 seconds |
| Started | Oct 12 03:00:44 PM UTC 24 |
| Finished | Oct 12 03:02:21 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754267449 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.1754267449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/31.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_slow_rsp.3209448785 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 9512950069 ps |
| CPU time | 78.76 seconds |
| Started | Oct 12 03:00:44 PM UTC 24 |
| Finished | Oct 12 03:02:05 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209448785 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.3209448785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/31.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_zero_delays.3563803491 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 12441773 ps |
| CPU time | 1.84 seconds |
| Started | Oct 12 03:00:41 PM UTC 24 |
| Finished | Oct 12 03:00:44 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563803491 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.3563803491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/31.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_same_source.969151999 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 141626105 ps |
| CPU time | 3.26 seconds |
| Started | Oct 12 03:00:46 PM UTC 24 |
| Finished | Oct 12 03:00:50 PM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969151999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.969151999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/31.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke.2847778011 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 83737234 ps |
| CPU time | 2.18 seconds |
| Started | Oct 12 03:00:36 PM UTC 24 |
| Finished | Oct 12 03:00:39 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847778011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2847778011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/31.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_large_delays.1244153687 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 11029025938 ps |
| CPU time | 16.69 seconds |
| Started | Oct 12 03:00:38 PM UTC 24 |
| Finished | Oct 12 03:00:56 PM UTC 24 |
| Peak memory | 212688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244153687 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.1244153687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/31.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.3328151132 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 968391473 ps |
| CPU time | 9.62 seconds |
| Started | Oct 12 03:00:38 PM UTC 24 |
| Finished | Oct 12 03:00:49 PM UTC 24 |
| Peak memory | 210508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328151132 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3328151132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.2987981894 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 12359043 ps |
| CPU time | 1.71 seconds |
| Started | Oct 12 03:00:36 PM UTC 24 |
| Finished | Oct 12 03:00:39 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987981894 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.2987981894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/31.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all.1426772105 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 4104799970 ps |
| CPU time | 89.03 seconds |
| Started | Oct 12 03:00:51 PM UTC 24 |
| Finished | Oct 12 03:02:22 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426772105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.1426772105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/31.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_error.3457504760 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 10154390657 ps |
| CPU time | 64.77 seconds |
| Started | Oct 12 03:00:53 PM UTC 24 |
| Finished | Oct 12 03:01:59 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457504760 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3457504760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/31.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.280961969 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 1524291316 ps |
| CPU time | 190.84 seconds |
| Started | Oct 12 03:00:51 PM UTC 24 |
| Finished | Oct 12 03:04:05 PM UTC 24 |
| Peak memory | 216556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280961969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.280961969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.812369999 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 211064069 ps |
| CPU time | 12.25 seconds |
| Started | Oct 12 03:00:54 PM UTC 24 |
| Finished | Oct 12 03:01:07 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812369999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.812369999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_unmapped_addr.1418807837 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 219265859 ps |
| CPU time | 5.39 seconds |
| Started | Oct 12 03:00:49 PM UTC 24 |
| Finished | Oct 12 03:00:55 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418807837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1418807837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/31.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device.336531961 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 50185338 ps |
| CPU time | 9.2 seconds |
| Started | Oct 12 03:01:03 PM UTC 24 |
| Finished | Oct 12 03:01:13 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336531961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.336531961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/32.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.4094975046 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 14776194607 ps |
| CPU time | 81.28 seconds |
| Started | Oct 12 03:01:03 PM UTC 24 |
| Finished | Oct 12 03:02:26 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094975046 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.4094975046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2499759054 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 21659996 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 03:01:08 PM UTC 24 |
| Finished | Oct 12 03:01:10 PM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499759054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.2499759054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_error_random.1415880774 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 11030086 ps |
| CPU time | 1.59 seconds |
| Started | Oct 12 03:01:03 PM UTC 24 |
| Finished | Oct 12 03:01:06 PM UTC 24 |
| Peak memory | 211948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415880774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1415880774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/32.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random.4201160798 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 1838978315 ps |
| CPU time | 11.13 seconds |
| Started | Oct 12 03:01:00 PM UTC 24 |
| Finished | Oct 12 03:01:13 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201160798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.4201160798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/32.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.1955495364 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 22882416702 ps |
| CPU time | 26.98 seconds |
| Started | Oct 12 03:01:00 PM UTC 24 |
| Finished | Oct 12 03:01:29 PM UTC 24 |
| Peak memory | 210484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955495364 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.1955495364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/32.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.2456362505 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 1136631446 ps |
| CPU time | 9.51 seconds |
| Started | Oct 12 03:01:00 PM UTC 24 |
| Finished | Oct 12 03:01:11 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456362505 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2456362505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/32.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_zero_delays.2182140270 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 80426878 ps |
| CPU time | 4.05 seconds |
| Started | Oct 12 03:01:00 PM UTC 24 |
| Finished | Oct 12 03:01:06 PM UTC 24 |
| Peak memory | 210460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182140270 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.2182140270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/32.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_same_source.1951049139 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 10649745 ps |
| CPU time | 1.76 seconds |
| Started | Oct 12 03:01:03 PM UTC 24 |
| Finished | Oct 12 03:01:06 PM UTC 24 |
| Peak memory | 209932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951049139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1951049139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/32.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke.3805747896 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 463575596 ps |
| CPU time | 2.47 seconds |
| Started | Oct 12 03:00:57 PM UTC 24 |
| Finished | Oct 12 03:01:00 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805747896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3805747896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/32.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_large_delays.3191015220 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 2313816053 ps |
| CPU time | 11.73 seconds |
| Started | Oct 12 03:01:00 PM UTC 24 |
| Finished | Oct 12 03:01:13 PM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191015220 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.3191015220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/32.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.1617214671 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 3807567371 ps |
| CPU time | 10.51 seconds |
| Started | Oct 12 03:01:00 PM UTC 24 |
| Finished | Oct 12 03:01:12 PM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617214671 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.1617214671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.3807083498 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 9417356 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 03:00:57 PM UTC 24 |
| Finished | Oct 12 03:00:59 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807083498 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.3807083498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/32.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all.211123537 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 1951089076 ps |
| CPU time | 32.74 seconds |
| Started | Oct 12 03:01:08 PM UTC 24 |
| Finished | Oct 12 03:01:42 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211123537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.211123537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/32.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1262729180 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 29537233798 ps |
| CPU time | 90.21 seconds |
| Started | Oct 12 03:01:11 PM UTC 24 |
| Finished | Oct 12 03:02:43 PM UTC 24 |
| Peak memory | 213160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262729180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1262729180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/32.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.4249119464 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 182237507 ps |
| CPU time | 23.89 seconds |
| Started | Oct 12 03:01:08 PM UTC 24 |
| Finished | Oct 12 03:01:33 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249119464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.4249119464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.368485721 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 533314338 ps |
| CPU time | 86.28 seconds |
| Started | Oct 12 03:01:11 PM UTC 24 |
| Finished | Oct 12 03:02:39 PM UTC 24 |
| Peak memory | 212952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368485721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.368485721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_unmapped_addr.1881216834 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 50699342 ps |
| CPU time | 1.79 seconds |
| Started | Oct 12 03:01:04 PM UTC 24 |
| Finished | Oct 12 03:01:07 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881216834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1881216834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/32.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device.2948561135 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 931138420 ps |
| CPU time | 20.59 seconds |
| Started | Oct 12 03:01:15 PM UTC 24 |
| Finished | Oct 12 03:01:37 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948561135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.2948561135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/33.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.3195913097 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 41705607867 ps |
| CPU time | 176.66 seconds |
| Started | Oct 12 03:01:15 PM UTC 24 |
| Finished | Oct 12 03:04:15 PM UTC 24 |
| Peak memory | 213156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195913097 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.3195913097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.1168371986 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 263395652 ps |
| CPU time | 6.57 seconds |
| Started | Oct 12 03:01:19 PM UTC 24 |
| Finished | Oct 12 03:01:27 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168371986 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.1168371986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_error_random.306468295 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 1250723501 ps |
| CPU time | 12.9 seconds |
| Started | Oct 12 03:01:17 PM UTC 24 |
| Finished | Oct 12 03:01:32 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306468295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.306468295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/33.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random.2958355534 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 23517742 ps |
| CPU time | 3.96 seconds |
| Started | Oct 12 03:01:15 PM UTC 24 |
| Finished | Oct 12 03:01:20 PM UTC 24 |
| Peak memory | 212932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958355534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.2958355534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/33.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_large_delays.3084975558 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 9645353282 ps |
| CPU time | 49.84 seconds |
| Started | Oct 12 03:01:15 PM UTC 24 |
| Finished | Oct 12 03:02:07 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084975558 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.3084975558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/33.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_slow_rsp.973025868 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 9436374175 ps |
| CPU time | 41.51 seconds |
| Started | Oct 12 03:01:15 PM UTC 24 |
| Finished | Oct 12 03:01:58 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973025868 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.973025868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/33.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_zero_delays.792068992 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 108445856 ps |
| CPU time | 3.17 seconds |
| Started | Oct 12 03:01:15 PM UTC 24 |
| Finished | Oct 12 03:01:20 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792068992 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.792068992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/33.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_same_source.4116543421 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 993629538 ps |
| CPU time | 13.24 seconds |
| Started | Oct 12 03:01:15 PM UTC 24 |
| Finished | Oct 12 03:01:30 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116543421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.4116543421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/33.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke.715076915 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 61060853 ps |
| CPU time | 1.84 seconds |
| Started | Oct 12 03:01:11 PM UTC 24 |
| Finished | Oct 12 03:01:14 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715076915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.715076915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/33.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_large_delays.561879857 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 4484372548 ps |
| CPU time | 17.78 seconds |
| Started | Oct 12 03:01:11 PM UTC 24 |
| Finished | Oct 12 03:01:30 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561879857 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.561879857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/33.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.879970880 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 848600835 ps |
| CPU time | 9.64 seconds |
| Started | Oct 12 03:01:13 PM UTC 24 |
| Finished | Oct 12 03:01:23 PM UTC 24 |
| Peak memory | 213000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879970880 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.879970880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.1808587651 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 7699195 ps |
| CPU time | 1.42 seconds |
| Started | Oct 12 03:01:11 PM UTC 24 |
| Finished | Oct 12 03:01:13 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808587651 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.1808587651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/33.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_error.2615108038 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 1980196377 ps |
| CPU time | 38.44 seconds |
| Started | Oct 12 03:01:24 PM UTC 24 |
| Finished | Oct 12 03:02:04 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615108038 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.2615108038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/33.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.1632662884 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 617943742 ps |
| CPU time | 91.72 seconds |
| Started | Oct 12 03:01:22 PM UTC 24 |
| Finished | Oct 12 03:02:56 PM UTC 24 |
| Peak memory | 215016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632662884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.1632662884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.4119056746 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 98243917 ps |
| CPU time | 6.73 seconds |
| Started | Oct 12 03:01:25 PM UTC 24 |
| Finished | Oct 12 03:01:33 PM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119056746 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.4119056746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_unmapped_addr.67858511 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 64706069 ps |
| CPU time | 7.58 seconds |
| Started | Oct 12 03:01:17 PM UTC 24 |
| Finished | Oct 12 03:01:26 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67858511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.67858511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/33.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device.2458472449 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 11816605 ps |
| CPU time | 2.4 seconds |
| Started | Oct 12 03:01:31 PM UTC 24 |
| Finished | Oct 12 03:01:34 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458472449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.2458472449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/34.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.481638487 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 182654851 ps |
| CPU time | 4.72 seconds |
| Started | Oct 12 03:01:34 PM UTC 24 |
| Finished | Oct 12 03:01:39 PM UTC 24 |
| Peak memory | 212952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481638487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.481638487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_error_random.342353104 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 109847235 ps |
| CPU time | 7.7 seconds |
| Started | Oct 12 03:01:33 PM UTC 24 |
| Finished | Oct 12 03:01:42 PM UTC 24 |
| Peak memory | 213012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342353104 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.342353104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/34.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random.2145637705 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 1235045544 ps |
| CPU time | 14.52 seconds |
| Started | Oct 12 03:01:28 PM UTC 24 |
| Finished | Oct 12 03:01:44 PM UTC 24 |
| Peak memory | 212940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145637705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.2145637705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/34.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.1739819603 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 30183387985 ps |
| CPU time | 119.32 seconds |
| Started | Oct 12 03:01:31 PM UTC 24 |
| Finished | Oct 12 03:03:32 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739819603 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1739819603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/34.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_slow_rsp.1226113690 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 11094101152 ps |
| CPU time | 85.64 seconds |
| Started | Oct 12 03:01:31 PM UTC 24 |
| Finished | Oct 12 03:02:58 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226113690 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1226113690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/34.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_zero_delays.495036448 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 97964248 ps |
| CPU time | 4.07 seconds |
| Started | Oct 12 03:01:30 PM UTC 24 |
| Finished | Oct 12 03:01:36 PM UTC 24 |
| Peak memory | 212984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495036448 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.495036448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/34.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_same_source.59656333 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 424491652 ps |
| CPU time | 4.86 seconds |
| Started | Oct 12 03:01:33 PM UTC 24 |
| Finished | Oct 12 03:01:39 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59656333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.59656333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/34.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke.1299132900 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 42284095 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 03:01:25 PM UTC 24 |
| Finished | Oct 12 03:01:28 PM UTC 24 |
| Peak memory | 211952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299132900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1299132900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/34.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_large_delays.3323542865 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 1754319966 ps |
| CPU time | 10.26 seconds |
| Started | Oct 12 03:01:28 PM UTC 24 |
| Finished | Oct 12 03:01:39 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323542865 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.3323542865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/34.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1099437294 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 2274037767 ps |
| CPU time | 11.02 seconds |
| Started | Oct 12 03:01:28 PM UTC 24 |
| Finished | Oct 12 03:01:40 PM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099437294 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1099437294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.3196146005 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 11182467 ps |
| CPU time | 1.68 seconds |
| Started | Oct 12 03:01:25 PM UTC 24 |
| Finished | Oct 12 03:01:28 PM UTC 24 |
| Peak memory | 211968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196146005 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.3196146005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/34.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all.4281143508 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 3968403887 ps |
| CPU time | 28.6 seconds |
| Started | Oct 12 03:01:36 PM UTC 24 |
| Finished | Oct 12 03:02:06 PM UTC 24 |
| Peak memory | 213132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281143508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.4281143508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/34.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_error.606353384 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 348579649 ps |
| CPU time | 9 seconds |
| Started | Oct 12 03:01:36 PM UTC 24 |
| Finished | Oct 12 03:01:46 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606353384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.606353384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/34.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.1048000122 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 1730839509 ps |
| CPU time | 46.04 seconds |
| Started | Oct 12 03:01:36 PM UTC 24 |
| Finished | Oct 12 03:02:24 PM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048000122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.1048000122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.4044850738 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 2920796665 ps |
| CPU time | 52.55 seconds |
| Started | Oct 12 03:01:38 PM UTC 24 |
| Finished | Oct 12 03:02:32 PM UTC 24 |
| Peak memory | 215152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044850738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.4044850738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_unmapped_addr.515460913 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 13132325 ps |
| CPU time | 1.61 seconds |
| Started | Oct 12 03:01:33 PM UTC 24 |
| Finished | Oct 12 03:01:36 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515460913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.515460913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/34.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device.2230240134 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1764400428 ps |
| CPU time | 11.15 seconds |
| Started | Oct 12 03:01:44 PM UTC 24 |
| Finished | Oct 12 03:01:57 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230240134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.2230240134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/35.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2707377555 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 11974442281 ps |
| CPU time | 35.6 seconds |
| Started | Oct 12 03:01:44 PM UTC 24 |
| Finished | Oct 12 03:02:21 PM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707377555 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.2707377555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.3637176145 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 25006812 ps |
| CPU time | 3.13 seconds |
| Started | Oct 12 03:01:47 PM UTC 24 |
| Finished | Oct 12 03:01:51 PM UTC 24 |
| Peak memory | 213056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637176145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.3637176145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_error_random.4120968143 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 827568741 ps |
| CPU time | 13.61 seconds |
| Started | Oct 12 03:01:47 PM UTC 24 |
| Finished | Oct 12 03:02:02 PM UTC 24 |
| Peak memory | 211020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120968143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.4120968143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/35.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random.4185002276 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 4009413033 ps |
| CPU time | 17.16 seconds |
| Started | Oct 12 03:01:44 PM UTC 24 |
| Finished | Oct 12 03:02:02 PM UTC 24 |
| Peak memory | 211024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185002276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.4185002276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/35.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.4280947493 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 1552192102 ps |
| CPU time | 12.64 seconds |
| Started | Oct 12 03:01:44 PM UTC 24 |
| Finished | Oct 12 03:01:58 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280947493 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.4280947493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/35.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.888346658 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 8415096433 ps |
| CPU time | 27.26 seconds |
| Started | Oct 12 03:01:44 PM UTC 24 |
| Finished | Oct 12 03:02:13 PM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888346658 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.888346658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/35.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_zero_delays.2049271275 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 64699525 ps |
| CPU time | 10.5 seconds |
| Started | Oct 12 03:01:44 PM UTC 24 |
| Finished | Oct 12 03:01:56 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049271275 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.2049271275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/35.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_same_source.2293897621 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 1178385375 ps |
| CPU time | 13.77 seconds |
| Started | Oct 12 03:01:47 PM UTC 24 |
| Finished | Oct 12 03:02:02 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293897621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.2293897621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/35.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke.938837938 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 43331026 ps |
| CPU time | 1.85 seconds |
| Started | Oct 12 03:01:38 PM UTC 24 |
| Finished | Oct 12 03:01:41 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938837938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.938837938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/35.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_large_delays.3591761199 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 1818573406 ps |
| CPU time | 9.8 seconds |
| Started | Oct 12 03:01:41 PM UTC 24 |
| Finished | Oct 12 03:01:51 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591761199 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3591761199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/35.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.1928431065 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 2085737533 ps |
| CPU time | 5.91 seconds |
| Started | Oct 12 03:01:41 PM UTC 24 |
| Finished | Oct 12 03:01:48 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928431065 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1928431065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.2902128963 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 10414827 ps |
| CPU time | 1.63 seconds |
| Started | Oct 12 03:01:41 PM UTC 24 |
| Finished | Oct 12 03:01:43 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902128963 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.2902128963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/35.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all.1196033634 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 1804984791 ps |
| CPU time | 23.02 seconds |
| Started | Oct 12 03:01:49 PM UTC 24 |
| Finished | Oct 12 03:02:13 PM UTC 24 |
| Peak memory | 212932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196033634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.1196033634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/35.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_error.4070872131 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 14655640333 ps |
| CPU time | 58.67 seconds |
| Started | Oct 12 03:01:53 PM UTC 24 |
| Finished | Oct 12 03:02:54 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070872131 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.4070872131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/35.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1046608824 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 6402851720 ps |
| CPU time | 115.24 seconds |
| Started | Oct 12 03:01:50 PM UTC 24 |
| Finished | Oct 12 03:03:47 PM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046608824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.1046608824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.882691312 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 5188846297 ps |
| CPU time | 114.56 seconds |
| Started | Oct 12 03:01:53 PM UTC 24 |
| Finished | Oct 12 03:03:50 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882691312 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.882691312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_unmapped_addr.3549426732 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 62436865 ps |
| CPU time | 7.46 seconds |
| Started | Oct 12 03:01:47 PM UTC 24 |
| Finished | Oct 12 03:01:55 PM UTC 24 |
| Peak memory | 212968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549426732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3549426732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/35.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device.953786904 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 1257232015 ps |
| CPU time | 24.21 seconds |
| Started | Oct 12 03:02:04 PM UTC 24 |
| Finished | Oct 12 03:02:30 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953786904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.953786904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/36.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.2467184971 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 11914090256 ps |
| CPU time | 33.77 seconds |
| Started | Oct 12 03:02:04 PM UTC 24 |
| Finished | Oct 12 03:02:39 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467184971 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.2467184971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.2828945588 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 30782447 ps |
| CPU time | 3.52 seconds |
| Started | Oct 12 03:02:07 PM UTC 24 |
| Finished | Oct 12 03:02:12 PM UTC 24 |
| Peak memory | 213000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828945588 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.2828945588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_error_random.1964201420 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 61238921 ps |
| CPU time | 4.01 seconds |
| Started | Oct 12 03:02:04 PM UTC 24 |
| Finished | Oct 12 03:02:09 PM UTC 24 |
| Peak memory | 212908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964201420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1964201420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/36.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random.1730225775 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 859059008 ps |
| CPU time | 20.61 seconds |
| Started | Oct 12 03:02:01 PM UTC 24 |
| Finished | Oct 12 03:02:23 PM UTC 24 |
| Peak memory | 213000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730225775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.1730225775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/36.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.680543852 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 20605332028 ps |
| CPU time | 38.74 seconds |
| Started | Oct 12 03:02:01 PM UTC 24 |
| Finished | Oct 12 03:02:41 PM UTC 24 |
| Peak memory | 211108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680543852 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.680543852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/36.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.41797996 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 13429937036 ps |
| CPU time | 46.15 seconds |
| Started | Oct 12 03:02:04 PM UTC 24 |
| Finished | Oct 12 03:02:52 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41797996 -assert nopostproc +UVM_TESTN AME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.41797996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/36.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_zero_delays.3995633507 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 57863624 ps |
| CPU time | 8.41 seconds |
| Started | Oct 12 03:02:01 PM UTC 24 |
| Finished | Oct 12 03:02:10 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995633507 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.3995633507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/36.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_same_source.3393920640 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 2547776666 ps |
| CPU time | 12.33 seconds |
| Started | Oct 12 03:02:04 PM UTC 24 |
| Finished | Oct 12 03:02:18 PM UTC 24 |
| Peak memory | 213000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393920640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3393920640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/36.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke.1446303940 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 20063782 ps |
| CPU time | 1.68 seconds |
| Started | Oct 12 03:01:58 PM UTC 24 |
| Finished | Oct 12 03:02:01 PM UTC 24 |
| Peak memory | 211944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446303940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1446303940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/36.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_large_delays.2776465461 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 8395324320 ps |
| CPU time | 12.05 seconds |
| Started | Oct 12 03:01:58 PM UTC 24 |
| Finished | Oct 12 03:02:12 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776465461 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2776465461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/36.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.2526563833 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 1179757966 ps |
| CPU time | 7.97 seconds |
| Started | Oct 12 03:01:58 PM UTC 24 |
| Finished | Oct 12 03:02:08 PM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526563833 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.2526563833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.197002326 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 9058407 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 03:01:58 PM UTC 24 |
| Finished | Oct 12 03:02:01 PM UTC 24 |
| Peak memory | 211960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197002326 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.197002326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/36.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all.4200933941 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 1576170956 ps |
| CPU time | 28.36 seconds |
| Started | Oct 12 03:02:07 PM UTC 24 |
| Finished | Oct 12 03:02:37 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200933941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.4200933941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/36.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_error.2718264127 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 18837429679 ps |
| CPU time | 76.75 seconds |
| Started | Oct 12 03:02:09 PM UTC 24 |
| Finished | Oct 12 03:03:28 PM UTC 24 |
| Peak memory | 213008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718264127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.2718264127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/36.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1105517239 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 3416669111 ps |
| CPU time | 150.47 seconds |
| Started | Oct 12 03:02:07 PM UTC 24 |
| Finished | Oct 12 03:04:40 PM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105517239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.1105517239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.56663987 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 2766440218 ps |
| CPU time | 95.52 seconds |
| Started | Oct 12 03:02:10 PM UTC 24 |
| Finished | Oct 12 03:03:47 PM UTC 24 |
| Peak memory | 217128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56663987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.56663987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_unmapped_addr.805847965 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 62045343 ps |
| CPU time | 6.6 seconds |
| Started | Oct 12 03:02:07 PM UTC 24 |
| Finished | Oct 12 03:02:15 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805847965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.805847965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/36.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device.1912651606 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 1275257295 ps |
| CPU time | 17.28 seconds |
| Started | Oct 12 03:02:17 PM UTC 24 |
| Finished | Oct 12 03:02:36 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912651606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.1912651606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/37.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.2389478736 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 20826587174 ps |
| CPU time | 69.94 seconds |
| Started | Oct 12 03:02:17 PM UTC 24 |
| Finished | Oct 12 03:03:29 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389478736 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.2389478736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.1617473578 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 641520984 ps |
| CPU time | 8.44 seconds |
| Started | Oct 12 03:02:25 PM UTC 24 |
| Finished | Oct 12 03:02:35 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617473578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.1617473578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_error_random.2508809377 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 179643709 ps |
| CPU time | 2.41 seconds |
| Started | Oct 12 03:02:20 PM UTC 24 |
| Finished | Oct 12 03:02:23 PM UTC 24 |
| Peak memory | 212936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508809377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2508809377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/37.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random.1884598907 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 24536280 ps |
| CPU time | 2.57 seconds |
| Started | Oct 12 03:02:14 PM UTC 24 |
| Finished | Oct 12 03:02:17 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884598907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.1884598907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/37.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.3475799162 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 4690805180 ps |
| CPU time | 37.23 seconds |
| Started | Oct 12 03:02:17 PM UTC 24 |
| Finished | Oct 12 03:02:56 PM UTC 24 |
| Peak memory | 213020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475799162 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.3475799162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/37.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.2254445825 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 4352308938 ps |
| CPU time | 36.58 seconds |
| Started | Oct 12 03:02:17 PM UTC 24 |
| Finished | Oct 12 03:02:55 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254445825 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2254445825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/37.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_zero_delays.3360900175 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 39334829 ps |
| CPU time | 4.44 seconds |
| Started | Oct 12 03:02:17 PM UTC 24 |
| Finished | Oct 12 03:02:23 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360900175 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.3360900175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/37.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_same_source.2279929473 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 86974338 ps |
| CPU time | 6.62 seconds |
| Started | Oct 12 03:02:20 PM UTC 24 |
| Finished | Oct 12 03:02:28 PM UTC 24 |
| Peak memory | 213004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279929473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2279929473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/37.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke.2397718145 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 45170363 ps |
| CPU time | 2.19 seconds |
| Started | Oct 12 03:02:12 PM UTC 24 |
| Finished | Oct 12 03:02:15 PM UTC 24 |
| Peak memory | 212948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397718145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2397718145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/37.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_large_delays.317649305 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 4930930570 ps |
| CPU time | 24.9 seconds |
| Started | Oct 12 03:02:12 PM UTC 24 |
| Finished | Oct 12 03:02:38 PM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317649305 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.317649305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/37.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.794057172 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 881799460 ps |
| CPU time | 11.44 seconds |
| Started | Oct 12 03:02:14 PM UTC 24 |
| Finished | Oct 12 03:02:27 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794057172 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.794057172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.4042319825 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 13404132 ps |
| CPU time | 1.56 seconds |
| Started | Oct 12 03:02:12 PM UTC 24 |
| Finished | Oct 12 03:02:14 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042319825 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.4042319825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/37.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.663122158 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 167904359 ps |
| CPU time | 13.61 seconds |
| Started | Oct 12 03:02:25 PM UTC 24 |
| Finished | Oct 12 03:02:40 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663122158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.663122158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/37.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_error.423025155 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 122480208 ps |
| CPU time | 10.69 seconds |
| Started | Oct 12 03:02:25 PM UTC 24 |
| Finished | Oct 12 03:02:37 PM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423025155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.423025155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/37.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.3820641400 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 752624465 ps |
| CPU time | 52.59 seconds |
| Started | Oct 12 03:02:25 PM UTC 24 |
| Finished | Oct 12 03:03:19 PM UTC 24 |
| Peak memory | 213092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820641400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.3820641400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.902289535 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 4605221543 ps |
| CPU time | 128.44 seconds |
| Started | Oct 12 03:02:25 PM UTC 24 |
| Finished | Oct 12 03:04:36 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902289535 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.902289535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_unmapped_addr.2138917325 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 230464066 ps |
| CPU time | 6.9 seconds |
| Started | Oct 12 03:02:20 PM UTC 24 |
| Finished | Oct 12 03:02:28 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138917325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.2138917325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/37.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device.407070790 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 79869403 ps |
| CPU time | 10.79 seconds |
| Started | Oct 12 03:02:31 PM UTC 24 |
| Finished | Oct 12 03:02:43 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407070790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.407070790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/38.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.2857335280 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 20233992885 ps |
| CPU time | 87.44 seconds |
| Started | Oct 12 03:02:33 PM UTC 24 |
| Finished | Oct 12 03:04:02 PM UTC 24 |
| Peak memory | 213016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857335280 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.2857335280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.4208640509 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 99399240 ps |
| CPU time | 3.31 seconds |
| Started | Oct 12 03:02:39 PM UTC 24 |
| Finished | Oct 12 03:02:44 PM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208640509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.4208640509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_error_random.941646128 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 43017597 ps |
| CPU time | 5.35 seconds |
| Started | Oct 12 03:02:36 PM UTC 24 |
| Finished | Oct 12 03:02:43 PM UTC 24 |
| Peak memory | 212916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941646128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.941646128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/38.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random.3891118636 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 21396443 ps |
| CPU time | 2.36 seconds |
| Started | Oct 12 03:02:30 PM UTC 24 |
| Finished | Oct 12 03:02:33 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891118636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.3891118636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/38.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.2781269243 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 52640969607 ps |
| CPU time | 80.76 seconds |
| Started | Oct 12 03:02:30 PM UTC 24 |
| Finished | Oct 12 03:03:52 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781269243 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.2781269243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/38.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.939514780 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 5857633936 ps |
| CPU time | 13.55 seconds |
| Started | Oct 12 03:02:31 PM UTC 24 |
| Finished | Oct 12 03:02:46 PM UTC 24 |
| Peak memory | 213076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939514780 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.939514780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/38.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_zero_delays.2775198026 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 137531750 ps |
| CPU time | 6.33 seconds |
| Started | Oct 12 03:02:30 PM UTC 24 |
| Finished | Oct 12 03:02:37 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775198026 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.2775198026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/38.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_same_source.347137776 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 1914984411 ps |
| CPU time | 10.34 seconds |
| Started | Oct 12 03:02:35 PM UTC 24 |
| Finished | Oct 12 03:02:46 PM UTC 24 |
| Peak memory | 212940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347137776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.347137776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/38.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke.537356637 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 287481296 ps |
| CPU time | 2.2 seconds |
| Started | Oct 12 03:02:26 PM UTC 24 |
| Finished | Oct 12 03:02:29 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537356637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.537356637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/38.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_large_delays.3460067308 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 2010308464 ps |
| CPU time | 14.67 seconds |
| Started | Oct 12 03:02:27 PM UTC 24 |
| Finished | Oct 12 03:02:43 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460067308 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.3460067308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/38.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.2502473685 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 4119728335 ps |
| CPU time | 9.4 seconds |
| Started | Oct 12 03:02:28 PM UTC 24 |
| Finished | Oct 12 03:02:38 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502473685 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2502473685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.1747903326 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 9643988 ps |
| CPU time | 1.71 seconds |
| Started | Oct 12 03:02:27 PM UTC 24 |
| Finished | Oct 12 03:02:30 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747903326 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.1747903326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/38.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.2693918519 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 733558845 ps |
| CPU time | 17.27 seconds |
| Started | Oct 12 03:02:39 PM UTC 24 |
| Finished | Oct 12 03:02:58 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693918519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.2693918519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/38.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.313789949 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 426677525 ps |
| CPU time | 11.48 seconds |
| Started | Oct 12 03:02:39 PM UTC 24 |
| Finished | Oct 12 03:02:52 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313789949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.313789949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/38.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.4119700662 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 20815953883 ps |
| CPU time | 274.45 seconds |
| Started | Oct 12 03:02:39 PM UTC 24 |
| Finished | Oct 12 03:07:18 PM UTC 24 |
| Peak memory | 221296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119700662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.4119700662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.733933663 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 6003869719 ps |
| CPU time | 100.07 seconds |
| Started | Oct 12 03:02:43 PM UTC 24 |
| Finished | Oct 12 03:04:25 PM UTC 24 |
| Peak memory | 217196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733933663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.733933663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_unmapped_addr.3821544195 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 273317823 ps |
| CPU time | 4.81 seconds |
| Started | Oct 12 03:02:39 PM UTC 24 |
| Finished | Oct 12 03:02:46 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821544195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3821544195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/38.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device.3477776944 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1354332663 ps |
| CPU time | 30.83 seconds |
| Started | Oct 12 03:02:47 PM UTC 24 |
| Finished | Oct 12 03:03:20 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477776944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.3477776944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/39.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3149861729 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 41275838555 ps |
| CPU time | 201.76 seconds |
| Started | Oct 12 03:02:47 PM UTC 24 |
| Finished | Oct 12 03:06:12 PM UTC 24 |
| Peak memory | 214564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149861729 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.3149861729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.943369994 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 107540007 ps |
| CPU time | 2.93 seconds |
| Started | Oct 12 03:02:50 PM UTC 24 |
| Finished | Oct 12 03:02:54 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943369994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.943369994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_error_random.4172865470 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 56189621 ps |
| CPU time | 4.47 seconds |
| Started | Oct 12 03:02:48 PM UTC 24 |
| Finished | Oct 12 03:02:53 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172865470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.4172865470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/39.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random.46223176 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 2244281730 ps |
| CPU time | 8.66 seconds |
| Started | Oct 12 03:02:47 PM UTC 24 |
| Finished | Oct 12 03:02:57 PM UTC 24 |
| Peak memory | 213020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46223176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.46223176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/39.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.1737335779 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 61948498053 ps |
| CPU time | 42.24 seconds |
| Started | Oct 12 03:02:47 PM UTC 24 |
| Finished | Oct 12 03:03:31 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737335779 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1737335779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/39.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.2786424207 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 4844289465 ps |
| CPU time | 30.96 seconds |
| Started | Oct 12 03:02:47 PM UTC 24 |
| Finished | Oct 12 03:03:20 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786424207 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.2786424207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/39.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_zero_delays.1258805129 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 111843859 ps |
| CPU time | 6.14 seconds |
| Started | Oct 12 03:02:47 PM UTC 24 |
| Finished | Oct 12 03:02:54 PM UTC 24 |
| Peak memory | 212984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258805129 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.1258805129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/39.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_same_source.918054656 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 25790313 ps |
| CPU time | 1.85 seconds |
| Started | Oct 12 03:02:48 PM UTC 24 |
| Finished | Oct 12 03:02:50 PM UTC 24 |
| Peak memory | 211964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918054656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.918054656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/39.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke.454533917 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 103406833 ps |
| CPU time | 2.2 seconds |
| Started | Oct 12 03:02:43 PM UTC 24 |
| Finished | Oct 12 03:02:46 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454533917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.454533917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/39.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_large_delays.1105035815 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 12850204294 ps |
| CPU time | 16.46 seconds |
| Started | Oct 12 03:02:43 PM UTC 24 |
| Finished | Oct 12 03:03:01 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105035815 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.1105035815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/39.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.3794518264 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 2151002443 ps |
| CPU time | 19.17 seconds |
| Started | Oct 12 03:02:47 PM UTC 24 |
| Finished | Oct 12 03:03:08 PM UTC 24 |
| Peak memory | 212976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794518264 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.3794518264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.4283078571 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 10963712 ps |
| CPU time | 1.64 seconds |
| Started | Oct 12 03:02:43 PM UTC 24 |
| Finished | Oct 12 03:02:45 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283078571 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.4283078571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/39.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.1031216708 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 220384558 ps |
| CPU time | 22.14 seconds |
| Started | Oct 12 03:02:50 PM UTC 24 |
| Finished | Oct 12 03:03:13 PM UTC 24 |
| Peak memory | 213008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031216708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.1031216708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/39.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.3627443932 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 211234198 ps |
| CPU time | 10.22 seconds |
| Started | Oct 12 03:02:55 PM UTC 24 |
| Finished | Oct 12 03:03:07 PM UTC 24 |
| Peak memory | 210508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627443932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3627443932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/39.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.889223501 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 14180026840 ps |
| CPU time | 213.42 seconds |
| Started | Oct 12 03:02:52 PM UTC 24 |
| Finished | Oct 12 03:06:28 PM UTC 24 |
| Peak memory | 216620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889223501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.889223501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.785110625 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 595676850 ps |
| CPU time | 61.83 seconds |
| Started | Oct 12 03:02:55 PM UTC 24 |
| Finished | Oct 12 03:03:59 PM UTC 24 |
| Peak memory | 215016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785110625 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.785110625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_unmapped_addr.4122072950 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 51406839 ps |
| CPU time | 5.94 seconds |
| Started | Oct 12 03:02:50 PM UTC 24 |
| Finished | Oct 12 03:02:57 PM UTC 24 |
| Peak memory | 213084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122072950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.4122072950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/39.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device.2568995340 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 29497544 ps |
| CPU time | 8.05 seconds |
| Started | Oct 12 02:53:28 PM UTC 24 |
| Finished | Oct 12 02:53:37 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568995340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.2568995340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/4.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.3617493875 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 2364804952 ps |
| CPU time | 33.75 seconds |
| Started | Oct 12 02:53:29 PM UTC 24 |
| Finished | Oct 12 02:54:05 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617493875 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.3617493875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.1619014042 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 11483649 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 02:53:36 PM UTC 24 |
| Finished | Oct 12 02:53:38 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619014042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.1619014042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_error_random.2068733439 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1421487017 ps |
| CPU time | 17.78 seconds |
| Started | Oct 12 02:53:32 PM UTC 24 |
| Finished | Oct 12 02:53:51 PM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068733439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.2068733439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/4.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random.381219479 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 45307160 ps |
| CPU time | 6.77 seconds |
| Started | Oct 12 02:53:27 PM UTC 24 |
| Finished | Oct 12 02:53:35 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381219479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.381219479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/4.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_large_delays.2675207748 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 15696713777 ps |
| CPU time | 80.72 seconds |
| Started | Oct 12 02:53:28 PM UTC 24 |
| Finished | Oct 12 02:54:51 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675207748 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.2675207748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/4.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_slow_rsp.2713782556 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 7545869098 ps |
| CPU time | 77.49 seconds |
| Started | Oct 12 02:53:28 PM UTC 24 |
| Finished | Oct 12 02:54:48 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713782556 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.2713782556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/4.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_zero_delays.913335588 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 43893706 ps |
| CPU time | 7.07 seconds |
| Started | Oct 12 02:53:27 PM UTC 24 |
| Finished | Oct 12 02:53:35 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913335588 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.913335588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/4.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_same_source.3647515182 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 50907261 ps |
| CPU time | 5.57 seconds |
| Started | Oct 12 02:53:29 PM UTC 24 |
| Finished | Oct 12 02:53:36 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647515182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3647515182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/4.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke.1353229857 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 116769387 ps |
| CPU time | 2.25 seconds |
| Started | Oct 12 02:53:24 PM UTC 24 |
| Finished | Oct 12 02:53:27 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353229857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1353229857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/4.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_large_delays.2966587754 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 5089059690 ps |
| CPU time | 17.98 seconds |
| Started | Oct 12 02:53:27 PM UTC 24 |
| Finished | Oct 12 02:53:46 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966587754 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2966587754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/4.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.3725088411 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1290531653 ps |
| CPU time | 9.17 seconds |
| Started | Oct 12 02:53:27 PM UTC 24 |
| Finished | Oct 12 02:53:37 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725088411 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.3725088411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.2616784383 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 13692026 ps |
| CPU time | 1.87 seconds |
| Started | Oct 12 02:53:25 PM UTC 24 |
| Finished | Oct 12 02:53:28 PM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616784383 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.2616784383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/4.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all.2692764525 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 678525279 ps |
| CPU time | 16.08 seconds |
| Started | Oct 12 02:53:37 PM UTC 24 |
| Finished | Oct 12 02:53:54 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692764525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2692764525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/4.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_error.3379900788 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 6311783 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 02:53:38 PM UTC 24 |
| Finished | Oct 12 02:53:40 PM UTC 24 |
| Peak memory | 201156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379900788 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.3379900788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/4.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.4087038481 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 9247672289 ps |
| CPU time | 81.77 seconds |
| Started | Oct 12 02:53:38 PM UTC 24 |
| Finished | Oct 12 02:55:02 PM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087038481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.4087038481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.746591680 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 222873815 ps |
| CPU time | 12.53 seconds |
| Started | Oct 12 02:53:38 PM UTC 24 |
| Finished | Oct 12 02:53:52 PM UTC 24 |
| Peak memory | 212968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746591680 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.746591680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_unmapped_addr.3755847395 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 278638709 ps |
| CPU time | 4.4 seconds |
| Started | Oct 12 02:53:36 PM UTC 24 |
| Finished | Oct 12 02:53:41 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755847395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3755847395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/4.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device.1078907079 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 723737581 ps |
| CPU time | 6 seconds |
| Started | Oct 12 03:02:59 PM UTC 24 |
| Finished | Oct 12 03:03:06 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078907079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.1078907079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/40.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.343543460 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 17488558126 ps |
| CPU time | 155.32 seconds |
| Started | Oct 12 03:02:59 PM UTC 24 |
| Finished | Oct 12 03:05:37 PM UTC 24 |
| Peak memory | 213036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343543460 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.343543460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.698829148 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 439162368 ps |
| CPU time | 8.37 seconds |
| Started | Oct 12 03:03:03 PM UTC 24 |
| Finished | Oct 12 03:03:12 PM UTC 24 |
| Peak memory | 212968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698829148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.698829148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_error_random.2821915702 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 55813644 ps |
| CPU time | 2.25 seconds |
| Started | Oct 12 03:03:03 PM UTC 24 |
| Finished | Oct 12 03:03:06 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821915702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.2821915702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/40.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random.1439319103 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 1366013916 ps |
| CPU time | 11.15 seconds |
| Started | Oct 12 03:02:59 PM UTC 24 |
| Finished | Oct 12 03:03:11 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439319103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.1439319103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/40.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.1207695243 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 21730113823 ps |
| CPU time | 63.93 seconds |
| Started | Oct 12 03:02:59 PM UTC 24 |
| Finished | Oct 12 03:04:05 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207695243 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.1207695243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/40.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1401170308 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 23485379949 ps |
| CPU time | 64.92 seconds |
| Started | Oct 12 03:02:59 PM UTC 24 |
| Finished | Oct 12 03:04:06 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401170308 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1401170308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/40.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_zero_delays.1090363938 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 13890428 ps |
| CPU time | 1.6 seconds |
| Started | Oct 12 03:02:59 PM UTC 24 |
| Finished | Oct 12 03:03:02 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090363938 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.1090363938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/40.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_same_source.3048470617 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 2089121817 ps |
| CPU time | 13.72 seconds |
| Started | Oct 12 03:03:03 PM UTC 24 |
| Finished | Oct 12 03:03:18 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048470617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3048470617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/40.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke.2809845771 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 67845409 ps |
| CPU time | 1.8 seconds |
| Started | Oct 12 03:02:55 PM UTC 24 |
| Finished | Oct 12 03:02:59 PM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809845771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2809845771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/40.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_large_delays.4209371456 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 3797366354 ps |
| CPU time | 7.41 seconds |
| Started | Oct 12 03:02:59 PM UTC 24 |
| Finished | Oct 12 03:03:07 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209371456 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.4209371456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/40.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.1724257829 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 3192494274 ps |
| CPU time | 12.56 seconds |
| Started | Oct 12 03:02:59 PM UTC 24 |
| Finished | Oct 12 03:03:13 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724257829 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1724257829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.2782316761 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 7666354 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 03:02:55 PM UTC 24 |
| Finished | Oct 12 03:02:58 PM UTC 24 |
| Peak memory | 209600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782316761 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.2782316761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/40.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.1092957152 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 805077676 ps |
| CPU time | 14.12 seconds |
| Started | Oct 12 03:03:03 PM UTC 24 |
| Finished | Oct 12 03:03:18 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092957152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1092957152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/40.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.254982955 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 182053002 ps |
| CPU time | 12.7 seconds |
| Started | Oct 12 03:03:08 PM UTC 24 |
| Finished | Oct 12 03:03:22 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254982955 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.254982955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/40.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.538492793 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 1070807855 ps |
| CPU time | 102.55 seconds |
| Started | Oct 12 03:03:08 PM UTC 24 |
| Finished | Oct 12 03:04:53 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538492793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.538492793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.4127137343 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 315864474 ps |
| CPU time | 60.87 seconds |
| Started | Oct 12 03:03:11 PM UTC 24 |
| Finished | Oct 12 03:04:14 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127137343 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.4127137343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_unmapped_addr.1863138527 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 37603706 ps |
| CPU time | 4.8 seconds |
| Started | Oct 12 03:03:03 PM UTC 24 |
| Finished | Oct 12 03:03:09 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863138527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1863138527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/40.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device.2093169931 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 34850372 ps |
| CPU time | 6.24 seconds |
| Started | Oct 12 03:03:17 PM UTC 24 |
| Finished | Oct 12 03:03:24 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093169931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.2093169931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/41.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.800835605 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 37897075385 ps |
| CPU time | 78.38 seconds |
| Started | Oct 12 03:03:19 PM UTC 24 |
| Finished | Oct 12 03:04:40 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800835605 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.800835605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.2021374971 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 119247686 ps |
| CPU time | 5.71 seconds |
| Started | Oct 12 03:03:23 PM UTC 24 |
| Finished | Oct 12 03:03:30 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021374971 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.2021374971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_error_random.3420585134 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 124361910 ps |
| CPU time | 2.43 seconds |
| Started | Oct 12 03:03:20 PM UTC 24 |
| Finished | Oct 12 03:03:23 PM UTC 24 |
| Peak memory | 212936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420585134 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3420585134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/41.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random.4221830560 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 389541510 ps |
| CPU time | 8.02 seconds |
| Started | Oct 12 03:03:14 PM UTC 24 |
| Finished | Oct 12 03:03:23 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221830560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.4221830560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/41.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.1155000384 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 10100654749 ps |
| CPU time | 50.48 seconds |
| Started | Oct 12 03:03:17 PM UTC 24 |
| Finished | Oct 12 03:04:09 PM UTC 24 |
| Peak memory | 213012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155000384 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1155000384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/41.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.3277310321 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 19348683400 ps |
| CPU time | 96.72 seconds |
| Started | Oct 12 03:03:17 PM UTC 24 |
| Finished | Oct 12 03:04:55 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277310321 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.3277310321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/41.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_zero_delays.2857464518 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 32690735 ps |
| CPU time | 2.7 seconds |
| Started | Oct 12 03:03:17 PM UTC 24 |
| Finished | Oct 12 03:03:20 PM UTC 24 |
| Peak memory | 211040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857464518 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.2857464518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/41.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_same_source.3462116584 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 691037397 ps |
| CPU time | 12.96 seconds |
| Started | Oct 12 03:03:19 PM UTC 24 |
| Finished | Oct 12 03:03:34 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462116584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.3462116584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/41.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke.728861437 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 52660808 ps |
| CPU time | 2.1 seconds |
| Started | Oct 12 03:03:11 PM UTC 24 |
| Finished | Oct 12 03:03:15 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728861437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.728861437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/41.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_large_delays.1964293922 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 2275897980 ps |
| CPU time | 12.14 seconds |
| Started | Oct 12 03:03:12 PM UTC 24 |
| Finished | Oct 12 03:03:25 PM UTC 24 |
| Peak memory | 213020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964293922 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.1964293922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/41.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.2032329746 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 1703236561 ps |
| CPU time | 12.22 seconds |
| Started | Oct 12 03:03:14 PM UTC 24 |
| Finished | Oct 12 03:03:27 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032329746 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2032329746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.3976866726 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 12955382 ps |
| CPU time | 1.78 seconds |
| Started | Oct 12 03:03:12 PM UTC 24 |
| Finished | Oct 12 03:03:14 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976866726 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.3976866726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/41.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.1859956992 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 336348098 ps |
| CPU time | 15.98 seconds |
| Started | Oct 12 03:03:23 PM UTC 24 |
| Finished | Oct 12 03:03:40 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859956992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1859956992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/41.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.635564417 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 5545275827 ps |
| CPU time | 64.72 seconds |
| Started | Oct 12 03:03:23 PM UTC 24 |
| Finished | Oct 12 03:04:30 PM UTC 24 |
| Peak memory | 213036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635564417 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.635564417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/41.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1236896050 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4561478655 ps |
| CPU time | 144.54 seconds |
| Started | Oct 12 03:03:23 PM UTC 24 |
| Finished | Oct 12 03:05:50 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236896050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.1236896050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.743299542 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 8536537124 ps |
| CPU time | 196.48 seconds |
| Started | Oct 12 03:03:25 PM UTC 24 |
| Finished | Oct 12 03:06:45 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743299542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.743299542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_unmapped_addr.3543753072 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 3469312776 ps |
| CPU time | 11.89 seconds |
| Started | Oct 12 03:03:23 PM UTC 24 |
| Finished | Oct 12 03:03:36 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543753072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3543753072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/41.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device.3463721112 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 1850659693 ps |
| CPU time | 10.52 seconds |
| Started | Oct 12 03:03:32 PM UTC 24 |
| Finished | Oct 12 03:03:44 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463721112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.3463721112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/42.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.1813046659 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 3064809006 ps |
| CPU time | 26.68 seconds |
| Started | Oct 12 03:03:32 PM UTC 24 |
| Finished | Oct 12 03:04:00 PM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813046659 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.1813046659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.4242531028 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 25842196 ps |
| CPU time | 2.53 seconds |
| Started | Oct 12 03:03:36 PM UTC 24 |
| Finished | Oct 12 03:03:40 PM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242531028 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.4242531028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_error_random.3924978609 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 55817945 ps |
| CPU time | 6.53 seconds |
| Started | Oct 12 03:03:34 PM UTC 24 |
| Finished | Oct 12 03:03:42 PM UTC 24 |
| Peak memory | 211028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924978609 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3924978609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/42.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random.2659804809 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 56744281 ps |
| CPU time | 4.32 seconds |
| Started | Oct 12 03:03:30 PM UTC 24 |
| Finished | Oct 12 03:03:35 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659804809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2659804809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/42.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.2638370702 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 12652853567 ps |
| CPU time | 42.88 seconds |
| Started | Oct 12 03:03:30 PM UTC 24 |
| Finished | Oct 12 03:04:14 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638370702 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2638370702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/42.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.3652247938 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 13105409481 ps |
| CPU time | 43.5 seconds |
| Started | Oct 12 03:03:32 PM UTC 24 |
| Finished | Oct 12 03:04:17 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652247938 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.3652247938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/42.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_zero_delays.2002477175 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 14985332 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 03:03:30 PM UTC 24 |
| Finished | Oct 12 03:03:32 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002477175 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.2002477175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/42.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_same_source.1700234136 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 4047714337 ps |
| CPU time | 12.51 seconds |
| Started | Oct 12 03:03:34 PM UTC 24 |
| Finished | Oct 12 03:03:48 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700234136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.1700234136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/42.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke.323127427 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 37039809 ps |
| CPU time | 2.07 seconds |
| Started | Oct 12 03:03:25 PM UTC 24 |
| Finished | Oct 12 03:03:28 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323127427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.323127427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/42.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_large_delays.2841550889 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 5256240614 ps |
| CPU time | 7.93 seconds |
| Started | Oct 12 03:03:28 PM UTC 24 |
| Finished | Oct 12 03:03:37 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841550889 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.2841550889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/42.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.4108620828 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 3192652856 ps |
| CPU time | 10.16 seconds |
| Started | Oct 12 03:03:28 PM UTC 24 |
| Finished | Oct 12 03:03:39 PM UTC 24 |
| Peak memory | 213004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108620828 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.4108620828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.3912449697 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 12717182 ps |
| CPU time | 1.69 seconds |
| Started | Oct 12 03:03:25 PM UTC 24 |
| Finished | Oct 12 03:03:28 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912449697 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.3912449697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/42.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.1087538761 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 1250582726 ps |
| CPU time | 33.36 seconds |
| Started | Oct 12 03:03:39 PM UTC 24 |
| Finished | Oct 12 03:04:14 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087538761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1087538761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/42.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.4041847326 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 23011393155 ps |
| CPU time | 58.8 seconds |
| Started | Oct 12 03:03:42 PM UTC 24 |
| Finished | Oct 12 03:04:42 PM UTC 24 |
| Peak memory | 213004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041847326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.4041847326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/42.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.4224262804 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 8648208533 ps |
| CPU time | 104.23 seconds |
| Started | Oct 12 03:03:39 PM UTC 24 |
| Finished | Oct 12 03:05:25 PM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224262804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.4224262804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.190990325 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 4948702498 ps |
| CPU time | 108.55 seconds |
| Started | Oct 12 03:03:42 PM UTC 24 |
| Finished | Oct 12 03:05:32 PM UTC 24 |
| Peak memory | 217128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190990325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.190990325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_unmapped_addr.2718160912 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 135409137 ps |
| CPU time | 2.3 seconds |
| Started | Oct 12 03:03:36 PM UTC 24 |
| Finished | Oct 12 03:03:40 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718160912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2718160912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/42.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.3580724574 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 195439689 ps |
| CPU time | 4.33 seconds |
| Started | Oct 12 03:03:51 PM UTC 24 |
| Finished | Oct 12 03:03:56 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580724574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.3580724574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/43.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.458172597 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 13304910944 ps |
| CPU time | 79.25 seconds |
| Started | Oct 12 03:03:54 PM UTC 24 |
| Finished | Oct 12 03:05:15 PM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458172597 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.458172597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.959243667 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 142517987 ps |
| CPU time | 3.78 seconds |
| Started | Oct 12 03:03:58 PM UTC 24 |
| Finished | Oct 12 03:04:03 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959243667 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.959243667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random.1448096446 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 33392514 ps |
| CPU time | 4.15 seconds |
| Started | Oct 12 03:03:46 PM UTC 24 |
| Finished | Oct 12 03:03:51 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448096446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.1448096446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/43.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.204912796 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 5182476391 ps |
| CPU time | 23.96 seconds |
| Started | Oct 12 03:03:50 PM UTC 24 |
| Finished | Oct 12 03:04:16 PM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204912796 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.204912796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/43.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3078229252 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 3281762265 ps |
| CPU time | 16.97 seconds |
| Started | Oct 12 03:03:50 PM UTC 24 |
| Finished | Oct 12 03:04:09 PM UTC 24 |
| Peak memory | 212984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078229252 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3078229252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/43.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.3391490965 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 61276792 ps |
| CPU time | 10.67 seconds |
| Started | Oct 12 03:03:48 PM UTC 24 |
| Finished | Oct 12 03:03:59 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391490965 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.3391490965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/43.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.2558536303 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 1421103437 ps |
| CPU time | 16.21 seconds |
| Started | Oct 12 03:03:54 PM UTC 24 |
| Finished | Oct 12 03:04:11 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558536303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.2558536303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/43.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke.3728308764 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 8254179 ps |
| CPU time | 1.58 seconds |
| Started | Oct 12 03:03:42 PM UTC 24 |
| Finished | Oct 12 03:03:44 PM UTC 24 |
| Peak memory | 209864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728308764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3728308764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/43.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.1179489063 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 3204809520 ps |
| CPU time | 12.49 seconds |
| Started | Oct 12 03:03:44 PM UTC 24 |
| Finished | Oct 12 03:03:57 PM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179489063 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1179489063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/43.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.28299287 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 1532766695 ps |
| CPU time | 14.42 seconds |
| Started | Oct 12 03:03:46 PM UTC 24 |
| Finished | Oct 12 03:04:02 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28299287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.28299287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.1053624219 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 11150600 ps |
| CPU time | 1.79 seconds |
| Started | Oct 12 03:03:44 PM UTC 24 |
| Finished | Oct 12 03:03:46 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053624219 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.1053624219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/43.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.2961499557 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 63746259 ps |
| CPU time | 5.34 seconds |
| Started | Oct 12 03:03:59 PM UTC 24 |
| Finished | Oct 12 03:04:06 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961499557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2961499557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/43.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1936125313 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 5962891 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 03:04:02 PM UTC 24 |
| Finished | Oct 12 03:04:04 PM UTC 24 |
| Peak memory | 201308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936125313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1936125313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/43.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.4079673587 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 3806081857 ps |
| CPU time | 83.42 seconds |
| Started | Oct 12 03:04:02 PM UTC 24 |
| Finished | Oct 12 03:05:27 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079673587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.4079673587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.648155901 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 5638016375 ps |
| CPU time | 124.51 seconds |
| Started | Oct 12 03:04:02 PM UTC 24 |
| Finished | Oct 12 03:06:09 PM UTC 24 |
| Peak memory | 215196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648155901 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.648155901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.3819638472 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 1031992833 ps |
| CPU time | 7.87 seconds |
| Started | Oct 12 03:03:54 PM UTC 24 |
| Finished | Oct 12 03:04:03 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819638472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.3819638472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/43.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.3121982534 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 548888702 ps |
| CPU time | 12.43 seconds |
| Started | Oct 12 03:04:11 PM UTC 24 |
| Finished | Oct 12 03:04:24 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121982534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.3121982534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/44.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.1358061816 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 6232625070 ps |
| CPU time | 17.93 seconds |
| Started | Oct 12 03:04:11 PM UTC 24 |
| Finished | Oct 12 03:04:30 PM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358061816 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.1358061816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.1436074251 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 84581882 ps |
| CPU time | 5.31 seconds |
| Started | Oct 12 03:04:14 PM UTC 24 |
| Finished | Oct 12 03:04:20 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436074251 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.1436074251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.1387397078 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 121122552 ps |
| CPU time | 6.31 seconds |
| Started | Oct 12 03:04:11 PM UTC 24 |
| Finished | Oct 12 03:04:18 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387397078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1387397078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/44.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random.2552174881 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 851434372 ps |
| CPU time | 15.07 seconds |
| Started | Oct 12 03:04:06 PM UTC 24 |
| Finished | Oct 12 03:04:22 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552174881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.2552174881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/44.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.2818464632 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 4797316875 ps |
| CPU time | 16.82 seconds |
| Started | Oct 12 03:04:11 PM UTC 24 |
| Finished | Oct 12 03:04:29 PM UTC 24 |
| Peak memory | 211040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818464632 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2818464632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/44.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.2065967308 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 5800076513 ps |
| CPU time | 47.6 seconds |
| Started | Oct 12 03:04:11 PM UTC 24 |
| Finished | Oct 12 03:05:00 PM UTC 24 |
| Peak memory | 211032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065967308 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.2065967308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/44.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.490941119 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 37593070 ps |
| CPU time | 6.15 seconds |
| Started | Oct 12 03:04:11 PM UTC 24 |
| Finished | Oct 12 03:04:18 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490941119 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.490941119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/44.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.1750525154 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 175690121 ps |
| CPU time | 4.74 seconds |
| Started | Oct 12 03:04:11 PM UTC 24 |
| Finished | Oct 12 03:04:17 PM UTC 24 |
| Peak memory | 212920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750525154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1750525154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/44.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.1410575398 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 13915552 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 03:04:06 PM UTC 24 |
| Finished | Oct 12 03:04:08 PM UTC 24 |
| Peak memory | 209860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410575398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1410575398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/44.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.904782095 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 3220061872 ps |
| CPU time | 8.9 seconds |
| Started | Oct 12 03:04:06 PM UTC 24 |
| Finished | Oct 12 03:04:16 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904782095 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.904782095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/44.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.3480638899 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2863437085 ps |
| CPU time | 6.33 seconds |
| Started | Oct 12 03:04:06 PM UTC 24 |
| Finished | Oct 12 03:04:14 PM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480638899 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.3480638899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.4073053082 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 10164120 ps |
| CPU time | 1.81 seconds |
| Started | Oct 12 03:04:06 PM UTC 24 |
| Finished | Oct 12 03:04:09 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073053082 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.4073053082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/44.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.4000583784 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 2139866992 ps |
| CPU time | 44.27 seconds |
| Started | Oct 12 03:04:14 PM UTC 24 |
| Finished | Oct 12 03:04:59 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000583784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.4000583784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/44.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2176840505 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 5132356613 ps |
| CPU time | 66.85 seconds |
| Started | Oct 12 03:04:20 PM UTC 24 |
| Finished | Oct 12 03:05:29 PM UTC 24 |
| Peak memory | 213012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176840505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2176840505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/44.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.2584858130 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 1075137555 ps |
| CPU time | 88.72 seconds |
| Started | Oct 12 03:04:20 PM UTC 24 |
| Finished | Oct 12 03:05:51 PM UTC 24 |
| Peak memory | 214988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584858130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.2584858130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.1657896705 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 739191966 ps |
| CPU time | 162.19 seconds |
| Started | Oct 12 03:04:20 PM UTC 24 |
| Finished | Oct 12 03:07:05 PM UTC 24 |
| Peak memory | 219528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657896705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.1657896705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.1040015999 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 1242872072 ps |
| CPU time | 9.67 seconds |
| Started | Oct 12 03:04:14 PM UTC 24 |
| Finished | Oct 12 03:04:24 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040015999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.1040015999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/44.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.687237894 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 54056693 ps |
| CPU time | 15.69 seconds |
| Started | Oct 12 03:04:23 PM UTC 24 |
| Finished | Oct 12 03:04:40 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687237894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.687237894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/45.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.3460004793 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 24746051313 ps |
| CPU time | 122.9 seconds |
| Started | Oct 12 03:04:26 PM UTC 24 |
| Finished | Oct 12 03:06:31 PM UTC 24 |
| Peak memory | 213084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460004793 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.3460004793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.3201367170 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 605340333 ps |
| CPU time | 4.66 seconds |
| Started | Oct 12 03:04:29 PM UTC 24 |
| Finished | Oct 12 03:04:35 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201367170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.3201367170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.615235575 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 39471241 ps |
| CPU time | 5.4 seconds |
| Started | Oct 12 03:04:26 PM UTC 24 |
| Finished | Oct 12 03:04:32 PM UTC 24 |
| Peak memory | 212948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615235575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.615235575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/45.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random.3860686373 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 95008318 ps |
| CPU time | 9.68 seconds |
| Started | Oct 12 03:04:20 PM UTC 24 |
| Finished | Oct 12 03:04:31 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860686373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.3860686373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/45.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.3174721000 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 37726427604 ps |
| CPU time | 58.54 seconds |
| Started | Oct 12 03:04:23 PM UTC 24 |
| Finished | Oct 12 03:05:23 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174721000 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3174721000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/45.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.4141784720 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 8938335670 ps |
| CPU time | 39.97 seconds |
| Started | Oct 12 03:04:23 PM UTC 24 |
| Finished | Oct 12 03:05:04 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141784720 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.4141784720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/45.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.3266774541 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 15641758 ps |
| CPU time | 1.66 seconds |
| Started | Oct 12 03:04:20 PM UTC 24 |
| Finished | Oct 12 03:04:23 PM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266774541 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.3266774541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/45.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.1151039802 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 1695717542 ps |
| CPU time | 9.61 seconds |
| Started | Oct 12 03:04:26 PM UTC 24 |
| Finished | Oct 12 03:04:37 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151039802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1151039802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/45.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.715898832 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 70825113 ps |
| CPU time | 2.14 seconds |
| Started | Oct 12 03:04:20 PM UTC 24 |
| Finished | Oct 12 03:04:23 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715898832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.715898832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/45.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.3571408195 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 11134269113 ps |
| CPU time | 15.72 seconds |
| Started | Oct 12 03:04:20 PM UTC 24 |
| Finished | Oct 12 03:04:37 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571408195 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.3571408195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/45.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.2296041390 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 2503137849 ps |
| CPU time | 10.89 seconds |
| Started | Oct 12 03:04:20 PM UTC 24 |
| Finished | Oct 12 03:04:32 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296041390 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.2296041390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.3301645574 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 10834673 ps |
| CPU time | 1.51 seconds |
| Started | Oct 12 03:04:20 PM UTC 24 |
| Finished | Oct 12 03:04:23 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301645574 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.3301645574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/45.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.3485374492 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 15156744710 ps |
| CPU time | 104.58 seconds |
| Started | Oct 12 03:04:29 PM UTC 24 |
| Finished | Oct 12 03:06:16 PM UTC 24 |
| Peak memory | 213092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485374492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3485374492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/45.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.811493224 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 7183486787 ps |
| CPU time | 99.27 seconds |
| Started | Oct 12 03:04:31 PM UTC 24 |
| Finished | Oct 12 03:06:12 PM UTC 24 |
| Peak memory | 213092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811493224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.811493224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/45.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.331492819 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 235985072 ps |
| CPU time | 20.38 seconds |
| Started | Oct 12 03:04:29 PM UTC 24 |
| Finished | Oct 12 03:04:51 PM UTC 24 |
| Peak memory | 212968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331492819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.331492819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.606188190 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 1117900132 ps |
| CPU time | 111.8 seconds |
| Started | Oct 12 03:04:31 PM UTC 24 |
| Finished | Oct 12 03:06:25 PM UTC 24 |
| Peak memory | 217068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606188190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.606188190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.2142465354 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 70762793 ps |
| CPU time | 8.39 seconds |
| Started | Oct 12 03:04:26 PM UTC 24 |
| Finished | Oct 12 03:04:35 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142465354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.2142465354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/45.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.155752048 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 914174887 ps |
| CPU time | 4.52 seconds |
| Started | Oct 12 03:04:41 PM UTC 24 |
| Finished | Oct 12 03:04:47 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155752048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.155752048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/46.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1034366893 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 6802235898 ps |
| CPU time | 39.76 seconds |
| Started | Oct 12 03:04:41 PM UTC 24 |
| Finished | Oct 12 03:05:23 PM UTC 24 |
| Peak memory | 213080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034366893 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.1034366893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.3405134627 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 242683769 ps |
| CPU time | 4.22 seconds |
| Started | Oct 12 03:04:45 PM UTC 24 |
| Finished | Oct 12 03:04:51 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405134627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.3405134627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.2942753186 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 103068899 ps |
| CPU time | 7.35 seconds |
| Started | Oct 12 03:04:42 PM UTC 24 |
| Finished | Oct 12 03:04:50 PM UTC 24 |
| Peak memory | 211024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942753186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2942753186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/46.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random.3252078084 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 419164215 ps |
| CPU time | 7.58 seconds |
| Started | Oct 12 03:04:38 PM UTC 24 |
| Finished | Oct 12 03:04:47 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252078084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.3252078084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/46.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.1117688780 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 65151421450 ps |
| CPU time | 73.66 seconds |
| Started | Oct 12 03:04:38 PM UTC 24 |
| Finished | Oct 12 03:05:54 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117688780 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1117688780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/46.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.2073027959 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 10920091891 ps |
| CPU time | 52.23 seconds |
| Started | Oct 12 03:04:38 PM UTC 24 |
| Finished | Oct 12 03:05:32 PM UTC 24 |
| Peak memory | 212988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073027959 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2073027959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/46.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.3266233836 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 40823263 ps |
| CPU time | 5.82 seconds |
| Started | Oct 12 03:04:38 PM UTC 24 |
| Finished | Oct 12 03:04:45 PM UTC 24 |
| Peak memory | 213020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266233836 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.3266233836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/46.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.211095490 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 370848902 ps |
| CPU time | 7.07 seconds |
| Started | Oct 12 03:04:42 PM UTC 24 |
| Finished | Oct 12 03:04:50 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211095490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.211095490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/46.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.1709932072 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 15146181 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 03:04:34 PM UTC 24 |
| Finished | Oct 12 03:04:36 PM UTC 24 |
| Peak memory | 209864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709932072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.1709932072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/46.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.3703890663 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 6584040946 ps |
| CPU time | 7.13 seconds |
| Started | Oct 12 03:04:34 PM UTC 24 |
| Finished | Oct 12 03:04:42 PM UTC 24 |
| Peak memory | 213068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703890663 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.3703890663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/46.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.3704011541 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 2590618991 ps |
| CPU time | 22.96 seconds |
| Started | Oct 12 03:04:35 PM UTC 24 |
| Finished | Oct 12 03:05:00 PM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704011541 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.3704011541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.469809435 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 9165002 ps |
| CPU time | 1.76 seconds |
| Started | Oct 12 03:04:34 PM UTC 24 |
| Finished | Oct 12 03:04:36 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469809435 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.469809435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/46.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.577985137 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 22509464316 ps |
| CPU time | 124.76 seconds |
| Started | Oct 12 03:04:45 PM UTC 24 |
| Finished | Oct 12 03:06:52 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577985137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.577985137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/46.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.3436194945 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 487420840 ps |
| CPU time | 42.05 seconds |
| Started | Oct 12 03:04:47 PM UTC 24 |
| Finished | Oct 12 03:05:31 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436194945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.3436194945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/46.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.648362499 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 557429205 ps |
| CPU time | 59.69 seconds |
| Started | Oct 12 03:04:45 PM UTC 24 |
| Finished | Oct 12 03:05:47 PM UTC 24 |
| Peak memory | 215012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648362499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.648362499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.1013268176 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 11536929981 ps |
| CPU time | 118.62 seconds |
| Started | Oct 12 03:04:49 PM UTC 24 |
| Finished | Oct 12 03:06:50 PM UTC 24 |
| Peak memory | 217200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013268176 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.1013268176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.1146359696 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 692173216 ps |
| CPU time | 6.34 seconds |
| Started | Oct 12 03:04:45 PM UTC 24 |
| Finished | Oct 12 03:04:53 PM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146359696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1146359696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/46.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.4139527750 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 54869380 ps |
| CPU time | 5.56 seconds |
| Started | Oct 12 03:04:56 PM UTC 24 |
| Finished | Oct 12 03:05:03 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139527750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.4139527750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/47.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.1497163405 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 15881917501 ps |
| CPU time | 117.51 seconds |
| Started | Oct 12 03:04:58 PM UTC 24 |
| Finished | Oct 12 03:06:58 PM UTC 24 |
| Peak memory | 213004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497163405 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.1497163405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.1455206983 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 1359186542 ps |
| CPU time | 7.72 seconds |
| Started | Oct 12 03:05:05 PM UTC 24 |
| Finished | Oct 12 03:05:13 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455206983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.1455206983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.1447257146 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 88268305 ps |
| CPU time | 2.48 seconds |
| Started | Oct 12 03:05:01 PM UTC 24 |
| Finished | Oct 12 03:05:05 PM UTC 24 |
| Peak memory | 210884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447257146 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1447257146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/47.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random.2926974453 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 921873959 ps |
| CPU time | 10.25 seconds |
| Started | Oct 12 03:04:53 PM UTC 24 |
| Finished | Oct 12 03:05:04 PM UTC 24 |
| Peak memory | 211024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926974453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.2926974453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/47.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.2025483706 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 26081254059 ps |
| CPU time | 87.39 seconds |
| Started | Oct 12 03:04:56 PM UTC 24 |
| Finished | Oct 12 03:06:25 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025483706 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.2025483706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/47.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1043588498 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 2246256144 ps |
| CPU time | 14.75 seconds |
| Started | Oct 12 03:04:56 PM UTC 24 |
| Finished | Oct 12 03:05:12 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043588498 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1043588498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/47.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.2563146201 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 51458492 ps |
| CPU time | 7.75 seconds |
| Started | Oct 12 03:04:53 PM UTC 24 |
| Finished | Oct 12 03:05:02 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563146201 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.2563146201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/47.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.2641084006 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 34834320 ps |
| CPU time | 3.18 seconds |
| Started | Oct 12 03:04:58 PM UTC 24 |
| Finished | Oct 12 03:05:02 PM UTC 24 |
| Peak memory | 212936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641084006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2641084006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/47.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.2652353438 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 13290853 ps |
| CPU time | 1.82 seconds |
| Started | Oct 12 03:04:49 PM UTC 24 |
| Finished | Oct 12 03:04:52 PM UTC 24 |
| Peak memory | 209864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652353438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.2652353438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/47.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2352734540 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 6595100249 ps |
| CPU time | 13.48 seconds |
| Started | Oct 12 03:04:53 PM UTC 24 |
| Finished | Oct 12 03:05:07 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352734540 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2352734540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/47.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3671972888 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 1105089525 ps |
| CPU time | 12.31 seconds |
| Started | Oct 12 03:04:53 PM UTC 24 |
| Finished | Oct 12 03:05:06 PM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671972888 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3671972888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1065345703 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 15863742 ps |
| CPU time | 1.84 seconds |
| Started | Oct 12 03:04:53 PM UTC 24 |
| Finished | Oct 12 03:04:56 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065345703 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.1065345703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/47.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.37288824 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 6793180483 ps |
| CPU time | 76.72 seconds |
| Started | Oct 12 03:05:05 PM UTC 24 |
| Finished | Oct 12 03:06:23 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37288824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-si m-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.37288824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/47.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2839781790 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 685750994 ps |
| CPU time | 15.15 seconds |
| Started | Oct 12 03:05:05 PM UTC 24 |
| Finished | Oct 12 03:05:21 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839781790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.2839781790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/47.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2871853325 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 449696387 ps |
| CPU time | 78.1 seconds |
| Started | Oct 12 03:05:05 PM UTC 24 |
| Finished | Oct 12 03:06:25 PM UTC 24 |
| Peak memory | 215012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871853325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.2871853325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.269069584 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 872676653 ps |
| CPU time | 123.83 seconds |
| Started | Oct 12 03:05:07 PM UTC 24 |
| Finished | Oct 12 03:07:14 PM UTC 24 |
| Peak memory | 217068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269069584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.269069584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.2950471216 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 1195194742 ps |
| CPU time | 8.46 seconds |
| Started | Oct 12 03:05:01 PM UTC 24 |
| Finished | Oct 12 03:05:11 PM UTC 24 |
| Peak memory | 212940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950471216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2950471216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/47.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.2635755123 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 121358350 ps |
| CPU time | 7.23 seconds |
| Started | Oct 12 03:05:16 PM UTC 24 |
| Finished | Oct 12 03:05:24 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635755123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.2635755123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/48.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.1589523091 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 50992539208 ps |
| CPU time | 104.87 seconds |
| Started | Oct 12 03:05:19 PM UTC 24 |
| Finished | Oct 12 03:07:06 PM UTC 24 |
| Peak memory | 213020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589523091 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.1589523091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.481466910 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 689474760 ps |
| CPU time | 14.65 seconds |
| Started | Oct 12 03:05:22 PM UTC 24 |
| Finished | Oct 12 03:05:38 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481466910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.481466910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.2782914272 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 717777190 ps |
| CPU time | 4.43 seconds |
| Started | Oct 12 03:05:19 PM UTC 24 |
| Finished | Oct 12 03:05:24 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782914272 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2782914272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/48.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random.513248645 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 27061681 ps |
| CPU time | 3.08 seconds |
| Started | Oct 12 03:05:13 PM UTC 24 |
| Finished | Oct 12 03:05:17 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513248645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.513248645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/48.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.1507446436 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 24847679646 ps |
| CPU time | 70.19 seconds |
| Started | Oct 12 03:05:13 PM UTC 24 |
| Finished | Oct 12 03:06:25 PM UTC 24 |
| Peak memory | 213088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507446436 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1507446436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/48.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3278928986 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 14285642261 ps |
| CPU time | 47.3 seconds |
| Started | Oct 12 03:05:16 PM UTC 24 |
| Finished | Oct 12 03:06:04 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278928986 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3278928986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/48.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.618926358 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 30451735 ps |
| CPU time | 4.1 seconds |
| Started | Oct 12 03:05:13 PM UTC 24 |
| Finished | Oct 12 03:05:18 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618926358 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.618926358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/48.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.658185360 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 802102000 ps |
| CPU time | 14.45 seconds |
| Started | Oct 12 03:05:19 PM UTC 24 |
| Finished | Oct 12 03:05:34 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658185360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.658185360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/48.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.1020988730 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 80484357 ps |
| CPU time | 2.36 seconds |
| Started | Oct 12 03:05:08 PM UTC 24 |
| Finished | Oct 12 03:05:11 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020988730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.1020988730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/48.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1530637483 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 3157114251 ps |
| CPU time | 22.43 seconds |
| Started | Oct 12 03:05:10 PM UTC 24 |
| Finished | Oct 12 03:05:34 PM UTC 24 |
| Peak memory | 212996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530637483 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.1530637483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/48.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.3967174339 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 1022438275 ps |
| CPU time | 5.53 seconds |
| Started | Oct 12 03:05:10 PM UTC 24 |
| Finished | Oct 12 03:05:17 PM UTC 24 |
| Peak memory | 212952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967174339 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3967174339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2433204705 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 9018779 ps |
| CPU time | 1.65 seconds |
| Started | Oct 12 03:05:08 PM UTC 24 |
| Finished | Oct 12 03:05:10 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433204705 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.2433204705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/48.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.3264512566 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 349424094 ps |
| CPU time | 25.28 seconds |
| Started | Oct 12 03:05:26 PM UTC 24 |
| Finished | Oct 12 03:05:52 PM UTC 24 |
| Peak memory | 212920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264512566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3264512566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/48.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.838252245 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 6518639872 ps |
| CPU time | 36.18 seconds |
| Started | Oct 12 03:05:26 PM UTC 24 |
| Finished | Oct 12 03:06:03 PM UTC 24 |
| Peak memory | 213092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838252245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.838252245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/48.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.1141029014 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 6765573203 ps |
| CPU time | 61.2 seconds |
| Started | Oct 12 03:05:26 PM UTC 24 |
| Finished | Oct 12 03:06:29 PM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141029014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.1141029014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.2057141312 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 981005539 ps |
| CPU time | 26.15 seconds |
| Started | Oct 12 03:05:26 PM UTC 24 |
| Finished | Oct 12 03:05:53 PM UTC 24 |
| Peak memory | 212976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057141312 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.2057141312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.3966880185 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 3033628025 ps |
| CPU time | 14.93 seconds |
| Started | Oct 12 03:05:21 PM UTC 24 |
| Finished | Oct 12 03:05:37 PM UTC 24 |
| Peak memory | 213020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966880185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3966880185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/48.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.3550760544 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 180484305 ps |
| CPU time | 9.49 seconds |
| Started | Oct 12 03:05:38 PM UTC 24 |
| Finished | Oct 12 03:05:49 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550760544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.3550760544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/49.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.770811689 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 89233256717 ps |
| CPU time | 147.38 seconds |
| Started | Oct 12 03:05:38 PM UTC 24 |
| Finished | Oct 12 03:08:08 PM UTC 24 |
| Peak memory | 216584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770811689 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.770811689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2875220431 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 503734879 ps |
| CPU time | 6.78 seconds |
| Started | Oct 12 03:05:45 PM UTC 24 |
| Finished | Oct 12 03:05:52 PM UTC 24 |
| Peak memory | 212956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875220431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.2875220431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.3558966413 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 4517742230 ps |
| CPU time | 10.96 seconds |
| Started | Oct 12 03:05:41 PM UTC 24 |
| Finished | Oct 12 03:05:53 PM UTC 24 |
| Peak memory | 211024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558966413 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3558966413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/49.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random.3108733641 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 392416526 ps |
| CPU time | 7.98 seconds |
| Started | Oct 12 03:05:35 PM UTC 24 |
| Finished | Oct 12 03:05:44 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108733641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.3108733641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/49.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.4010208735 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 27461234390 ps |
| CPU time | 70.49 seconds |
| Started | Oct 12 03:05:35 PM UTC 24 |
| Finished | Oct 12 03:06:47 PM UTC 24 |
| Peak memory | 213056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010208735 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.4010208735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/49.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.1999302634 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 5555237146 ps |
| CPU time | 47.69 seconds |
| Started | Oct 12 03:05:38 PM UTC 24 |
| Finished | Oct 12 03:06:28 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999302634 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.1999302634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/49.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.3676182418 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 88114138 ps |
| CPU time | 7.12 seconds |
| Started | Oct 12 03:05:35 PM UTC 24 |
| Finished | Oct 12 03:05:43 PM UTC 24 |
| Peak memory | 212988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676182418 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.3676182418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/49.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.4069303278 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 411761629 ps |
| CPU time | 7.8 seconds |
| Started | Oct 12 03:05:38 PM UTC 24 |
| Finished | Oct 12 03:05:47 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069303278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.4069303278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/49.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.498357480 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 14091866 ps |
| CPU time | 1.5 seconds |
| Started | Oct 12 03:05:28 PM UTC 24 |
| Finished | Oct 12 03:05:30 PM UTC 24 |
| Peak memory | 211968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498357480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.498357480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/49.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.1230827557 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 2136932807 ps |
| CPU time | 16.34 seconds |
| Started | Oct 12 03:05:30 PM UTC 24 |
| Finished | Oct 12 03:05:47 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230827557 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1230827557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/49.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.2666162115 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 2744744654 ps |
| CPU time | 12.71 seconds |
| Started | Oct 12 03:05:31 PM UTC 24 |
| Finished | Oct 12 03:05:45 PM UTC 24 |
| Peak memory | 211032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666162115 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.2666162115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.4245486193 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 9578206 ps |
| CPU time | 1.81 seconds |
| Started | Oct 12 03:05:30 PM UTC 24 |
| Finished | Oct 12 03:05:32 PM UTC 24 |
| Peak memory | 211968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245486193 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.4245486193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/49.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.3704965347 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 5129297601 ps |
| CPU time | 47.5 seconds |
| Started | Oct 12 03:05:47 PM UTC 24 |
| Finished | Oct 12 03:06:37 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704965347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3704965347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/49.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.3809400812 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 7207151352 ps |
| CPU time | 61 seconds |
| Started | Oct 12 03:05:47 PM UTC 24 |
| Finished | Oct 12 03:06:50 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809400812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.3809400812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/49.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.3819280211 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 475716769 ps |
| CPU time | 55.27 seconds |
| Started | Oct 12 03:05:47 PM UTC 24 |
| Finished | Oct 12 03:06:44 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819280211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.3819280211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.4056950138 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 190014929 ps |
| CPU time | 24.69 seconds |
| Started | Oct 12 03:05:51 PM UTC 24 |
| Finished | Oct 12 03:06:17 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056950138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.4056950138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.3037818299 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 97462127 ps |
| CPU time | 3.01 seconds |
| Started | Oct 12 03:05:41 PM UTC 24 |
| Finished | Oct 12 03:05:45 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037818299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3037818299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/49.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device.1182308400 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 122742860 ps |
| CPU time | 13.26 seconds |
| Started | Oct 12 02:53:45 PM UTC 24 |
| Finished | Oct 12 02:53:59 PM UTC 24 |
| Peak memory | 213036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182308400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1182308400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/5.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.2319852278 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 36137090 ps |
| CPU time | 3.65 seconds |
| Started | Oct 12 02:53:50 PM UTC 24 |
| Finished | Oct 12 02:53:55 PM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319852278 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.2319852278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_error_random.280784338 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 2813195598 ps |
| CPU time | 12.49 seconds |
| Started | Oct 12 02:53:48 PM UTC 24 |
| Finished | Oct 12 02:54:02 PM UTC 24 |
| Peak memory | 211088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280784338 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.280784338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/5.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random.3237504112 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 55611205 ps |
| CPU time | 2.34 seconds |
| Started | Oct 12 02:53:42 PM UTC 24 |
| Finished | Oct 12 02:53:46 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237504112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.3237504112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/5.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_large_delays.3717740457 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 11379042433 ps |
| CPU time | 45.59 seconds |
| Started | Oct 12 02:53:44 PM UTC 24 |
| Finished | Oct 12 02:54:31 PM UTC 24 |
| Peak memory | 213048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717740457 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3717740457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/5.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_slow_rsp.1460901115 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 4958748200 ps |
| CPU time | 37.4 seconds |
| Started | Oct 12 02:53:45 PM UTC 24 |
| Finished | Oct 12 02:54:24 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460901115 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.1460901115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/5.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_zero_delays.840910142 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 65373870 ps |
| CPU time | 6.4 seconds |
| Started | Oct 12 02:53:43 PM UTC 24 |
| Finished | Oct 12 02:53:50 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840910142 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.840910142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/5.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_same_source.417172183 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 112539555 ps |
| CPU time | 8.07 seconds |
| Started | Oct 12 02:53:47 PM UTC 24 |
| Finished | Oct 12 02:53:56 PM UTC 24 |
| Peak memory | 213000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417172183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.417172183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/5.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke.1675557454 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 96712297 ps |
| CPU time | 2.28 seconds |
| Started | Oct 12 02:53:39 PM UTC 24 |
| Finished | Oct 12 02:53:42 PM UTC 24 |
| Peak memory | 212920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675557454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.1675557454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/5.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_large_delays.3290722657 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 2509355453 ps |
| CPU time | 20.03 seconds |
| Started | Oct 12 02:53:41 PM UTC 24 |
| Finished | Oct 12 02:54:03 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290722657 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.3290722657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/5.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.4141571117 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 1638219076 ps |
| CPU time | 9.71 seconds |
| Started | Oct 12 02:53:41 PM UTC 24 |
| Finished | Oct 12 02:53:52 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141571117 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.4141571117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.896978188 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 13477108 ps |
| CPU time | 1.69 seconds |
| Started | Oct 12 02:53:41 PM UTC 24 |
| Finished | Oct 12 02:53:44 PM UTC 24 |
| Peak memory | 209864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896978188 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.896978188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/5.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all.1176552404 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 2361398044 ps |
| CPU time | 30.87 seconds |
| Started | Oct 12 02:53:50 PM UTC 24 |
| Finished | Oct 12 02:54:23 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176552404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1176552404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/5.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_error.3395566783 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 10762153633 ps |
| CPU time | 81.05 seconds |
| Started | Oct 12 02:53:53 PM UTC 24 |
| Finished | Oct 12 02:55:16 PM UTC 24 |
| Peak memory | 213096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395566783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.3395566783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/5.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.3405099452 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1927050283 ps |
| CPU time | 216.03 seconds |
| Started | Oct 12 02:53:52 PM UTC 24 |
| Finished | Oct 12 02:57:31 PM UTC 24 |
| Peak memory | 214700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405099452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.3405099452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.1386938157 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 4605970691 ps |
| CPU time | 68.31 seconds |
| Started | Oct 12 02:53:53 PM UTC 24 |
| Finished | Oct 12 02:55:03 PM UTC 24 |
| Peak memory | 213040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386938157 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.1386938157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_unmapped_addr.1567127930 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 497925929 ps |
| CPU time | 9.54 seconds |
| Started | Oct 12 02:53:49 PM UTC 24 |
| Finished | Oct 12 02:54:00 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567127930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.1567127930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/5.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device.1869543678 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 5844261672 ps |
| CPU time | 31.35 seconds |
| Started | Oct 12 02:54:03 PM UTC 24 |
| Finished | Oct 12 02:54:36 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869543678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.1869543678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/6.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.3723688664 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 8574019323 ps |
| CPU time | 69.76 seconds |
| Started | Oct 12 02:54:03 PM UTC 24 |
| Finished | Oct 12 02:55:14 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723688664 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.3723688664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.1294474791 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 417637395 ps |
| CPU time | 6.58 seconds |
| Started | Oct 12 02:54:06 PM UTC 24 |
| Finished | Oct 12 02:54:13 PM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294474791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.1294474791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_error_random.4148369816 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1064316595 ps |
| CPU time | 23.43 seconds |
| Started | Oct 12 02:54:05 PM UTC 24 |
| Finished | Oct 12 02:54:30 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148369816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.4148369816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/6.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random.3862982738 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 1839853761 ps |
| CPU time | 9.67 seconds |
| Started | Oct 12 02:53:59 PM UTC 24 |
| Finished | Oct 12 02:54:10 PM UTC 24 |
| Peak memory | 213004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862982738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.3862982738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/6.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_large_delays.3891211980 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 7871193281 ps |
| CPU time | 22.41 seconds |
| Started | Oct 12 02:54:01 PM UTC 24 |
| Finished | Oct 12 02:54:24 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891211980 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.3891211980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/6.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_slow_rsp.3279247753 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 10383519835 ps |
| CPU time | 56.3 seconds |
| Started | Oct 12 02:54:01 PM UTC 24 |
| Finished | Oct 12 02:54:59 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279247753 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3279247753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/6.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_zero_delays.2878559896 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 67433008 ps |
| CPU time | 3.16 seconds |
| Started | Oct 12 02:53:59 PM UTC 24 |
| Finished | Oct 12 02:54:04 PM UTC 24 |
| Peak memory | 213004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878559896 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.2878559896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/6.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_same_source.1993831674 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 679444929 ps |
| CPU time | 12.72 seconds |
| Started | Oct 12 02:54:04 PM UTC 24 |
| Finished | Oct 12 02:54:18 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993831674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.1993831674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/6.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke.1512589551 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 125186530 ps |
| CPU time | 2.1 seconds |
| Started | Oct 12 02:53:55 PM UTC 24 |
| Finished | Oct 12 02:53:58 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512589551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1512589551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/6.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_large_delays.193514424 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 1505231985 ps |
| CPU time | 11.63 seconds |
| Started | Oct 12 02:53:57 PM UTC 24 |
| Finished | Oct 12 02:54:10 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193514424 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.193514424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/6.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.2431268296 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 5093100515 ps |
| CPU time | 8.88 seconds |
| Started | Oct 12 02:53:58 PM UTC 24 |
| Finished | Oct 12 02:54:08 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431268296 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.2431268296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.2397215420 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 8275846 ps |
| CPU time | 1.66 seconds |
| Started | Oct 12 02:53:56 PM UTC 24 |
| Finished | Oct 12 02:53:59 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397215420 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.2397215420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/6.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all.2638171988 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 993798251 ps |
| CPU time | 55.11 seconds |
| Started | Oct 12 02:54:07 PM UTC 24 |
| Finished | Oct 12 02:55:03 PM UTC 24 |
| Peak memory | 215008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638171988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2638171988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/6.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_error.2717704620 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 16877679851 ps |
| CPU time | 30.66 seconds |
| Started | Oct 12 02:54:11 PM UTC 24 |
| Finished | Oct 12 02:54:43 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717704620 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.2717704620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/6.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.2803234089 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 294598697 ps |
| CPU time | 29.47 seconds |
| Started | Oct 12 02:54:09 PM UTC 24 |
| Finished | Oct 12 02:54:39 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803234089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.2803234089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1424205624 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 9361619029 ps |
| CPU time | 108.07 seconds |
| Started | Oct 12 02:54:11 PM UTC 24 |
| Finished | Oct 12 02:56:01 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424205624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.1424205624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_unmapped_addr.1283386508 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 329991141 ps |
| CPU time | 5.84 seconds |
| Started | Oct 12 02:54:05 PM UTC 24 |
| Finished | Oct 12 02:54:12 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283386508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.1283386508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/6.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device.3168086557 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1409363207 ps |
| CPU time | 23.82 seconds |
| Started | Oct 12 02:54:23 PM UTC 24 |
| Finished | Oct 12 02:54:48 PM UTC 24 |
| Peak memory | 211060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168086557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.3168086557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/7.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.1159811168 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 7765236911 ps |
| CPU time | 19.49 seconds |
| Started | Oct 12 02:54:23 PM UTC 24 |
| Finished | Oct 12 02:54:44 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159811168 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.1159811168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.2159856868 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 1267518822 ps |
| CPU time | 11.31 seconds |
| Started | Oct 12 02:54:29 PM UTC 24 |
| Finished | Oct 12 02:54:41 PM UTC 24 |
| Peak memory | 212968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159856868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.2159856868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_error_random.3472450997 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 10177012 ps |
| CPU time | 1.6 seconds |
| Started | Oct 12 02:54:26 PM UTC 24 |
| Finished | Oct 12 02:54:28 PM UTC 24 |
| Peak memory | 211956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472450997 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3472450997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/7.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random.989869107 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 939454159 ps |
| CPU time | 7.94 seconds |
| Started | Oct 12 02:54:17 PM UTC 24 |
| Finished | Oct 12 02:54:26 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989869107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.989869107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/7.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_large_delays.3219845825 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 25382185081 ps |
| CPU time | 56.81 seconds |
| Started | Oct 12 02:54:18 PM UTC 24 |
| Finished | Oct 12 02:55:16 PM UTC 24 |
| Peak memory | 213156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219845825 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3219845825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/7.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_slow_rsp.859564128 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 8559355143 ps |
| CPU time | 42.87 seconds |
| Started | Oct 12 02:54:19 PM UTC 24 |
| Finished | Oct 12 02:55:03 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859564128 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.859564128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/7.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_zero_delays.3040904506 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 34684491 ps |
| CPU time | 4.76 seconds |
| Started | Oct 12 02:54:17 PM UTC 24 |
| Finished | Oct 12 02:54:23 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040904506 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.3040904506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/7.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_same_source.31797093 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 186034437 ps |
| CPU time | 7.71 seconds |
| Started | Oct 12 02:54:24 PM UTC 24 |
| Finished | Oct 12 02:54:33 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31797093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.31797093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/7.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke.1575006314 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 124877915 ps |
| CPU time | 2.75 seconds |
| Started | Oct 12 02:54:12 PM UTC 24 |
| Finished | Oct 12 02:54:16 PM UTC 24 |
| Peak memory | 212952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575006314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.1575006314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/7.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_large_delays.3255655027 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 3171925563 ps |
| CPU time | 20.15 seconds |
| Started | Oct 12 02:54:14 PM UTC 24 |
| Finished | Oct 12 02:54:36 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255655027 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3255655027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/7.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.782292969 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 17354773322 ps |
| CPU time | 22.3 seconds |
| Started | Oct 12 02:54:16 PM UTC 24 |
| Finished | Oct 12 02:54:39 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782292969 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.782292969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.2600243480 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 11491409 ps |
| CPU time | 1.62 seconds |
| Started | Oct 12 02:54:13 PM UTC 24 |
| Finished | Oct 12 02:54:16 PM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600243480 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.2600243480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/7.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all.2927508053 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 6119893130 ps |
| CPU time | 27.83 seconds |
| Started | Oct 12 02:54:31 PM UTC 24 |
| Finished | Oct 12 02:55:00 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927508053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2927508053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/7.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_error.3185639501 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 16678642432 ps |
| CPU time | 53.39 seconds |
| Started | Oct 12 02:54:32 PM UTC 24 |
| Finished | Oct 12 02:55:28 PM UTC 24 |
| Peak memory | 213016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185639501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3185639501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/7.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.3598996792 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 697032607 ps |
| CPU time | 107.93 seconds |
| Started | Oct 12 02:54:34 PM UTC 24 |
| Finished | Oct 12 02:56:24 PM UTC 24 |
| Peak memory | 215020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598996792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.3598996792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_unmapped_addr.2350947994 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 1204779700 ps |
| CPU time | 7.16 seconds |
| Started | Oct 12 02:54:27 PM UTC 24 |
| Finished | Oct 12 02:54:35 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350947994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2350947994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/7.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device.1512115889 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 730987832 ps |
| CPU time | 8.16 seconds |
| Started | Oct 12 02:54:43 PM UTC 24 |
| Finished | Oct 12 02:54:52 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512115889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.1512115889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/8.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.441489103 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 994230276 ps |
| CPU time | 15.74 seconds |
| Started | Oct 12 02:54:46 PM UTC 24 |
| Finished | Oct 12 02:55:03 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441489103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.441489103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_error_random.1779821867 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 1095628133 ps |
| CPU time | 17.02 seconds |
| Started | Oct 12 02:54:45 PM UTC 24 |
| Finished | Oct 12 02:55:03 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779821867 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.1779821867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/8.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random.4056050130 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 244779848 ps |
| CPU time | 2.1 seconds |
| Started | Oct 12 02:54:39 PM UTC 24 |
| Finished | Oct 12 02:54:43 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056050130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.4056050130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/8.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_large_delays.1349107149 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 15072952036 ps |
| CPU time | 60.55 seconds |
| Started | Oct 12 02:54:41 PM UTC 24 |
| Finished | Oct 12 02:55:43 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349107149 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1349107149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/8.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_slow_rsp.2129421326 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 4183715834 ps |
| CPU time | 33.84 seconds |
| Started | Oct 12 02:54:41 PM UTC 24 |
| Finished | Oct 12 02:55:16 PM UTC 24 |
| Peak memory | 211088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129421326 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.2129421326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/8.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_zero_delays.3327987611 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 13506894 ps |
| CPU time | 2.14 seconds |
| Started | Oct 12 02:54:40 PM UTC 24 |
| Finished | Oct 12 02:54:44 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327987611 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.3327987611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/8.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_same_source.238480036 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 124516698 ps |
| CPU time | 3.96 seconds |
| Started | Oct 12 02:54:44 PM UTC 24 |
| Finished | Oct 12 02:54:49 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238480036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.238480036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/8.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke.2133406944 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 46451757 ps |
| CPU time | 2.15 seconds |
| Started | Oct 12 02:54:35 PM UTC 24 |
| Finished | Oct 12 02:54:38 PM UTC 24 |
| Peak memory | 212952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133406944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.2133406944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/8.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_large_delays.1523263488 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 17855381106 ps |
| CPU time | 13.34 seconds |
| Started | Oct 12 02:54:37 PM UTC 24 |
| Finished | Oct 12 02:54:52 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523263488 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.1523263488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/8.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2278222655 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 1807180252 ps |
| CPU time | 9.36 seconds |
| Started | Oct 12 02:54:37 PM UTC 24 |
| Finished | Oct 12 02:54:48 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278222655 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2278222655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.2548318569 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 8598691 ps |
| CPU time | 1.73 seconds |
| Started | Oct 12 02:54:36 PM UTC 24 |
| Finished | Oct 12 02:54:39 PM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548318569 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.2548318569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/8.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all.1703541830 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 5018723213 ps |
| CPU time | 18.5 seconds |
| Started | Oct 12 02:54:49 PM UTC 24 |
| Finished | Oct 12 02:55:08 PM UTC 24 |
| Peak memory | 213080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703541830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1703541830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/8.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_error.2354711916 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 2911890465 ps |
| CPU time | 40.24 seconds |
| Started | Oct 12 02:54:50 PM UTC 24 |
| Finished | Oct 12 02:55:32 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354711916 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.2354711916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/8.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.2146049239 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 96298313 ps |
| CPU time | 11.54 seconds |
| Started | Oct 12 02:54:50 PM UTC 24 |
| Finished | Oct 12 02:55:03 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146049239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.2146049239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.2517232916 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 4671944838 ps |
| CPU time | 122.14 seconds |
| Started | Oct 12 02:54:50 PM UTC 24 |
| Finished | Oct 12 02:56:55 PM UTC 24 |
| Peak memory | 217200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517232916 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.2517232916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_unmapped_addr.3446808725 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 131488547 ps |
| CPU time | 3.28 seconds |
| Started | Oct 12 02:54:45 PM UTC 24 |
| Finished | Oct 12 02:54:50 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446808725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.3446808725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/8.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device.1566496320 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 107255845 ps |
| CPU time | 9.43 seconds |
| Started | Oct 12 02:54:55 PM UTC 24 |
| Finished | Oct 12 02:55:06 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566496320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1566496320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/9.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.1580442327 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 12584763947 ps |
| CPU time | 44.47 seconds |
| Started | Oct 12 02:54:59 PM UTC 24 |
| Finished | Oct 12 02:55:45 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580442327 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.1580442327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.3869389127 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 2775106332 ps |
| CPU time | 8.75 seconds |
| Started | Oct 12 02:55:02 PM UTC 24 |
| Finished | Oct 12 02:55:12 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869389127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.3869389127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_error_random.872953815 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 1266288275 ps |
| CPU time | 16.76 seconds |
| Started | Oct 12 02:55:01 PM UTC 24 |
| Finished | Oct 12 02:55:19 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872953815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.872953815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/9.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random.372201680 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 22057550 ps |
| CPU time | 2.87 seconds |
| Started | Oct 12 02:54:54 PM UTC 24 |
| Finished | Oct 12 02:54:58 PM UTC 24 |
| Peak memory | 212952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372201680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.372201680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/9.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_large_delays.1138132686 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 12017262800 ps |
| CPU time | 43.52 seconds |
| Started | Oct 12 02:54:54 PM UTC 24 |
| Finished | Oct 12 02:55:39 PM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138132686 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1138132686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/9.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_slow_rsp.2923736510 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 8194016788 ps |
| CPU time | 33.79 seconds |
| Started | Oct 12 02:54:54 PM UTC 24 |
| Finished | Oct 12 02:55:30 PM UTC 24 |
| Peak memory | 210956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923736510 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2923736510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/9.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_zero_delays.1125812123 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 54126294 ps |
| CPU time | 4.85 seconds |
| Started | Oct 12 02:54:54 PM UTC 24 |
| Finished | Oct 12 02:55:00 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125812123 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.1125812123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/9.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_same_source.484077274 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 3104917088 ps |
| CPU time | 18.89 seconds |
| Started | Oct 12 02:54:59 PM UTC 24 |
| Finished | Oct 12 02:55:20 PM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484077274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.484077274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/9.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke.1347763873 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 10657462 ps |
| CPU time | 1.63 seconds |
| Started | Oct 12 02:54:50 PM UTC 24 |
| Finished | Oct 12 02:54:53 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347763873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.1347763873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/9.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_large_delays.2959850480 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 2403686948 ps |
| CPU time | 12.64 seconds |
| Started | Oct 12 02:54:52 PM UTC 24 |
| Finished | Oct 12 02:55:06 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959850480 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.2959850480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/9.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.3843456819 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 1838415276 ps |
| CPU time | 13.69 seconds |
| Started | Oct 12 02:54:52 PM UTC 24 |
| Finished | Oct 12 02:55:07 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843456819 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3843456819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.599377974 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 13802995 ps |
| CPU time | 1.77 seconds |
| Started | Oct 12 02:54:51 PM UTC 24 |
| Finished | Oct 12 02:54:54 PM UTC 24 |
| Peak memory | 211960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599377974 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.599377974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/9.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all.2470504427 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 1263963327 ps |
| CPU time | 13 seconds |
| Started | Oct 12 02:55:03 PM UTC 24 |
| Finished | Oct 12 02:55:18 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470504427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2470504427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/9.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_error.1623160311 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 203626016 ps |
| CPU time | 18.8 seconds |
| Started | Oct 12 02:55:03 PM UTC 24 |
| Finished | Oct 12 02:55:24 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623160311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.1623160311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/9.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.3010838969 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 8630128629 ps |
| CPU time | 208.35 seconds |
| Started | Oct 12 02:55:03 PM UTC 24 |
| Finished | Oct 12 02:58:35 PM UTC 24 |
| Peak memory | 218756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010838969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.3010838969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.3097153093 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 486281421 ps |
| CPU time | 52.93 seconds |
| Started | Oct 12 02:55:05 PM UTC 24 |
| Finished | Oct 12 02:55:59 PM UTC 24 |
| Peak memory | 213004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097153093 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.3097153093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_unmapped_addr.3699334545 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 99501119 ps |
| CPU time | 7.05 seconds |
| Started | Oct 12 02:55:01 PM UTC 24 |
| Finished | Oct 12 02:55:09 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699334545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3699334545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/9.xbar_unmapped_addr/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |