Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	430	1			T82	3		T226	2		T187	1
all_values[1]	479	1			T43	1		T46	1		T226	1
all_values[2]	478	1			T43	1		T226	1		T52	1
all_values[3]	476	1			T82	2		T163	4		T302	1
all_values[4]	466	1			T23	1		T43	2		T302	1
all_values[5]	489	1			T43	2		T65	1		T82	1
all_values[6]	459	1			T82	1		T88	1		T162	1
all_values[7]	466	1			T43	1		T46	1		T82	1
all_values[8]	510	1			T46	1		T52	1		T162	1
all_values[9]	493	1			T23	1		T46	1		T82	2
all_values[10]	476	1			T43	1		T226	1		T162	1
all_values[11]	489	1			T46	1		T302	1		T290	1
all_values[12]	486	1			T23	1		T46	2		T82	1
all_values[13]	478	1			T65	1		T226	1		T52	1
all_values[14]	454	1			T23	1		T43	2		T46	2
all_values[15]	467	1			T43	1		T82	1		T226	1
all_values[16]	453	1			T46	2		T82	2		T52	1
all_values[17]	500	1			T23	1		T43	1		T46	1
all_values[18]	519	1			T43	1		T82	1		T226	1
all_values[19]	441	1			T65	1		T46	1		T226	2
all_values[20]	462	1			T46	1		T82	2		T302	2
all_values[21]	447	1			T82	2		T163	2		T302	1
all_values[22]	474	1			T46	1		T82	2		T226	1
all_values[23]	441	1			T43	1		T46	1		T82	2
all_values[24]	473	1			T82	4		T226	1		T52	2
all_values[25]	490	1			T46	1		T226	2		T162	2
all_values[26]	456	1			T43	1		T46	1		T163	2