Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	457	1			T15	2		T295	3		T290	5
all_values[1]	414	1			T15	2		T41	1		T173	3
all_values[2]	405	1			T215	1		T173	1		T296	1
all_values[3]	442	1			T36	1		T37	1		T173	2
all_values[4]	451	1			T15	2		T215	2		T37	1
all_values[5]	411	1			T41	2		T215	1		T71	1
all_values[6]	438	1			T15	2		T41	1		T53	1
all_values[7]	399	1			T15	2		T41	1		T215	1
all_values[8]	409	1			T15	1		T37	2		T296	2
all_values[9]	429	1			T4	1		T41	1		T37	2
all_values[10]	439	1			T41	1		T173	1		T71	1
all_values[11]	421	1			T15	1		T215	1		T171	1
all_values[12]	441	1			T15	2		T41	1		T173	1
all_values[13]	426	1			T41	3		T53	1		T296	1
all_values[14]	424	1			T41	1		T215	1		T173	2
all_values[15]	415	1			T215	1		T36	2		T171	1
all_values[16]	414	1			T41	1		T36	1		T173	5
all_values[17]	448	1			T41	1		T215	1		T36	1
all_values[18]	429	1			T15	1		T41	2		T36	1
all_values[19]	443	1			T41	2		T215	1		T171	1
all_values[20]	416	1			T15	1		T215	1		T53	1
all_values[21]	446	1			T173	1		T53	1		T71	2
all_values[22]	445	1			T15	2		T41	1		T215	1
all_values[23]	448	1			T36	1		T173	3		T296	2
all_values[24]	447	1			T15	1		T215	1		T36	1
all_values[25]	416	1			T41	1		T173	1		T295	3
all_values[26]	404	1			T15	1		T37	1		T173	1