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 LINE       167
 EXPRESSION (gen_u_o[22].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[23].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[24].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[25].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[26].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 EXPRESSION (dev_select_t == 5'(idx))
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       189
 EXPRESSION (tl_t_o.a_valid & hfifo_reqready)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (dev_select_outstanding == 5'(idx))
            -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION (tl_t_o.a_valid & (dev_select_t >= 5'(N)) & ((~hold_all_requests)))
             -------1------   -----------2-----------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T12,T13
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T14,T15
1	1	1	Covered	T5,T16,T17