ALERT_HANDLER Simulation Results

Monday May 22 2023 07:05:49 UTC

GitHub Revision: e3fb01b5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3641199223

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.335m	5.411ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.750s	856.371us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.230s	127.493us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	9.086m	8.709ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	2.214m	2.184ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	8.260s	263.831us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.230s	127.493us	20	20	100.00
		alert_handler_csr_aliasing	2.214m	2.184ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.409m	11.375ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.125m	1.121ms	50	50	100.00
V2	entropy	alert_handler_entropy	53.949m	222.683ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.144m	4.422ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.335m	5.411ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.040m	4.543ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.026m	1.048ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	9.697m	56.025ms	50	50	100.00
V2	lpg	alert_handler_lpg	54.180m	111.443ms	50	50	100.00
		alert_handler_lpg_stub_clk	55.493m	441.595ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.252h	81.326ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	57.850s	5.665ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.200s	73.215us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.700s	13.150us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	24.750s	1.335ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	24.750s	1.335ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.750s	856.371us	5	5	100.00
		alert_handler_csr_rw	9.230s	127.493us	20	20	100.00
		alert_handler_csr_aliasing	2.214m	2.184ms	5	5	100.00
		alert_handler_same_csr_outstanding	46.950s	1.387ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.750s	856.371us	5	5	100.00
		alert_handler_csr_rw	9.230s	127.493us	20	20	100.00
		alert_handler_csr_aliasing	2.214m	2.184ms	5	5	100.00
		alert_handler_same_csr_outstanding	46.950s	1.387ms	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	24.072m	81.195ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	24.072m	81.195ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	24.072m	81.195ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	24.072m	81.195ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	1.212h	59.654ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	1.056m	1.646ms	5	5	100.00
		alert_handler_tl_intg_err	1.307m	5.231ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.307m	5.231ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	24.072m	81.195ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.335m	5.411ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.335m	5.411ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.335m	5.411ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.335m	5.411ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.144m	4.422ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	54.180m	111.443ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.144m	4.422ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	53.949m	222.683ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	53.949m	222.683ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	1.056m	1.646ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	1.056m	1.646ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	1.056m	1.646ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	1.056m	1.646ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	1.056m	1.646ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	1.056m	1.646ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	1.056m	1.646ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	1.056m	1.646ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	1.056m	1.646ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.589h	134.171ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			849	850	99.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	99.99	98.74	100.00	100.00	100.00	99.25	99.60

Failure Buckets

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
  • Test alert_handler_sig_int_fail has 1 failures.

    • 32.alert_handler_sig_int_fail.2882213780
      Line 227, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/32.alert_handler_sig_int_fail/latest/run.log

        UVM_ERROR @ 263265612 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 263265612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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