ALERT_HANDLER Simulation Results

Tuesday May 23 2023 07:02:27 UTC

GitHub Revision: 83db9403d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1254715506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.005m	4.155ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.190s	391.356us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.950s	914.797us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.142m	8.914ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	5.410m	5.157ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	7.030s	67.590us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.950s	914.797us	20	20	100.00
		alert_handler_csr_aliasing	5.410m	5.157ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.328m	5.958ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.286m	2.856ms	50	50	100.00
V2	entropy	alert_handler_entropy	55.961m	583.693ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.049m	1.133ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.005m	4.155ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.016m	2.315ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.143m	4.138ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.075m	30.368ms	50	50	100.00
V2	lpg	alert_handler_lpg	51.665m	56.129ms	50	50	100.00
		alert_handler_lpg_stub_clk	56.289m	58.211ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.174h	78.337ms	48	50	96.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	49.010s	1.197ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	3.810s	79.423us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.680s	13.688us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	27.330s	2.417ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	27.330s	2.417ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.190s	391.356us	5	5	100.00
		alert_handler_csr_rw	9.950s	914.797us	20	20	100.00
		alert_handler_csr_aliasing	5.410m	5.157ms	5	5	100.00
		alert_handler_same_csr_outstanding	44.090s	713.045us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.190s	391.356us	5	5	100.00
		alert_handler_csr_rw	9.950s	914.797us	20	20	100.00
		alert_handler_csr_aliasing	5.410m	5.157ms	5	5	100.00
		alert_handler_same_csr_outstanding	44.090s	713.045us	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	22.569m	63.915ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	22.569m	63.915ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	22.569m	63.915ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	22.569m	63.915ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	1.334h	244.258ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	22.830s	1.701ms	5	5	100.00
		alert_handler_tl_intg_err	1.420m	2.502ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.420m	2.502ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	22.569m	63.915ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.005m	4.155ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.005m	4.155ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.005m	4.155ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.005m	4.155ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.049m	1.133ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	51.665m	56.129ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.049m	1.133ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	55.961m	583.693ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	55.961m	583.693ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	22.830s	1.701ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	22.830s	1.701ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	22.830s	1.701ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	22.830s	1.701ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	22.830s	1.701ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	22.830s	1.701ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	22.830s	1.701ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	22.830s	1.701ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	22.830s	1.701ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.862h	772.115ms	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			845	850	99.41

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	99.99	98.68	100.00	100.00	100.00	99.25	99.64

Failure Buckets

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_stress_all has 1 failures.

    • 14.alert_handler_stress_all.1804707362
      Line 454, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_stress_all/latest/run.log

        UVM_ERROR @ 218776677017 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 218776677017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_d, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_stress_all has 1 failures.

    • 16.alert_handler_stress_all.1872098894
      Line 330, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_stress_all/latest/run.log

        UVM_ERROR @ 1884865903 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_d, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 1884865903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 16.alert_handler_stress_all_with_rand_reset.3702342107
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:43d071b8-a4bd-40fe-83e0-f502dc06a70b
      

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_state has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 22.alert_handler_stress_all_with_rand_reset.321353590
      Line 243, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/22.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 104146944 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (7 [0x7] vs 3 [0x3]) reg name: alert_handler_reg_block.classa_state
        UVM_INFO @ 104146944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 29.alert_handler_stress_all_with_rand_reset.1435928880
      Line 1465, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/29.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 296783529195 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 296783529195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2023.05.22_19.52.19
• 2023.05.21_20.29.12
• 2023.05.20_19.45.40
• 2023.05.19_16.29.43
• 2023.05.18_19.29.44
• 2023.05.17_18.15.47
• 2023.05.16_19.38.54