ALERT_HANDLER Simulation Results

Wednesday May 24 2023 07:09:34 UTC

GitHub Revision: 26b0ee226

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 844256362

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.135m	7.153ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.070s	131.902us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.060s	256.312us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.835m	77.695ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.448m	15.837ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	8.640s	87.702us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.060s	256.312us	20	20	100.00
		alert_handler_csr_aliasing	4.448m	15.837ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.929m	20.862ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.105m	1.136ms	50	50	100.00
V2	entropy	alert_handler_entropy	59.678m	56.849ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.135m	10.300ms	48	50	96.00
V2	clk_skew	alert_handler_smoke	1.135m	7.153ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.107m	1.096ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.250m	6.245ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	9.595m	62.499ms	49	50	98.00
V2	lpg	alert_handler_lpg	55.984m	218.959ms	50	50	100.00
		alert_handler_lpg_stub_clk	56.462m	429.775ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.164h	311.223ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	50.580s	2.421ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.420s	100.500us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.730s	13.860us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	24.280s	2.825ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	24.280s	2.825ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.070s	131.902us	5	5	100.00
		alert_handler_csr_rw	10.060s	256.312us	20	20	100.00
		alert_handler_csr_aliasing	4.448m	15.837ms	5	5	100.00
		alert_handler_same_csr_outstanding	49.840s	730.957us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.070s	131.902us	5	5	100.00
		alert_handler_csr_rw	10.060s	256.312us	20	20	100.00
		alert_handler_csr_aliasing	4.448m	15.837ms	5	5	100.00
		alert_handler_same_csr_outstanding	49.840s	730.957us	20	20	100.00
V2		TOTAL			627	630	99.52
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	24.209m	90.320ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	24.209m	90.320ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	24.209m	90.320ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	24.209m	90.320ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	1.074h	115.141ms	19	20	95.00
V2S	tl_intg_err	alert_handler_sec_cm	49.810s	1.130ms	5	5	100.00
		alert_handler_tl_intg_err	1.232m	12.541ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.232m	12.541ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	24.209m	90.320ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.135m	7.153ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.135m	7.153ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.135m	7.153ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.135m	7.153ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.135m	10.300ms	48	50	96.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	55.984m	218.959ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.135m	10.300ms	48	50	96.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	59.678m	56.849ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	59.678m	56.849ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	49.810s	1.130ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	49.810s	1.130ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	49.810s	1.130ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	49.810s	1.130ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	49.810s	1.130ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	49.810s	1.130ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	49.810s	1.130ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	49.810s	1.130ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	49.810s	1.130ms	5	5	100.00
V2S		TOTAL			64	65	98.46
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.731h	107.249ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			846	850	99.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	3	75.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	99.99	98.71	100.00	100.00	100.00	99.25	99.76

Failure Buckets

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_d, is_local_err *, local_alert_type LocalEscPingFail has 1 failures:

  • Test alert_handler_ping_timeout has 1 failures.

    • 2.alert_handler_ping_timeout.2581172607
      Line 225, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_ping_timeout/latest/run.log

        UVM_ERROR @ 2342557630 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_d, is_local_err 1, local_alert_type LocalEscPingFail
        UVM_INFO @ 2342557630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test alert_handler_shadow_reg_errors_with_csr_rw has 1 failures.

    • 8.alert_handler_shadow_reg_errors_with_csr_rw.1146873246
      Line 220, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_FATAL @ 500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_accum_cnt has 1 failures:

  • Test alert_handler_sig_int_fail has 1 failures.

    • 29.alert_handler_sig_int_fail.2164419213
      Line 223, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/29.alert_handler_sig_int_fail/latest/run.log

        UVM_ERROR @  39891820 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (12 [0xc] vs 13 [0xd]) reg name: alert_handler_reg_block.classa_accum_cnt
        UVM_INFO @  39891820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_sig_int_fail has 1 failures.

    • 31.alert_handler_sig_int_fail.3564716837
      Line 226, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_sig_int_fail/latest/run.log

        UVM_ERROR @ 812131521 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 812131521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2023.05.23_18.09.35
• 2023.05.22_19.52.19
• 2023.05.21_20.29.12
• 2023.05.20_19.45.40
• 2023.05.19_16.29.43
• 2023.05.18_19.29.44
• 2023.05.17_18.15.47