ALERT_HANDLER Simulation Results

Thursday May 25 2023 07:02:34 UTC

GitHub Revision: `94eb0df12`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 77475240

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.120m	4.523ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.690s	467.834us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	8.610s	702.270us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.221m	8.563ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.298m	18.416ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	8.050s	81.197us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	8.610s	702.270us	20	20	100.00
		alert_handler_csr_aliasing	4.298m	18.416ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.598m	5.604ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.143m	24.368ms	50	50	100.00
V2	entropy	alert_handler_entropy	56.173m	110.931ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.055m	1.875ms	48	50	96.00
V2	clk_skew	alert_handler_smoke	1.120m	4.523ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	57.880s	15.462ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.157m	4.759ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	9.899m	114.433ms	50	50	100.00
V2	lpg	alert_handler_lpg	57.896m	179.231ms	49	50	98.00
		alert_handler_lpg_stub_clk	50.370m	197.565ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.298h	405.631ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.097m	1.562ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	3.790s	44.337us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.180s	27.662us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	20.840s	4.515ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	20.840s	4.515ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.690s	467.834us	5	5	100.00
		alert_handler_csr_rw	8.610s	702.270us	20	20	100.00
		alert_handler_csr_aliasing	4.298m	18.416ms	5	5	100.00
		alert_handler_same_csr_outstanding	48.360s	706.786us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.690s	467.834us	5	5	100.00
		alert_handler_csr_rw	8.610s	702.270us	20	20	100.00
		alert_handler_csr_aliasing	4.298m	18.416ms	5	5	100.00
		alert_handler_same_csr_outstanding	48.360s	706.786us	20	20	100.00
V2		TOTAL			626	630	99.37
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	20.271m	59.554ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	20.271m	59.554ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	20.271m	59.554ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	20.271m	59.554ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	1.188h	88.793ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	47.450s	1.132ms	5	5	100.00
		alert_handler_tl_intg_err	1.529m	1.087ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.529m	1.087ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	20.271m	59.554ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.120m	4.523ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.120m	4.523ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.120m	4.523ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.120m	4.523ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.055m	1.875ms	48	50	96.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	57.896m	179.231ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.055m	1.875ms	48	50	96.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	56.173m	110.931ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	56.173m	110.931ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	47.450s	1.132ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	47.450s	1.132ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	47.450s	1.132ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	47.450s	1.132ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	47.450s	1.132ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	47.450s	1.132ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	47.450s	1.132ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	47.450s	1.132ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	47.450s	1.132ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.554h	120.256ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			846	850	99.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	12	80.00
V2S	4	4	4	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	99.99	98.74	100.00	100.00	100.00	99.25	99.68

Failure Buckets

UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 2 failures:

Test alert_handler_sig_int_fail has 1 failures.

32.alert_handler_sig_int_fail.3416327041
Line 225, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/32.alert_handler_sig_int_fail/latest/run.log

  UVM_ERROR @ 258612387 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 258612387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test alert_handler_stress_all has 1 failures.

49.alert_handler_stress_all.1714308045
Line 251, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/49.alert_handler_stress_all/latest/run.log

  UVM_ERROR @ 1606902719 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 1606902719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test alert_handler_lpg has 1 failures.
  - 15.alert_handler_lpg.2712378944
    Line 222, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_lpg/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:483) [alert_handler_sig_int_fail_vseq] Check failed data == * (* [*] vs * [*]) has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 38.alert_handler_sig_int_fail.152170101
    Line 231, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/38.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 10573578137 ps: (cip_base_vseq.sv:483) [uvm_test_top.env.virtual_sequencer.alert_handler_sig_int_fail_vseq] Check failed data == 0 (4 [0x4] vs 0 [0x0])
  UVM_INFO @ 10573578137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```