ALERT_HANDLER Simulation Results

Friday May 26 2023 07:06:59 UTC

GitHub Revision: 213e792ea

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2340441291

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.010m	1.240ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	5.540s	65.007us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.540s	244.308us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.442m	95.053ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.343m	13.314ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	7.290s	153.035us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.540s	244.308us	20	20	100.00
		alert_handler_csr_aliasing	4.343m	13.314ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.211m	6.038ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.089m	4.484ms	50	50	100.00
V2	entropy	alert_handler_entropy	57.261m	124.194ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.026m	2.200ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.010m	1.240ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.244m	2.302ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.057m	1.152ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.974m	74.698ms	50	50	100.00
V2	lpg	alert_handler_lpg	52.082m	349.382ms	50	50	100.00
		alert_handler_lpg_stub_clk	48.972m	454.560ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.022h	130.709ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.431m	12.042ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.010s	266.143us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.640s	14.405us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	17.730s	290.102us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	17.730s	290.102us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	5.540s	65.007us	5	5	100.00
		alert_handler_csr_rw	9.540s	244.308us	20	20	100.00
		alert_handler_csr_aliasing	4.343m	13.314ms	5	5	100.00
		alert_handler_same_csr_outstanding	46.000s	3.203ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	5.540s	65.007us	5	5	100.00
		alert_handler_csr_rw	9.540s	244.308us	20	20	100.00
		alert_handler_csr_aliasing	4.343m	13.314ms	5	5	100.00
		alert_handler_same_csr_outstanding	46.000s	3.203ms	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	24.874m	20.827ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	24.874m	20.827ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	24.874m	20.827ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	24.874m	20.827ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	1.226h	408.155ms	19	20	95.00
V2S	tl_intg_err	alert_handler_sec_cm	57.050s	1.401ms	5	5	100.00
		alert_handler_tl_intg_err	1.342m	1.266ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.342m	1.266ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	24.874m	20.827ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.010m	1.240ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.010m	1.240ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.010m	1.240ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.010m	1.240ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.026m	2.200ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	52.082m	349.382ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.026m	2.200ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	57.261m	124.194ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	57.261m	124.194ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	57.050s	1.401ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	57.050s	1.401ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	57.050s	1.401ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	57.050s	1.401ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	57.050s	1.401ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	57.050s	1.401ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	57.050s	1.401ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	57.050s	1.401ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	57.050s	1.401ms	5	5	100.00
V2S		TOTAL			64	65	98.46
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.327h	126.788ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			847	850	99.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.66	99.99	98.76	100.00	100.00	100.00	99.25	99.60

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test alert_handler_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.alert_handler_shadow_reg_errors_with_csr_rw.3596117120
      Line 220, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_FATAL @ 500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_state has 1 failures:

  • Test alert_handler_sig_int_fail has 1 failures.

    • 4.alert_handler_sig_int_fail.2648783927
      Line 223, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_sig_int_fail/latest/run.log

        UVM_ERROR @ 167610852 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (7 [0x7] vs 6 [0x6]) reg name: alert_handler_reg_block.classa_state
        UVM_INFO @ 167610852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 21.alert_handler_stress_all_with_rand_reset.476018625
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/21.alert_handler_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:a614fe2c-ff00-4fa7-abb1-19b2095503ad
      

Past Results

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