ALERT_HANDLER Simulation Results

Saturday May 27 2023 07:02:22 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2359737659

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.017m	8.805ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	8.720s	477.457us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	8.760s	850.211us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.645m	5.810ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.309m	16.603ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	7.810s	279.883us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	8.760s	850.211us	20	20	100.00
		alert_handler_csr_aliasing	4.309m	16.603ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.893m	23.717ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.058m	4.158ms	50	50	100.00
V2	entropy	alert_handler_entropy	53.395m	56.253ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.139m	8.699ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.017m	8.805ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.223m	4.634ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.283m	12.791ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.309m	212.281ms	50	50	100.00
V2	lpg	alert_handler_lpg	57.745m	238.652ms	50	50	100.00
		alert_handler_lpg_stub_clk	55.740m	110.410ms	49	50	98.00
V2	stress_all	alert_handler_stress_all	1.302h	77.588ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	59.610s	1.505ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.170s	68.901us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.650s	46.013us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	19.650s	694.295us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	19.650s	694.295us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	8.720s	477.457us	5	5	100.00
		alert_handler_csr_rw	8.760s	850.211us	20	20	100.00
		alert_handler_csr_aliasing	4.309m	16.603ms	5	5	100.00
		alert_handler_same_csr_outstanding	43.990s	674.801us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	8.720s	477.457us	5	5	100.00
		alert_handler_csr_rw	8.760s	850.211us	20	20	100.00
		alert_handler_csr_aliasing	4.309m	16.603ms	5	5	100.00
		alert_handler_same_csr_outstanding	43.990s	674.801us	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	22.252m	39.912ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	22.252m	39.912ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	22.252m	39.912ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	22.252m	39.912ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	1.182h	66.795ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	21.420s	426.230us	5	5	100.00
		alert_handler_tl_intg_err	1.374m	5.166ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.374m	5.166ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	22.252m	39.912ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.017m	8.805ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.017m	8.805ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.017m	8.805ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.017m	8.805ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.139m	8.699ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	57.745m	238.652ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.139m	8.699ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	53.395m	56.253ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	53.395m	56.253ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	21.420s	426.230us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	21.420s	426.230us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	21.420s	426.230us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	21.420s	426.230us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	21.420s	426.230us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	21.420s	426.230us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	21.420s	426.230us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	21.420s	426.230us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	21.420s	426.230us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.561h	585.275ms	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			845	850	99.41

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	99.99	98.71	100.00	100.00	100.00	99.25	99.76

Failure Buckets

Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test alert_handler_lpg_stub_clk has 1 failures.
  - 31.alert_handler_lpg_stub_clk.1708162479
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_lpg_stub_clk/latest/run.log
```
  Job ID: smart:ada9955d-9665-4b7f-8bc2-3309219f1835
```
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 45.alert_handler_stress_all_with_rand_reset.2644857244
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/45.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:f33c9f74-548a-48a3-a409-e89949812bdc
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 3.alert_handler_stress_all_with_rand_reset.2888827158
    Line 566, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 756976682098 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 756976682098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_d, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 22.alert_handler_sig_int_fail.3048168462
    Line 221, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/22.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @  59998536 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_d, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @  59998536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:332) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 42.alert_handler_stress_all_with_rand_reset.2960874373
    Line 1635, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/42.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 336903260351 ps: (alert_handler_scoreboard.sv:332) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (38 [0x26] vs 60 [0x3c])
  UVM_INFO @ 336903260351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Saturday May 27 2023 07:02:22 UTC

GitHub Revision: c06cc3921

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2359737659

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c06cc3921`