ALERT_HANDLER Simulation Results

Sunday May 28 2023 07:05:15 UTC

GitHub Revision: c06cc3921

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2869101736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.204m	2.479ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.820s	495.600us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.520s	125.472us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	7.042m	17.422ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.359m	8.051ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	8.120s	938.051us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.520s	125.472us	20	20	100.00
		alert_handler_csr_aliasing	4.359m	8.051ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.078m	6.117ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.038m	1.099ms	50	50	100.00
V2	entropy	alert_handler_entropy	55.910m	59.199ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.153m	1.244ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.204m	2.479ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.299m	5.782ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.057m	2.233ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	9.862m	61.339ms	50	50	100.00
V2	lpg	alert_handler_lpg	57.798m	251.436ms	48	50	96.00
		alert_handler_lpg_stub_clk	53.294m	216.015ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.049h	141.740ms	46	50	92.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	59.310s	2.859ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.450s	346.782us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.770s	14.683us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	24.520s	306.900us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	24.520s	306.900us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.820s	495.600us	5	5	100.00
		alert_handler_csr_rw	10.520s	125.472us	20	20	100.00
		alert_handler_csr_aliasing	4.359m	8.051ms	5	5	100.00
		alert_handler_same_csr_outstanding	44.270s	726.744us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.820s	495.600us	5	5	100.00
		alert_handler_csr_rw	10.520s	125.472us	20	20	100.00
		alert_handler_csr_aliasing	4.359m	8.051ms	5	5	100.00
		alert_handler_same_csr_outstanding	44.270s	726.744us	20	20	100.00
V2		TOTAL			623	630	98.89
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	22.797m	82.890ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	22.797m	82.890ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	22.797m	82.890ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	22.797m	82.890ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	1.224h	96.673ms	19	20	95.00
V2S	tl_intg_err	alert_handler_sec_cm	25.210s	493.061us	5	5	100.00
		alert_handler_tl_intg_err	1.383m	1.264ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.383m	1.264ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	22.797m	82.890ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.204m	2.479ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.204m	2.479ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.204m	2.479ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.204m	2.479ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.153m	1.244ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	57.798m	251.436ms	48	50	96.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.153m	1.244ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	55.910m	59.199ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	55.910m	59.199ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	25.210s	493.061us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	25.210s	493.061us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	25.210s	493.061us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	25.210s	493.061us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	25.210s	493.061us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	25.210s	493.061us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	25.210s	493.061us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	25.210s	493.061us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	25.210s	493.061us	5	5	100.00
V2S		TOTAL			64	65	98.46
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.645h	559.854ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			842	850	99.06

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	12	80.00
V2S	4	4	3	75.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	99.99	98.66	100.00	100.00	100.00	99.25	99.64

Failure Buckets

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_accum_cnt has 1 failures:

  • Test alert_handler_lpg has 1 failures.

    • 3.alert_handler_lpg.960390317
      Line 223, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_lpg/latest/run.log

        UVM_ERROR @ 4433990844 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (259 [0x103] vs 258 [0x102]) reg name: alert_handler_reg_block.classa_accum_cnt
        UVM_INFO @ 4433990844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:330) [scoreboard] Check failed cycle_cnt <= exp_cycle (* [*] vs * [*]) has 1 failures:

  • Test alert_handler_stress_all has 1 failures.

    • 8.alert_handler_stress_all.1732209453
      Line 235, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_stress_all/latest/run.log

        UVM_ERROR @ 918548282 ps: (alert_handler_scoreboard.sv:330) [uvm_test_top.env.scoreboard] Check failed cycle_cnt <= exp_cycle (655 [0x28f] vs 346 [0x15a])
        UVM_INFO @ 918548282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test alert_handler_shadow_reg_errors_with_csr_rw has 1 failures.

    • 11.alert_handler_shadow_reg_errors_with_csr_rw.2145754860
      Line 219, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_FATAL @ 500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_d, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_stress_all has 1 failures.

    • 23.alert_handler_stress_all.2969045250
      Line 280, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/23.alert_handler_stress_all/latest/run.log

        UVM_ERROR @ 10227913803 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_d, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 10227913803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:332) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) has 1 failures:

  • Test alert_handler_stress_all has 1 failures.

    • 24.alert_handler_stress_all.2624978676
      Line 316, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/24.alert_handler_stress_all/latest/run.log

        UVM_ERROR @ 32788749171 ps: (alert_handler_scoreboard.sv:332) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (393 [0x189] vs 458 [0x1ca])
        UVM_INFO @ 32788749171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test alert_handler_lpg has 1 failures.

    • 34.alert_handler_lpg.1323394704
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/34.alert_handler_lpg/latest/run.log

        Job ID: smart:05a6e40f-0390-4dce-85f1-a9783b0026d4
      

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classb_state has 1 failures:

  • Test alert_handler_stress_all has 1 failures.

    • 35.alert_handler_stress_all.581904193
      Line 226, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/35.alert_handler_stress_all/latest/run.log

        UVM_ERROR @ 451125108 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 7 [0x7]) reg name: alert_handler_reg_block.classb_state
        UVM_INFO @ 451125108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:483) [alert_handler_sig_int_fail_vseq] Check failed data == * (* [*] vs * [*]) has 1 failures:

  • Test alert_handler_sig_int_fail has 1 failures.

    • 44.alert_handler_sig_int_fail.3684323438
      Line 223, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/44.alert_handler_sig_int_fail/latest/run.log

        UVM_ERROR @ 694204523 ps: (cip_base_vseq.sv:483) [uvm_test_top.env.virtual_sequencer.alert_handler_sig_int_fail_vseq] Check failed data == 0 (2 [0x2] vs 0 [0x0])
        UVM_INFO @ 694204523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2023.05.27_19.12.29
• 2023.05.26_19.16.22
• 2023.05.25_18.30.23
• 2023.05.24_17.47.50
• 2023.05.23_18.09.35
• 2023.05.22_19.52.19
• 2023.05.21_20.29.12