Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg
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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 1 9 90.00
Crosses 16 6 10 62.50


Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
class_index_cp 4 1 3 75.00 100 1 1 0
esc_index_cp 4 0 4 100.00 100 1 1 0
loc_alert_cause_cp 2 0 2 100.00 100 1 1 0


Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
loc_alert_cause_cross_alert_index 8 2 6 75.00 100 1 1 0
loc_alert_cause_cross_class_index 8 4 4 50.00 100 1 1 0


Summary for Variable class_index_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 1 3 75.00


User Defined Bins for class_index_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
class_i[0x3] 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
class_i[0x0] 155400 1 T52 1 T56 1 T26 3107
class_i[0x1] 800 1 T18 4 T32 4 T47 4
class_i[0x2] 21650 1 T17 51 T52 204 T25 51



Summary for Variable esc_index_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for esc_index_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
alert[0x0] 52300 1 T17 4 T52 168 T25 4
alert[0x1] 41400 1 T17 11 T52 11 T25 11
alert[0x2] 45950 1 T17 22 T18 3 T32 3
alert[0x3] 38200 1 T17 14 T18 1 T32 1



Summary for Variable loc_alert_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
esc_integrity_fail 177650 1 T17 51 T52 211 T25 51
esc_ping_fail 200 1 T18 4 T32 4 T47 4



Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 2 6 75.00 2


Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Uncovered bins
loc_alert_cause_cpesc_index_cpCOUNTAT LEASTNUMBERSTATUS
[esc_ping_fail] [alert[0x0] , alert[0x1]] -- -- 2


Covered bins
loc_alert_cause_cpesc_index_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
esc_integrity_fail alert[0x0] 52300 1 T17 4 T52 168 T25 4
esc_integrity_fail alert[0x1] 41400 1 T17 11 T52 11 T25 11
esc_integrity_fail alert[0x2] 45800 1 T17 22 T52 18 T25 22
esc_integrity_fail alert[0x3] 38150 1 T17 14 T52 14 T25 14
esc_ping_fail alert[0x2] 150 1 T18 3 T32 3 T47 3
esc_ping_fail alert[0x3] 50 1 T18 1 T32 1 T47 1



Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 4 4 50.00 4


Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Uncovered bins
loc_alert_cause_cpclass_index_cpCOUNTAT LEASTNUMBERSTATUS
[esc_integrity_fail] [class_i[0x3]] 0 1 1
[esc_ping_fail] [class_i[0x0]] 0 1 1
[esc_ping_fail] [class_i[0x2] , class_i[0x3]] -- -- 2


Covered bins
loc_alert_cause_cpclass_index_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
esc_integrity_fail class_i[0x0] 155400 1 T52 1 T56 1 T26 3107
esc_integrity_fail class_i[0x1] 600 1 T52 6 T56 6 T26 6
esc_integrity_fail class_i[0x2] 21650 1 T17 51 T52 204 T25 51
esc_ping_fail class_i[0x1] 200 1 T18 4 T32 4 T47 4

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