Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg
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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 3 12 80.00
Crosses 44 31 13 29.55


Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
esc_sig_index_cp 4 0 4 100.00 100 1 1 0
esc_sig_len_cp 11 3 8 72.73 100 1 1 0


Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
len_per_esc_sig 44 31 13 29.55 100 1 1 0


Summary for Variable esc_sig_index_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for esc_sig_index_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
index[0x0] 250 1 T17 3 T27 1 T28 1
index[0x1] 350 1 T17 1 T31 1 T52 1
index[0x2] 400 1 T17 3 T27 1 T28 1
index[0x3] 150 1 T17 1 T25 1 T26 2



Summary for Variable esc_sig_len_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 11 3 8 72.73


User Defined Bins for esc_sig_len_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
lens_less_than_1000[7] 0 1 1
lens_less_than_1000[8] 0 1 1
lens_less_than_1000[9] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lens_less_than_1000[0] 150 1 T52 1 T56 1 T26 2
lens_less_than_1000[1] 400 1 T17 4 T27 1 T28 1
lens_less_than_1000[2] 150 1 T17 2 T58 1 T25 2
lens_less_than_1000[3] 50 1 T26 1 T65 1 T85 1
lens_less_than_1000[4] 50 1 T26 1 T65 1 T85 1
lens_less_than_1000[5] 150 1 T17 1 T31 1 T54 1
lens_less_than_1000[6] 100 1 T26 2 T65 2 T85 2
len_2 100 1 T17 1 T27 1 T28 1



Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 44 31 13 29.55 31


Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins
esc_sig_index_cpesc_sig_len_cpCOUNTAT LEASTNUMBERSTATUS
[index[0x0]] [lens_less_than_1000[3] , lens_less_than_1000[4] , lens_less_than_1000[5] , lens_less_than_1000[6] , lens_less_than_1000[7] , lens_less_than_1000[8] , lens_less_than_1000[9] , len_2] -- -- 8
[index[0x1]] [lens_less_than_1000[1]] 0 1 1
[index[0x1]] [lens_less_than_1000[3]] 0 1 1
[index[0x1]] [lens_less_than_1000[6] , lens_less_than_1000[7] , lens_less_than_1000[8] , lens_less_than_1000[9] , len_2] -- -- 5
[index[0x2]] [lens_less_than_1000[0]] 0 1 1
[index[0x2]] [lens_less_than_1000[2]] 0 1 1
[index[0x2]] [lens_less_than_1000[4] , lens_less_than_1000[5]] -- -- 2
[index[0x2]] [lens_less_than_1000[7] , lens_less_than_1000[8] , lens_less_than_1000[9]] -- -- 3
[index[0x3]] [lens_less_than_1000[0]] 0 1 1
[index[0x3]] [lens_less_than_1000[2] , lens_less_than_1000[3] , lens_less_than_1000[4]] -- -- 3
[index[0x3]] [lens_less_than_1000[6] , lens_less_than_1000[7] , lens_less_than_1000[8] , lens_less_than_1000[9] , len_2] -- -- 5


Covered bins
esc_sig_index_cpesc_sig_len_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
index[0x0] lens_less_than_1000[0] 50 1 T26 1 T65 1 T85 1
index[0x0] lens_less_than_1000[1] 150 1 T17 2 T27 1 T28 1
index[0x0] lens_less_than_1000[2] 50 1 T17 1 T25 1 T60 1
index[0x1] lens_less_than_1000[0] 100 1 T52 1 T56 1 T26 1
index[0x1] lens_less_than_1000[2] 100 1 T17 1 T58 1 T25 1
index[0x1] lens_less_than_1000[4] 50 1 T26 1 T65 1 T85 1
index[0x1] lens_less_than_1000[5] 100 1 T31 1 T54 1 T55 1
index[0x2] lens_less_than_1000[1] 150 1 T17 2 T25 2 T26 1
index[0x2] lens_less_than_1000[3] 50 1 T26 1 T65 1 T85 1
index[0x2] lens_less_than_1000[6] 100 1 T26 2 T65 2 T85 2
index[0x2] len_2 100 1 T17 1 T27 1 T28 1
index[0x3] lens_less_than_1000[1] 100 1 T26 2 T65 2 T85 2
index[0x3] lens_less_than_1000[5] 50 1 T17 1 T25 1 T60 1

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