Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
29.63	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	5	9	64.29
Crosses	40	33	7	17.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	5	5	50.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	33	7	17.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	150	1			T17	2		T25	2		T26	1
class_index[0x1]	50	1			T17	1		T25	1		T60	1
class_index[0x2]	100	1			T17	2		T25	2		T60	2
class_index[0x3]	100	1			T17	2		T25	2		T60	2

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	5	5	50.00

User Defined Bins for intr_timeout_cnt_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
intr_timeout_cnt[2]	0	1	1
intr_timeout_cnt[3]	0	1	1
intr_timeout_cnt[4]	0	1	1
intr_timeout_cnt[6]	0	1	1
intr_timeout_cnt[7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	100	1			T17	2		T25	2		T60	2
intr_timeout_cnt[1]	100	1			T17	1		T25	1		T26	1
intr_timeout_cnt[5]	50	1			T17	1		T25	1		T60	1
intr_timeout_cnt[8]	100	1			T17	2		T25	2		T60	2
intr_timeout_cnt[9]	50	1			T17	1		T25	1		T60	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	33	7	17.50	33

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[2] , intr_timeout_cnt[3] , intr_timeout_cnt[4] , intr_timeout_cnt[5] , intr_timeout_cnt[6] , intr_timeout_cnt[7] , intr_timeout_cnt[8]]	--	--	7
[class_index[0x1]]	[intr_timeout_cnt[0] , intr_timeout_cnt[1] , intr_timeout_cnt[2] , intr_timeout_cnt[3] , intr_timeout_cnt[4]]	--	--	5
[class_index[0x1]]	[intr_timeout_cnt[6] , intr_timeout_cnt[7] , intr_timeout_cnt[8] , intr_timeout_cnt[9]]	--	--	4
[class_index[0x2]]	[intr_timeout_cnt[2] , intr_timeout_cnt[3] , intr_timeout_cnt[4] , intr_timeout_cnt[5] , intr_timeout_cnt[6] , intr_timeout_cnt[7] , intr_timeout_cnt[8] , intr_timeout_cnt[9]]	--	--	8
[class_index[0x3]]	[intr_timeout_cnt[0] , intr_timeout_cnt[1] , intr_timeout_cnt[2] , intr_timeout_cnt[3] , intr_timeout_cnt[4] , intr_timeout_cnt[5] , intr_timeout_cnt[6] , intr_timeout_cnt[7]]	--	--	8
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	50	1			T17	1		T25	1		T60	1
class_index[0x0]	intr_timeout_cnt[1]	50	1			T26	1		T65	1		T85	1
class_index[0x0]	intr_timeout_cnt[9]	50	1			T17	1		T25	1		T60	1
class_index[0x1]	intr_timeout_cnt[5]	50	1			T17	1		T25	1		T60	1
class_index[0x2]	intr_timeout_cnt[0]	50	1			T17	1		T25	1		T60	1
class_index[0x2]	intr_timeout_cnt[1]	50	1			T17	1		T25	1		T60	1
class_index[0x3]	intr_timeout_cnt[8]	100	1			T17	2		T25	2		T60	2