Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	352720	1			T34	8		T2	1		T13	8
all_values[1]	352720	1			T34	8		T2	1		T13	8
all_values[2]	352720	1			T34	8		T2	1		T13	8
all_values[3]	352720	1			T34	8		T2	1		T13	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

703130

1

T34

19

T2

4

T13

19

auto[1]

707750

1

T34

13

T13

13

T14

13

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

802430

1

T34

17

T2

4

T13

17

auto[1]

608450

1

T34

15

T13

15

T14

15

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	97620	1			T34	5		T2	1		T13	5
all_values[0]	auto[0]	auto[1]	76600	1			T34	2		T13	2		T14	2
all_values[0]	auto[1]	auto[0]	100150	1			T34	1		T13	1		T14	1
all_values[0]	auto[1]	auto[1]	78350	1			T17	280		T19	7		T23	8
all_values[1]	auto[0]	auto[0]	105270	1			T34	3		T2	1		T13	3
all_values[1]	auto[0]	auto[1]	73350	1			T34	2		T13	2		T14	2
all_values[1]	auto[1]	auto[0]	104450	1			T34	2		T13	2		T14	2
all_values[1]	auto[1]	auto[1]	69650	1			T34	1		T13	1		T14	1
all_values[2]	auto[0]	auto[0]	99320	1			T34	2		T2	1		T13	2
all_values[2]	auto[0]	auto[1]	76600	1			T34	4		T13	4		T14	4
all_values[2]	auto[1]	auto[0]	100400	1			T17	368		T18	41		T19	12
all_values[2]	auto[1]	auto[1]	76400	1			T34	2		T13	2		T14	2
all_values[3]	auto[0]	auto[0]	97720	1			T34	1		T2	1		T13	1
all_values[3]	auto[0]	auto[1]	76650	1			T17	249		T19	7		T24	7
all_values[3]	auto[1]	auto[0]	97500	1			T34	3		T13	3		T14	3
all_values[3]	auto[1]	auto[1]	80850	1			T34	4		T13	4		T14	4