Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	352720	1			T34	8		T2	1		T13	8
all_pins[1]	352720	1			T34	8		T2	1		T13	8
all_pins[2]	352720	1			T34	8		T2	1		T13	8
all_pins[3]	352720	1			T34	8		T2	1		T13	8

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1105630	1			T34	25		T2	4		T13	25
values[0x1]	305250	1			T34	7		T13	7		T14	7
transitions[0x0=>0x1]	202650	1			T34	6		T13	6		T14	6
transitions[0x1=>0x0]	202800	1			T34	6		T13	6		T14	6

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	274370	1			T34	8		T2	1		T13	8
all_pins[0]	values[0x1]	78350	1			T17	280		T19	7		T23	8
all_pins[0]	transitions[0x0=>0x1]	77100	1			T17	272		T19	7		T23	8
all_pins[0]	transitions[0x1=>0x0]	79750	1			T34	4		T13	4		T14	4
all_pins[1]	values[0x0]	283070	1			T34	7		T2	1		T13	7
all_pins[1]	values[0x1]	69650	1			T34	1		T13	1		T14	1
all_pins[1]	transitions[0x0=>0x1]	36850	1			T34	1		T13	1		T14	1
all_pins[1]	transitions[0x1=>0x0]	45550	1			T17	170		T19	1		T23	8
all_pins[2]	values[0x0]	276320	1			T34	6		T2	1		T13	6
all_pins[2]	values[0x1]	76400	1			T34	2		T13	2		T14	2
all_pins[2]	transitions[0x0=>0x1]	44450	1			T34	2		T13	2		T14	2
all_pins[2]	transitions[0x1=>0x0]	37700	1			T34	1		T13	1		T14	1
all_pins[3]	values[0x0]	271870	1			T34	4		T2	1		T13	4
all_pins[3]	values[0x1]	80850	1			T34	4		T13	4		T14	4
all_pins[3]	transitions[0x0=>0x1]	44250	1			T34	3		T13	3		T14	3
all_pins[3]	transitions[0x1=>0x0]	39800	1			T34	1		T13	1		T14	1