Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.12	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	2	22	91.67

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	2	22	91.67	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	26700	1			T27	148		T28	148		T53	386
accum_cnt_1000	319650	1			T17	830		T30	2778		T27	1116
accum_cnt_100	57950	1			T17	392		T23	5		T29	5
accum_cnt_50	149300	1			T17	440		T19	6		T23	8
accum_cnt_10	245400	1			T17	551		T18	16		T19	50
accum_cnt_0	250600	1			T17	1403		T18	92		T19	88

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	262400	1			T17	904		T18	27		T19	36
class_index[0x1]	262400	1			T17	904		T18	27		T19	36
class_index[0x2]	262400	1			T17	904		T18	27		T19	36
class_index[0x3]	262400	1			T17	904		T18	27		T19	36

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	2	22	91.67	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[accum_cnt_2000]	0	1	1
[class_index[0x3]]	[accum_cnt_2000]	0	1	1

Covered bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_1000	62800	1			T17	281		T30	829		T31	47
class_index[0x0]	accum_cnt_100	18350	1			T17	115		T23	5		T29	5
class_index[0x0]	accum_cnt_50	104250	1			T17	224		T19	2		T23	8
class_index[0x0]	accum_cnt_10	68900	1			T17	250		T19	23		T23	8
class_index[0x0]	accum_cnt_0	8100	1			T17	34		T18	27		T19	11
class_index[0x1]	accum_cnt_2000	19300	1			T53	386		T107	386		T108	386
class_index[0x1]	accum_cnt_1000	105800	1			T17	184		T27	624		T31	56
class_index[0x1]	accum_cnt_100	14400	1			T17	122		T27	37		T31	18
class_index[0x1]	accum_cnt_50	16900	1			T17	85		T27	30		T31	16
class_index[0x1]	accum_cnt_10	64550	1			T17	58		T18	16		T19	4
class_index[0x1]	accum_cnt_0	41450	1			T17	455		T18	11		T19	32
class_index[0x2]	accum_cnt_2000	7400	1			T27	148		T28	148		T66	148
class_index[0x2]	accum_cnt_1000	87500	1			T17	155		T30	961		T27	492
class_index[0x2]	accum_cnt_100	14800	1			T17	79		T30	102		T27	30
class_index[0x2]	accum_cnt_50	13250	1			T17	56		T30	58		T27	23
class_index[0x2]	accum_cnt_10	7950	1			T17	50		T30	15		T27	7
class_index[0x2]	accum_cnt_0	131500	1			T17	564		T18	27		T19	36
class_index[0x3]	accum_cnt_1000	63550	1			T17	210		T30	988		T31	57
class_index[0x3]	accum_cnt_100	10400	1			T17	76		T30	71		T31	20
class_index[0x3]	accum_cnt_50	14900	1			T17	75		T19	4		T24	4
class_index[0x3]	accum_cnt_10	104000	1			T17	193		T19	23		T24	23
class_index[0x3]	accum_cnt_0	69550	1			T17	350		T18	27		T19	9