Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
47.37	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	26	45	63.38
Crosses	138	84	54	39.13

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	26	39	60.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	83	47	36.15	100	1	1	0
loc_alert_cause_cross_class_index	8	1	7	87.50	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	26	39	60.00

User Defined Bins for alert_index_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
alert[0x0]	0	1	1
alert[0x1]	0	1	1
alert[0x2]	0	1	1
alert[0x3]	0	1	1
alert[0x7]	0	1	1
alert[0xb]	0	1	1
alert[0xc]	0	1	1
alert[0xe]	0	1	1
alert[0xf]	0	1	1
alert[0x12]	0	1	1
alert[0x13]	0	1	1
alert[0x16]	0	1	1
alert[0x18]	0	1	1
alert[0x19]	0	1	1
alert[0x1b]	0	1	1
alert[0x1c]	0	1	1
alert[0x29]	0	1	1
alert[0x2a]	0	1	1
alert[0x2e]	0	1	1
alert[0x2f]	0	1	1
alert[0x30]	0	1	1
alert[0x36]	0	1	1
alert[0x3a]	0	1	1
alert[0x3b]	0	1	1
alert[0x3c]	0	1	1
alert[0x3e]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x4]	13600	1			T17	66		T27	194		T28	194
alert[0x5]	50	1			T18	1		T32	1		T47	1
alert[0x6]	50	1			T18	1		T32	1		T47	1
alert[0x8]	5900	1			T17	9		T18	1		T32	1
alert[0x9]	50	1			T18	1		T32	1		T47	1
alert[0xa]	17000	1			T17	26		T27	130		T28	130
alert[0xd]	13150	1			T17	18		T27	103		T28	103
alert[0x10]	5950	1			T17	12		T18	2		T32	2
alert[0x11]	1300	1			T17	8		T27	16		T28	16
alert[0x14]	4000	1			T17	6		T18	1		T32	1
alert[0x15]	650	1			T17	2		T27	6		T28	6
alert[0x17]	950	1			T17	3		T27	6		T28	6
alert[0x1a]	161150	1			T17	456		T27	1189		T28	1189
alert[0x1d]	27650	1			T17	45		T27	215		T28	215
alert[0x1e]	50	1			T18	1		T32	1		T47	1
alert[0x1f]	17250	1			T17	57		T30	1		T27	102
alert[0x20]	2950	1			T17	13		T27	19		T28	19
alert[0x21]	15900	1			T17	50		T18	1		T32	1
alert[0x22]	100	1			T18	1		T32	1		T30	1
alert[0x23]	27200	1			T17	78		T27	201		T28	201
alert[0x24]	2050	1			T17	7		T27	14		T28	14
alert[0x25]	300	1			T17	1		T27	5		T28	5
alert[0x26]	50	1			T18	1		T32	1		T47	1
alert[0x27]	300	1			T17	1		T27	2		T28	2
alert[0x28]	100	1			T18	2		T32	2		T47	2
alert[0x2b]	700	1			T17	4		T27	5		T28	5
alert[0x2c]	7000	1			T17	20		T30	1		T27	106
alert[0x2d]	2850	1			T17	5		T27	21		T28	21
alert[0x31]	14850	1			T17	45		T27	100		T28	100
alert[0x32]	400	1			T17	1		T27	4		T28	4
alert[0x33]	20050	1			T17	22		T27	161		T28	161
alert[0x34]	3650	1			T17	1		T27	31		T28	31
alert[0x35]	14050	1			T17	16		T27	113		T28	113
alert[0x37]	6400	1			T17	17		T27	109		T28	109
alert[0x38]	850	1			T17	3		T27	4		T28	4
alert[0x39]	31850	1			T17	82		T18	2		T32	2
alert[0x3d]	750	1			T17	4		T18	1		T32	1
alert[0x3f]	1000	1			T17	2		T27	9		T28	9
alert[0x40]	40250	1			T17	104		T27	319		T28	319

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	430450	1			T17	626		T27	3680		T28	3680
class_i[0x1]	1100	1			T18	1		T32	1		T47	1
class_i[0x2]	400	1			T30	3		T26	5		T86	3
class_i[0x3]	30400	1			T17	558		T18	15		T32	15

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

461400

1

T17

1184

T27

3680

T28

3680

alert_ping_fail

950

1

T18

16

T32

16

T30

3

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	83	47	36.15	83

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Uncovered bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	NUMBER	STATUS
[alert_integrity_fail]	[alert[0x0] , alert[0x1] , alert[0x2] , alert[0x3]]	--	--	4
[alert_integrity_fail]	[alert[0x5] , alert[0x6] , alert[0x7]]	--	--	3
[alert_integrity_fail]	[alert[0x9]]	0	1	1
[alert_integrity_fail]	[alert[0xb] , alert[0xc]]	--	--	2
[alert_integrity_fail]	[alert[0xe] , alert[0xf]]	--	--	2
[alert_integrity_fail]	[alert[0x12] , alert[0x13]]	--	--	2
[alert_integrity_fail]	[alert[0x16]]	0	1	1
[alert_integrity_fail]	[alert[0x18] , alert[0x19]]	--	--	2
[alert_integrity_fail]	[alert[0x1b] , alert[0x1c]]	--	--	2
[alert_integrity_fail]	[alert[0x1e]]	0	1	1
[alert_integrity_fail]	[alert[0x22]]	0	1	1
[alert_integrity_fail]	[alert[0x26]]	0	1	1
[alert_integrity_fail]	[alert[0x28] , alert[0x29] , alert[0x2a]]	--	--	3
[alert_integrity_fail]	[alert[0x2e] , alert[0x2f] , alert[0x30]]	--	--	3
[alert_integrity_fail]	[alert[0x36]]	0	1	1
[alert_integrity_fail]	[alert[0x3a] , alert[0x3b] , alert[0x3c]]	--	--	3
[alert_integrity_fail]	[alert[0x3e]]	0	1	1
[alert_ping_fail]	[alert[0x0] , alert[0x1] , alert[0x2] , alert[0x3] , alert[0x4]]	--	--	5
[alert_ping_fail]	[alert[0x7]]	0	1	1
[alert_ping_fail]	[alert[0xa] , alert[0xb] , alert[0xc] , alert[0xd] , alert[0xe] , alert[0xf]]	--	--	6
[alert_ping_fail]	[alert[0x11] , alert[0x12] , alert[0x13]]	--	--	3
[alert_ping_fail]	[alert[0x15] , alert[0x16] , alert[0x17] , alert[0x18] , alert[0x19] , alert[0x1a] , alert[0x1b] , alert[0x1c] , alert[0x1d]]	--	--	9
[alert_ping_fail]	[alert[0x20]]	0	1	1
[alert_ping_fail]	[alert[0x23] , alert[0x24] , alert[0x25]]	--	--	3
[alert_ping_fail]	[alert[0x27]]	0	1	1
[alert_ping_fail]	[alert[0x29] , alert[0x2a] , alert[0x2b]]	--	--	3
[alert_ping_fail]	[alert[0x2d] , alert[0x2e] , alert[0x2f] , alert[0x30] , alert[0x31] , alert[0x32] , alert[0x33] , alert[0x34] , alert[0x35] , alert[0x36] , alert[0x37] , alert[0x38]]	--	--	12
[alert_ping_fail]	[alert[0x3a] , alert[0x3b] , alert[0x3c]]	--	--	3
[alert_ping_fail]	[alert[0x3e] , alert[0x3f] , alert[0x40]]	--	--	3

Covered bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x4]	13600	1			T17	66		T27	194		T28	194
alert_integrity_fail	alert[0x8]	5850	1			T17	9		T27	50		T28	50
alert_integrity_fail	alert[0xa]	17000	1			T17	26		T27	130		T28	130
alert_integrity_fail	alert[0xd]	13150	1			T17	18		T27	103		T28	103
alert_integrity_fail	alert[0x10]	5850	1			T17	12		T27	44		T28	44
alert_integrity_fail	alert[0x11]	1300	1			T17	8		T27	16		T28	16
alert_integrity_fail	alert[0x14]	3950	1			T17	6		T27	35		T28	35
alert_integrity_fail	alert[0x15]	650	1			T17	2		T27	6		T28	6
alert_integrity_fail	alert[0x17]	950	1			T17	3		T27	6		T28	6
alert_integrity_fail	alert[0x1a]	161150	1			T17	456		T27	1189		T28	1189
alert_integrity_fail	alert[0x1d]	27650	1			T17	45		T27	215		T28	215
alert_integrity_fail	alert[0x1f]	17200	1			T17	57		T27	102		T28	102
alert_integrity_fail	alert[0x20]	2950	1			T17	13		T27	19		T28	19
alert_integrity_fail	alert[0x21]	15850	1			T17	50		T27	110		T28	110
alert_integrity_fail	alert[0x23]	27200	1			T17	78		T27	201		T28	201
alert_integrity_fail	alert[0x24]	2050	1			T17	7		T27	14		T28	14
alert_integrity_fail	alert[0x25]	300	1			T17	1		T27	5		T28	5
alert_integrity_fail	alert[0x27]	300	1			T17	1		T27	2		T28	2
alert_integrity_fail	alert[0x2b]	700	1			T17	4		T27	5		T28	5
alert_integrity_fail	alert[0x2c]	6950	1			T17	20		T27	106		T28	106
alert_integrity_fail	alert[0x2d]	2850	1			T17	5		T27	21		T28	21
alert_integrity_fail	alert[0x31]	14850	1			T17	45		T27	100		T28	100
alert_integrity_fail	alert[0x32]	400	1			T17	1		T27	4		T28	4
alert_integrity_fail	alert[0x33]	20050	1			T17	22		T27	161		T28	161
alert_integrity_fail	alert[0x34]	3650	1			T17	1		T27	31		T28	31
alert_integrity_fail	alert[0x35]	14050	1			T17	16		T27	113		T28	113
alert_integrity_fail	alert[0x37]	6400	1			T17	17		T27	109		T28	109
alert_integrity_fail	alert[0x38]	850	1			T17	3		T27	4		T28	4
alert_integrity_fail	alert[0x39]	31750	1			T17	82		T27	247		T28	247
alert_integrity_fail	alert[0x3d]	700	1			T17	4		T27	10		T28	10
alert_integrity_fail	alert[0x3f]	1000	1			T17	2		T27	9		T28	9
alert_integrity_fail	alert[0x40]	40250	1			T17	104		T27	319		T28	319
alert_ping_fail	alert[0x5]	50	1			T18	1		T32	1		T47	1
alert_ping_fail	alert[0x6]	50	1			T18	1		T32	1		T47	1
alert_ping_fail	alert[0x8]	50	1			T18	1		T32	1		T47	1
alert_ping_fail	alert[0x9]	50	1			T18	1		T32	1		T47	1
alert_ping_fail	alert[0x10]	100	1			T18	2		T32	2		T47	2
alert_ping_fail	alert[0x14]	50	1			T18	1		T32	1		T47	1
alert_ping_fail	alert[0x1e]	50	1			T18	1		T32	1		T47	1
alert_ping_fail	alert[0x1f]	50	1			T30	1		T86	1		T123	1
alert_ping_fail	alert[0x21]	50	1			T18	1		T32	1		T47	1
alert_ping_fail	alert[0x22]	100	1			T18	1		T32	1		T30	1
alert_ping_fail	alert[0x26]	50	1			T18	1		T32	1		T47	1
alert_ping_fail	alert[0x28]	100	1			T18	2		T32	2		T47	2
alert_ping_fail	alert[0x2c]	50	1			T30	1		T86	1		T123	1
alert_ping_fail	alert[0x39]	100	1			T18	2		T32	2		T47	2
alert_ping_fail	alert[0x3d]	50	1			T18	1		T32	1		T47	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	1	7	87.50	1

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Uncovered bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	NUMBER	STATUS
[alert_ping_fail]	[class_i[0x0]]	0	1	1

Covered bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	430450	1			T17	626		T27	3680		T28	3680
alert_integrity_fail	class_i[0x1]	1050	1			T52	3		T56	3		T26	18
alert_integrity_fail	class_i[0x2]	250	1			T26	5		T65	5		T85	5
alert_integrity_fail	class_i[0x3]	29650	1			T17	558		T25	558		T26	35
alert_ping_fail	class_i[0x1]	50	1			T18	1		T32	1		T47	1
alert_ping_fail	class_i[0x2]	150	1			T30	3		T86	3		T123	3
alert_ping_fail	class_i[0x3]	750	1			T18	15		T32	15		T47	15